]>
Commit | Line | Data |
---|---|---|
8187a2b7 ZN |
1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ | |
3 | ||
633cf8f5 VS |
4 | /* |
5 | * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 "Ring Buffer Use" | |
6 | * Gen3 BSpec "vol1c Memory Interface Functions" / 2.3.4.5 "Ring Buffer Use" | |
7 | * Gen4+ BSpec "vol1c Memory Interface and Command Stream" / 5.3.4.5 "Ring Buffer Use" | |
8 | * | |
9 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the same | |
10 | * cacheline, the Head Pointer must not be greater than the Tail | |
11 | * Pointer." | |
12 | */ | |
13 | #define I915_RING_FREE_SPACE 64 | |
14 | ||
8187a2b7 | 15 | struct intel_hw_status_page { |
4225d0f2 | 16 | u32 *page_addr; |
8187a2b7 | 17 | unsigned int gfx_addr; |
05394f39 | 18 | struct drm_i915_gem_object *obj; |
8187a2b7 ZN |
19 | }; |
20 | ||
b7287d80 BW |
21 | #define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base)) |
22 | #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) | |
cae5852d | 23 | |
b7287d80 BW |
24 | #define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base)) |
25 | #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) | |
cae5852d | 26 | |
b7287d80 BW |
27 | #define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base)) |
28 | #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) | |
cae5852d | 29 | |
b7287d80 BW |
30 | #define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base)) |
31 | #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) | |
cae5852d | 32 | |
b7287d80 BW |
33 | #define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base)) |
34 | #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) | |
870e86dd | 35 | |
f2f4d82f | 36 | enum intel_ring_hangcheck_action { |
da661464 | 37 | HANGCHECK_IDLE = 0, |
f2f4d82f JN |
38 | HANGCHECK_WAIT, |
39 | HANGCHECK_ACTIVE, | |
40 | HANGCHECK_KICK, | |
41 | HANGCHECK_HUNG, | |
42 | }; | |
ad8beaea | 43 | |
b6b0fac0 MK |
44 | #define HANGCHECK_SCORE_RING_HUNG 31 |
45 | ||
92cab734 | 46 | struct intel_ring_hangcheck { |
6274f212 | 47 | bool deadlock; |
92cab734 | 48 | u32 seqno; |
05407ff8 MK |
49 | u32 acthd; |
50 | int score; | |
ad8beaea | 51 | enum intel_ring_hangcheck_action action; |
92cab734 MK |
52 | }; |
53 | ||
8187a2b7 ZN |
54 | struct intel_ring_buffer { |
55 | const char *name; | |
9220434a | 56 | enum intel_ring_id { |
96154f2f DV |
57 | RCS = 0x0, |
58 | VCS, | |
59 | BCS, | |
4a3dd19d | 60 | VECS, |
9220434a | 61 | } id; |
4a3dd19d | 62 | #define I915_NUM_RINGS 4 |
333e9fe9 | 63 | u32 mmio_base; |
311bd68e | 64 | void __iomem *virtual_start; |
8187a2b7 | 65 | struct drm_device *dev; |
05394f39 | 66 | struct drm_i915_gem_object *obj; |
8187a2b7 | 67 | |
8c0a6bfe CW |
68 | u32 head; |
69 | u32 tail; | |
780f0ca3 | 70 | int space; |
c2c347a9 | 71 | int size; |
55249baa | 72 | int effective_size; |
8187a2b7 ZN |
73 | struct intel_hw_status_page status_page; |
74 | ||
a71d8d94 CW |
75 | /** We track the position of the requests in the ring buffer, and |
76 | * when each is retired we increment last_retired_head as the GPU | |
77 | * must have finished processing the request and so we know we | |
78 | * can advance the ringbuffer up to that position. | |
79 | * | |
80 | * last_retired_head is set to -1 after the value is consumed so | |
81 | * we can detect new retirements. | |
82 | */ | |
83 | u32 last_retired_head; | |
84 | ||
c7113cc3 | 85 | unsigned irq_refcount; /* protected by dev_priv->irq_lock */ |
6a848ccb | 86 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ |
db53a302 | 87 | u32 trace_irq_seqno; |
1ec14ad3 | 88 | u32 sync_seqno[I915_NUM_RINGS-1]; |
b13c2b96 | 89 | bool __must_check (*irq_get)(struct intel_ring_buffer *ring); |
1ec14ad3 | 90 | void (*irq_put)(struct intel_ring_buffer *ring); |
8187a2b7 | 91 | |
78501eac | 92 | int (*init)(struct intel_ring_buffer *ring); |
8187a2b7 | 93 | |
78501eac | 94 | void (*write_tail)(struct intel_ring_buffer *ring, |
297b0c5b | 95 | u32 value); |
b72f3acb CW |
96 | int __must_check (*flush)(struct intel_ring_buffer *ring, |
97 | u32 invalidate_domains, | |
98 | u32 flush_domains); | |
9d773091 | 99 | int (*add_request)(struct intel_ring_buffer *ring); |
b2eadbc8 CW |
100 | /* Some chipsets are not quite as coherent as advertised and need |
101 | * an expensive kick to force a true read of the up-to-date seqno. | |
102 | * However, the up-to-date seqno is not always required and the last | |
103 | * seen value is good enough. Note that the seqno will always be | |
104 | * monotonic, even if not coherent. | |
105 | */ | |
106 | u32 (*get_seqno)(struct intel_ring_buffer *ring, | |
107 | bool lazy_coherency); | |
b70ec5bf MK |
108 | void (*set_seqno)(struct intel_ring_buffer *ring, |
109 | u32 seqno); | |
78501eac | 110 | int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, |
d7d4eedd CW |
111 | u32 offset, u32 length, |
112 | unsigned flags); | |
113 | #define I915_DISPATCH_SECURE 0x1 | |
b45305fc | 114 | #define I915_DISPATCH_PINNED 0x2 |
8d19215b | 115 | void (*cleanup)(struct intel_ring_buffer *ring); |
c8c99b0f BW |
116 | int (*sync_to)(struct intel_ring_buffer *ring, |
117 | struct intel_ring_buffer *to, | |
118 | u32 seqno); | |
ad776f8b | 119 | |
5586181f BW |
120 | /* our mbox written by others */ |
121 | u32 semaphore_register[I915_NUM_RINGS]; | |
ad776f8b BW |
122 | /* mboxes this ring signals to */ |
123 | u32 signal_mbox[I915_NUM_RINGS]; | |
124 | ||
8187a2b7 ZN |
125 | /** |
126 | * List of objects currently involved in rendering from the | |
127 | * ringbuffer. | |
128 | * | |
129 | * Includes buffers having the contents of their GPU caches | |
130 | * flushed, not necessarily primitives. last_rendering_seqno | |
131 | * represents when the rendering involved will be completed. | |
132 | * | |
133 | * A reference is held on the buffer while on this list. | |
134 | */ | |
135 | struct list_head active_list; | |
136 | ||
137 | /** | |
138 | * List of breadcrumbs associated with GPU requests currently | |
139 | * outstanding. | |
140 | */ | |
141 | struct list_head request_list; | |
142 | ||
a56ba56c CW |
143 | /** |
144 | * Do we have some not yet emitted requests outstanding? | |
145 | */ | |
3c0e234c | 146 | struct drm_i915_gem_request *preallocated_lazy_request; |
1823521d | 147 | u32 outstanding_lazy_seqno; |
cc889e0f | 148 | bool gpu_caches_dirty; |
c65355bb | 149 | bool fbc_dirty; |
a56ba56c | 150 | |
8187a2b7 | 151 | wait_queue_head_t irq_queue; |
8d19215b | 152 | |
12b0286f BW |
153 | /** |
154 | * Do an explicit TLB flush before MI_SET_CONTEXT | |
155 | */ | |
156 | bool itlb_before_ctx_switch; | |
40521054 | 157 | struct i915_hw_context *default_context; |
112522f6 | 158 | struct i915_hw_context *last_context; |
40521054 | 159 | |
92cab734 MK |
160 | struct intel_ring_hangcheck hangcheck; |
161 | ||
0d1aacac CW |
162 | struct { |
163 | struct drm_i915_gem_object *obj; | |
164 | u32 gtt_offset; | |
165 | volatile u32 *cpu_page; | |
166 | } scratch; | |
351e3db2 BV |
167 | |
168 | /* | |
169 | * Tables of commands the command parser needs to know about | |
170 | * for this ring. | |
171 | */ | |
172 | const struct drm_i915_cmd_table *cmd_tables; | |
173 | int cmd_table_count; | |
174 | ||
175 | /* | |
176 | * Table of registers allowed in commands that read/write registers. | |
177 | */ | |
178 | const u32 *reg_table; | |
179 | int reg_count; | |
180 | ||
181 | /* | |
182 | * Table of registers allowed in commands that read/write registers, but | |
183 | * only from the DRM master. | |
184 | */ | |
185 | const u32 *master_reg_table; | |
186 | int master_reg_count; | |
187 | ||
188 | /* | |
189 | * Returns the bitmask for the length field of the specified command. | |
190 | * Return 0 for an unrecognized/invalid command. | |
191 | * | |
192 | * If the command parser finds an entry for a command in the ring's | |
193 | * cmd_tables, it gets the command's length based on the table entry. | |
194 | * If not, it calls this function to determine the per-ring length field | |
195 | * encoding for the command (i.e. certain opcode ranges use certain bits | |
196 | * to encode the command length in the header). | |
197 | */ | |
198 | u32 (*get_cmd_length_mask)(u32 cmd_header); | |
8187a2b7 ZN |
199 | }; |
200 | ||
b4519513 CW |
201 | static inline bool |
202 | intel_ring_initialized(struct intel_ring_buffer *ring) | |
203 | { | |
204 | return ring->obj != NULL; | |
205 | } | |
206 | ||
96154f2f DV |
207 | static inline unsigned |
208 | intel_ring_flag(struct intel_ring_buffer *ring) | |
209 | { | |
210 | return 1 << ring->id; | |
211 | } | |
212 | ||
1ec14ad3 CW |
213 | static inline u32 |
214 | intel_ring_sync_index(struct intel_ring_buffer *ring, | |
215 | struct intel_ring_buffer *other) | |
216 | { | |
217 | int idx; | |
218 | ||
219 | /* | |
220 | * cs -> 0 = vcs, 1 = bcs | |
221 | * vcs -> 0 = bcs, 1 = cs, | |
222 | * bcs -> 0 = cs, 1 = vcs. | |
223 | */ | |
224 | ||
225 | idx = (other - ring) - 1; | |
226 | if (idx < 0) | |
227 | idx += I915_NUM_RINGS; | |
228 | ||
229 | return idx; | |
230 | } | |
231 | ||
8187a2b7 ZN |
232 | static inline u32 |
233 | intel_read_status_page(struct intel_ring_buffer *ring, | |
78501eac | 234 | int reg) |
8187a2b7 | 235 | { |
4225d0f2 DV |
236 | /* Ensure that the compiler doesn't optimize away the load. */ |
237 | barrier(); | |
238 | return ring->status_page.page_addr[reg]; | |
8187a2b7 ZN |
239 | } |
240 | ||
b70ec5bf MK |
241 | static inline void |
242 | intel_write_status_page(struct intel_ring_buffer *ring, | |
243 | int reg, u32 value) | |
244 | { | |
245 | ring->status_page.page_addr[reg] = value; | |
246 | } | |
247 | ||
311bd68e CW |
248 | /** |
249 | * Reads a dword out of the status page, which is written to from the command | |
250 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
251 | * MI_STORE_DATA_IMM. | |
252 | * | |
253 | * The following dwords have a reserved meaning: | |
254 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. | |
255 | * 0x04: ring 0 head pointer | |
256 | * 0x05: ring 1 head pointer (915-class) | |
257 | * 0x06: ring 2 head pointer (915-class) | |
258 | * 0x10-0x1b: Context status DWords (GM45) | |
259 | * 0x1f: Last written status offset. (GM45) | |
260 | * | |
261 | * The area from dword 0x20 to 0x3ff is available for driver usage. | |
262 | */ | |
311bd68e | 263 | #define I915_GEM_HWS_INDEX 0x20 |
9a289771 JB |
264 | #define I915_GEM_HWS_SCRATCH_INDEX 0x30 |
265 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) | |
311bd68e | 266 | |
78501eac | 267 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring); |
96f298aa | 268 | |
e1f99ce6 | 269 | int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n); |
753b1ad4 | 270 | int __must_check intel_ring_cacheline_align(struct intel_ring_buffer *ring); |
78501eac CW |
271 | static inline void intel_ring_emit(struct intel_ring_buffer *ring, |
272 | u32 data) | |
e898cd22 | 273 | { |
78501eac | 274 | iowrite32(data, ring->virtual_start + ring->tail); |
e898cd22 CW |
275 | ring->tail += 4; |
276 | } | |
09246732 CW |
277 | static inline void intel_ring_advance(struct intel_ring_buffer *ring) |
278 | { | |
279 | ring->tail &= ring->size - 1; | |
280 | } | |
281 | void __intel_ring_advance(struct intel_ring_buffer *ring); | |
282 | ||
3e960501 | 283 | int __must_check intel_ring_idle(struct intel_ring_buffer *ring); |
f7e98ad4 | 284 | void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno); |
a7b9761d CW |
285 | int intel_ring_flush_all_caches(struct intel_ring_buffer *ring); |
286 | int intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring); | |
8187a2b7 | 287 | |
5c1143bb XH |
288 | int intel_init_render_ring_buffer(struct drm_device *dev); |
289 | int intel_init_bsd_ring_buffer(struct drm_device *dev); | |
549f7365 | 290 | int intel_init_blt_ring_buffer(struct drm_device *dev); |
9a8a2213 | 291 | int intel_init_vebox_ring_buffer(struct drm_device *dev); |
8187a2b7 | 292 | |
78501eac CW |
293 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring); |
294 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring); | |
79f321b7 | 295 | |
a71d8d94 CW |
296 | static inline u32 intel_ring_get_tail(struct intel_ring_buffer *ring) |
297 | { | |
298 | return ring->tail; | |
299 | } | |
300 | ||
9d773091 CW |
301 | static inline u32 intel_ring_get_seqno(struct intel_ring_buffer *ring) |
302 | { | |
1823521d CW |
303 | BUG_ON(ring->outstanding_lazy_seqno == 0); |
304 | return ring->outstanding_lazy_seqno; | |
9d773091 CW |
305 | } |
306 | ||
db53a302 CW |
307 | static inline void i915_trace_irq_get(struct intel_ring_buffer *ring, u32 seqno) |
308 | { | |
309 | if (ring->trace_irq_seqno == 0 && ring->irq_get(ring)) | |
310 | ring->trace_irq_seqno = seqno; | |
311 | } | |
312 | ||
e8616b6c CW |
313 | /* DRI warts */ |
314 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size); | |
315 | ||
8187a2b7 | 316 | #endif /* _INTEL_RINGBUFFER_H_ */ |