]>
Commit | Line | Data |
---|---|---|
b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
8187a2b7 ZN |
2 | #ifndef _INTEL_RINGBUFFER_H_ |
3 | #define _INTEL_RINGBUFFER_H_ | |
4 | ||
44e895a8 | 5 | #include <linux/hashtable.h> |
06fbca71 | 6 | #include "i915_gem_batch_pool.h" |
dcff85c8 | 7 | #include "i915_gem_request.h" |
73cb9701 | 8 | #include "i915_gem_timeline.h" |
f97fbf96 | 9 | #include "i915_selftest.h" |
44e895a8 | 10 | |
f636edb2 CW |
11 | struct drm_printer; |
12 | ||
44e895a8 BV |
13 | #define I915_CMD_HASH_ORDER 9 |
14 | ||
4712274c OM |
15 | /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, |
16 | * but keeps the logic simple. Indeed, the whole purpose of this macro is just | |
17 | * to give some inclination as to some of the magic values used in the various | |
18 | * workarounds! | |
19 | */ | |
20 | #define CACHELINE_BYTES 64 | |
17ee950d | 21 | #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t)) |
4712274c | 22 | |
57e88531 CW |
23 | struct intel_hw_status_page { |
24 | struct i915_vma *vma; | |
25 | u32 *page_addr; | |
26 | u32 ggtt_offset; | |
8187a2b7 ZN |
27 | }; |
28 | ||
bbdc070a DG |
29 | #define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base)) |
30 | #define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val) | |
cae5852d | 31 | |
bbdc070a DG |
32 | #define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base)) |
33 | #define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val) | |
cae5852d | 34 | |
bbdc070a DG |
35 | #define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base)) |
36 | #define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val) | |
cae5852d | 37 | |
bbdc070a DG |
38 | #define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base)) |
39 | #define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val) | |
cae5852d | 40 | |
bbdc070a DG |
41 | #define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base)) |
42 | #define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val) | |
870e86dd | 43 | |
bbdc070a DG |
44 | #define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base)) |
45 | #define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val) | |
e9fea574 | 46 | |
3e78998a BW |
47 | /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to |
48 | * do the writes, and that must have qw aligned offsets, simply pretend it's 8b. | |
49 | */ | |
8c12672e CW |
50 | #define gen8_semaphore_seqno_size sizeof(uint64_t) |
51 | #define GEN8_SEMAPHORE_OFFSET(__from, __to) \ | |
52 | (((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size) | |
3e78998a | 53 | #define GEN8_SIGNAL_OFFSET(__ring, to) \ |
51d545d0 | 54 | (dev_priv->semaphore->node.start + \ |
8c12672e | 55 | GEN8_SEMAPHORE_OFFSET((__ring)->id, (to))) |
3e78998a | 56 | #define GEN8_WAIT_OFFSET(__ring, from) \ |
51d545d0 | 57 | (dev_priv->semaphore->node.start + \ |
8c12672e | 58 | GEN8_SEMAPHORE_OFFSET(from, (__ring)->id)) |
3e78998a | 59 | |
7e37f889 | 60 | enum intel_engine_hangcheck_action { |
3fe3b030 MK |
61 | ENGINE_IDLE = 0, |
62 | ENGINE_WAIT, | |
63 | ENGINE_ACTIVE_SEQNO, | |
64 | ENGINE_ACTIVE_HEAD, | |
65 | ENGINE_ACTIVE_SUBUNITS, | |
66 | ENGINE_WAIT_KICK, | |
67 | ENGINE_DEAD, | |
f2f4d82f | 68 | }; |
ad8beaea | 69 | |
3fe3b030 MK |
70 | static inline const char * |
71 | hangcheck_action_to_str(const enum intel_engine_hangcheck_action a) | |
72 | { | |
73 | switch (a) { | |
74 | case ENGINE_IDLE: | |
75 | return "idle"; | |
76 | case ENGINE_WAIT: | |
77 | return "wait"; | |
78 | case ENGINE_ACTIVE_SEQNO: | |
79 | return "active seqno"; | |
80 | case ENGINE_ACTIVE_HEAD: | |
81 | return "active head"; | |
82 | case ENGINE_ACTIVE_SUBUNITS: | |
83 | return "active subunits"; | |
84 | case ENGINE_WAIT_KICK: | |
85 | return "wait kick"; | |
86 | case ENGINE_DEAD: | |
87 | return "dead"; | |
88 | } | |
89 | ||
90 | return "unknown"; | |
91 | } | |
b6b0fac0 | 92 | |
f9e61372 BW |
93 | #define I915_MAX_SLICES 3 |
94 | #define I915_MAX_SUBSLICES 3 | |
95 | ||
96 | #define instdone_slice_mask(dev_priv__) \ | |
97 | (INTEL_GEN(dev_priv__) == 7 ? \ | |
98 | 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask) | |
99 | ||
100 | #define instdone_subslice_mask(dev_priv__) \ | |
101 | (INTEL_GEN(dev_priv__) == 7 ? \ | |
102 | 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask) | |
103 | ||
104 | #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \ | |
105 | for ((slice__) = 0, (subslice__) = 0; \ | |
106 | (slice__) < I915_MAX_SLICES; \ | |
107 | (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \ | |
108 | (slice__) += ((subslice__) == 0)) \ | |
109 | for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \ | |
110 | (BIT(subslice__) & instdone_subslice_mask(dev_priv__))) | |
111 | ||
d636951e BW |
112 | struct intel_instdone { |
113 | u32 instdone; | |
114 | /* The following exist only in the RCS engine */ | |
115 | u32 slice_common; | |
f9e61372 BW |
116 | u32 sampler[I915_MAX_SLICES][I915_MAX_SUBSLICES]; |
117 | u32 row[I915_MAX_SLICES][I915_MAX_SUBSLICES]; | |
d636951e BW |
118 | }; |
119 | ||
7e37f889 | 120 | struct intel_engine_hangcheck { |
50877445 | 121 | u64 acthd; |
92cab734 | 122 | u32 seqno; |
7e37f889 | 123 | enum intel_engine_hangcheck_action action; |
3fe3b030 | 124 | unsigned long action_timestamp; |
4be17381 | 125 | int deadlock; |
d636951e | 126 | struct intel_instdone instdone; |
c64992e0 | 127 | struct drm_i915_gem_request *active_request; |
3fe3b030 | 128 | bool stalled; |
92cab734 MK |
129 | }; |
130 | ||
7e37f889 | 131 | struct intel_ring { |
0eb973d3 | 132 | struct i915_vma *vma; |
57e88531 | 133 | void *vaddr; |
8ee14975 | 134 | |
675d9ad7 CW |
135 | struct list_head request_list; |
136 | ||
8ee14975 OM |
137 | u32 head; |
138 | u32 tail; | |
e6ba9992 | 139 | u32 emit; |
eca56a35 | 140 | |
605d5b32 CW |
141 | u32 space; |
142 | u32 size; | |
143 | u32 effective_size; | |
8ee14975 OM |
144 | }; |
145 | ||
e2efd130 | 146 | struct i915_gem_context; |
361b027b | 147 | struct drm_i915_reg_table; |
21076372 | 148 | |
17ee950d AS |
149 | /* |
150 | * we use a single page to load ctx workarounds so all of these | |
151 | * values are referred in terms of dwords | |
152 | * | |
153 | * struct i915_wa_ctx_bb: | |
154 | * offset: specifies batch starting position, also helpful in case | |
155 | * if we want to have multiple batches at different offsets based on | |
156 | * some criteria. It is not a requirement at the moment but provides | |
157 | * an option for future use. | |
158 | * size: size of the batch in DWORDS | |
159 | */ | |
48bb74e4 | 160 | struct i915_ctx_workarounds { |
17ee950d AS |
161 | struct i915_wa_ctx_bb { |
162 | u32 offset; | |
163 | u32 size; | |
164 | } indirect_ctx, per_ctx; | |
48bb74e4 | 165 | struct i915_vma *vma; |
17ee950d AS |
166 | }; |
167 | ||
c81d4613 | 168 | struct drm_i915_gem_request; |
4e50f082 | 169 | struct intel_render_state; |
c81d4613 | 170 | |
237ae7c7 MW |
171 | /* |
172 | * Engine IDs definitions. | |
173 | * Keep instances of the same type engine together. | |
174 | */ | |
175 | enum intel_engine_id { | |
176 | RCS = 0, | |
177 | BCS, | |
178 | VCS, | |
179 | VCS2, | |
180 | #define _VCS(n) (VCS + (n)) | |
181 | VECS | |
182 | }; | |
183 | ||
6c067579 CW |
184 | struct i915_priolist { |
185 | struct rb_node node; | |
186 | struct list_head requests; | |
187 | int priority; | |
188 | }; | |
189 | ||
b620e870 MK |
190 | /** |
191 | * struct intel_engine_execlists - execlist submission queue and port state | |
192 | * | |
193 | * The struct intel_engine_execlists represents the combined logical state of | |
194 | * driver and the hardware state for execlist mode of submission. | |
195 | */ | |
196 | struct intel_engine_execlists { | |
197 | /** | |
198 | * @irq_tasklet: softirq tasklet for bottom handler | |
199 | */ | |
200 | struct tasklet_struct irq_tasklet; | |
201 | ||
202 | /** | |
203 | * @default_priolist: priority list for I915_PRIORITY_NORMAL | |
204 | */ | |
205 | struct i915_priolist default_priolist; | |
206 | ||
207 | /** | |
208 | * @no_priolist: priority lists disabled | |
209 | */ | |
210 | bool no_priolist; | |
211 | ||
212 | /** | |
213 | * @port: execlist port states | |
214 | * | |
215 | * For each hardware ELSP (ExecList Submission Port) we keep | |
216 | * track of the last request and the number of times we submitted | |
217 | * that port to hw. We then count the number of times the hw reports | |
218 | * a context completion or preemption. As only one context can | |
219 | * be active on hw, we limit resubmission of context to port[0]. This | |
220 | * is called Lite Restore, of the context. | |
221 | */ | |
222 | struct execlist_port { | |
223 | /** | |
224 | * @request_count: combined request and submission count | |
225 | */ | |
226 | struct drm_i915_gem_request *request_count; | |
227 | #define EXECLIST_COUNT_BITS 2 | |
228 | #define port_request(p) ptr_mask_bits((p)->request_count, EXECLIST_COUNT_BITS) | |
229 | #define port_count(p) ptr_unmask_bits((p)->request_count, EXECLIST_COUNT_BITS) | |
230 | #define port_pack(rq, count) ptr_pack_bits(rq, count, EXECLIST_COUNT_BITS) | |
231 | #define port_unpack(p, count) ptr_unpack_bits((p)->request_count, count, EXECLIST_COUNT_BITS) | |
232 | #define port_set(p, packed) ((p)->request_count = (packed)) | |
233 | #define port_isset(p) ((p)->request_count) | |
7a62cc61 | 234 | #define port_index(p, execlists) ((p) - (execlists)->port) |
b620e870 MK |
235 | |
236 | /** | |
237 | * @context_id: context ID for port | |
238 | */ | |
239 | GEM_DEBUG_DECL(u32 context_id); | |
76e70087 MK |
240 | |
241 | #define EXECLIST_MAX_PORTS 2 | |
242 | } port[EXECLIST_MAX_PORTS]; | |
243 | ||
beecec90 | 244 | /** |
5d266692 CW |
245 | * @active: is the HW active? We consider the HW as active after |
246 | * submitting any context for execution and until we have seen the | |
247 | * last context completion event. After that, we do not expect any | |
248 | * more events until we submit, and so can park the HW. | |
249 | * | |
250 | * As we have a small number of different sources from which we feed | |
251 | * the HW, we track the state of each inside a single bitfield. | |
beecec90 | 252 | */ |
5d266692 CW |
253 | unsigned int active; |
254 | #define EXECLISTS_ACTIVE_USER 0 | |
255 | #define EXECLISTS_ACTIVE_PREEMPT 1 | |
beecec90 | 256 | |
76e70087 MK |
257 | /** |
258 | * @port_mask: number of execlist ports - 1 | |
259 | */ | |
260 | unsigned int port_mask; | |
b620e870 MK |
261 | |
262 | /** | |
263 | * @queue: queue of requests, in priority lists | |
264 | */ | |
265 | struct rb_root queue; | |
266 | ||
267 | /** | |
268 | * @first: leftmost level in priority @queue | |
269 | */ | |
270 | struct rb_node *first; | |
271 | ||
272 | /** | |
273 | * @fw_domains: forcewake domains for irq tasklet | |
274 | */ | |
275 | unsigned int fw_domains; | |
276 | ||
277 | /** | |
278 | * @csb_head: context status buffer head | |
279 | */ | |
280 | unsigned int csb_head; | |
281 | ||
282 | /** | |
283 | * @csb_use_mmio: access csb through mmio, instead of hwsp | |
284 | */ | |
285 | bool csb_use_mmio; | |
286 | }; | |
287 | ||
6e516148 OM |
288 | #define INTEL_ENGINE_CS_MAX_NAME 8 |
289 | ||
c033666a CW |
290 | struct intel_engine_cs { |
291 | struct drm_i915_private *i915; | |
6e516148 | 292 | char name[INTEL_ENGINE_CS_MAX_NAME]; |
237ae7c7 | 293 | enum intel_engine_id id; |
1d39f281 | 294 | unsigned int uabi_id; |
237ae7c7 | 295 | unsigned int hw_id; |
63ffbcda | 296 | unsigned int guc_id; |
0908180b DCS |
297 | |
298 | u8 class; | |
299 | u8 instance; | |
63ffbcda JL |
300 | u32 context_size; |
301 | u32 mmio_base; | |
c2c7f240 | 302 | unsigned int irq_shift; |
63ffbcda | 303 | |
7e37f889 | 304 | struct intel_ring *buffer; |
73cb9701 | 305 | struct intel_timeline *timeline; |
8187a2b7 | 306 | |
4e50f082 CW |
307 | struct intel_render_state *render_state; |
308 | ||
2246bea6 | 309 | atomic_t irq_count; |
538b257d CW |
310 | unsigned long irq_posted; |
311 | #define ENGINE_IRQ_BREADCRUMB 0 | |
f747026c | 312 | #define ENGINE_IRQ_EXECLIST 1 |
538b257d | 313 | |
688e6c72 CW |
314 | /* Rather than have every client wait upon all user interrupts, |
315 | * with the herd waking after every interrupt and each doing the | |
316 | * heavyweight seqno dance, we delegate the task (of being the | |
317 | * bottom-half of the user interrupt) to the first client. After | |
318 | * every interrupt, we wake up one client, who does the heavyweight | |
319 | * coherent seqno read and either goes back to sleep (if incomplete), | |
320 | * or wakes up all the completed clients in parallel, before then | |
321 | * transferring the bottom-half status to the next client in the queue. | |
322 | * | |
323 | * Compared to walking the entire list of waiters in a single dedicated | |
324 | * bottom-half, we reduce the latency of the first waiter by avoiding | |
325 | * a context switch, but incur additional coherent seqno reads when | |
326 | * following the chain of request breadcrumbs. Since it is most likely | |
327 | * that we have a single client waiting on each seqno, then reducing | |
328 | * the overhead of waking that client is much preferred. | |
329 | */ | |
330 | struct intel_breadcrumbs { | |
61d3dc70 CW |
331 | spinlock_t irq_lock; /* protects irq_*; irqsafe */ |
332 | struct intel_wait *irq_wait; /* oldest waiter by retirement */ | |
333 | ||
334 | spinlock_t rb_lock; /* protects the rb and wraps irq_lock */ | |
688e6c72 | 335 | struct rb_root waiters; /* sorted by retirement, priority */ |
c81d4613 | 336 | struct rb_root signals; /* sorted by retirement */ |
c81d4613 | 337 | struct task_struct *signaler; /* used for fence signalling */ |
cced5e2f | 338 | struct drm_i915_gem_request __rcu *first_signal; |
688e6c72 | 339 | struct timer_list fake_irq; /* used after a missed interrupt */ |
83348ba8 CW |
340 | struct timer_list hangcheck; /* detect missed interrupts */ |
341 | ||
2246bea6 | 342 | unsigned int hangcheck_interrupts; |
aca34b6e | 343 | |
67b807a8 | 344 | bool irq_armed : 1; |
aca34b6e | 345 | bool irq_enabled : 1; |
f97fbf96 | 346 | I915_SELFTEST_DECLARE(bool mock : 1); |
688e6c72 CW |
347 | } breadcrumbs; |
348 | ||
06fbca71 CW |
349 | /* |
350 | * A pool of objects to use as shadow copies of client batch buffers | |
351 | * when the command parser is enabled. Prevents the client from | |
352 | * modifying the batch contents after software parsing. | |
353 | */ | |
354 | struct i915_gem_batch_pool batch_pool; | |
355 | ||
8187a2b7 | 356 | struct intel_hw_status_page status_page; |
17ee950d | 357 | struct i915_ctx_workarounds wa_ctx; |
56c0f1a7 | 358 | struct i915_vma *scratch; |
8187a2b7 | 359 | |
61ff75ac CW |
360 | u32 irq_keep_mask; /* always keep these interrupts */ |
361 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ | |
38a0f2db DG |
362 | void (*irq_enable)(struct intel_engine_cs *engine); |
363 | void (*irq_disable)(struct intel_engine_cs *engine); | |
8187a2b7 | 364 | |
38a0f2db | 365 | int (*init_hw)(struct intel_engine_cs *engine); |
821ed7df CW |
366 | void (*reset_hw)(struct intel_engine_cs *engine, |
367 | struct drm_i915_gem_request *req); | |
8187a2b7 | 368 | |
ff44ad51 CW |
369 | void (*set_default_submission)(struct intel_engine_cs *engine); |
370 | ||
266a240b CW |
371 | struct intel_ring *(*context_pin)(struct intel_engine_cs *engine, |
372 | struct i915_gem_context *ctx); | |
e8a9c58f CW |
373 | void (*context_unpin)(struct intel_engine_cs *engine, |
374 | struct i915_gem_context *ctx); | |
f73e7399 | 375 | int (*request_alloc)(struct drm_i915_gem_request *req); |
8753181e | 376 | int (*init_context)(struct drm_i915_gem_request *req); |
86d7f238 | 377 | |
ddd66c51 CW |
378 | int (*emit_flush)(struct drm_i915_gem_request *request, |
379 | u32 mode); | |
380 | #define EMIT_INVALIDATE BIT(0) | |
381 | #define EMIT_FLUSH BIT(1) | |
382 | #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH) | |
383 | int (*emit_bb_start)(struct drm_i915_gem_request *req, | |
384 | u64 offset, u32 length, | |
385 | unsigned int dispatch_flags); | |
386 | #define I915_DISPATCH_SECURE BIT(0) | |
387 | #define I915_DISPATCH_PINNED BIT(1) | |
388 | #define I915_DISPATCH_RS BIT(2) | |
caddfe71 | 389 | void (*emit_breadcrumb)(struct drm_i915_gem_request *req, |
73dec95e | 390 | u32 *cs); |
98f29e8d | 391 | int emit_breadcrumb_sz; |
5590af3e CW |
392 | |
393 | /* Pass the request to the hardware queue (e.g. directly into | |
394 | * the legacy ringbuffer or to the end of an execlist). | |
395 | * | |
396 | * This is called from an atomic context with irqs disabled; must | |
397 | * be irq safe. | |
398 | */ | |
ddd66c51 | 399 | void (*submit_request)(struct drm_i915_gem_request *req); |
5590af3e | 400 | |
0de9136d CW |
401 | /* Call when the priority on a request has changed and it and its |
402 | * dependencies may need rescheduling. Note the request itself may | |
403 | * not be ready to run! | |
404 | * | |
405 | * Called under the struct_mutex. | |
406 | */ | |
407 | void (*schedule)(struct drm_i915_gem_request *request, | |
408 | int priority); | |
409 | ||
27a5f61b CW |
410 | /* |
411 | * Cancel all requests on the hardware, or queued for execution. | |
412 | * This should only cancel the ready requests that have been | |
413 | * submitted to the engine (via the engine->submit_request callback). | |
414 | * This is called when marking the device as wedged. | |
415 | */ | |
416 | void (*cancel_requests)(struct intel_engine_cs *engine); | |
417 | ||
b2eadbc8 CW |
418 | /* Some chipsets are not quite as coherent as advertised and need |
419 | * an expensive kick to force a true read of the up-to-date seqno. | |
420 | * However, the up-to-date seqno is not always required and the last | |
421 | * seen value is good enough. Note that the seqno will always be | |
422 | * monotonic, even if not coherent. | |
423 | */ | |
38a0f2db | 424 | void (*irq_seqno_barrier)(struct intel_engine_cs *engine); |
38a0f2db | 425 | void (*cleanup)(struct intel_engine_cs *engine); |
ebc348b2 | 426 | |
3e78998a BW |
427 | /* GEN8 signal/wait table - never trust comments! |
428 | * signal to signal to signal to signal to signal to | |
429 | * RCS VCS BCS VECS VCS2 | |
430 | * -------------------------------------------------------------------- | |
431 | * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) | | |
432 | * |------------------------------------------------------------------- | |
433 | * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) | | |
434 | * |------------------------------------------------------------------- | |
435 | * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) | | |
436 | * |------------------------------------------------------------------- | |
437 | * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) | | |
438 | * |------------------------------------------------------------------- | |
439 | * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) | | |
440 | * |------------------------------------------------------------------- | |
441 | * | |
442 | * Generalization: | |
443 | * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id) | |
444 | * ie. transpose of g(x, y) | |
445 | * | |
446 | * sync from sync from sync from sync from sync from | |
447 | * RCS VCS BCS VECS VCS2 | |
448 | * -------------------------------------------------------------------- | |
449 | * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) | | |
450 | * |------------------------------------------------------------------- | |
451 | * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) | | |
452 | * |------------------------------------------------------------------- | |
453 | * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) | | |
454 | * |------------------------------------------------------------------- | |
455 | * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) | | |
456 | * |------------------------------------------------------------------- | |
457 | * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) | | |
458 | * |------------------------------------------------------------------- | |
459 | * | |
460 | * Generalization: | |
461 | * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id) | |
462 | * ie. transpose of f(x, y) | |
463 | */ | |
ebc348b2 | 464 | struct { |
3e78998a | 465 | union { |
318f89ca TU |
466 | #define GEN6_SEMAPHORE_LAST VECS_HW |
467 | #define GEN6_NUM_SEMAPHORES (GEN6_SEMAPHORE_LAST + 1) | |
468 | #define GEN6_SEMAPHORES_MASK GENMASK(GEN6_SEMAPHORE_LAST, 0) | |
3e78998a BW |
469 | struct { |
470 | /* our mbox written by others */ | |
318f89ca | 471 | u32 wait[GEN6_NUM_SEMAPHORES]; |
3e78998a | 472 | /* mboxes this ring signals to */ |
318f89ca | 473 | i915_reg_t signal[GEN6_NUM_SEMAPHORES]; |
3e78998a | 474 | } mbox; |
666796da | 475 | u64 signal_ggtt[I915_NUM_ENGINES]; |
3e78998a | 476 | }; |
78325f2d BW |
477 | |
478 | /* AKA wait() */ | |
ad7bdb2b CW |
479 | int (*sync_to)(struct drm_i915_gem_request *req, |
480 | struct drm_i915_gem_request *signal); | |
73dec95e | 481 | u32 *(*signal)(struct drm_i915_gem_request *req, u32 *cs); |
ebc348b2 | 482 | } semaphore; |
ad776f8b | 483 | |
b620e870 | 484 | struct intel_engine_execlists execlists; |
4da46e1e | 485 | |
e8a9c58f CW |
486 | /* Contexts are pinned whilst they are active on the GPU. The last |
487 | * context executed remains active whilst the GPU is idle - the | |
488 | * switch away and write to the context object only occurs on the | |
489 | * next execution. Contexts are only unpinned on retirement of the | |
490 | * following request ensuring that we can always write to the object | |
491 | * on the context switch even after idling. Across suspend, we switch | |
492 | * to the kernel context and trash it as the save may not happen | |
493 | * before the hardware is powered down. | |
494 | */ | |
495 | struct i915_gem_context *last_retired_context; | |
496 | ||
497 | /* We track the current MI_SET_CONTEXT in order to eliminate | |
498 | * redudant context switches. This presumes that requests are not | |
499 | * reordered! Or when they are the tracking is updated along with | |
500 | * the emission of individual requests into the legacy command | |
501 | * stream (ring). | |
502 | */ | |
503 | struct i915_gem_context *legacy_active_context; | |
40521054 | 504 | |
3fc03069 CD |
505 | /* status_notifier: list of callbacks for context-switch changes */ |
506 | struct atomic_notifier_head context_status_notifier; | |
507 | ||
7e37f889 | 508 | struct intel_engine_hangcheck hangcheck; |
92cab734 | 509 | |
44e895a8 BV |
510 | bool needs_cmd_parser; |
511 | ||
351e3db2 | 512 | /* |
44e895a8 | 513 | * Table of commands the command parser needs to know about |
33a051a5 | 514 | * for this engine. |
351e3db2 | 515 | */ |
44e895a8 | 516 | DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER); |
351e3db2 BV |
517 | |
518 | /* | |
519 | * Table of registers allowed in commands that read/write registers. | |
520 | */ | |
361b027b JJ |
521 | const struct drm_i915_reg_table *reg_tables; |
522 | int reg_table_count; | |
351e3db2 BV |
523 | |
524 | /* | |
525 | * Returns the bitmask for the length field of the specified command. | |
526 | * Return 0 for an unrecognized/invalid command. | |
527 | * | |
33a051a5 | 528 | * If the command parser finds an entry for a command in the engine's |
351e3db2 | 529 | * cmd_tables, it gets the command's length based on the table entry. |
33a051a5 CW |
530 | * If not, it calls this function to determine the per-engine length |
531 | * field encoding for the command (i.e. different opcode ranges use | |
532 | * certain bits to encode the command length in the header). | |
351e3db2 BV |
533 | */ |
534 | u32 (*get_cmd_length_mask)(u32 cmd_header); | |
8187a2b7 ZN |
535 | }; |
536 | ||
5d266692 CW |
537 | static inline void |
538 | execlists_set_active(struct intel_engine_execlists *execlists, | |
539 | unsigned int bit) | |
540 | { | |
541 | __set_bit(bit, (unsigned long *)&execlists->active); | |
542 | } | |
543 | ||
544 | static inline void | |
545 | execlists_clear_active(struct intel_engine_execlists *execlists, | |
546 | unsigned int bit) | |
547 | { | |
548 | __clear_bit(bit, (unsigned long *)&execlists->active); | |
549 | } | |
550 | ||
551 | static inline bool | |
552 | execlists_is_active(const struct intel_engine_execlists *execlists, | |
553 | unsigned int bit) | |
554 | { | |
555 | return test_bit(bit, (unsigned long *)&execlists->active); | |
556 | } | |
557 | ||
76e70087 MK |
558 | static inline unsigned int |
559 | execlists_num_ports(const struct intel_engine_execlists * const execlists) | |
560 | { | |
561 | return execlists->port_mask + 1; | |
562 | } | |
563 | ||
7a62cc61 MK |
564 | static inline void |
565 | execlists_port_complete(struct intel_engine_execlists * const execlists, | |
566 | struct execlist_port * const port) | |
567 | { | |
76e70087 | 568 | const unsigned int m = execlists->port_mask; |
7a62cc61 MK |
569 | |
570 | GEM_BUG_ON(port_index(port, execlists) != 0); | |
5d266692 | 571 | GEM_BUG_ON(!execlists_is_active(execlists, EXECLISTS_ACTIVE_USER)); |
7a62cc61 | 572 | |
76e70087 MK |
573 | memmove(port, port + 1, m * sizeof(struct execlist_port)); |
574 | memset(port + m, 0, sizeof(struct execlist_port)); | |
7a62cc61 MK |
575 | } |
576 | ||
59ce1310 | 577 | static inline unsigned int |
67d97da3 | 578 | intel_engine_flag(const struct intel_engine_cs *engine) |
96154f2f | 579 | { |
59ce1310 | 580 | return BIT(engine->id); |
96154f2f DV |
581 | } |
582 | ||
8187a2b7 | 583 | static inline u32 |
5dd8e50c | 584 | intel_read_status_page(struct intel_engine_cs *engine, int reg) |
8187a2b7 | 585 | { |
4225d0f2 | 586 | /* Ensure that the compiler doesn't optimize away the load. */ |
5dd8e50c | 587 | return READ_ONCE(engine->status_page.page_addr[reg]); |
8187a2b7 ZN |
588 | } |
589 | ||
b70ec5bf | 590 | static inline void |
9a29dd85 | 591 | intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) |
b70ec5bf | 592 | { |
9a29dd85 CW |
593 | /* Writing into the status page should be done sparingly. Since |
594 | * we do when we are uncertain of the device state, we take a bit | |
595 | * of extra paranoia to try and ensure that the HWS takes the value | |
596 | * we give and that it doesn't end up trapped inside the CPU! | |
597 | */ | |
598 | if (static_cpu_has(X86_FEATURE_CLFLUSH)) { | |
599 | mb(); | |
600 | clflush(&engine->status_page.page_addr[reg]); | |
601 | engine->status_page.page_addr[reg] = value; | |
602 | clflush(&engine->status_page.page_addr[reg]); | |
603 | mb(); | |
604 | } else { | |
605 | WRITE_ONCE(engine->status_page.page_addr[reg], value); | |
606 | } | |
b70ec5bf MK |
607 | } |
608 | ||
e2828914 | 609 | /* |
311bd68e CW |
610 | * Reads a dword out of the status page, which is written to from the command |
611 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
612 | * MI_STORE_DATA_IMM. | |
613 | * | |
614 | * The following dwords have a reserved meaning: | |
615 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. | |
616 | * 0x04: ring 0 head pointer | |
617 | * 0x05: ring 1 head pointer (915-class) | |
618 | * 0x06: ring 2 head pointer (915-class) | |
619 | * 0x10-0x1b: Context status DWords (GM45) | |
620 | * 0x1f: Last written status offset. (GM45) | |
b07da53c | 621 | * 0x20-0x2f: Reserved (Gen6+) |
311bd68e | 622 | * |
b07da53c | 623 | * The area from dword 0x30 to 0x3ff is available for driver usage. |
311bd68e | 624 | */ |
b07da53c | 625 | #define I915_GEM_HWS_INDEX 0x30 |
7c17d377 | 626 | #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
b07da53c | 627 | #define I915_GEM_HWS_SCRATCH_INDEX 0x40 |
9a289771 | 628 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
311bd68e | 629 | |
6d2cb5aa | 630 | #define I915_HWS_CSB_BUF0_INDEX 0x10 |
767a983a CW |
631 | #define I915_HWS_CSB_WRITE_INDEX 0x1f |
632 | #define CNL_HWS_CSB_WRITE_INDEX 0x2f | |
6d2cb5aa | 633 | |
7e37f889 CW |
634 | struct intel_ring * |
635 | intel_engine_create_ring(struct intel_engine_cs *engine, int size); | |
d822bb18 CW |
636 | int intel_ring_pin(struct intel_ring *ring, |
637 | struct drm_i915_private *i915, | |
638 | unsigned int offset_bias); | |
e6ba9992 | 639 | void intel_ring_reset(struct intel_ring *ring, u32 tail); |
95aebcb2 | 640 | unsigned int intel_ring_update_space(struct intel_ring *ring); |
aad29fbb | 641 | void intel_ring_unpin(struct intel_ring *ring); |
7e37f889 | 642 | void intel_ring_free(struct intel_ring *ring); |
84c2377f | 643 | |
7e37f889 CW |
644 | void intel_engine_stop(struct intel_engine_cs *engine); |
645 | void intel_engine_cleanup(struct intel_engine_cs *engine); | |
96f298aa | 646 | |
821ed7df CW |
647 | void intel_legacy_submission_resume(struct drm_i915_private *dev_priv); |
648 | ||
bba09b12 | 649 | int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req); |
406ea8d2 | 650 | |
5e5655c3 CW |
651 | u32 __must_check *intel_ring_begin(struct drm_i915_gem_request *req, |
652 | unsigned int n); | |
406ea8d2 | 653 | |
73dec95e TU |
654 | static inline void |
655 | intel_ring_advance(struct drm_i915_gem_request *req, u32 *cs) | |
09246732 | 656 | { |
8f942018 CW |
657 | /* Dummy function. |
658 | * | |
659 | * This serves as a placeholder in the code so that the reader | |
660 | * can compare against the preceding intel_ring_begin() and | |
661 | * check that the number of dwords emitted matches the space | |
662 | * reserved for the command packet (i.e. the value passed to | |
663 | * intel_ring_begin()). | |
c5efa1ad | 664 | */ |
e6ba9992 | 665 | GEM_BUG_ON((req->ring->vaddr + req->ring->emit) != cs); |
8f942018 CW |
666 | } |
667 | ||
73dec95e | 668 | static inline u32 |
450362d3 CW |
669 | intel_ring_wrap(const struct intel_ring *ring, u32 pos) |
670 | { | |
671 | return pos & (ring->size - 1); | |
672 | } | |
673 | ||
674 | static inline u32 | |
675 | intel_ring_offset(const struct drm_i915_gem_request *req, void *addr) | |
8f942018 CW |
676 | { |
677 | /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */ | |
73dec95e TU |
678 | u32 offset = addr - req->ring->vaddr; |
679 | GEM_BUG_ON(offset > req->ring->size); | |
450362d3 | 680 | return intel_ring_wrap(req->ring, offset); |
09246732 | 681 | } |
406ea8d2 | 682 | |
ed1501d4 CW |
683 | static inline void |
684 | assert_ring_tail_valid(const struct intel_ring *ring, unsigned int tail) | |
685 | { | |
686 | /* We could combine these into a single tail operation, but keeping | |
687 | * them as seperate tests will help identify the cause should one | |
688 | * ever fire. | |
689 | */ | |
690 | GEM_BUG_ON(!IS_ALIGNED(tail, 8)); | |
691 | GEM_BUG_ON(tail >= ring->size); | |
605d5b32 CW |
692 | |
693 | /* | |
694 | * "Ring Buffer Use" | |
695 | * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 | |
696 | * Gen3 BSpec "1c Memory Interface Functions" / 2.3.4.5 | |
697 | * Gen4+ BSpec "1c Memory Interface and Command Stream" / 5.3.4.5 | |
698 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the | |
699 | * same cacheline, the Head Pointer must not be greater than the Tail | |
700 | * Pointer." | |
701 | * | |
702 | * We use ring->head as the last known location of the actual RING_HEAD, | |
703 | * it may have advanced but in the worst case it is equally the same | |
704 | * as ring->head and so we should never program RING_TAIL to advance | |
705 | * into the same cacheline as ring->head. | |
706 | */ | |
707 | #define cacheline(a) round_down(a, CACHELINE_BYTES) | |
708 | GEM_BUG_ON(cacheline(tail) == cacheline(ring->head) && | |
709 | tail < ring->head); | |
710 | #undef cacheline | |
ed1501d4 CW |
711 | } |
712 | ||
e6ba9992 CW |
713 | static inline unsigned int |
714 | intel_ring_set_tail(struct intel_ring *ring, unsigned int tail) | |
715 | { | |
716 | /* Whilst writes to the tail are strictly order, there is no | |
717 | * serialisation between readers and the writers. The tail may be | |
718 | * read by i915_gem_request_retire() just as it is being updated | |
719 | * by execlists, as although the breadcrumb is complete, the context | |
720 | * switch hasn't been seen. | |
721 | */ | |
722 | assert_ring_tail_valid(ring, tail); | |
723 | ring->tail = tail; | |
724 | return tail; | |
725 | } | |
09246732 | 726 | |
73cb9701 | 727 | void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno); |
8187a2b7 | 728 | |
019bf277 TU |
729 | void intel_engine_setup_common(struct intel_engine_cs *engine); |
730 | int intel_engine_init_common(struct intel_engine_cs *engine); | |
adc320c4 | 731 | int intel_engine_create_scratch(struct intel_engine_cs *engine, int size); |
96a945aa | 732 | void intel_engine_cleanup_common(struct intel_engine_cs *engine); |
019bf277 | 733 | |
8b3e2d36 TU |
734 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine); |
735 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine); | |
8b3e2d36 TU |
736 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine); |
737 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine); | |
8187a2b7 | 738 | |
7e37f889 | 739 | u64 intel_engine_get_active_head(struct intel_engine_cs *engine); |
1b36595f CW |
740 | u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine); |
741 | ||
1b7744e7 CW |
742 | static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine) |
743 | { | |
744 | return intel_read_status_page(engine, I915_GEM_HWS_INDEX); | |
745 | } | |
79f321b7 | 746 | |
cb399eab CW |
747 | static inline u32 intel_engine_last_submit(struct intel_engine_cs *engine) |
748 | { | |
749 | /* We are only peeking at the tail of the submit queue (and not the | |
750 | * queue itself) in order to gain a hint as to the current active | |
751 | * state of the engine. Callers are not expected to be taking | |
752 | * engine->timeline->lock, nor are they expected to be concerned | |
753 | * wtih serialising this hint with anything, so document it as | |
754 | * a hint and nothing more. | |
755 | */ | |
9b6586ae | 756 | return READ_ONCE(engine->timeline->seqno); |
cb399eab CW |
757 | } |
758 | ||
0bc40be8 | 759 | int init_workarounds_ring(struct intel_engine_cs *engine); |
4ac9659e | 760 | int intel_ring_workarounds_emit(struct drm_i915_gem_request *req); |
771b9a53 | 761 | |
0e704476 CW |
762 | void intel_engine_get_instdone(struct intel_engine_cs *engine, |
763 | struct intel_instdone *instdone); | |
764 | ||
29b1b415 JH |
765 | /* |
766 | * Arbitrary size for largest possible 'add request' sequence. The code paths | |
767 | * are complex and variable. Empirical measurement shows that the worst case | |
596e5efc CW |
768 | * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However, |
769 | * we need to allocate double the largest single packet within that emission | |
770 | * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW). | |
29b1b415 | 771 | */ |
596e5efc | 772 | #define MIN_SPACE_FOR_ADD_REQUEST 336 |
29b1b415 | 773 | |
a58c01aa CW |
774 | static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine) |
775 | { | |
57e88531 | 776 | return engine->status_page.ggtt_offset + I915_GEM_HWS_INDEX_ADDR; |
a58c01aa CW |
777 | } |
778 | ||
688e6c72 | 779 | /* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */ |
688e6c72 CW |
780 | int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine); |
781 | ||
56299fb7 CW |
782 | static inline void intel_wait_init(struct intel_wait *wait, |
783 | struct drm_i915_gem_request *rq) | |
688e6c72 CW |
784 | { |
785 | wait->tsk = current; | |
56299fb7 | 786 | wait->request = rq; |
754c9fd5 CW |
787 | } |
788 | ||
789 | static inline void intel_wait_init_for_seqno(struct intel_wait *wait, u32 seqno) | |
790 | { | |
791 | wait->tsk = current; | |
792 | wait->seqno = seqno; | |
793 | } | |
794 | ||
795 | static inline bool intel_wait_has_seqno(const struct intel_wait *wait) | |
796 | { | |
797 | return wait->seqno; | |
798 | } | |
799 | ||
800 | static inline bool | |
801 | intel_wait_update_seqno(struct intel_wait *wait, u32 seqno) | |
802 | { | |
688e6c72 | 803 | wait->seqno = seqno; |
754c9fd5 CW |
804 | return intel_wait_has_seqno(wait); |
805 | } | |
806 | ||
807 | static inline bool | |
808 | intel_wait_update_request(struct intel_wait *wait, | |
809 | const struct drm_i915_gem_request *rq) | |
810 | { | |
811 | return intel_wait_update_seqno(wait, i915_gem_request_global_seqno(rq)); | |
812 | } | |
813 | ||
814 | static inline bool | |
815 | intel_wait_check_seqno(const struct intel_wait *wait, u32 seqno) | |
816 | { | |
817 | return wait->seqno == seqno; | |
818 | } | |
819 | ||
820 | static inline bool | |
821 | intel_wait_check_request(const struct intel_wait *wait, | |
822 | const struct drm_i915_gem_request *rq) | |
823 | { | |
824 | return intel_wait_check_seqno(wait, i915_gem_request_global_seqno(rq)); | |
688e6c72 CW |
825 | } |
826 | ||
827 | static inline bool intel_wait_complete(const struct intel_wait *wait) | |
828 | { | |
829 | return RB_EMPTY_NODE(&wait->node); | |
830 | } | |
831 | ||
832 | bool intel_engine_add_wait(struct intel_engine_cs *engine, | |
833 | struct intel_wait *wait); | |
834 | void intel_engine_remove_wait(struct intel_engine_cs *engine, | |
835 | struct intel_wait *wait); | |
f7b02a52 CW |
836 | void intel_engine_enable_signaling(struct drm_i915_gem_request *request, |
837 | bool wakeup); | |
9eb143bb | 838 | void intel_engine_cancel_signaling(struct drm_i915_gem_request *request); |
688e6c72 | 839 | |
dbd6ef29 | 840 | static inline bool intel_engine_has_waiter(const struct intel_engine_cs *engine) |
688e6c72 | 841 | { |
61d3dc70 | 842 | return READ_ONCE(engine->breadcrumbs.irq_wait); |
688e6c72 CW |
843 | } |
844 | ||
8d769ea7 CW |
845 | unsigned int intel_engine_wakeup(struct intel_engine_cs *engine); |
846 | #define ENGINE_WAKEUP_WAITER BIT(0) | |
67b807a8 CW |
847 | #define ENGINE_WAKEUP_ASLEEP BIT(1) |
848 | ||
849 | void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine); | |
850 | void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine); | |
688e6c72 | 851 | |
ad07dfcd | 852 | void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine); |
688e6c72 | 853 | void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine); |
9b6586ae | 854 | bool intel_breadcrumbs_busy(struct intel_engine_cs *engine); |
688e6c72 | 855 | |
9f235dfa TU |
856 | static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset) |
857 | { | |
858 | memset(batch, 0, 6 * sizeof(u32)); | |
859 | ||
860 | batch[0] = GFX_OP_PIPE_CONTROL(6); | |
861 | batch[1] = flags; | |
862 | batch[2] = offset; | |
863 | ||
864 | return batch + 6; | |
865 | } | |
866 | ||
5400367a | 867 | bool intel_engine_is_idle(struct intel_engine_cs *engine); |
05425249 | 868 | bool intel_engines_are_idle(struct drm_i915_private *dev_priv); |
5400367a | 869 | |
6c067579 | 870 | void intel_engines_mark_idle(struct drm_i915_private *i915); |
ff44ad51 CW |
871 | void intel_engines_reset_default_submission(struct drm_i915_private *i915); |
872 | ||
90cad095 | 873 | bool intel_engine_can_store_dword(struct intel_engine_cs *engine); |
f2f5c061 | 874 | |
f636edb2 | 875 | void intel_engine_dump(struct intel_engine_cs *engine, struct drm_printer *p); |
f2f5c061 | 876 | |
8187a2b7 | 877 | #endif /* _INTEL_RINGBUFFER_H_ */ |