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8187a2b7 ZN |
1 | #ifndef _INTEL_RINGBUFFER_H_ |
2 | #define _INTEL_RINGBUFFER_H_ | |
3 | ||
44e895a8 | 4 | #include <linux/hashtable.h> |
06fbca71 | 5 | #include "i915_gem_batch_pool.h" |
dcff85c8 | 6 | #include "i915_gem_request.h" |
73cb9701 | 7 | #include "i915_gem_timeline.h" |
f97fbf96 | 8 | #include "i915_selftest.h" |
44e895a8 BV |
9 | |
10 | #define I915_CMD_HASH_ORDER 9 | |
11 | ||
4712274c OM |
12 | /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill, |
13 | * but keeps the logic simple. Indeed, the whole purpose of this macro is just | |
14 | * to give some inclination as to some of the magic values used in the various | |
15 | * workarounds! | |
16 | */ | |
17 | #define CACHELINE_BYTES 64 | |
17ee950d | 18 | #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t)) |
4712274c | 19 | |
57e88531 CW |
20 | struct intel_hw_status_page { |
21 | struct i915_vma *vma; | |
22 | u32 *page_addr; | |
23 | u32 ggtt_offset; | |
8187a2b7 ZN |
24 | }; |
25 | ||
bbdc070a DG |
26 | #define I915_READ_TAIL(engine) I915_READ(RING_TAIL((engine)->mmio_base)) |
27 | #define I915_WRITE_TAIL(engine, val) I915_WRITE(RING_TAIL((engine)->mmio_base), val) | |
cae5852d | 28 | |
bbdc070a DG |
29 | #define I915_READ_START(engine) I915_READ(RING_START((engine)->mmio_base)) |
30 | #define I915_WRITE_START(engine, val) I915_WRITE(RING_START((engine)->mmio_base), val) | |
cae5852d | 31 | |
bbdc070a DG |
32 | #define I915_READ_HEAD(engine) I915_READ(RING_HEAD((engine)->mmio_base)) |
33 | #define I915_WRITE_HEAD(engine, val) I915_WRITE(RING_HEAD((engine)->mmio_base), val) | |
cae5852d | 34 | |
bbdc070a DG |
35 | #define I915_READ_CTL(engine) I915_READ(RING_CTL((engine)->mmio_base)) |
36 | #define I915_WRITE_CTL(engine, val) I915_WRITE(RING_CTL((engine)->mmio_base), val) | |
cae5852d | 37 | |
bbdc070a DG |
38 | #define I915_READ_IMR(engine) I915_READ(RING_IMR((engine)->mmio_base)) |
39 | #define I915_WRITE_IMR(engine, val) I915_WRITE(RING_IMR((engine)->mmio_base), val) | |
870e86dd | 40 | |
bbdc070a DG |
41 | #define I915_READ_MODE(engine) I915_READ(RING_MI_MODE((engine)->mmio_base)) |
42 | #define I915_WRITE_MODE(engine, val) I915_WRITE(RING_MI_MODE((engine)->mmio_base), val) | |
e9fea574 | 43 | |
3e78998a BW |
44 | /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to |
45 | * do the writes, and that must have qw aligned offsets, simply pretend it's 8b. | |
46 | */ | |
8c12672e CW |
47 | #define gen8_semaphore_seqno_size sizeof(uint64_t) |
48 | #define GEN8_SEMAPHORE_OFFSET(__from, __to) \ | |
49 | (((__from) * I915_NUM_ENGINES + (__to)) * gen8_semaphore_seqno_size) | |
3e78998a | 50 | #define GEN8_SIGNAL_OFFSET(__ring, to) \ |
51d545d0 | 51 | (dev_priv->semaphore->node.start + \ |
8c12672e | 52 | GEN8_SEMAPHORE_OFFSET((__ring)->id, (to))) |
3e78998a | 53 | #define GEN8_WAIT_OFFSET(__ring, from) \ |
51d545d0 | 54 | (dev_priv->semaphore->node.start + \ |
8c12672e | 55 | GEN8_SEMAPHORE_OFFSET(from, (__ring)->id)) |
3e78998a | 56 | |
7e37f889 | 57 | enum intel_engine_hangcheck_action { |
3fe3b030 MK |
58 | ENGINE_IDLE = 0, |
59 | ENGINE_WAIT, | |
60 | ENGINE_ACTIVE_SEQNO, | |
61 | ENGINE_ACTIVE_HEAD, | |
62 | ENGINE_ACTIVE_SUBUNITS, | |
63 | ENGINE_WAIT_KICK, | |
64 | ENGINE_DEAD, | |
f2f4d82f | 65 | }; |
ad8beaea | 66 | |
3fe3b030 MK |
67 | static inline const char * |
68 | hangcheck_action_to_str(const enum intel_engine_hangcheck_action a) | |
69 | { | |
70 | switch (a) { | |
71 | case ENGINE_IDLE: | |
72 | return "idle"; | |
73 | case ENGINE_WAIT: | |
74 | return "wait"; | |
75 | case ENGINE_ACTIVE_SEQNO: | |
76 | return "active seqno"; | |
77 | case ENGINE_ACTIVE_HEAD: | |
78 | return "active head"; | |
79 | case ENGINE_ACTIVE_SUBUNITS: | |
80 | return "active subunits"; | |
81 | case ENGINE_WAIT_KICK: | |
82 | return "wait kick"; | |
83 | case ENGINE_DEAD: | |
84 | return "dead"; | |
85 | } | |
86 | ||
87 | return "unknown"; | |
88 | } | |
b6b0fac0 | 89 | |
f9e61372 BW |
90 | #define I915_MAX_SLICES 3 |
91 | #define I915_MAX_SUBSLICES 3 | |
92 | ||
93 | #define instdone_slice_mask(dev_priv__) \ | |
94 | (INTEL_GEN(dev_priv__) == 7 ? \ | |
95 | 1 : INTEL_INFO(dev_priv__)->sseu.slice_mask) | |
96 | ||
97 | #define instdone_subslice_mask(dev_priv__) \ | |
98 | (INTEL_GEN(dev_priv__) == 7 ? \ | |
99 | 1 : INTEL_INFO(dev_priv__)->sseu.subslice_mask) | |
100 | ||
101 | #define for_each_instdone_slice_subslice(dev_priv__, slice__, subslice__) \ | |
102 | for ((slice__) = 0, (subslice__) = 0; \ | |
103 | (slice__) < I915_MAX_SLICES; \ | |
104 | (subslice__) = ((subslice__) + 1) < I915_MAX_SUBSLICES ? (subslice__) + 1 : 0, \ | |
105 | (slice__) += ((subslice__) == 0)) \ | |
106 | for_each_if((BIT(slice__) & instdone_slice_mask(dev_priv__)) && \ | |
107 | (BIT(subslice__) & instdone_subslice_mask(dev_priv__))) | |
108 | ||
d636951e BW |
109 | struct intel_instdone { |
110 | u32 instdone; | |
111 | /* The following exist only in the RCS engine */ | |
112 | u32 slice_common; | |
f9e61372 BW |
113 | u32 sampler[I915_MAX_SLICES][I915_MAX_SUBSLICES]; |
114 | u32 row[I915_MAX_SLICES][I915_MAX_SUBSLICES]; | |
d636951e BW |
115 | }; |
116 | ||
7e37f889 | 117 | struct intel_engine_hangcheck { |
50877445 | 118 | u64 acthd; |
92cab734 | 119 | u32 seqno; |
7e37f889 | 120 | enum intel_engine_hangcheck_action action; |
3fe3b030 | 121 | unsigned long action_timestamp; |
4be17381 | 122 | int deadlock; |
d636951e | 123 | struct intel_instdone instdone; |
3fe3b030 | 124 | bool stalled; |
92cab734 MK |
125 | }; |
126 | ||
7e37f889 | 127 | struct intel_ring { |
0eb973d3 | 128 | struct i915_vma *vma; |
57e88531 | 129 | void *vaddr; |
8ee14975 | 130 | |
675d9ad7 CW |
131 | struct list_head request_list; |
132 | ||
8ee14975 OM |
133 | u32 head; |
134 | u32 tail; | |
e6ba9992 | 135 | u32 emit; |
eca56a35 | 136 | |
605d5b32 CW |
137 | u32 space; |
138 | u32 size; | |
139 | u32 effective_size; | |
8ee14975 OM |
140 | }; |
141 | ||
e2efd130 | 142 | struct i915_gem_context; |
361b027b | 143 | struct drm_i915_reg_table; |
21076372 | 144 | |
17ee950d AS |
145 | /* |
146 | * we use a single page to load ctx workarounds so all of these | |
147 | * values are referred in terms of dwords | |
148 | * | |
149 | * struct i915_wa_ctx_bb: | |
150 | * offset: specifies batch starting position, also helpful in case | |
151 | * if we want to have multiple batches at different offsets based on | |
152 | * some criteria. It is not a requirement at the moment but provides | |
153 | * an option for future use. | |
154 | * size: size of the batch in DWORDS | |
155 | */ | |
48bb74e4 | 156 | struct i915_ctx_workarounds { |
17ee950d AS |
157 | struct i915_wa_ctx_bb { |
158 | u32 offset; | |
159 | u32 size; | |
160 | } indirect_ctx, per_ctx; | |
48bb74e4 | 161 | struct i915_vma *vma; |
17ee950d AS |
162 | }; |
163 | ||
c81d4613 | 164 | struct drm_i915_gem_request; |
4e50f082 | 165 | struct intel_render_state; |
c81d4613 | 166 | |
237ae7c7 MW |
167 | /* |
168 | * Engine IDs definitions. | |
169 | * Keep instances of the same type engine together. | |
170 | */ | |
171 | enum intel_engine_id { | |
172 | RCS = 0, | |
173 | BCS, | |
174 | VCS, | |
175 | VCS2, | |
176 | #define _VCS(n) (VCS + (n)) | |
177 | VECS | |
178 | }; | |
179 | ||
6c067579 CW |
180 | struct i915_priolist { |
181 | struct rb_node node; | |
182 | struct list_head requests; | |
183 | int priority; | |
184 | }; | |
185 | ||
6e516148 OM |
186 | #define INTEL_ENGINE_CS_MAX_NAME 8 |
187 | ||
c033666a CW |
188 | struct intel_engine_cs { |
189 | struct drm_i915_private *i915; | |
6e516148 | 190 | char name[INTEL_ENGINE_CS_MAX_NAME]; |
237ae7c7 | 191 | enum intel_engine_id id; |
1d39f281 | 192 | unsigned int uabi_id; |
237ae7c7 | 193 | unsigned int hw_id; |
63ffbcda | 194 | unsigned int guc_id; |
0908180b DCS |
195 | |
196 | u8 class; | |
197 | u8 instance; | |
63ffbcda JL |
198 | u32 context_size; |
199 | u32 mmio_base; | |
c2c7f240 | 200 | unsigned int irq_shift; |
63ffbcda | 201 | |
7e37f889 | 202 | struct intel_ring *buffer; |
73cb9701 | 203 | struct intel_timeline *timeline; |
8187a2b7 | 204 | |
4e50f082 CW |
205 | struct intel_render_state *render_state; |
206 | ||
2246bea6 | 207 | atomic_t irq_count; |
538b257d CW |
208 | unsigned long irq_posted; |
209 | #define ENGINE_IRQ_BREADCRUMB 0 | |
f747026c | 210 | #define ENGINE_IRQ_EXECLIST 1 |
538b257d | 211 | |
688e6c72 CW |
212 | /* Rather than have every client wait upon all user interrupts, |
213 | * with the herd waking after every interrupt and each doing the | |
214 | * heavyweight seqno dance, we delegate the task (of being the | |
215 | * bottom-half of the user interrupt) to the first client. After | |
216 | * every interrupt, we wake up one client, who does the heavyweight | |
217 | * coherent seqno read and either goes back to sleep (if incomplete), | |
218 | * or wakes up all the completed clients in parallel, before then | |
219 | * transferring the bottom-half status to the next client in the queue. | |
220 | * | |
221 | * Compared to walking the entire list of waiters in a single dedicated | |
222 | * bottom-half, we reduce the latency of the first waiter by avoiding | |
223 | * a context switch, but incur additional coherent seqno reads when | |
224 | * following the chain of request breadcrumbs. Since it is most likely | |
225 | * that we have a single client waiting on each seqno, then reducing | |
226 | * the overhead of waking that client is much preferred. | |
227 | */ | |
228 | struct intel_breadcrumbs { | |
61d3dc70 CW |
229 | spinlock_t irq_lock; /* protects irq_*; irqsafe */ |
230 | struct intel_wait *irq_wait; /* oldest waiter by retirement */ | |
231 | ||
232 | spinlock_t rb_lock; /* protects the rb and wraps irq_lock */ | |
688e6c72 | 233 | struct rb_root waiters; /* sorted by retirement, priority */ |
c81d4613 | 234 | struct rb_root signals; /* sorted by retirement */ |
c81d4613 | 235 | struct task_struct *signaler; /* used for fence signalling */ |
cced5e2f | 236 | struct drm_i915_gem_request __rcu *first_signal; |
688e6c72 | 237 | struct timer_list fake_irq; /* used after a missed interrupt */ |
83348ba8 CW |
238 | struct timer_list hangcheck; /* detect missed interrupts */ |
239 | ||
2246bea6 | 240 | unsigned int hangcheck_interrupts; |
aca34b6e | 241 | |
67b807a8 | 242 | bool irq_armed : 1; |
aca34b6e | 243 | bool irq_enabled : 1; |
f97fbf96 | 244 | I915_SELFTEST_DECLARE(bool mock : 1); |
688e6c72 CW |
245 | } breadcrumbs; |
246 | ||
06fbca71 CW |
247 | /* |
248 | * A pool of objects to use as shadow copies of client batch buffers | |
249 | * when the command parser is enabled. Prevents the client from | |
250 | * modifying the batch contents after software parsing. | |
251 | */ | |
252 | struct i915_gem_batch_pool batch_pool; | |
253 | ||
8187a2b7 | 254 | struct intel_hw_status_page status_page; |
17ee950d | 255 | struct i915_ctx_workarounds wa_ctx; |
56c0f1a7 | 256 | struct i915_vma *scratch; |
8187a2b7 | 257 | |
61ff75ac CW |
258 | u32 irq_keep_mask; /* always keep these interrupts */ |
259 | u32 irq_enable_mask; /* bitmask to enable ring interrupt */ | |
38a0f2db DG |
260 | void (*irq_enable)(struct intel_engine_cs *engine); |
261 | void (*irq_disable)(struct intel_engine_cs *engine); | |
8187a2b7 | 262 | |
38a0f2db | 263 | int (*init_hw)(struct intel_engine_cs *engine); |
821ed7df CW |
264 | void (*reset_hw)(struct intel_engine_cs *engine, |
265 | struct drm_i915_gem_request *req); | |
8187a2b7 | 266 | |
ff44ad51 CW |
267 | void (*set_default_submission)(struct intel_engine_cs *engine); |
268 | ||
266a240b CW |
269 | struct intel_ring *(*context_pin)(struct intel_engine_cs *engine, |
270 | struct i915_gem_context *ctx); | |
e8a9c58f CW |
271 | void (*context_unpin)(struct intel_engine_cs *engine, |
272 | struct i915_gem_context *ctx); | |
f73e7399 | 273 | int (*request_alloc)(struct drm_i915_gem_request *req); |
8753181e | 274 | int (*init_context)(struct drm_i915_gem_request *req); |
86d7f238 | 275 | |
ddd66c51 CW |
276 | int (*emit_flush)(struct drm_i915_gem_request *request, |
277 | u32 mode); | |
278 | #define EMIT_INVALIDATE BIT(0) | |
279 | #define EMIT_FLUSH BIT(1) | |
280 | #define EMIT_BARRIER (EMIT_INVALIDATE | EMIT_FLUSH) | |
281 | int (*emit_bb_start)(struct drm_i915_gem_request *req, | |
282 | u64 offset, u32 length, | |
283 | unsigned int dispatch_flags); | |
284 | #define I915_DISPATCH_SECURE BIT(0) | |
285 | #define I915_DISPATCH_PINNED BIT(1) | |
286 | #define I915_DISPATCH_RS BIT(2) | |
caddfe71 | 287 | void (*emit_breadcrumb)(struct drm_i915_gem_request *req, |
73dec95e | 288 | u32 *cs); |
98f29e8d | 289 | int emit_breadcrumb_sz; |
5590af3e CW |
290 | |
291 | /* Pass the request to the hardware queue (e.g. directly into | |
292 | * the legacy ringbuffer or to the end of an execlist). | |
293 | * | |
294 | * This is called from an atomic context with irqs disabled; must | |
295 | * be irq safe. | |
296 | */ | |
ddd66c51 | 297 | void (*submit_request)(struct drm_i915_gem_request *req); |
5590af3e | 298 | |
0de9136d CW |
299 | /* Call when the priority on a request has changed and it and its |
300 | * dependencies may need rescheduling. Note the request itself may | |
301 | * not be ready to run! | |
302 | * | |
303 | * Called under the struct_mutex. | |
304 | */ | |
305 | void (*schedule)(struct drm_i915_gem_request *request, | |
306 | int priority); | |
307 | ||
b2eadbc8 CW |
308 | /* Some chipsets are not quite as coherent as advertised and need |
309 | * an expensive kick to force a true read of the up-to-date seqno. | |
310 | * However, the up-to-date seqno is not always required and the last | |
311 | * seen value is good enough. Note that the seqno will always be | |
312 | * monotonic, even if not coherent. | |
313 | */ | |
38a0f2db | 314 | void (*irq_seqno_barrier)(struct intel_engine_cs *engine); |
38a0f2db | 315 | void (*cleanup)(struct intel_engine_cs *engine); |
ebc348b2 | 316 | |
3e78998a BW |
317 | /* GEN8 signal/wait table - never trust comments! |
318 | * signal to signal to signal to signal to signal to | |
319 | * RCS VCS BCS VECS VCS2 | |
320 | * -------------------------------------------------------------------- | |
321 | * RCS | NOP (0x00) | VCS (0x08) | BCS (0x10) | VECS (0x18) | VCS2 (0x20) | | |
322 | * |------------------------------------------------------------------- | |
323 | * VCS | RCS (0x28) | NOP (0x30) | BCS (0x38) | VECS (0x40) | VCS2 (0x48) | | |
324 | * |------------------------------------------------------------------- | |
325 | * BCS | RCS (0x50) | VCS (0x58) | NOP (0x60) | VECS (0x68) | VCS2 (0x70) | | |
326 | * |------------------------------------------------------------------- | |
327 | * VECS | RCS (0x78) | VCS (0x80) | BCS (0x88) | NOP (0x90) | VCS2 (0x98) | | |
328 | * |------------------------------------------------------------------- | |
329 | * VCS2 | RCS (0xa0) | VCS (0xa8) | BCS (0xb0) | VECS (0xb8) | NOP (0xc0) | | |
330 | * |------------------------------------------------------------------- | |
331 | * | |
332 | * Generalization: | |
333 | * f(x, y) := (x->id * NUM_RINGS * seqno_size) + (seqno_size * y->id) | |
334 | * ie. transpose of g(x, y) | |
335 | * | |
336 | * sync from sync from sync from sync from sync from | |
337 | * RCS VCS BCS VECS VCS2 | |
338 | * -------------------------------------------------------------------- | |
339 | * RCS | NOP (0x00) | VCS (0x28) | BCS (0x50) | VECS (0x78) | VCS2 (0xa0) | | |
340 | * |------------------------------------------------------------------- | |
341 | * VCS | RCS (0x08) | NOP (0x30) | BCS (0x58) | VECS (0x80) | VCS2 (0xa8) | | |
342 | * |------------------------------------------------------------------- | |
343 | * BCS | RCS (0x10) | VCS (0x38) | NOP (0x60) | VECS (0x88) | VCS2 (0xb0) | | |
344 | * |------------------------------------------------------------------- | |
345 | * VECS | RCS (0x18) | VCS (0x40) | BCS (0x68) | NOP (0x90) | VCS2 (0xb8) | | |
346 | * |------------------------------------------------------------------- | |
347 | * VCS2 | RCS (0x20) | VCS (0x48) | BCS (0x70) | VECS (0x98) | NOP (0xc0) | | |
348 | * |------------------------------------------------------------------- | |
349 | * | |
350 | * Generalization: | |
351 | * g(x, y) := (y->id * NUM_RINGS * seqno_size) + (seqno_size * x->id) | |
352 | * ie. transpose of f(x, y) | |
353 | */ | |
ebc348b2 | 354 | struct { |
3e78998a | 355 | union { |
318f89ca TU |
356 | #define GEN6_SEMAPHORE_LAST VECS_HW |
357 | #define GEN6_NUM_SEMAPHORES (GEN6_SEMAPHORE_LAST + 1) | |
358 | #define GEN6_SEMAPHORES_MASK GENMASK(GEN6_SEMAPHORE_LAST, 0) | |
3e78998a BW |
359 | struct { |
360 | /* our mbox written by others */ | |
318f89ca | 361 | u32 wait[GEN6_NUM_SEMAPHORES]; |
3e78998a | 362 | /* mboxes this ring signals to */ |
318f89ca | 363 | i915_reg_t signal[GEN6_NUM_SEMAPHORES]; |
3e78998a | 364 | } mbox; |
666796da | 365 | u64 signal_ggtt[I915_NUM_ENGINES]; |
3e78998a | 366 | }; |
78325f2d BW |
367 | |
368 | /* AKA wait() */ | |
ad7bdb2b CW |
369 | int (*sync_to)(struct drm_i915_gem_request *req, |
370 | struct drm_i915_gem_request *signal); | |
73dec95e | 371 | u32 *(*signal)(struct drm_i915_gem_request *req, u32 *cs); |
ebc348b2 | 372 | } semaphore; |
ad776f8b | 373 | |
4da46e1e | 374 | /* Execlists */ |
27af5eea | 375 | struct tasklet_struct irq_tasklet; |
6c067579 CW |
376 | struct i915_priolist default_priolist; |
377 | bool no_priolist; | |
70c2a24d | 378 | struct execlist_port { |
77f0d0e9 CW |
379 | struct drm_i915_gem_request *request_count; |
380 | #define EXECLIST_COUNT_BITS 2 | |
381 | #define port_request(p) ptr_mask_bits((p)->request_count, EXECLIST_COUNT_BITS) | |
382 | #define port_count(p) ptr_unmask_bits((p)->request_count, EXECLIST_COUNT_BITS) | |
383 | #define port_pack(rq, count) ptr_pack_bits(rq, count, EXECLIST_COUNT_BITS) | |
384 | #define port_unpack(p, count) ptr_unpack_bits((p)->request_count, count, EXECLIST_COUNT_BITS) | |
385 | #define port_set(p, packed) ((p)->request_count = (packed)) | |
386 | #define port_isset(p) ((p)->request_count) | |
387 | #define port_index(p, e) ((p) - (e)->execlist_port) | |
ae9a043b | 388 | GEM_DEBUG_DECL(u32 context_id); |
70c2a24d | 389 | } execlist_port[2]; |
20311bd3 CW |
390 | struct rb_root execlist_queue; |
391 | struct rb_node *execlist_first; | |
3756685a | 392 | unsigned int fw_domains; |
4da46e1e | 393 | |
e8a9c58f CW |
394 | /* Contexts are pinned whilst they are active on the GPU. The last |
395 | * context executed remains active whilst the GPU is idle - the | |
396 | * switch away and write to the context object only occurs on the | |
397 | * next execution. Contexts are only unpinned on retirement of the | |
398 | * following request ensuring that we can always write to the object | |
399 | * on the context switch even after idling. Across suspend, we switch | |
400 | * to the kernel context and trash it as the save may not happen | |
401 | * before the hardware is powered down. | |
402 | */ | |
403 | struct i915_gem_context *last_retired_context; | |
404 | ||
405 | /* We track the current MI_SET_CONTEXT in order to eliminate | |
406 | * redudant context switches. This presumes that requests are not | |
407 | * reordered! Or when they are the tracking is updated along with | |
408 | * the emission of individual requests into the legacy command | |
409 | * stream (ring). | |
410 | */ | |
411 | struct i915_gem_context *legacy_active_context; | |
40521054 | 412 | |
3fc03069 CD |
413 | /* status_notifier: list of callbacks for context-switch changes */ |
414 | struct atomic_notifier_head context_status_notifier; | |
415 | ||
7e37f889 | 416 | struct intel_engine_hangcheck hangcheck; |
92cab734 | 417 | |
44e895a8 BV |
418 | bool needs_cmd_parser; |
419 | ||
351e3db2 | 420 | /* |
44e895a8 | 421 | * Table of commands the command parser needs to know about |
33a051a5 | 422 | * for this engine. |
351e3db2 | 423 | */ |
44e895a8 | 424 | DECLARE_HASHTABLE(cmd_hash, I915_CMD_HASH_ORDER); |
351e3db2 BV |
425 | |
426 | /* | |
427 | * Table of registers allowed in commands that read/write registers. | |
428 | */ | |
361b027b JJ |
429 | const struct drm_i915_reg_table *reg_tables; |
430 | int reg_table_count; | |
351e3db2 BV |
431 | |
432 | /* | |
433 | * Returns the bitmask for the length field of the specified command. | |
434 | * Return 0 for an unrecognized/invalid command. | |
435 | * | |
33a051a5 | 436 | * If the command parser finds an entry for a command in the engine's |
351e3db2 | 437 | * cmd_tables, it gets the command's length based on the table entry. |
33a051a5 CW |
438 | * If not, it calls this function to determine the per-engine length |
439 | * field encoding for the command (i.e. different opcode ranges use | |
440 | * certain bits to encode the command length in the header). | |
351e3db2 BV |
441 | */ |
442 | u32 (*get_cmd_length_mask)(u32 cmd_header); | |
8187a2b7 ZN |
443 | }; |
444 | ||
59ce1310 | 445 | static inline unsigned int |
67d97da3 | 446 | intel_engine_flag(const struct intel_engine_cs *engine) |
96154f2f | 447 | { |
59ce1310 | 448 | return BIT(engine->id); |
96154f2f DV |
449 | } |
450 | ||
8187a2b7 | 451 | static inline u32 |
5dd8e50c | 452 | intel_read_status_page(struct intel_engine_cs *engine, int reg) |
8187a2b7 | 453 | { |
4225d0f2 | 454 | /* Ensure that the compiler doesn't optimize away the load. */ |
5dd8e50c | 455 | return READ_ONCE(engine->status_page.page_addr[reg]); |
8187a2b7 ZN |
456 | } |
457 | ||
b70ec5bf | 458 | static inline void |
9a29dd85 | 459 | intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value) |
b70ec5bf | 460 | { |
9a29dd85 CW |
461 | /* Writing into the status page should be done sparingly. Since |
462 | * we do when we are uncertain of the device state, we take a bit | |
463 | * of extra paranoia to try and ensure that the HWS takes the value | |
464 | * we give and that it doesn't end up trapped inside the CPU! | |
465 | */ | |
466 | if (static_cpu_has(X86_FEATURE_CLFLUSH)) { | |
467 | mb(); | |
468 | clflush(&engine->status_page.page_addr[reg]); | |
469 | engine->status_page.page_addr[reg] = value; | |
470 | clflush(&engine->status_page.page_addr[reg]); | |
471 | mb(); | |
472 | } else { | |
473 | WRITE_ONCE(engine->status_page.page_addr[reg], value); | |
474 | } | |
b70ec5bf MK |
475 | } |
476 | ||
e2828914 | 477 | /* |
311bd68e CW |
478 | * Reads a dword out of the status page, which is written to from the command |
479 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
480 | * MI_STORE_DATA_IMM. | |
481 | * | |
482 | * The following dwords have a reserved meaning: | |
483 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. | |
484 | * 0x04: ring 0 head pointer | |
485 | * 0x05: ring 1 head pointer (915-class) | |
486 | * 0x06: ring 2 head pointer (915-class) | |
487 | * 0x10-0x1b: Context status DWords (GM45) | |
488 | * 0x1f: Last written status offset. (GM45) | |
b07da53c | 489 | * 0x20-0x2f: Reserved (Gen6+) |
311bd68e | 490 | * |
b07da53c | 491 | * The area from dword 0x30 to 0x3ff is available for driver usage. |
311bd68e | 492 | */ |
b07da53c | 493 | #define I915_GEM_HWS_INDEX 0x30 |
7c17d377 | 494 | #define I915_GEM_HWS_INDEX_ADDR (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
b07da53c | 495 | #define I915_GEM_HWS_SCRATCH_INDEX 0x40 |
9a289771 | 496 | #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) |
311bd68e | 497 | |
7e37f889 CW |
498 | struct intel_ring * |
499 | intel_engine_create_ring(struct intel_engine_cs *engine, int size); | |
d822bb18 CW |
500 | int intel_ring_pin(struct intel_ring *ring, |
501 | struct drm_i915_private *i915, | |
502 | unsigned int offset_bias); | |
e6ba9992 | 503 | void intel_ring_reset(struct intel_ring *ring, u32 tail); |
95aebcb2 | 504 | unsigned int intel_ring_update_space(struct intel_ring *ring); |
aad29fbb | 505 | void intel_ring_unpin(struct intel_ring *ring); |
7e37f889 | 506 | void intel_ring_free(struct intel_ring *ring); |
84c2377f | 507 | |
7e37f889 CW |
508 | void intel_engine_stop(struct intel_engine_cs *engine); |
509 | void intel_engine_cleanup(struct intel_engine_cs *engine); | |
96f298aa | 510 | |
821ed7df CW |
511 | void intel_legacy_submission_resume(struct drm_i915_private *dev_priv); |
512 | ||
bba09b12 | 513 | int __must_check intel_ring_cacheline_align(struct drm_i915_gem_request *req); |
406ea8d2 | 514 | |
5e5655c3 CW |
515 | u32 __must_check *intel_ring_begin(struct drm_i915_gem_request *req, |
516 | unsigned int n); | |
406ea8d2 | 517 | |
73dec95e TU |
518 | static inline void |
519 | intel_ring_advance(struct drm_i915_gem_request *req, u32 *cs) | |
09246732 | 520 | { |
8f942018 CW |
521 | /* Dummy function. |
522 | * | |
523 | * This serves as a placeholder in the code so that the reader | |
524 | * can compare against the preceding intel_ring_begin() and | |
525 | * check that the number of dwords emitted matches the space | |
526 | * reserved for the command packet (i.e. the value passed to | |
527 | * intel_ring_begin()). | |
c5efa1ad | 528 | */ |
e6ba9992 | 529 | GEM_BUG_ON((req->ring->vaddr + req->ring->emit) != cs); |
8f942018 CW |
530 | } |
531 | ||
73dec95e | 532 | static inline u32 |
450362d3 CW |
533 | intel_ring_wrap(const struct intel_ring *ring, u32 pos) |
534 | { | |
535 | return pos & (ring->size - 1); | |
536 | } | |
537 | ||
538 | static inline u32 | |
539 | intel_ring_offset(const struct drm_i915_gem_request *req, void *addr) | |
8f942018 CW |
540 | { |
541 | /* Don't write ring->size (equivalent to 0) as that hangs some GPUs. */ | |
73dec95e TU |
542 | u32 offset = addr - req->ring->vaddr; |
543 | GEM_BUG_ON(offset > req->ring->size); | |
450362d3 | 544 | return intel_ring_wrap(req->ring, offset); |
09246732 | 545 | } |
406ea8d2 | 546 | |
ed1501d4 CW |
547 | static inline void |
548 | assert_ring_tail_valid(const struct intel_ring *ring, unsigned int tail) | |
549 | { | |
550 | /* We could combine these into a single tail operation, but keeping | |
551 | * them as seperate tests will help identify the cause should one | |
552 | * ever fire. | |
553 | */ | |
554 | GEM_BUG_ON(!IS_ALIGNED(tail, 8)); | |
555 | GEM_BUG_ON(tail >= ring->size); | |
605d5b32 CW |
556 | |
557 | /* | |
558 | * "Ring Buffer Use" | |
559 | * Gen2 BSpec "1. Programming Environment" / 1.4.4.6 | |
560 | * Gen3 BSpec "1c Memory Interface Functions" / 2.3.4.5 | |
561 | * Gen4+ BSpec "1c Memory Interface and Command Stream" / 5.3.4.5 | |
562 | * "If the Ring Buffer Head Pointer and the Tail Pointer are on the | |
563 | * same cacheline, the Head Pointer must not be greater than the Tail | |
564 | * Pointer." | |
565 | * | |
566 | * We use ring->head as the last known location of the actual RING_HEAD, | |
567 | * it may have advanced but in the worst case it is equally the same | |
568 | * as ring->head and so we should never program RING_TAIL to advance | |
569 | * into the same cacheline as ring->head. | |
570 | */ | |
571 | #define cacheline(a) round_down(a, CACHELINE_BYTES) | |
572 | GEM_BUG_ON(cacheline(tail) == cacheline(ring->head) && | |
573 | tail < ring->head); | |
574 | #undef cacheline | |
ed1501d4 CW |
575 | } |
576 | ||
e6ba9992 CW |
577 | static inline unsigned int |
578 | intel_ring_set_tail(struct intel_ring *ring, unsigned int tail) | |
579 | { | |
580 | /* Whilst writes to the tail are strictly order, there is no | |
581 | * serialisation between readers and the writers. The tail may be | |
582 | * read by i915_gem_request_retire() just as it is being updated | |
583 | * by execlists, as although the breadcrumb is complete, the context | |
584 | * switch hasn't been seen. | |
585 | */ | |
586 | assert_ring_tail_valid(ring, tail); | |
587 | ring->tail = tail; | |
588 | return tail; | |
589 | } | |
09246732 | 590 | |
73cb9701 | 591 | void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno); |
8187a2b7 | 592 | |
019bf277 TU |
593 | void intel_engine_setup_common(struct intel_engine_cs *engine); |
594 | int intel_engine_init_common(struct intel_engine_cs *engine); | |
adc320c4 | 595 | int intel_engine_create_scratch(struct intel_engine_cs *engine, int size); |
96a945aa | 596 | void intel_engine_cleanup_common(struct intel_engine_cs *engine); |
019bf277 | 597 | |
8b3e2d36 TU |
598 | int intel_init_render_ring_buffer(struct intel_engine_cs *engine); |
599 | int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine); | |
8b3e2d36 TU |
600 | int intel_init_blt_ring_buffer(struct intel_engine_cs *engine); |
601 | int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine); | |
8187a2b7 | 602 | |
7e37f889 | 603 | u64 intel_engine_get_active_head(struct intel_engine_cs *engine); |
1b36595f CW |
604 | u64 intel_engine_get_last_batch_head(struct intel_engine_cs *engine); |
605 | ||
1b7744e7 CW |
606 | static inline u32 intel_engine_get_seqno(struct intel_engine_cs *engine) |
607 | { | |
608 | return intel_read_status_page(engine, I915_GEM_HWS_INDEX); | |
609 | } | |
79f321b7 | 610 | |
cb399eab CW |
611 | static inline u32 intel_engine_last_submit(struct intel_engine_cs *engine) |
612 | { | |
613 | /* We are only peeking at the tail of the submit queue (and not the | |
614 | * queue itself) in order to gain a hint as to the current active | |
615 | * state of the engine. Callers are not expected to be taking | |
616 | * engine->timeline->lock, nor are they expected to be concerned | |
617 | * wtih serialising this hint with anything, so document it as | |
618 | * a hint and nothing more. | |
619 | */ | |
9b6586ae | 620 | return READ_ONCE(engine->timeline->seqno); |
cb399eab CW |
621 | } |
622 | ||
0bc40be8 | 623 | int init_workarounds_ring(struct intel_engine_cs *engine); |
4ac9659e | 624 | int intel_ring_workarounds_emit(struct drm_i915_gem_request *req); |
771b9a53 | 625 | |
0e704476 CW |
626 | void intel_engine_get_instdone(struct intel_engine_cs *engine, |
627 | struct intel_instdone *instdone); | |
628 | ||
29b1b415 JH |
629 | /* |
630 | * Arbitrary size for largest possible 'add request' sequence. The code paths | |
631 | * are complex and variable. Empirical measurement shows that the worst case | |
596e5efc CW |
632 | * is BDW at 192 bytes (6 + 6 + 36 dwords), then ILK at 136 bytes. However, |
633 | * we need to allocate double the largest single packet within that emission | |
634 | * to account for tail wraparound (so 6 + 6 + 72 dwords for BDW). | |
29b1b415 | 635 | */ |
596e5efc | 636 | #define MIN_SPACE_FOR_ADD_REQUEST 336 |
29b1b415 | 637 | |
a58c01aa CW |
638 | static inline u32 intel_hws_seqno_address(struct intel_engine_cs *engine) |
639 | { | |
57e88531 | 640 | return engine->status_page.ggtt_offset + I915_GEM_HWS_INDEX_ADDR; |
a58c01aa CW |
641 | } |
642 | ||
688e6c72 | 643 | /* intel_breadcrumbs.c -- user interrupt bottom-half for waiters */ |
688e6c72 CW |
644 | int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine); |
645 | ||
56299fb7 CW |
646 | static inline void intel_wait_init(struct intel_wait *wait, |
647 | struct drm_i915_gem_request *rq) | |
688e6c72 CW |
648 | { |
649 | wait->tsk = current; | |
56299fb7 | 650 | wait->request = rq; |
754c9fd5 CW |
651 | } |
652 | ||
653 | static inline void intel_wait_init_for_seqno(struct intel_wait *wait, u32 seqno) | |
654 | { | |
655 | wait->tsk = current; | |
656 | wait->seqno = seqno; | |
657 | } | |
658 | ||
659 | static inline bool intel_wait_has_seqno(const struct intel_wait *wait) | |
660 | { | |
661 | return wait->seqno; | |
662 | } | |
663 | ||
664 | static inline bool | |
665 | intel_wait_update_seqno(struct intel_wait *wait, u32 seqno) | |
666 | { | |
688e6c72 | 667 | wait->seqno = seqno; |
754c9fd5 CW |
668 | return intel_wait_has_seqno(wait); |
669 | } | |
670 | ||
671 | static inline bool | |
672 | intel_wait_update_request(struct intel_wait *wait, | |
673 | const struct drm_i915_gem_request *rq) | |
674 | { | |
675 | return intel_wait_update_seqno(wait, i915_gem_request_global_seqno(rq)); | |
676 | } | |
677 | ||
678 | static inline bool | |
679 | intel_wait_check_seqno(const struct intel_wait *wait, u32 seqno) | |
680 | { | |
681 | return wait->seqno == seqno; | |
682 | } | |
683 | ||
684 | static inline bool | |
685 | intel_wait_check_request(const struct intel_wait *wait, | |
686 | const struct drm_i915_gem_request *rq) | |
687 | { | |
688 | return intel_wait_check_seqno(wait, i915_gem_request_global_seqno(rq)); | |
688e6c72 CW |
689 | } |
690 | ||
691 | static inline bool intel_wait_complete(const struct intel_wait *wait) | |
692 | { | |
693 | return RB_EMPTY_NODE(&wait->node); | |
694 | } | |
695 | ||
696 | bool intel_engine_add_wait(struct intel_engine_cs *engine, | |
697 | struct intel_wait *wait); | |
698 | void intel_engine_remove_wait(struct intel_engine_cs *engine, | |
699 | struct intel_wait *wait); | |
f7b02a52 CW |
700 | void intel_engine_enable_signaling(struct drm_i915_gem_request *request, |
701 | bool wakeup); | |
9eb143bb | 702 | void intel_engine_cancel_signaling(struct drm_i915_gem_request *request); |
688e6c72 | 703 | |
dbd6ef29 | 704 | static inline bool intel_engine_has_waiter(const struct intel_engine_cs *engine) |
688e6c72 | 705 | { |
61d3dc70 | 706 | return READ_ONCE(engine->breadcrumbs.irq_wait); |
688e6c72 CW |
707 | } |
708 | ||
8d769ea7 CW |
709 | unsigned int intel_engine_wakeup(struct intel_engine_cs *engine); |
710 | #define ENGINE_WAKEUP_WAITER BIT(0) | |
67b807a8 CW |
711 | #define ENGINE_WAKEUP_ASLEEP BIT(1) |
712 | ||
713 | void __intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine); | |
714 | void intel_engine_disarm_breadcrumbs(struct intel_engine_cs *engine); | |
688e6c72 | 715 | |
ad07dfcd | 716 | void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine); |
688e6c72 | 717 | void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine); |
9b6586ae | 718 | bool intel_breadcrumbs_busy(struct intel_engine_cs *engine); |
688e6c72 | 719 | |
9f235dfa TU |
720 | static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset) |
721 | { | |
722 | memset(batch, 0, 6 * sizeof(u32)); | |
723 | ||
724 | batch[0] = GFX_OP_PIPE_CONTROL(6); | |
725 | batch[1] = flags; | |
726 | batch[2] = offset; | |
727 | ||
728 | return batch + 6; | |
729 | } | |
730 | ||
5400367a | 731 | bool intel_engine_is_idle(struct intel_engine_cs *engine); |
05425249 | 732 | bool intel_engines_are_idle(struct drm_i915_private *dev_priv); |
5400367a | 733 | |
6c067579 | 734 | void intel_engines_mark_idle(struct drm_i915_private *i915); |
ff44ad51 CW |
735 | void intel_engines_reset_default_submission(struct drm_i915_private *i915); |
736 | ||
8187a2b7 | 737 | #endif /* _INTEL_RINGBUFFER_H_ */ |