]>
Commit | Line | Data |
---|---|---|
9c065a7d DV |
1 | /* |
2 | * Copyright © 2012-2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * Daniel Vetter <daniel.vetter@ffwll.ch> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/pm_runtime.h> | |
30 | #include <linux/vgaarb.h> | |
31 | ||
32 | #include "i915_drv.h" | |
33 | #include "intel_drv.h" | |
9c065a7d | 34 | |
e4e7684f DV |
35 | /** |
36 | * DOC: runtime pm | |
37 | * | |
38 | * The i915 driver supports dynamic enabling and disabling of entire hardware | |
39 | * blocks at runtime. This is especially important on the display side where | |
40 | * software is supposed to control many power gates manually on recent hardware, | |
41 | * since on the GT side a lot of the power management is done by the hardware. | |
42 | * But even there some manual control at the device level is required. | |
43 | * | |
44 | * Since i915 supports a diverse set of platforms with a unified codebase and | |
45 | * hardware engineers just love to shuffle functionality around between power | |
46 | * domains there's a sizeable amount of indirection required. This file provides | |
47 | * generic functions to the driver for grabbing and releasing references for | |
48 | * abstract power domains. It then maps those to the actual power wells | |
49 | * present for a given platform. | |
50 | */ | |
51 | ||
9c065a7d DV |
52 | #define for_each_power_well(i, power_well, domain_mask, power_domains) \ |
53 | for (i = 0; \ | |
54 | i < (power_domains)->power_well_count && \ | |
55 | ((power_well) = &(power_domains)->power_wells[i]); \ | |
56 | i++) \ | |
95150bdf | 57 | for_each_if ((power_well)->domains & (domain_mask)) |
9c065a7d DV |
58 | |
59 | #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ | |
60 | for (i = (power_domains)->power_well_count - 1; \ | |
61 | i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ | |
62 | i--) \ | |
95150bdf | 63 | for_each_if ((power_well)->domains & (domain_mask)) |
9c065a7d | 64 | |
5aefb239 SS |
65 | bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, |
66 | int power_well_id); | |
67 | ||
9895ad03 DS |
68 | const char * |
69 | intel_display_power_domain_str(enum intel_display_power_domain domain) | |
70 | { | |
71 | switch (domain) { | |
72 | case POWER_DOMAIN_PIPE_A: | |
73 | return "PIPE_A"; | |
74 | case POWER_DOMAIN_PIPE_B: | |
75 | return "PIPE_B"; | |
76 | case POWER_DOMAIN_PIPE_C: | |
77 | return "PIPE_C"; | |
78 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: | |
79 | return "PIPE_A_PANEL_FITTER"; | |
80 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: | |
81 | return "PIPE_B_PANEL_FITTER"; | |
82 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: | |
83 | return "PIPE_C_PANEL_FITTER"; | |
84 | case POWER_DOMAIN_TRANSCODER_A: | |
85 | return "TRANSCODER_A"; | |
86 | case POWER_DOMAIN_TRANSCODER_B: | |
87 | return "TRANSCODER_B"; | |
88 | case POWER_DOMAIN_TRANSCODER_C: | |
89 | return "TRANSCODER_C"; | |
90 | case POWER_DOMAIN_TRANSCODER_EDP: | |
91 | return "TRANSCODER_EDP"; | |
92 | case POWER_DOMAIN_PORT_DDI_A_LANES: | |
93 | return "PORT_DDI_A_LANES"; | |
94 | case POWER_DOMAIN_PORT_DDI_B_LANES: | |
95 | return "PORT_DDI_B_LANES"; | |
96 | case POWER_DOMAIN_PORT_DDI_C_LANES: | |
97 | return "PORT_DDI_C_LANES"; | |
98 | case POWER_DOMAIN_PORT_DDI_D_LANES: | |
99 | return "PORT_DDI_D_LANES"; | |
100 | case POWER_DOMAIN_PORT_DDI_E_LANES: | |
101 | return "PORT_DDI_E_LANES"; | |
102 | case POWER_DOMAIN_PORT_DSI: | |
103 | return "PORT_DSI"; | |
104 | case POWER_DOMAIN_PORT_CRT: | |
105 | return "PORT_CRT"; | |
106 | case POWER_DOMAIN_PORT_OTHER: | |
107 | return "PORT_OTHER"; | |
108 | case POWER_DOMAIN_VGA: | |
109 | return "VGA"; | |
110 | case POWER_DOMAIN_AUDIO: | |
111 | return "AUDIO"; | |
112 | case POWER_DOMAIN_PLLS: | |
113 | return "PLLS"; | |
114 | case POWER_DOMAIN_AUX_A: | |
115 | return "AUX_A"; | |
116 | case POWER_DOMAIN_AUX_B: | |
117 | return "AUX_B"; | |
118 | case POWER_DOMAIN_AUX_C: | |
119 | return "AUX_C"; | |
120 | case POWER_DOMAIN_AUX_D: | |
121 | return "AUX_D"; | |
122 | case POWER_DOMAIN_GMBUS: | |
123 | return "GMBUS"; | |
124 | case POWER_DOMAIN_INIT: | |
125 | return "INIT"; | |
126 | case POWER_DOMAIN_MODESET: | |
127 | return "MODESET"; | |
128 | default: | |
129 | MISSING_CASE(domain); | |
130 | return "?"; | |
131 | } | |
132 | } | |
133 | ||
e8ca9320 DL |
134 | static void intel_power_well_enable(struct drm_i915_private *dev_priv, |
135 | struct i915_power_well *power_well) | |
136 | { | |
137 | DRM_DEBUG_KMS("enabling %s\n", power_well->name); | |
138 | power_well->ops->enable(dev_priv, power_well); | |
139 | power_well->hw_enabled = true; | |
140 | } | |
141 | ||
dcddab3a DL |
142 | static void intel_power_well_disable(struct drm_i915_private *dev_priv, |
143 | struct i915_power_well *power_well) | |
144 | { | |
145 | DRM_DEBUG_KMS("disabling %s\n", power_well->name); | |
146 | power_well->hw_enabled = false; | |
147 | power_well->ops->disable(dev_priv, power_well); | |
148 | } | |
149 | ||
e4e7684f | 150 | /* |
9c065a7d DV |
151 | * We should only use the power well if we explicitly asked the hardware to |
152 | * enable it, so check if it's enabled and also check if we've requested it to | |
153 | * be enabled. | |
154 | */ | |
155 | static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, | |
156 | struct i915_power_well *power_well) | |
157 | { | |
158 | return I915_READ(HSW_PWR_WELL_DRIVER) == | |
159 | (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); | |
160 | } | |
161 | ||
e4e7684f DV |
162 | /** |
163 | * __intel_display_power_is_enabled - unlocked check for a power domain | |
164 | * @dev_priv: i915 device instance | |
165 | * @domain: power domain to check | |
166 | * | |
167 | * This is the unlocked version of intel_display_power_is_enabled() and should | |
168 | * only be used from error capture and recovery code where deadlocks are | |
169 | * possible. | |
170 | * | |
171 | * Returns: | |
172 | * True when the power domain is enabled, false otherwise. | |
173 | */ | |
f458ebbc DV |
174 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
175 | enum intel_display_power_domain domain) | |
9c065a7d DV |
176 | { |
177 | struct i915_power_domains *power_domains; | |
178 | struct i915_power_well *power_well; | |
179 | bool is_enabled; | |
180 | int i; | |
181 | ||
182 | if (dev_priv->pm.suspended) | |
183 | return false; | |
184 | ||
185 | power_domains = &dev_priv->power_domains; | |
186 | ||
187 | is_enabled = true; | |
188 | ||
189 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { | |
190 | if (power_well->always_on) | |
191 | continue; | |
192 | ||
193 | if (!power_well->hw_enabled) { | |
194 | is_enabled = false; | |
195 | break; | |
196 | } | |
197 | } | |
198 | ||
199 | return is_enabled; | |
200 | } | |
201 | ||
e4e7684f | 202 | /** |
f61ccae3 | 203 | * intel_display_power_is_enabled - check for a power domain |
e4e7684f DV |
204 | * @dev_priv: i915 device instance |
205 | * @domain: power domain to check | |
206 | * | |
207 | * This function can be used to check the hw power domain state. It is mostly | |
208 | * used in hardware state readout functions. Everywhere else code should rely | |
209 | * upon explicit power domain reference counting to ensure that the hardware | |
210 | * block is powered up before accessing it. | |
211 | * | |
212 | * Callers must hold the relevant modesetting locks to ensure that concurrent | |
213 | * threads can't disable the power well while the caller tries to read a few | |
214 | * registers. | |
215 | * | |
216 | * Returns: | |
217 | * True when the power domain is enabled, false otherwise. | |
218 | */ | |
f458ebbc DV |
219 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
220 | enum intel_display_power_domain domain) | |
9c065a7d DV |
221 | { |
222 | struct i915_power_domains *power_domains; | |
223 | bool ret; | |
224 | ||
225 | power_domains = &dev_priv->power_domains; | |
226 | ||
227 | mutex_lock(&power_domains->lock); | |
f458ebbc | 228 | ret = __intel_display_power_is_enabled(dev_priv, domain); |
9c065a7d DV |
229 | mutex_unlock(&power_domains->lock); |
230 | ||
231 | return ret; | |
232 | } | |
233 | ||
e4e7684f DV |
234 | /** |
235 | * intel_display_set_init_power - set the initial power domain state | |
236 | * @dev_priv: i915 device instance | |
237 | * @enable: whether to enable or disable the initial power domain state | |
238 | * | |
239 | * For simplicity our driver load/unload and system suspend/resume code assumes | |
240 | * that all power domains are always enabled. This functions controls the state | |
241 | * of this little hack. While the initial power domain state is enabled runtime | |
242 | * pm is effectively disabled. | |
243 | */ | |
d9bc89d9 DV |
244 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, |
245 | bool enable) | |
246 | { | |
247 | if (dev_priv->power_domains.init_power_on == enable) | |
248 | return; | |
249 | ||
250 | if (enable) | |
251 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
252 | else | |
253 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
254 | ||
255 | dev_priv->power_domains.init_power_on = enable; | |
256 | } | |
257 | ||
9c065a7d DV |
258 | /* |
259 | * Starting with Haswell, we have a "Power Down Well" that can be turned off | |
260 | * when not needed anymore. We have 4 registers that can request the power well | |
261 | * to be enabled, and it will only be disabled if none of the registers is | |
262 | * requesting it to be enabled. | |
263 | */ | |
264 | static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) | |
265 | { | |
266 | struct drm_device *dev = dev_priv->dev; | |
267 | ||
268 | /* | |
269 | * After we re-enable the power well, if we touch VGA register 0x3d5 | |
270 | * we'll get unclaimed register interrupts. This stops after we write | |
271 | * anything to the VGA MSR register. The vgacon module uses this | |
272 | * register all the time, so if we unbind our driver and, as a | |
273 | * consequence, bind vgacon, we'll get stuck in an infinite loop at | |
274 | * console_unlock(). So make here we touch the VGA MSR register, making | |
275 | * sure vgacon can keep working normally without triggering interrupts | |
276 | * and error messages. | |
277 | */ | |
278 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
279 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); | |
280 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
281 | ||
25400392 | 282 | if (IS_BROADWELL(dev)) |
4c6c03be DL |
283 | gen8_irq_power_well_post_enable(dev_priv, |
284 | 1 << PIPE_C | 1 << PIPE_B); | |
9c065a7d DV |
285 | } |
286 | ||
d14c0343 DL |
287 | static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, |
288 | struct i915_power_well *power_well) | |
289 | { | |
290 | struct drm_device *dev = dev_priv->dev; | |
291 | ||
292 | /* | |
293 | * After we re-enable the power well, if we touch VGA register 0x3d5 | |
294 | * we'll get unclaimed register interrupts. This stops after we write | |
295 | * anything to the VGA MSR register. The vgacon module uses this | |
296 | * register all the time, so if we unbind our driver and, as a | |
297 | * consequence, bind vgacon, we'll get stuck in an infinite loop at | |
298 | * console_unlock(). So make here we touch the VGA MSR register, making | |
299 | * sure vgacon can keep working normally without triggering interrupts | |
300 | * and error messages. | |
301 | */ | |
302 | if (power_well->data == SKL_DISP_PW_2) { | |
303 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
304 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); | |
305 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
306 | ||
307 | gen8_irq_power_well_post_enable(dev_priv, | |
308 | 1 << PIPE_C | 1 << PIPE_B); | |
309 | } | |
d14c0343 DL |
310 | } |
311 | ||
9c065a7d DV |
312 | static void hsw_set_power_well(struct drm_i915_private *dev_priv, |
313 | struct i915_power_well *power_well, bool enable) | |
314 | { | |
315 | bool is_enabled, enable_requested; | |
316 | uint32_t tmp; | |
317 | ||
318 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); | |
319 | is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; | |
320 | enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; | |
321 | ||
322 | if (enable) { | |
323 | if (!enable_requested) | |
324 | I915_WRITE(HSW_PWR_WELL_DRIVER, | |
325 | HSW_PWR_WELL_ENABLE_REQUEST); | |
326 | ||
327 | if (!is_enabled) { | |
328 | DRM_DEBUG_KMS("Enabling power well\n"); | |
329 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & | |
330 | HSW_PWR_WELL_STATE_ENABLED), 20)) | |
331 | DRM_ERROR("Timeout enabling power well\n"); | |
6d729bff | 332 | hsw_power_well_post_enable(dev_priv); |
9c065a7d DV |
333 | } |
334 | ||
9c065a7d DV |
335 | } else { |
336 | if (enable_requested) { | |
337 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); | |
338 | POSTING_READ(HSW_PWR_WELL_DRIVER); | |
339 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); | |
340 | } | |
341 | } | |
342 | } | |
343 | ||
94dd5138 S |
344 | #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ |
345 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ | |
346 | BIT(POWER_DOMAIN_PIPE_B) | \ | |
347 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ | |
348 | BIT(POWER_DOMAIN_PIPE_C) | \ | |
349 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ | |
350 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ | |
351 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ | |
6331a704 PJ |
352 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
353 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ | |
354 | BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ | |
355 | BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \ | |
94dd5138 S |
356 | BIT(POWER_DOMAIN_AUX_B) | \ |
357 | BIT(POWER_DOMAIN_AUX_C) | \ | |
358 | BIT(POWER_DOMAIN_AUX_D) | \ | |
359 | BIT(POWER_DOMAIN_AUDIO) | \ | |
360 | BIT(POWER_DOMAIN_VGA) | \ | |
361 | BIT(POWER_DOMAIN_INIT)) | |
94dd5138 | 362 | #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \ |
6331a704 PJ |
363 | BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ |
364 | BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \ | |
94dd5138 S |
365 | BIT(POWER_DOMAIN_INIT)) |
366 | #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \ | |
6331a704 | 367 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
94dd5138 S |
368 | BIT(POWER_DOMAIN_INIT)) |
369 | #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \ | |
6331a704 | 370 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ |
94dd5138 S |
371 | BIT(POWER_DOMAIN_INIT)) |
372 | #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \ | |
6331a704 | 373 | BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ |
94dd5138 | 374 | BIT(POWER_DOMAIN_INIT)) |
9f836f90 PJ |
375 | #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ |
376 | SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ | |
377 | BIT(POWER_DOMAIN_MODESET) | \ | |
378 | BIT(POWER_DOMAIN_AUX_A) | \ | |
379 | BIT(POWER_DOMAIN_INIT)) | |
94dd5138 | 380 | #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ |
4a76f295 | 381 | (POWER_DOMAIN_MASK & ~( \ |
9f836f90 PJ |
382 | SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ |
383 | SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \ | |
94dd5138 S |
384 | BIT(POWER_DOMAIN_INIT)) |
385 | ||
0b4a2a36 S |
386 | #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ |
387 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ | |
388 | BIT(POWER_DOMAIN_PIPE_B) | \ | |
389 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ | |
390 | BIT(POWER_DOMAIN_PIPE_C) | \ | |
391 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ | |
392 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ | |
393 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ | |
6331a704 PJ |
394 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
395 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ | |
0b4a2a36 S |
396 | BIT(POWER_DOMAIN_AUX_B) | \ |
397 | BIT(POWER_DOMAIN_AUX_C) | \ | |
398 | BIT(POWER_DOMAIN_AUDIO) | \ | |
399 | BIT(POWER_DOMAIN_VGA) | \ | |
f0ab43e6 | 400 | BIT(POWER_DOMAIN_GMBUS) | \ |
0b4a2a36 S |
401 | BIT(POWER_DOMAIN_INIT)) |
402 | #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ | |
403 | BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ | |
404 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
405 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ | |
406 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ | |
6331a704 | 407 | BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ |
0b4a2a36 S |
408 | BIT(POWER_DOMAIN_AUX_A) | \ |
409 | BIT(POWER_DOMAIN_PLLS) | \ | |
410 | BIT(POWER_DOMAIN_INIT)) | |
9f836f90 PJ |
411 | #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ |
412 | BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ | |
413 | BIT(POWER_DOMAIN_MODESET) | \ | |
414 | BIT(POWER_DOMAIN_AUX_A) | \ | |
415 | BIT(POWER_DOMAIN_INIT)) | |
0b4a2a36 S |
416 | #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ |
417 | (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ | |
418 | BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \ | |
419 | BIT(POWER_DOMAIN_INIT)) | |
420 | ||
664326f8 SK |
421 | static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) |
422 | { | |
423 | struct drm_device *dev = dev_priv->dev; | |
424 | ||
425 | WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n"); | |
426 | WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), | |
427 | "DC9 already programmed to be enabled.\n"); | |
428 | WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, | |
429 | "DC5 still not disabled to enable DC9.\n"); | |
430 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); | |
431 | WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); | |
432 | ||
433 | /* | |
434 | * TODO: check for the following to verify the conditions to enter DC9 | |
435 | * state are satisfied: | |
436 | * 1] Check relevant display engine registers to verify if mode set | |
437 | * disable sequence was followed. | |
438 | * 2] Check if display uninitialize sequence is initialized. | |
439 | */ | |
440 | } | |
441 | ||
442 | static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) | |
443 | { | |
444 | WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); | |
445 | WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), | |
446 | "DC9 already programmed to be disabled.\n"); | |
447 | WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, | |
448 | "DC5 still not disabled.\n"); | |
449 | ||
450 | /* | |
451 | * TODO: check for the following to verify DC9 state was indeed | |
452 | * entered before programming to disable it: | |
453 | * 1] Check relevant display engine registers to verify if mode | |
454 | * set disable sequence was followed. | |
455 | * 2] Check if display uninitialize sequence is initialized. | |
456 | */ | |
457 | } | |
458 | ||
4deccbb2 PJ |
459 | static void gen9_set_dc_state_debugmask_memory_up( |
460 | struct drm_i915_private *dev_priv) | |
461 | { | |
462 | uint32_t val; | |
463 | ||
464 | /* The below bit doesn't need to be cleared ever afterwards */ | |
465 | val = I915_READ(DC_STATE_DEBUG); | |
466 | if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) { | |
467 | val |= DC_STATE_DEBUG_MASK_MEMORY_UP; | |
468 | I915_WRITE(DC_STATE_DEBUG, val); | |
469 | POSTING_READ(DC_STATE_DEBUG); | |
470 | } | |
471 | } | |
472 | ||
13ae3a0d | 473 | static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) |
664326f8 SK |
474 | { |
475 | uint32_t val; | |
13ae3a0d | 476 | uint32_t mask; |
664326f8 | 477 | |
13ae3a0d ID |
478 | mask = DC_STATE_EN_UPTO_DC5; |
479 | if (IS_BROXTON(dev_priv)) | |
480 | mask |= DC_STATE_EN_DC9; | |
481 | else | |
482 | mask |= DC_STATE_EN_UPTO_DC6; | |
664326f8 | 483 | |
13ae3a0d | 484 | WARN_ON_ONCE(state & ~mask); |
664326f8 | 485 | |
443646c7 PJ |
486 | if (i915.enable_dc == 0) |
487 | state = DC_STATE_DISABLE; | |
488 | else if (i915.enable_dc == 1 && state > DC_STATE_EN_UPTO_DC5) | |
489 | state = DC_STATE_EN_UPTO_DC5; | |
490 | ||
4deccbb2 PJ |
491 | if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK) |
492 | gen9_set_dc_state_debugmask_memory_up(dev_priv); | |
493 | ||
664326f8 | 494 | val = I915_READ(DC_STATE_EN); |
13ae3a0d ID |
495 | DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", |
496 | val & mask, state); | |
497 | val &= ~mask; | |
498 | val |= state; | |
664326f8 SK |
499 | I915_WRITE(DC_STATE_EN, val); |
500 | POSTING_READ(DC_STATE_EN); | |
501 | } | |
502 | ||
13ae3a0d | 503 | void bxt_enable_dc9(struct drm_i915_private *dev_priv) |
664326f8 | 504 | { |
13ae3a0d ID |
505 | assert_can_enable_dc9(dev_priv); |
506 | ||
507 | DRM_DEBUG_KMS("Enabling DC9\n"); | |
664326f8 | 508 | |
13ae3a0d ID |
509 | gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); |
510 | } | |
511 | ||
512 | void bxt_disable_dc9(struct drm_i915_private *dev_priv) | |
513 | { | |
664326f8 SK |
514 | assert_can_disable_dc9(dev_priv); |
515 | ||
516 | DRM_DEBUG_KMS("Disabling DC9\n"); | |
517 | ||
13ae3a0d | 518 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); |
664326f8 SK |
519 | } |
520 | ||
af5fead2 DV |
521 | static void assert_csr_loaded(struct drm_i915_private *dev_priv) |
522 | { | |
523 | WARN_ONCE(!I915_READ(CSR_PROGRAM(0)), | |
524 | "CSR program storage start is NULL\n"); | |
525 | WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); | |
526 | WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); | |
527 | } | |
528 | ||
5aefb239 | 529 | static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) |
dc174300 | 530 | { |
6b457d31 | 531 | struct drm_device *dev = dev_priv->dev; |
5aefb239 SS |
532 | bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, |
533 | SKL_DISP_PW_2); | |
534 | ||
6ff8ab0d JB |
535 | WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n"); |
536 | WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); | |
537 | WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); | |
5aefb239 | 538 | |
6ff8ab0d JB |
539 | WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), |
540 | "DC5 already programmed to be enabled.\n"); | |
541 | WARN_ONCE(dev_priv->pm.suspended, | |
542 | "DC5 cannot be enabled, if platform is runtime-suspended.\n"); | |
5aefb239 SS |
543 | |
544 | assert_csr_loaded(dev_priv); | |
545 | } | |
546 | ||
547 | static void assert_can_disable_dc5(struct drm_i915_private *dev_priv) | |
548 | { | |
93c7cb6c SS |
549 | /* |
550 | * During initialization, the firmware may not be loaded yet. | |
551 | * We still want to make sure that the DC enabling flag is cleared. | |
552 | */ | |
553 | if (dev_priv->power_domains.initializing) | |
554 | return; | |
5aefb239 | 555 | |
6ff8ab0d | 556 | WARN_ONCE(dev_priv->pm.suspended, |
5aefb239 SS |
557 | "Disabling of DC5 while platform is runtime-suspended should never happen.\n"); |
558 | } | |
559 | ||
560 | static void gen9_enable_dc5(struct drm_i915_private *dev_priv) | |
561 | { | |
5aefb239 | 562 | assert_can_enable_dc5(dev_priv); |
6b457d31 SK |
563 | |
564 | DRM_DEBUG_KMS("Enabling DC5\n"); | |
565 | ||
13ae3a0d | 566 | gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); |
dc174300 SS |
567 | } |
568 | ||
93c7cb6c | 569 | static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) |
f75a1985 | 570 | { |
74b4f371 | 571 | struct drm_device *dev = dev_priv->dev; |
93c7cb6c | 572 | |
6ff8ab0d JB |
573 | WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n"); |
574 | WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); | |
575 | WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
576 | "Backlight is not disabled.\n"); | |
577 | WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), | |
578 | "DC6 already programmed to be enabled.\n"); | |
93c7cb6c SS |
579 | |
580 | assert_csr_loaded(dev_priv); | |
581 | } | |
582 | ||
583 | static void assert_can_disable_dc6(struct drm_i915_private *dev_priv) | |
584 | { | |
585 | /* | |
586 | * During initialization, the firmware may not be loaded yet. | |
587 | * We still want to make sure that the DC enabling flag is cleared. | |
588 | */ | |
589 | if (dev_priv->power_domains.initializing) | |
590 | return; | |
591 | ||
6ff8ab0d JB |
592 | WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), |
593 | "DC6 already programmed to be disabled.\n"); | |
93c7cb6c SS |
594 | } |
595 | ||
9f836f90 PJ |
596 | static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv) |
597 | { | |
598 | assert_can_disable_dc5(dev_priv); | |
443646c7 PJ |
599 | |
600 | if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && i915.enable_dc != 1) | |
601 | assert_can_disable_dc6(dev_priv); | |
9f836f90 PJ |
602 | |
603 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); | |
604 | } | |
605 | ||
0a9d2bed | 606 | void skl_enable_dc6(struct drm_i915_private *dev_priv) |
93c7cb6c | 607 | { |
93c7cb6c | 608 | assert_can_enable_dc6(dev_priv); |
74b4f371 SK |
609 | |
610 | DRM_DEBUG_KMS("Enabling DC6\n"); | |
611 | ||
13ae3a0d ID |
612 | gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); |
613 | ||
f75a1985 SS |
614 | } |
615 | ||
0a9d2bed | 616 | void skl_disable_dc6(struct drm_i915_private *dev_priv) |
f75a1985 | 617 | { |
93c7cb6c | 618 | assert_can_disable_dc6(dev_priv); |
74b4f371 SK |
619 | |
620 | DRM_DEBUG_KMS("Disabling DC6\n"); | |
621 | ||
13ae3a0d | 622 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); |
f75a1985 SS |
623 | } |
624 | ||
94dd5138 S |
625 | static void skl_set_power_well(struct drm_i915_private *dev_priv, |
626 | struct i915_power_well *power_well, bool enable) | |
627 | { | |
dc174300 | 628 | struct drm_device *dev = dev_priv->dev; |
94dd5138 S |
629 | uint32_t tmp, fuse_status; |
630 | uint32_t req_mask, state_mask; | |
2a51835f | 631 | bool is_enabled, enable_requested, check_fuse_status = false; |
94dd5138 S |
632 | |
633 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); | |
634 | fuse_status = I915_READ(SKL_FUSE_STATUS); | |
635 | ||
636 | switch (power_well->data) { | |
637 | case SKL_DISP_PW_1: | |
638 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & | |
639 | SKL_FUSE_PG0_DIST_STATUS), 1)) { | |
640 | DRM_ERROR("PG0 not enabled\n"); | |
641 | return; | |
642 | } | |
643 | break; | |
644 | case SKL_DISP_PW_2: | |
645 | if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { | |
646 | DRM_ERROR("PG1 in disabled state\n"); | |
647 | return; | |
648 | } | |
649 | break; | |
650 | case SKL_DISP_PW_DDI_A_E: | |
651 | case SKL_DISP_PW_DDI_B: | |
652 | case SKL_DISP_PW_DDI_C: | |
653 | case SKL_DISP_PW_DDI_D: | |
654 | case SKL_DISP_PW_MISC_IO: | |
655 | break; | |
656 | default: | |
657 | WARN(1, "Unknown power well %lu\n", power_well->data); | |
658 | return; | |
659 | } | |
660 | ||
661 | req_mask = SKL_POWER_WELL_REQ(power_well->data); | |
2a51835f | 662 | enable_requested = tmp & req_mask; |
94dd5138 | 663 | state_mask = SKL_POWER_WELL_STATE(power_well->data); |
2a51835f | 664 | is_enabled = tmp & state_mask; |
94dd5138 S |
665 | |
666 | if (enable) { | |
2a51835f | 667 | if (!enable_requested) { |
dc174300 SS |
668 | WARN((tmp & state_mask) && |
669 | !I915_READ(HSW_PWR_WELL_BIOS), | |
670 | "Invalid for power well status to be enabled, unless done by the BIOS, \ | |
671 | when request is to disable!\n"); | |
0a9d2bed | 672 | if (power_well->data == SKL_DISP_PW_2) { |
9f836f90 PJ |
673 | /* |
674 | * DDI buffer programming unnecessary during | |
675 | * driver-load/resume as it's already done | |
676 | * during modeset initialization then. It's | |
677 | * also invalid here as encoder list is still | |
678 | * uninitialized. | |
679 | */ | |
680 | if (!dev_priv->power_domains.initializing) | |
681 | intel_prepare_ddi(dev); | |
f75a1985 | 682 | } |
94dd5138 | 683 | I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); |
94dd5138 S |
684 | } |
685 | ||
2a51835f | 686 | if (!is_enabled) { |
510e6fdd | 687 | DRM_DEBUG_KMS("Enabling %s\n", power_well->name); |
94dd5138 S |
688 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & |
689 | state_mask), 1)) | |
690 | DRM_ERROR("%s enable timeout\n", | |
691 | power_well->name); | |
692 | check_fuse_status = true; | |
693 | } | |
694 | } else { | |
2a51835f | 695 | if (enable_requested) { |
4a76f295 ID |
696 | I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); |
697 | POSTING_READ(HSW_PWR_WELL_DRIVER); | |
698 | DRM_DEBUG_KMS("Disabling %s\n", power_well->name); | |
94dd5138 S |
699 | } |
700 | } | |
701 | ||
702 | if (check_fuse_status) { | |
703 | if (power_well->data == SKL_DISP_PW_1) { | |
704 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & | |
705 | SKL_FUSE_PG1_DIST_STATUS), 1)) | |
706 | DRM_ERROR("PG1 distributing status timeout\n"); | |
707 | } else if (power_well->data == SKL_DISP_PW_2) { | |
708 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & | |
709 | SKL_FUSE_PG2_DIST_STATUS), 1)) | |
710 | DRM_ERROR("PG2 distributing status timeout\n"); | |
711 | } | |
712 | } | |
d14c0343 DL |
713 | |
714 | if (enable && !is_enabled) | |
715 | skl_power_well_post_enable(dev_priv, power_well); | |
94dd5138 S |
716 | } |
717 | ||
9c065a7d DV |
718 | static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, |
719 | struct i915_power_well *power_well) | |
720 | { | |
721 | hsw_set_power_well(dev_priv, power_well, power_well->count > 0); | |
722 | ||
723 | /* | |
724 | * We're taking over the BIOS, so clear any requests made by it since | |
725 | * the driver is in charge now. | |
726 | */ | |
727 | if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) | |
728 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); | |
729 | } | |
730 | ||
731 | static void hsw_power_well_enable(struct drm_i915_private *dev_priv, | |
732 | struct i915_power_well *power_well) | |
733 | { | |
734 | hsw_set_power_well(dev_priv, power_well, true); | |
735 | } | |
736 | ||
737 | static void hsw_power_well_disable(struct drm_i915_private *dev_priv, | |
738 | struct i915_power_well *power_well) | |
739 | { | |
740 | hsw_set_power_well(dev_priv, power_well, false); | |
741 | } | |
742 | ||
94dd5138 S |
743 | static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, |
744 | struct i915_power_well *power_well) | |
745 | { | |
746 | uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) | | |
747 | SKL_POWER_WELL_STATE(power_well->data); | |
748 | ||
749 | return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; | |
750 | } | |
751 | ||
752 | static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
753 | struct i915_power_well *power_well) | |
754 | { | |
755 | skl_set_power_well(dev_priv, power_well, power_well->count > 0); | |
756 | ||
757 | /* Clear any request made by BIOS as driver is taking over */ | |
758 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); | |
759 | } | |
760 | ||
761 | static void skl_power_well_enable(struct drm_i915_private *dev_priv, | |
762 | struct i915_power_well *power_well) | |
763 | { | |
764 | skl_set_power_well(dev_priv, power_well, true); | |
765 | } | |
766 | ||
767 | static void skl_power_well_disable(struct drm_i915_private *dev_priv, | |
768 | struct i915_power_well *power_well) | |
769 | { | |
770 | skl_set_power_well(dev_priv, power_well, false); | |
771 | } | |
772 | ||
9f836f90 PJ |
773 | static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, |
774 | struct i915_power_well *power_well) | |
775 | { | |
776 | return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0; | |
777 | } | |
778 | ||
779 | static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, | |
780 | struct i915_power_well *power_well) | |
781 | { | |
782 | gen9_disable_dc5_dc6(dev_priv); | |
783 | } | |
784 | ||
785 | static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, | |
786 | struct i915_power_well *power_well) | |
787 | { | |
443646c7 | 788 | if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && i915.enable_dc != 1) |
9f836f90 PJ |
789 | skl_enable_dc6(dev_priv); |
790 | else | |
791 | gen9_enable_dc5(dev_priv); | |
792 | } | |
793 | ||
794 | static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
795 | struct i915_power_well *power_well) | |
796 | { | |
797 | if (power_well->count > 0) { | |
798 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); | |
799 | } else { | |
443646c7 PJ |
800 | if (IS_SKYLAKE(dev_priv) && i915.enable_dc != 0 && |
801 | i915.enable_dc != 1) | |
9f836f90 PJ |
802 | gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); |
803 | else | |
804 | gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); | |
805 | } | |
806 | } | |
807 | ||
9c065a7d DV |
808 | static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, |
809 | struct i915_power_well *power_well) | |
810 | { | |
811 | } | |
812 | ||
813 | static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, | |
814 | struct i915_power_well *power_well) | |
815 | { | |
816 | return true; | |
817 | } | |
818 | ||
819 | static void vlv_set_power_well(struct drm_i915_private *dev_priv, | |
820 | struct i915_power_well *power_well, bool enable) | |
821 | { | |
822 | enum punit_power_well power_well_id = power_well->data; | |
823 | u32 mask; | |
824 | u32 state; | |
825 | u32 ctrl; | |
826 | ||
827 | mask = PUNIT_PWRGT_MASK(power_well_id); | |
828 | state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : | |
829 | PUNIT_PWRGT_PWR_GATE(power_well_id); | |
830 | ||
831 | mutex_lock(&dev_priv->rps.hw_lock); | |
832 | ||
833 | #define COND \ | |
834 | ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) | |
835 | ||
836 | if (COND) | |
837 | goto out; | |
838 | ||
839 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); | |
840 | ctrl &= ~mask; | |
841 | ctrl |= state; | |
842 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); | |
843 | ||
844 | if (wait_for(COND, 100)) | |
7e35ab88 | 845 | DRM_ERROR("timeout setting power well state %08x (%08x)\n", |
9c065a7d DV |
846 | state, |
847 | vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); | |
848 | ||
849 | #undef COND | |
850 | ||
851 | out: | |
852 | mutex_unlock(&dev_priv->rps.hw_lock); | |
853 | } | |
854 | ||
855 | static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
856 | struct i915_power_well *power_well) | |
857 | { | |
858 | vlv_set_power_well(dev_priv, power_well, power_well->count > 0); | |
859 | } | |
860 | ||
861 | static void vlv_power_well_enable(struct drm_i915_private *dev_priv, | |
862 | struct i915_power_well *power_well) | |
863 | { | |
864 | vlv_set_power_well(dev_priv, power_well, true); | |
865 | } | |
866 | ||
867 | static void vlv_power_well_disable(struct drm_i915_private *dev_priv, | |
868 | struct i915_power_well *power_well) | |
869 | { | |
870 | vlv_set_power_well(dev_priv, power_well, false); | |
871 | } | |
872 | ||
873 | static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, | |
874 | struct i915_power_well *power_well) | |
875 | { | |
876 | int power_well_id = power_well->data; | |
877 | bool enabled = false; | |
878 | u32 mask; | |
879 | u32 state; | |
880 | u32 ctrl; | |
881 | ||
882 | mask = PUNIT_PWRGT_MASK(power_well_id); | |
883 | ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); | |
884 | ||
885 | mutex_lock(&dev_priv->rps.hw_lock); | |
886 | ||
887 | state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; | |
888 | /* | |
889 | * We only ever set the power-on and power-gate states, anything | |
890 | * else is unexpected. | |
891 | */ | |
892 | WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && | |
893 | state != PUNIT_PWRGT_PWR_GATE(power_well_id)); | |
894 | if (state == ctrl) | |
895 | enabled = true; | |
896 | ||
897 | /* | |
898 | * A transient state at this point would mean some unexpected party | |
899 | * is poking at the power controls too. | |
900 | */ | |
901 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; | |
902 | WARN_ON(ctrl != state); | |
903 | ||
904 | mutex_unlock(&dev_priv->rps.hw_lock); | |
905 | ||
906 | return enabled; | |
907 | } | |
908 | ||
2be7d540 | 909 | static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) |
9c065a7d | 910 | { |
5a8fbb7d VS |
911 | enum pipe pipe; |
912 | ||
913 | /* | |
914 | * Enable the CRI clock source so we can get at the | |
915 | * display and the reference clock for VGA | |
916 | * hotplug / manual detection. Supposedly DSI also | |
917 | * needs the ref clock up and running. | |
918 | * | |
919 | * CHV DPLL B/C have some issues if VGA mode is enabled. | |
920 | */ | |
921 | for_each_pipe(dev_priv->dev, pipe) { | |
922 | u32 val = I915_READ(DPLL(pipe)); | |
923 | ||
924 | val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
925 | if (pipe != PIPE_A) | |
926 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
927 | ||
928 | I915_WRITE(DPLL(pipe), val); | |
929 | } | |
9c065a7d DV |
930 | |
931 | spin_lock_irq(&dev_priv->irq_lock); | |
932 | valleyview_enable_display_irqs(dev_priv); | |
933 | spin_unlock_irq(&dev_priv->irq_lock); | |
934 | ||
935 | /* | |
936 | * During driver initialization/resume we can avoid restoring the | |
937 | * part of the HW/SW state that will be inited anyway explicitly. | |
938 | */ | |
939 | if (dev_priv->power_domains.initializing) | |
940 | return; | |
941 | ||
b963291c | 942 | intel_hpd_init(dev_priv); |
9c065a7d DV |
943 | |
944 | i915_redisable_vga_power_on(dev_priv->dev); | |
945 | } | |
946 | ||
2be7d540 VS |
947 | static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) |
948 | { | |
949 | spin_lock_irq(&dev_priv->irq_lock); | |
950 | valleyview_disable_display_irqs(dev_priv); | |
951 | spin_unlock_irq(&dev_priv->irq_lock); | |
952 | ||
953 | vlv_power_sequencer_reset(dev_priv); | |
954 | } | |
955 | ||
956 | static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, | |
957 | struct i915_power_well *power_well) | |
958 | { | |
959 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); | |
960 | ||
961 | vlv_set_power_well(dev_priv, power_well, true); | |
962 | ||
963 | vlv_display_power_well_init(dev_priv); | |
964 | } | |
965 | ||
9c065a7d DV |
966 | static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, |
967 | struct i915_power_well *power_well) | |
968 | { | |
969 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); | |
970 | ||
2be7d540 | 971 | vlv_display_power_well_deinit(dev_priv); |
9c065a7d DV |
972 | |
973 | vlv_set_power_well(dev_priv, power_well, false); | |
9c065a7d DV |
974 | } |
975 | ||
976 | static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, | |
977 | struct i915_power_well *power_well) | |
978 | { | |
979 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); | |
980 | ||
5a8fbb7d | 981 | /* since ref/cri clock was enabled */ |
9c065a7d DV |
982 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |
983 | ||
984 | vlv_set_power_well(dev_priv, power_well, true); | |
985 | ||
986 | /* | |
987 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
988 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
989 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
990 | * b. The other bits such as sfr settings / modesel may all | |
991 | * be set to 0. | |
992 | * | |
993 | * This should only be done on init and resume from S3 with | |
994 | * both PLLs disabled, or we risk losing DPIO and PLL | |
995 | * synchronization. | |
996 | */ | |
997 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
998 | } | |
999 | ||
1000 | static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, | |
1001 | struct i915_power_well *power_well) | |
1002 | { | |
1003 | enum pipe pipe; | |
1004 | ||
1005 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); | |
1006 | ||
1007 | for_each_pipe(dev_priv, pipe) | |
1008 | assert_pll_disabled(dev_priv, pipe); | |
1009 | ||
1010 | /* Assert common reset */ | |
1011 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); | |
1012 | ||
1013 | vlv_set_power_well(dev_priv, power_well, false); | |
1014 | } | |
1015 | ||
30142273 VS |
1016 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) |
1017 | ||
1018 | static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, | |
1019 | int power_well_id) | |
1020 | { | |
1021 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
30142273 VS |
1022 | int i; |
1023 | ||
fc17f227 ID |
1024 | for (i = 0; i < power_domains->power_well_count; i++) { |
1025 | struct i915_power_well *power_well; | |
1026 | ||
1027 | power_well = &power_domains->power_wells[i]; | |
30142273 VS |
1028 | if (power_well->data == power_well_id) |
1029 | return power_well; | |
1030 | } | |
1031 | ||
1032 | return NULL; | |
1033 | } | |
1034 | ||
1035 | #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) | |
1036 | ||
1037 | static void assert_chv_phy_status(struct drm_i915_private *dev_priv) | |
1038 | { | |
1039 | struct i915_power_well *cmn_bc = | |
1040 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); | |
1041 | struct i915_power_well *cmn_d = | |
1042 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); | |
1043 | u32 phy_control = dev_priv->chv_phy_control; | |
1044 | u32 phy_status = 0; | |
3be60de9 | 1045 | u32 phy_status_mask = 0xffffffff; |
30142273 VS |
1046 | u32 tmp; |
1047 | ||
3be60de9 VS |
1048 | /* |
1049 | * The BIOS can leave the PHY is some weird state | |
1050 | * where it doesn't fully power down some parts. | |
1051 | * Disable the asserts until the PHY has been fully | |
1052 | * reset (ie. the power well has been disabled at | |
1053 | * least once). | |
1054 | */ | |
1055 | if (!dev_priv->chv_phy_assert[DPIO_PHY0]) | |
1056 | phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | | |
1057 | PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | | |
1058 | PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | | |
1059 | PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | | |
1060 | PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | | |
1061 | PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); | |
1062 | ||
1063 | if (!dev_priv->chv_phy_assert[DPIO_PHY1]) | |
1064 | phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | | |
1065 | PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | | |
1066 | PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); | |
1067 | ||
30142273 VS |
1068 | if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { |
1069 | phy_status |= PHY_POWERGOOD(DPIO_PHY0); | |
1070 | ||
1071 | /* this assumes override is only used to enable lanes */ | |
1072 | if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) | |
1073 | phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); | |
1074 | ||
1075 | if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) | |
1076 | phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); | |
1077 | ||
1078 | /* CL1 is on whenever anything is on in either channel */ | |
1079 | if (BITS_SET(phy_control, | |
1080 | PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | | |
1081 | PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) | |
1082 | phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); | |
1083 | ||
1084 | /* | |
1085 | * The DPLLB check accounts for the pipe B + port A usage | |
1086 | * with CL2 powered up but all the lanes in the second channel | |
1087 | * powered down. | |
1088 | */ | |
1089 | if (BITS_SET(phy_control, | |
1090 | PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && | |
1091 | (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) | |
1092 | phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); | |
1093 | ||
1094 | if (BITS_SET(phy_control, | |
1095 | PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) | |
1096 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); | |
1097 | if (BITS_SET(phy_control, | |
1098 | PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) | |
1099 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); | |
1100 | ||
1101 | if (BITS_SET(phy_control, | |
1102 | PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) | |
1103 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); | |
1104 | if (BITS_SET(phy_control, | |
1105 | PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) | |
1106 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); | |
1107 | } | |
1108 | ||
1109 | if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { | |
1110 | phy_status |= PHY_POWERGOOD(DPIO_PHY1); | |
1111 | ||
1112 | /* this assumes override is only used to enable lanes */ | |
1113 | if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) | |
1114 | phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); | |
1115 | ||
1116 | if (BITS_SET(phy_control, | |
1117 | PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) | |
1118 | phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); | |
1119 | ||
1120 | if (BITS_SET(phy_control, | |
1121 | PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) | |
1122 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); | |
1123 | if (BITS_SET(phy_control, | |
1124 | PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) | |
1125 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); | |
1126 | } | |
1127 | ||
3be60de9 VS |
1128 | phy_status &= phy_status_mask; |
1129 | ||
30142273 VS |
1130 | /* |
1131 | * The PHY may be busy with some initial calibration and whatnot, | |
1132 | * so the power state can take a while to actually change. | |
1133 | */ | |
3be60de9 | 1134 | if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10)) |
30142273 VS |
1135 | WARN(phy_status != tmp, |
1136 | "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", | |
1137 | tmp, phy_status, dev_priv->chv_phy_control); | |
1138 | } | |
1139 | ||
1140 | #undef BITS_SET | |
1141 | ||
9c065a7d DV |
1142 | static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, |
1143 | struct i915_power_well *power_well) | |
1144 | { | |
1145 | enum dpio_phy phy; | |
e0fce78f VS |
1146 | enum pipe pipe; |
1147 | uint32_t tmp; | |
9c065a7d DV |
1148 | |
1149 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && | |
1150 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); | |
1151 | ||
e0fce78f VS |
1152 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { |
1153 | pipe = PIPE_A; | |
9c065a7d | 1154 | phy = DPIO_PHY0; |
e0fce78f VS |
1155 | } else { |
1156 | pipe = PIPE_C; | |
9c065a7d | 1157 | phy = DPIO_PHY1; |
e0fce78f | 1158 | } |
5a8fbb7d VS |
1159 | |
1160 | /* since ref/cri clock was enabled */ | |
9c065a7d DV |
1161 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |
1162 | vlv_set_power_well(dev_priv, power_well, true); | |
1163 | ||
1164 | /* Poll for phypwrgood signal */ | |
1165 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) | |
1166 | DRM_ERROR("Display PHY %d is not power up\n", phy); | |
1167 | ||
e0fce78f VS |
1168 | mutex_lock(&dev_priv->sb_lock); |
1169 | ||
1170 | /* Enable dynamic power down */ | |
1171 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); | |
ee279218 VS |
1172 | tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | |
1173 | DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; | |
e0fce78f VS |
1174 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); |
1175 | ||
1176 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { | |
1177 | tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); | |
1178 | tmp |= DPIO_DYNPWRDOWNEN_CH1; | |
1179 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); | |
3e288786 VS |
1180 | } else { |
1181 | /* | |
1182 | * Force the non-existing CL2 off. BXT does this | |
1183 | * too, so maybe it saves some power even though | |
1184 | * CL2 doesn't exist? | |
1185 | */ | |
1186 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); | |
1187 | tmp |= DPIO_CL2_LDOFUSE_PWRENB; | |
1188 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); | |
e0fce78f VS |
1189 | } |
1190 | ||
1191 | mutex_unlock(&dev_priv->sb_lock); | |
1192 | ||
70722468 VS |
1193 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); |
1194 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); | |
e0fce78f VS |
1195 | |
1196 | DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", | |
1197 | phy, dev_priv->chv_phy_control); | |
30142273 VS |
1198 | |
1199 | assert_chv_phy_status(dev_priv); | |
9c065a7d DV |
1200 | } |
1201 | ||
1202 | static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, | |
1203 | struct i915_power_well *power_well) | |
1204 | { | |
1205 | enum dpio_phy phy; | |
1206 | ||
1207 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && | |
1208 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); | |
1209 | ||
1210 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { | |
1211 | phy = DPIO_PHY0; | |
1212 | assert_pll_disabled(dev_priv, PIPE_A); | |
1213 | assert_pll_disabled(dev_priv, PIPE_B); | |
1214 | } else { | |
1215 | phy = DPIO_PHY1; | |
1216 | assert_pll_disabled(dev_priv, PIPE_C); | |
1217 | } | |
1218 | ||
70722468 VS |
1219 | dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); |
1220 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); | |
9c065a7d DV |
1221 | |
1222 | vlv_set_power_well(dev_priv, power_well, false); | |
e0fce78f VS |
1223 | |
1224 | DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", | |
1225 | phy, dev_priv->chv_phy_control); | |
30142273 | 1226 | |
3be60de9 VS |
1227 | /* PHY is fully reset now, so we can enable the PHY state asserts */ |
1228 | dev_priv->chv_phy_assert[phy] = true; | |
1229 | ||
30142273 | 1230 | assert_chv_phy_status(dev_priv); |
e0fce78f VS |
1231 | } |
1232 | ||
6669e39f VS |
1233 | static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
1234 | enum dpio_channel ch, bool override, unsigned int mask) | |
1235 | { | |
1236 | enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; | |
1237 | u32 reg, val, expected, actual; | |
1238 | ||
3be60de9 VS |
1239 | /* |
1240 | * The BIOS can leave the PHY is some weird state | |
1241 | * where it doesn't fully power down some parts. | |
1242 | * Disable the asserts until the PHY has been fully | |
1243 | * reset (ie. the power well has been disabled at | |
1244 | * least once). | |
1245 | */ | |
1246 | if (!dev_priv->chv_phy_assert[phy]) | |
1247 | return; | |
1248 | ||
6669e39f VS |
1249 | if (ch == DPIO_CH0) |
1250 | reg = _CHV_CMN_DW0_CH0; | |
1251 | else | |
1252 | reg = _CHV_CMN_DW6_CH1; | |
1253 | ||
1254 | mutex_lock(&dev_priv->sb_lock); | |
1255 | val = vlv_dpio_read(dev_priv, pipe, reg); | |
1256 | mutex_unlock(&dev_priv->sb_lock); | |
1257 | ||
1258 | /* | |
1259 | * This assumes !override is only used when the port is disabled. | |
1260 | * All lanes should power down even without the override when | |
1261 | * the port is disabled. | |
1262 | */ | |
1263 | if (!override || mask == 0xf) { | |
1264 | expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; | |
1265 | /* | |
1266 | * If CH1 common lane is not active anymore | |
1267 | * (eg. for pipe B DPLL) the entire channel will | |
1268 | * shut down, which causes the common lane registers | |
1269 | * to read as 0. That means we can't actually check | |
1270 | * the lane power down status bits, but as the entire | |
1271 | * register reads as 0 it's a good indication that the | |
1272 | * channel is indeed entirely powered down. | |
1273 | */ | |
1274 | if (ch == DPIO_CH1 && val == 0) | |
1275 | expected = 0; | |
1276 | } else if (mask != 0x0) { | |
1277 | expected = DPIO_ANYDL_POWERDOWN; | |
1278 | } else { | |
1279 | expected = 0; | |
1280 | } | |
1281 | ||
1282 | if (ch == DPIO_CH0) | |
1283 | actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; | |
1284 | else | |
1285 | actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; | |
1286 | actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; | |
1287 | ||
1288 | WARN(actual != expected, | |
1289 | "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", | |
1290 | !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), | |
1291 | !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), | |
1292 | reg, val); | |
1293 | } | |
1294 | ||
b0b33846 VS |
1295 | bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
1296 | enum dpio_channel ch, bool override) | |
1297 | { | |
1298 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1299 | bool was_override; | |
1300 | ||
1301 | mutex_lock(&power_domains->lock); | |
1302 | ||
1303 | was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); | |
1304 | ||
1305 | if (override == was_override) | |
1306 | goto out; | |
1307 | ||
1308 | if (override) | |
1309 | dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); | |
1310 | else | |
1311 | dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); | |
1312 | ||
1313 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); | |
1314 | ||
1315 | DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", | |
1316 | phy, ch, dev_priv->chv_phy_control); | |
1317 | ||
30142273 VS |
1318 | assert_chv_phy_status(dev_priv); |
1319 | ||
b0b33846 VS |
1320 | out: |
1321 | mutex_unlock(&power_domains->lock); | |
1322 | ||
1323 | return was_override; | |
1324 | } | |
1325 | ||
e0fce78f VS |
1326 | void chv_phy_powergate_lanes(struct intel_encoder *encoder, |
1327 | bool override, unsigned int mask) | |
1328 | { | |
1329 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1330 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1331 | enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); | |
1332 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); | |
1333 | ||
1334 | mutex_lock(&power_domains->lock); | |
1335 | ||
1336 | dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); | |
1337 | dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); | |
1338 | ||
1339 | if (override) | |
1340 | dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); | |
1341 | else | |
1342 | dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); | |
1343 | ||
1344 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); | |
1345 | ||
1346 | DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", | |
1347 | phy, ch, mask, dev_priv->chv_phy_control); | |
1348 | ||
30142273 VS |
1349 | assert_chv_phy_status(dev_priv); |
1350 | ||
6669e39f VS |
1351 | assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); |
1352 | ||
e0fce78f | 1353 | mutex_unlock(&power_domains->lock); |
9c065a7d DV |
1354 | } |
1355 | ||
1356 | static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, | |
1357 | struct i915_power_well *power_well) | |
1358 | { | |
1359 | enum pipe pipe = power_well->data; | |
1360 | bool enabled; | |
1361 | u32 state, ctrl; | |
1362 | ||
1363 | mutex_lock(&dev_priv->rps.hw_lock); | |
1364 | ||
1365 | state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); | |
1366 | /* | |
1367 | * We only ever set the power-on and power-gate states, anything | |
1368 | * else is unexpected. | |
1369 | */ | |
1370 | WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); | |
1371 | enabled = state == DP_SSS_PWR_ON(pipe); | |
1372 | ||
1373 | /* | |
1374 | * A transient state at this point would mean some unexpected party | |
1375 | * is poking at the power controls too. | |
1376 | */ | |
1377 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); | |
1378 | WARN_ON(ctrl << 16 != state); | |
1379 | ||
1380 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1381 | ||
1382 | return enabled; | |
1383 | } | |
1384 | ||
1385 | static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, | |
1386 | struct i915_power_well *power_well, | |
1387 | bool enable) | |
1388 | { | |
1389 | enum pipe pipe = power_well->data; | |
1390 | u32 state; | |
1391 | u32 ctrl; | |
1392 | ||
1393 | state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); | |
1394 | ||
1395 | mutex_lock(&dev_priv->rps.hw_lock); | |
1396 | ||
1397 | #define COND \ | |
1398 | ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) | |
1399 | ||
1400 | if (COND) | |
1401 | goto out; | |
1402 | ||
1403 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
1404 | ctrl &= ~DP_SSC_MASK(pipe); | |
1405 | ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); | |
1406 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); | |
1407 | ||
1408 | if (wait_for(COND, 100)) | |
7e35ab88 | 1409 | DRM_ERROR("timeout setting power well state %08x (%08x)\n", |
9c065a7d DV |
1410 | state, |
1411 | vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); | |
1412 | ||
1413 | #undef COND | |
1414 | ||
1415 | out: | |
1416 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1417 | } | |
1418 | ||
1419 | static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
1420 | struct i915_power_well *power_well) | |
1421 | { | |
8fcd5cd8 VS |
1422 | WARN_ON_ONCE(power_well->data != PIPE_A); |
1423 | ||
9c065a7d DV |
1424 | chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); |
1425 | } | |
1426 | ||
1427 | static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, | |
1428 | struct i915_power_well *power_well) | |
1429 | { | |
8fcd5cd8 | 1430 | WARN_ON_ONCE(power_well->data != PIPE_A); |
9c065a7d DV |
1431 | |
1432 | chv_set_pipe_power_well(dev_priv, power_well, true); | |
afd6275d | 1433 | |
2be7d540 | 1434 | vlv_display_power_well_init(dev_priv); |
9c065a7d DV |
1435 | } |
1436 | ||
1437 | static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, | |
1438 | struct i915_power_well *power_well) | |
1439 | { | |
8fcd5cd8 VS |
1440 | WARN_ON_ONCE(power_well->data != PIPE_A); |
1441 | ||
2be7d540 | 1442 | vlv_display_power_well_deinit(dev_priv); |
afd6275d | 1443 | |
9c065a7d DV |
1444 | chv_set_pipe_power_well(dev_priv, power_well, false); |
1445 | } | |
1446 | ||
e4e7684f DV |
1447 | /** |
1448 | * intel_display_power_get - grab a power domain reference | |
1449 | * @dev_priv: i915 device instance | |
1450 | * @domain: power domain to reference | |
1451 | * | |
1452 | * This function grabs a power domain reference for @domain and ensures that the | |
1453 | * power domain and all its parents are powered up. Therefore users should only | |
1454 | * grab a reference to the innermost power domain they need. | |
1455 | * | |
1456 | * Any power domain reference obtained by this function must have a symmetric | |
1457 | * call to intel_display_power_put() to release the reference again. | |
1458 | */ | |
9c065a7d DV |
1459 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
1460 | enum intel_display_power_domain domain) | |
1461 | { | |
1462 | struct i915_power_domains *power_domains; | |
1463 | struct i915_power_well *power_well; | |
1464 | int i; | |
1465 | ||
1466 | intel_runtime_pm_get(dev_priv); | |
1467 | ||
1468 | power_domains = &dev_priv->power_domains; | |
1469 | ||
1470 | mutex_lock(&power_domains->lock); | |
1471 | ||
1472 | for_each_power_well(i, power_well, BIT(domain), power_domains) { | |
e8ca9320 DL |
1473 | if (!power_well->count++) |
1474 | intel_power_well_enable(dev_priv, power_well); | |
9c065a7d DV |
1475 | } |
1476 | ||
1477 | power_domains->domain_use_count[domain]++; | |
1478 | ||
1479 | mutex_unlock(&power_domains->lock); | |
1480 | } | |
1481 | ||
e4e7684f DV |
1482 | /** |
1483 | * intel_display_power_put - release a power domain reference | |
1484 | * @dev_priv: i915 device instance | |
1485 | * @domain: power domain to reference | |
1486 | * | |
1487 | * This function drops the power domain reference obtained by | |
1488 | * intel_display_power_get() and might power down the corresponding hardware | |
1489 | * block right away if this is the last reference. | |
1490 | */ | |
9c065a7d DV |
1491 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
1492 | enum intel_display_power_domain domain) | |
1493 | { | |
1494 | struct i915_power_domains *power_domains; | |
1495 | struct i915_power_well *power_well; | |
1496 | int i; | |
1497 | ||
1498 | power_domains = &dev_priv->power_domains; | |
1499 | ||
1500 | mutex_lock(&power_domains->lock); | |
1501 | ||
11c86db8 DS |
1502 | WARN(!power_domains->domain_use_count[domain], |
1503 | "Use count on domain %s is already zero\n", | |
1504 | intel_display_power_domain_str(domain)); | |
9c065a7d DV |
1505 | power_domains->domain_use_count[domain]--; |
1506 | ||
1507 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { | |
11c86db8 DS |
1508 | WARN(!power_well->count, |
1509 | "Use count on power well %s is already zero", | |
1510 | power_well->name); | |
9c065a7d | 1511 | |
d314cd43 | 1512 | if (!--power_well->count) |
dcddab3a | 1513 | intel_power_well_disable(dev_priv, power_well); |
9c065a7d DV |
1514 | } |
1515 | ||
1516 | mutex_unlock(&power_domains->lock); | |
1517 | ||
1518 | intel_runtime_pm_put(dev_priv); | |
1519 | } | |
1520 | ||
9c065a7d DV |
1521 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ |
1522 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
1523 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ | |
6331a704 PJ |
1524 | BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ |
1525 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ | |
1526 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ | |
1527 | BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ | |
9c065a7d DV |
1528 | BIT(POWER_DOMAIN_PORT_CRT) | \ |
1529 | BIT(POWER_DOMAIN_PLLS) | \ | |
1407121a S |
1530 | BIT(POWER_DOMAIN_AUX_A) | \ |
1531 | BIT(POWER_DOMAIN_AUX_B) | \ | |
1532 | BIT(POWER_DOMAIN_AUX_C) | \ | |
1533 | BIT(POWER_DOMAIN_AUX_D) | \ | |
f0ab43e6 | 1534 | BIT(POWER_DOMAIN_GMBUS) | \ |
9c065a7d DV |
1535 | BIT(POWER_DOMAIN_INIT)) |
1536 | #define HSW_DISPLAY_POWER_DOMAINS ( \ | |
1537 | (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ | |
1538 | BIT(POWER_DOMAIN_INIT)) | |
1539 | ||
1540 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ | |
1541 | HSW_ALWAYS_ON_POWER_DOMAINS | \ | |
1542 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) | |
1543 | #define BDW_DISPLAY_POWER_DOMAINS ( \ | |
1544 | (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ | |
1545 | BIT(POWER_DOMAIN_INIT)) | |
1546 | ||
1547 | #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) | |
1548 | #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK | |
1549 | ||
1550 | #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ | |
6331a704 PJ |
1551 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
1552 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ | |
9c065a7d | 1553 | BIT(POWER_DOMAIN_PORT_CRT) | \ |
1407121a S |
1554 | BIT(POWER_DOMAIN_AUX_B) | \ |
1555 | BIT(POWER_DOMAIN_AUX_C) | \ | |
9c065a7d DV |
1556 | BIT(POWER_DOMAIN_INIT)) |
1557 | ||
1558 | #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ | |
6331a704 | 1559 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
1407121a | 1560 | BIT(POWER_DOMAIN_AUX_B) | \ |
9c065a7d DV |
1561 | BIT(POWER_DOMAIN_INIT)) |
1562 | ||
1563 | #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ | |
6331a704 | 1564 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
1407121a | 1565 | BIT(POWER_DOMAIN_AUX_B) | \ |
9c065a7d DV |
1566 | BIT(POWER_DOMAIN_INIT)) |
1567 | ||
1568 | #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ | |
6331a704 | 1569 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ |
1407121a | 1570 | BIT(POWER_DOMAIN_AUX_C) | \ |
9c065a7d DV |
1571 | BIT(POWER_DOMAIN_INIT)) |
1572 | ||
1573 | #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ | |
6331a704 | 1574 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ |
1407121a | 1575 | BIT(POWER_DOMAIN_AUX_C) | \ |
9c065a7d DV |
1576 | BIT(POWER_DOMAIN_INIT)) |
1577 | ||
9c065a7d | 1578 | #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ |
6331a704 PJ |
1579 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
1580 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ | |
1407121a S |
1581 | BIT(POWER_DOMAIN_AUX_B) | \ |
1582 | BIT(POWER_DOMAIN_AUX_C) | \ | |
9c065a7d DV |
1583 | BIT(POWER_DOMAIN_INIT)) |
1584 | ||
1585 | #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ | |
6331a704 | 1586 | BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ |
1407121a | 1587 | BIT(POWER_DOMAIN_AUX_D) | \ |
9c065a7d DV |
1588 | BIT(POWER_DOMAIN_INIT)) |
1589 | ||
9c065a7d DV |
1590 | static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { |
1591 | .sync_hw = i9xx_always_on_power_well_noop, | |
1592 | .enable = i9xx_always_on_power_well_noop, | |
1593 | .disable = i9xx_always_on_power_well_noop, | |
1594 | .is_enabled = i9xx_always_on_power_well_enabled, | |
1595 | }; | |
1596 | ||
1597 | static const struct i915_power_well_ops chv_pipe_power_well_ops = { | |
1598 | .sync_hw = chv_pipe_power_well_sync_hw, | |
1599 | .enable = chv_pipe_power_well_enable, | |
1600 | .disable = chv_pipe_power_well_disable, | |
1601 | .is_enabled = chv_pipe_power_well_enabled, | |
1602 | }; | |
1603 | ||
1604 | static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { | |
1605 | .sync_hw = vlv_power_well_sync_hw, | |
1606 | .enable = chv_dpio_cmn_power_well_enable, | |
1607 | .disable = chv_dpio_cmn_power_well_disable, | |
1608 | .is_enabled = vlv_power_well_enabled, | |
1609 | }; | |
1610 | ||
1611 | static struct i915_power_well i9xx_always_on_power_well[] = { | |
1612 | { | |
1613 | .name = "always-on", | |
1614 | .always_on = 1, | |
1615 | .domains = POWER_DOMAIN_MASK, | |
1616 | .ops = &i9xx_always_on_power_well_ops, | |
1617 | }, | |
1618 | }; | |
1619 | ||
1620 | static const struct i915_power_well_ops hsw_power_well_ops = { | |
1621 | .sync_hw = hsw_power_well_sync_hw, | |
1622 | .enable = hsw_power_well_enable, | |
1623 | .disable = hsw_power_well_disable, | |
1624 | .is_enabled = hsw_power_well_enabled, | |
1625 | }; | |
1626 | ||
94dd5138 S |
1627 | static const struct i915_power_well_ops skl_power_well_ops = { |
1628 | .sync_hw = skl_power_well_sync_hw, | |
1629 | .enable = skl_power_well_enable, | |
1630 | .disable = skl_power_well_disable, | |
1631 | .is_enabled = skl_power_well_enabled, | |
1632 | }; | |
1633 | ||
9f836f90 PJ |
1634 | static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { |
1635 | .sync_hw = gen9_dc_off_power_well_sync_hw, | |
1636 | .enable = gen9_dc_off_power_well_enable, | |
1637 | .disable = gen9_dc_off_power_well_disable, | |
1638 | .is_enabled = gen9_dc_off_power_well_enabled, | |
1639 | }; | |
1640 | ||
9c065a7d DV |
1641 | static struct i915_power_well hsw_power_wells[] = { |
1642 | { | |
1643 | .name = "always-on", | |
1644 | .always_on = 1, | |
1645 | .domains = HSW_ALWAYS_ON_POWER_DOMAINS, | |
1646 | .ops = &i9xx_always_on_power_well_ops, | |
1647 | }, | |
1648 | { | |
1649 | .name = "display", | |
1650 | .domains = HSW_DISPLAY_POWER_DOMAINS, | |
1651 | .ops = &hsw_power_well_ops, | |
1652 | }, | |
1653 | }; | |
1654 | ||
1655 | static struct i915_power_well bdw_power_wells[] = { | |
1656 | { | |
1657 | .name = "always-on", | |
1658 | .always_on = 1, | |
1659 | .domains = BDW_ALWAYS_ON_POWER_DOMAINS, | |
1660 | .ops = &i9xx_always_on_power_well_ops, | |
1661 | }, | |
1662 | { | |
1663 | .name = "display", | |
1664 | .domains = BDW_DISPLAY_POWER_DOMAINS, | |
1665 | .ops = &hsw_power_well_ops, | |
1666 | }, | |
1667 | }; | |
1668 | ||
1669 | static const struct i915_power_well_ops vlv_display_power_well_ops = { | |
1670 | .sync_hw = vlv_power_well_sync_hw, | |
1671 | .enable = vlv_display_power_well_enable, | |
1672 | .disable = vlv_display_power_well_disable, | |
1673 | .is_enabled = vlv_power_well_enabled, | |
1674 | }; | |
1675 | ||
1676 | static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { | |
1677 | .sync_hw = vlv_power_well_sync_hw, | |
1678 | .enable = vlv_dpio_cmn_power_well_enable, | |
1679 | .disable = vlv_dpio_cmn_power_well_disable, | |
1680 | .is_enabled = vlv_power_well_enabled, | |
1681 | }; | |
1682 | ||
1683 | static const struct i915_power_well_ops vlv_dpio_power_well_ops = { | |
1684 | .sync_hw = vlv_power_well_sync_hw, | |
1685 | .enable = vlv_power_well_enable, | |
1686 | .disable = vlv_power_well_disable, | |
1687 | .is_enabled = vlv_power_well_enabled, | |
1688 | }; | |
1689 | ||
1690 | static struct i915_power_well vlv_power_wells[] = { | |
1691 | { | |
1692 | .name = "always-on", | |
1693 | .always_on = 1, | |
1694 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, | |
1695 | .ops = &i9xx_always_on_power_well_ops, | |
56fcfd63 | 1696 | .data = PUNIT_POWER_WELL_ALWAYS_ON, |
9c065a7d DV |
1697 | }, |
1698 | { | |
1699 | .name = "display", | |
1700 | .domains = VLV_DISPLAY_POWER_DOMAINS, | |
1701 | .data = PUNIT_POWER_WELL_DISP2D, | |
1702 | .ops = &vlv_display_power_well_ops, | |
1703 | }, | |
1704 | { | |
1705 | .name = "dpio-tx-b-01", | |
1706 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1707 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1708 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1709 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1710 | .ops = &vlv_dpio_power_well_ops, | |
1711 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, | |
1712 | }, | |
1713 | { | |
1714 | .name = "dpio-tx-b-23", | |
1715 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1716 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1717 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1718 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1719 | .ops = &vlv_dpio_power_well_ops, | |
1720 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, | |
1721 | }, | |
1722 | { | |
1723 | .name = "dpio-tx-c-01", | |
1724 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1725 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1726 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1727 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1728 | .ops = &vlv_dpio_power_well_ops, | |
1729 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, | |
1730 | }, | |
1731 | { | |
1732 | .name = "dpio-tx-c-23", | |
1733 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1734 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1735 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1736 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1737 | .ops = &vlv_dpio_power_well_ops, | |
1738 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, | |
1739 | }, | |
1740 | { | |
1741 | .name = "dpio-common", | |
1742 | .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, | |
1743 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, | |
1744 | .ops = &vlv_dpio_cmn_power_well_ops, | |
1745 | }, | |
1746 | }; | |
1747 | ||
1748 | static struct i915_power_well chv_power_wells[] = { | |
1749 | { | |
1750 | .name = "always-on", | |
1751 | .always_on = 1, | |
1752 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, | |
1753 | .ops = &i9xx_always_on_power_well_ops, | |
1754 | }, | |
9c065a7d DV |
1755 | { |
1756 | .name = "display", | |
baa4e575 | 1757 | /* |
fde61e4b VS |
1758 | * Pipe A power well is the new disp2d well. Pipe B and C |
1759 | * power wells don't actually exist. Pipe A power well is | |
1760 | * required for any pipe to work. | |
baa4e575 | 1761 | */ |
fde61e4b | 1762 | .domains = VLV_DISPLAY_POWER_DOMAINS, |
9c065a7d DV |
1763 | .data = PIPE_A, |
1764 | .ops = &chv_pipe_power_well_ops, | |
1765 | }, | |
9c065a7d DV |
1766 | { |
1767 | .name = "dpio-common-bc", | |
71849b67 | 1768 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, |
9c065a7d DV |
1769 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, |
1770 | .ops = &chv_dpio_cmn_power_well_ops, | |
1771 | }, | |
1772 | { | |
1773 | .name = "dpio-common-d", | |
71849b67 | 1774 | .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, |
9c065a7d DV |
1775 | .data = PUNIT_POWER_WELL_DPIO_CMN_D, |
1776 | .ops = &chv_dpio_cmn_power_well_ops, | |
1777 | }, | |
9c065a7d DV |
1778 | }; |
1779 | ||
5aefb239 SS |
1780 | bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, |
1781 | int power_well_id) | |
1782 | { | |
1783 | struct i915_power_well *power_well; | |
1784 | bool ret; | |
1785 | ||
1786 | power_well = lookup_power_well(dev_priv, power_well_id); | |
1787 | ret = power_well->ops->is_enabled(dev_priv, power_well); | |
1788 | ||
1789 | return ret; | |
1790 | } | |
1791 | ||
94dd5138 S |
1792 | static struct i915_power_well skl_power_wells[] = { |
1793 | { | |
1794 | .name = "always-on", | |
1795 | .always_on = 1, | |
1796 | .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS, | |
1797 | .ops = &i9xx_always_on_power_well_ops, | |
56fcfd63 | 1798 | .data = SKL_DISP_PW_ALWAYS_ON, |
94dd5138 S |
1799 | }, |
1800 | { | |
1801 | .name = "power well 1", | |
4a76f295 ID |
1802 | /* Handled by the DMC firmware */ |
1803 | .domains = 0, | |
94dd5138 S |
1804 | .ops = &skl_power_well_ops, |
1805 | .data = SKL_DISP_PW_1, | |
1806 | }, | |
1807 | { | |
1808 | .name = "MISC IO power well", | |
4a76f295 ID |
1809 | /* Handled by the DMC firmware */ |
1810 | .domains = 0, | |
94dd5138 S |
1811 | .ops = &skl_power_well_ops, |
1812 | .data = SKL_DISP_PW_MISC_IO, | |
1813 | }, | |
9f836f90 PJ |
1814 | { |
1815 | .name = "DC off", | |
1816 | .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS, | |
1817 | .ops = &gen9_dc_off_power_well_ops, | |
1818 | .data = SKL_DISP_PW_DC_OFF, | |
1819 | }, | |
94dd5138 S |
1820 | { |
1821 | .name = "power well 2", | |
1822 | .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, | |
1823 | .ops = &skl_power_well_ops, | |
1824 | .data = SKL_DISP_PW_2, | |
1825 | }, | |
1826 | { | |
1827 | .name = "DDI A/E power well", | |
1828 | .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS, | |
1829 | .ops = &skl_power_well_ops, | |
1830 | .data = SKL_DISP_PW_DDI_A_E, | |
1831 | }, | |
1832 | { | |
1833 | .name = "DDI B power well", | |
1834 | .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS, | |
1835 | .ops = &skl_power_well_ops, | |
1836 | .data = SKL_DISP_PW_DDI_B, | |
1837 | }, | |
1838 | { | |
1839 | .name = "DDI C power well", | |
1840 | .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS, | |
1841 | .ops = &skl_power_well_ops, | |
1842 | .data = SKL_DISP_PW_DDI_C, | |
1843 | }, | |
1844 | { | |
1845 | .name = "DDI D power well", | |
1846 | .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS, | |
1847 | .ops = &skl_power_well_ops, | |
1848 | .data = SKL_DISP_PW_DDI_D, | |
1849 | }, | |
1850 | }; | |
1851 | ||
2f693e28 DL |
1852 | void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv) |
1853 | { | |
1854 | struct i915_power_well *well; | |
1855 | ||
1856 | if (!IS_SKYLAKE(dev_priv)) | |
1857 | return; | |
1858 | ||
1859 | well = lookup_power_well(dev_priv, SKL_DISP_PW_1); | |
1860 | intel_power_well_enable(dev_priv, well); | |
1861 | ||
1862 | well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); | |
1863 | intel_power_well_enable(dev_priv, well); | |
1864 | } | |
1865 | ||
1866 | void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv) | |
1867 | { | |
1868 | struct i915_power_well *well; | |
1869 | ||
1870 | if (!IS_SKYLAKE(dev_priv)) | |
1871 | return; | |
1872 | ||
1873 | well = lookup_power_well(dev_priv, SKL_DISP_PW_1); | |
1874 | intel_power_well_disable(dev_priv, well); | |
1875 | ||
1876 | well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); | |
1877 | intel_power_well_disable(dev_priv, well); | |
1878 | } | |
1879 | ||
0b4a2a36 S |
1880 | static struct i915_power_well bxt_power_wells[] = { |
1881 | { | |
1882 | .name = "always-on", | |
1883 | .always_on = 1, | |
1884 | .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS, | |
1885 | .ops = &i9xx_always_on_power_well_ops, | |
1886 | }, | |
1887 | { | |
1888 | .name = "power well 1", | |
1889 | .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS, | |
1890 | .ops = &skl_power_well_ops, | |
1891 | .data = SKL_DISP_PW_1, | |
1892 | }, | |
9f836f90 PJ |
1893 | { |
1894 | .name = "DC off", | |
1895 | .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS, | |
1896 | .ops = &gen9_dc_off_power_well_ops, | |
1897 | .data = SKL_DISP_PW_DC_OFF, | |
1898 | }, | |
0b4a2a36 S |
1899 | { |
1900 | .name = "power well 2", | |
1901 | .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, | |
1902 | .ops = &skl_power_well_ops, | |
1903 | .data = SKL_DISP_PW_2, | |
9f836f90 | 1904 | }, |
0b4a2a36 S |
1905 | }; |
1906 | ||
1b0e3a04 ID |
1907 | static int |
1908 | sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, | |
1909 | int disable_power_well) | |
1910 | { | |
1911 | if (disable_power_well >= 0) | |
1912 | return !!disable_power_well; | |
1913 | ||
18024199 MR |
1914 | if (IS_BROXTON(dev_priv)) { |
1915 | DRM_DEBUG_KMS("Disabling display power well support\n"); | |
1916 | return 0; | |
1917 | } | |
1918 | ||
1b0e3a04 ID |
1919 | return 1; |
1920 | } | |
1921 | ||
9c065a7d DV |
1922 | #define set_power_wells(power_domains, __power_wells) ({ \ |
1923 | (power_domains)->power_wells = (__power_wells); \ | |
1924 | (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ | |
1925 | }) | |
1926 | ||
e4e7684f DV |
1927 | /** |
1928 | * intel_power_domains_init - initializes the power domain structures | |
1929 | * @dev_priv: i915 device instance | |
1930 | * | |
1931 | * Initializes the power domain structures for @dev_priv depending upon the | |
1932 | * supported platform. | |
1933 | */ | |
9c065a7d DV |
1934 | int intel_power_domains_init(struct drm_i915_private *dev_priv) |
1935 | { | |
1936 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1937 | ||
1b0e3a04 ID |
1938 | i915.disable_power_well = sanitize_disable_power_well_option(dev_priv, |
1939 | i915.disable_power_well); | |
1940 | ||
f0ab43e6 VS |
1941 | BUILD_BUG_ON(POWER_DOMAIN_NUM > 31); |
1942 | ||
9c065a7d DV |
1943 | mutex_init(&power_domains->lock); |
1944 | ||
1945 | /* | |
1946 | * The enabling order will be from lower to higher indexed wells, | |
1947 | * the disabling order is reversed. | |
1948 | */ | |
1949 | if (IS_HASWELL(dev_priv->dev)) { | |
1950 | set_power_wells(power_domains, hsw_power_wells); | |
9c065a7d DV |
1951 | } else if (IS_BROADWELL(dev_priv->dev)) { |
1952 | set_power_wells(power_domains, bdw_power_wells); | |
ef11bdb3 | 1953 | } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) { |
94dd5138 | 1954 | set_power_wells(power_domains, skl_power_wells); |
0b4a2a36 S |
1955 | } else if (IS_BROXTON(dev_priv->dev)) { |
1956 | set_power_wells(power_domains, bxt_power_wells); | |
9c065a7d DV |
1957 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1958 | set_power_wells(power_domains, chv_power_wells); | |
1959 | } else if (IS_VALLEYVIEW(dev_priv->dev)) { | |
1960 | set_power_wells(power_domains, vlv_power_wells); | |
1961 | } else { | |
1962 | set_power_wells(power_domains, i9xx_always_on_power_well); | |
1963 | } | |
1964 | ||
1965 | return 0; | |
1966 | } | |
1967 | ||
e4e7684f DV |
1968 | /** |
1969 | * intel_power_domains_fini - finalizes the power domain structures | |
1970 | * @dev_priv: i915 device instance | |
1971 | * | |
1972 | * Finalizes the power domain structures for @dev_priv depending upon the | |
1973 | * supported platform. This function also disables runtime pm and ensures that | |
1974 | * the device stays powered up so that the driver can be reloaded. | |
1975 | */ | |
f458ebbc | 1976 | void intel_power_domains_fini(struct drm_i915_private *dev_priv) |
9c065a7d | 1977 | { |
f458ebbc DV |
1978 | /* The i915.ko module is still not prepared to be loaded when |
1979 | * the power well is not enabled, so just enable it in case | |
1980 | * we're going to unload/reload. */ | |
1981 | intel_display_set_init_power(dev_priv, true); | |
d314cd43 ID |
1982 | |
1983 | /* Remove the refcount we took to keep power well support disabled. */ | |
1984 | if (!i915.disable_power_well) | |
1985 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
9c065a7d DV |
1986 | } |
1987 | ||
30eade12 | 1988 | static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) |
9c065a7d DV |
1989 | { |
1990 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1991 | struct i915_power_well *power_well; | |
1992 | int i; | |
1993 | ||
1994 | mutex_lock(&power_domains->lock); | |
1995 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { | |
1996 | power_well->ops->sync_hw(dev_priv, power_well); | |
1997 | power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, | |
1998 | power_well); | |
1999 | } | |
2000 | mutex_unlock(&power_domains->lock); | |
2001 | } | |
2002 | ||
73dfc227 ID |
2003 | static void skl_display_core_init(struct drm_i915_private *dev_priv, |
2004 | bool resume) | |
2005 | { | |
2006 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2007 | uint32_t val; | |
2008 | ||
d26fa1d5 ID |
2009 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); |
2010 | ||
73dfc227 ID |
2011 | /* enable PCH reset handshake */ |
2012 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
2013 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); | |
2014 | ||
2015 | /* enable PG1 and Misc I/O */ | |
2016 | mutex_lock(&power_domains->lock); | |
2017 | skl_pw1_misc_io_init(dev_priv); | |
2018 | mutex_unlock(&power_domains->lock); | |
2019 | ||
2020 | if (!resume) | |
2021 | return; | |
2022 | ||
2023 | skl_init_cdclk(dev_priv); | |
2024 | ||
2025 | if (dev_priv->csr.dmc_payload) | |
2026 | intel_csr_load_program(dev_priv); | |
2027 | } | |
2028 | ||
2029 | static void skl_display_core_uninit(struct drm_i915_private *dev_priv) | |
2030 | { | |
2031 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2032 | ||
d26fa1d5 ID |
2033 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); |
2034 | ||
73dfc227 ID |
2035 | skl_uninit_cdclk(dev_priv); |
2036 | ||
2037 | /* The spec doesn't call for removing the reset handshake flag */ | |
2038 | /* disable PG1 and Misc I/O */ | |
2039 | mutex_lock(&power_domains->lock); | |
2040 | skl_pw1_misc_io_fini(dev_priv); | |
2041 | mutex_unlock(&power_domains->lock); | |
2042 | } | |
2043 | ||
70722468 VS |
2044 | static void chv_phy_control_init(struct drm_i915_private *dev_priv) |
2045 | { | |
2046 | struct i915_power_well *cmn_bc = | |
2047 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); | |
2048 | struct i915_power_well *cmn_d = | |
2049 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); | |
2050 | ||
2051 | /* | |
2052 | * DISPLAY_PHY_CONTROL can get corrupted if read. As a | |
2053 | * workaround never ever read DISPLAY_PHY_CONTROL, and | |
2054 | * instead maintain a shadow copy ourselves. Use the actual | |
e0fce78f VS |
2055 | * power well state and lane status to reconstruct the |
2056 | * expected initial value. | |
70722468 VS |
2057 | */ |
2058 | dev_priv->chv_phy_control = | |
bc284542 VS |
2059 | PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | |
2060 | PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | | |
e0fce78f VS |
2061 | PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | |
2062 | PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | | |
2063 | PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); | |
2064 | ||
2065 | /* | |
2066 | * If all lanes are disabled we leave the override disabled | |
2067 | * with all power down bits cleared to match the state we | |
2068 | * would use after disabling the port. Otherwise enable the | |
2069 | * override and set the lane powerdown bits accding to the | |
2070 | * current lane status. | |
2071 | */ | |
2072 | if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { | |
2073 | uint32_t status = I915_READ(DPLL(PIPE_A)); | |
2074 | unsigned int mask; | |
2075 | ||
2076 | mask = status & DPLL_PORTB_READY_MASK; | |
2077 | if (mask == 0xf) | |
2078 | mask = 0x0; | |
2079 | else | |
2080 | dev_priv->chv_phy_control |= | |
2081 | PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); | |
2082 | ||
2083 | dev_priv->chv_phy_control |= | |
2084 | PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); | |
2085 | ||
2086 | mask = (status & DPLL_PORTC_READY_MASK) >> 4; | |
2087 | if (mask == 0xf) | |
2088 | mask = 0x0; | |
2089 | else | |
2090 | dev_priv->chv_phy_control |= | |
2091 | PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); | |
2092 | ||
2093 | dev_priv->chv_phy_control |= | |
2094 | PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); | |
2095 | ||
70722468 | 2096 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); |
3be60de9 VS |
2097 | |
2098 | dev_priv->chv_phy_assert[DPIO_PHY0] = false; | |
2099 | } else { | |
2100 | dev_priv->chv_phy_assert[DPIO_PHY0] = true; | |
e0fce78f VS |
2101 | } |
2102 | ||
2103 | if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { | |
2104 | uint32_t status = I915_READ(DPIO_PHY_STATUS); | |
2105 | unsigned int mask; | |
2106 | ||
2107 | mask = status & DPLL_PORTD_READY_MASK; | |
2108 | ||
2109 | if (mask == 0xf) | |
2110 | mask = 0x0; | |
2111 | else | |
2112 | dev_priv->chv_phy_control |= | |
2113 | PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); | |
2114 | ||
2115 | dev_priv->chv_phy_control |= | |
2116 | PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); | |
2117 | ||
70722468 | 2118 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); |
3be60de9 VS |
2119 | |
2120 | dev_priv->chv_phy_assert[DPIO_PHY1] = false; | |
2121 | } else { | |
2122 | dev_priv->chv_phy_assert[DPIO_PHY1] = true; | |
e0fce78f VS |
2123 | } |
2124 | ||
2125 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); | |
2126 | ||
2127 | DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", | |
2128 | dev_priv->chv_phy_control); | |
70722468 VS |
2129 | } |
2130 | ||
9c065a7d DV |
2131 | static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) |
2132 | { | |
2133 | struct i915_power_well *cmn = | |
2134 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); | |
2135 | struct i915_power_well *disp2d = | |
2136 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); | |
2137 | ||
9c065a7d | 2138 | /* If the display might be already active skip this */ |
5d93a6e5 VS |
2139 | if (cmn->ops->is_enabled(dev_priv, cmn) && |
2140 | disp2d->ops->is_enabled(dev_priv, disp2d) && | |
9c065a7d DV |
2141 | I915_READ(DPIO_CTL) & DPIO_CMNRST) |
2142 | return; | |
2143 | ||
2144 | DRM_DEBUG_KMS("toggling display PHY side reset\n"); | |
2145 | ||
2146 | /* cmnlane needs DPLL registers */ | |
2147 | disp2d->ops->enable(dev_priv, disp2d); | |
2148 | ||
2149 | /* | |
2150 | * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: | |
2151 | * Need to assert and de-assert PHY SB reset by gating the | |
2152 | * common lane power, then un-gating it. | |
2153 | * Simply ungating isn't enough to reset the PHY enough to get | |
2154 | * ports and lanes running. | |
2155 | */ | |
2156 | cmn->ops->disable(dev_priv, cmn); | |
2157 | } | |
2158 | ||
e4e7684f DV |
2159 | /** |
2160 | * intel_power_domains_init_hw - initialize hardware power domain state | |
2161 | * @dev_priv: i915 device instance | |
2162 | * | |
2163 | * This function initializes the hardware power domain state and enables all | |
2164 | * power domains using intel_display_set_init_power(). | |
2165 | */ | |
73dfc227 | 2166 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) |
9c065a7d DV |
2167 | { |
2168 | struct drm_device *dev = dev_priv->dev; | |
2169 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2170 | ||
2171 | power_domains->initializing = true; | |
2172 | ||
73dfc227 ID |
2173 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
2174 | skl_display_core_init(dev_priv, resume); | |
2175 | } else if (IS_CHERRYVIEW(dev)) { | |
770effb1 | 2176 | mutex_lock(&power_domains->lock); |
70722468 | 2177 | chv_phy_control_init(dev_priv); |
770effb1 | 2178 | mutex_unlock(&power_domains->lock); |
70722468 | 2179 | } else if (IS_VALLEYVIEW(dev)) { |
9c065a7d DV |
2180 | mutex_lock(&power_domains->lock); |
2181 | vlv_cmnlane_wa(dev_priv); | |
2182 | mutex_unlock(&power_domains->lock); | |
2183 | } | |
2184 | ||
2185 | /* For now, we need the power well to be always enabled. */ | |
2186 | intel_display_set_init_power(dev_priv, true); | |
d314cd43 ID |
2187 | /* Disable power support if the user asked so. */ |
2188 | if (!i915.disable_power_well) | |
2189 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
30eade12 | 2190 | intel_power_domains_sync_hw(dev_priv); |
9c065a7d DV |
2191 | power_domains->initializing = false; |
2192 | } | |
2193 | ||
73dfc227 ID |
2194 | /** |
2195 | * intel_power_domains_suspend - suspend power domain state | |
2196 | * @dev_priv: i915 device instance | |
2197 | * | |
2198 | * This function prepares the hardware power domain state before entering | |
2199 | * system suspend. It must be paired with intel_power_domains_init_hw(). | |
2200 | */ | |
2201 | void intel_power_domains_suspend(struct drm_i915_private *dev_priv) | |
2202 | { | |
2203 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) | |
2204 | skl_display_core_uninit(dev_priv); | |
d314cd43 ID |
2205 | |
2206 | /* | |
2207 | * Even if power well support was disabled we still want to disable | |
2208 | * power wells while we are system suspended. | |
2209 | */ | |
2210 | if (!i915.disable_power_well) | |
2211 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
73dfc227 ID |
2212 | } |
2213 | ||
e4e7684f DV |
2214 | /** |
2215 | * intel_runtime_pm_get - grab a runtime pm reference | |
2216 | * @dev_priv: i915 device instance | |
2217 | * | |
2218 | * This function grabs a device-level runtime pm reference (mostly used for GEM | |
2219 | * code to ensure the GTT or GT is on) and ensures that it is powered up. | |
2220 | * | |
2221 | * Any runtime pm reference obtained by this function must have a symmetric | |
2222 | * call to intel_runtime_pm_put() to release the reference again. | |
2223 | */ | |
9c065a7d DV |
2224 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv) |
2225 | { | |
2226 | struct drm_device *dev = dev_priv->dev; | |
2227 | struct device *device = &dev->pdev->dev; | |
2228 | ||
2229 | if (!HAS_RUNTIME_PM(dev)) | |
2230 | return; | |
2231 | ||
2232 | pm_runtime_get_sync(device); | |
2233 | WARN(dev_priv->pm.suspended, "Device still suspended.\n"); | |
2234 | } | |
2235 | ||
e4e7684f DV |
2236 | /** |
2237 | * intel_runtime_pm_get_noresume - grab a runtime pm reference | |
2238 | * @dev_priv: i915 device instance | |
2239 | * | |
2240 | * This function grabs a device-level runtime pm reference (mostly used for GEM | |
2241 | * code to ensure the GTT or GT is on). | |
2242 | * | |
2243 | * It will _not_ power up the device but instead only check that it's powered | |
2244 | * on. Therefore it is only valid to call this functions from contexts where | |
2245 | * the device is known to be powered up and where trying to power it up would | |
2246 | * result in hilarity and deadlocks. That pretty much means only the system | |
2247 | * suspend/resume code where this is used to grab runtime pm references for | |
2248 | * delayed setup down in work items. | |
2249 | * | |
2250 | * Any runtime pm reference obtained by this function must have a symmetric | |
2251 | * call to intel_runtime_pm_put() to release the reference again. | |
2252 | */ | |
9c065a7d DV |
2253 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) |
2254 | { | |
2255 | struct drm_device *dev = dev_priv->dev; | |
2256 | struct device *device = &dev->pdev->dev; | |
2257 | ||
2258 | if (!HAS_RUNTIME_PM(dev)) | |
2259 | return; | |
2260 | ||
2261 | WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n"); | |
2262 | pm_runtime_get_noresume(device); | |
2263 | } | |
2264 | ||
e4e7684f DV |
2265 | /** |
2266 | * intel_runtime_pm_put - release a runtime pm reference | |
2267 | * @dev_priv: i915 device instance | |
2268 | * | |
2269 | * This function drops the device-level runtime pm reference obtained by | |
2270 | * intel_runtime_pm_get() and might power down the corresponding | |
2271 | * hardware block right away if this is the last reference. | |
2272 | */ | |
9c065a7d DV |
2273 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv) |
2274 | { | |
2275 | struct drm_device *dev = dev_priv->dev; | |
2276 | struct device *device = &dev->pdev->dev; | |
2277 | ||
2278 | if (!HAS_RUNTIME_PM(dev)) | |
2279 | return; | |
2280 | ||
2281 | pm_runtime_mark_last_busy(device); | |
2282 | pm_runtime_put_autosuspend(device); | |
2283 | } | |
2284 | ||
e4e7684f DV |
2285 | /** |
2286 | * intel_runtime_pm_enable - enable runtime pm | |
2287 | * @dev_priv: i915 device instance | |
2288 | * | |
2289 | * This function enables runtime pm at the end of the driver load sequence. | |
2290 | * | |
2291 | * Note that this function does currently not enable runtime pm for the | |
2292 | * subordinate display power domains. That is only done on the first modeset | |
2293 | * using intel_display_set_init_power(). | |
2294 | */ | |
f458ebbc | 2295 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) |
9c065a7d DV |
2296 | { |
2297 | struct drm_device *dev = dev_priv->dev; | |
2298 | struct device *device = &dev->pdev->dev; | |
2299 | ||
2300 | if (!HAS_RUNTIME_PM(dev)) | |
2301 | return; | |
2302 | ||
9c065a7d DV |
2303 | /* |
2304 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a | |
2305 | * requirement. | |
2306 | */ | |
2307 | if (!intel_enable_rc6(dev)) { | |
2308 | DRM_INFO("RC6 disabled, disabling runtime PM support\n"); | |
2309 | return; | |
2310 | } | |
2311 | ||
2312 | pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ | |
2313 | pm_runtime_mark_last_busy(device); | |
2314 | pm_runtime_use_autosuspend(device); | |
2315 | ||
2316 | pm_runtime_put_autosuspend(device); | |
2317 | } | |
2318 |