]>
Commit | Line | Data |
---|---|---|
9c065a7d DV |
1 | /* |
2 | * Copyright © 2012-2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * Daniel Vetter <daniel.vetter@ffwll.ch> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/pm_runtime.h> | |
30 | #include <linux/vgaarb.h> | |
31 | ||
32 | #include "i915_drv.h" | |
33 | #include "intel_drv.h" | |
9c065a7d | 34 | |
e4e7684f DV |
35 | /** |
36 | * DOC: runtime pm | |
37 | * | |
38 | * The i915 driver supports dynamic enabling and disabling of entire hardware | |
39 | * blocks at runtime. This is especially important on the display side where | |
40 | * software is supposed to control many power gates manually on recent hardware, | |
41 | * since on the GT side a lot of the power management is done by the hardware. | |
42 | * But even there some manual control at the device level is required. | |
43 | * | |
44 | * Since i915 supports a diverse set of platforms with a unified codebase and | |
45 | * hardware engineers just love to shuffle functionality around between power | |
46 | * domains there's a sizeable amount of indirection required. This file provides | |
47 | * generic functions to the driver for grabbing and releasing references for | |
48 | * abstract power domains. It then maps those to the actual power wells | |
49 | * present for a given platform. | |
50 | */ | |
51 | ||
9c065a7d DV |
52 | #define for_each_power_well(i, power_well, domain_mask, power_domains) \ |
53 | for (i = 0; \ | |
54 | i < (power_domains)->power_well_count && \ | |
55 | ((power_well) = &(power_domains)->power_wells[i]); \ | |
56 | i++) \ | |
57 | if ((power_well)->domains & (domain_mask)) | |
58 | ||
59 | #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ | |
60 | for (i = (power_domains)->power_well_count - 1; \ | |
61 | i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ | |
62 | i--) \ | |
63 | if ((power_well)->domains & (domain_mask)) | |
64 | ||
e4e7684f | 65 | /* |
9c065a7d DV |
66 | * We should only use the power well if we explicitly asked the hardware to |
67 | * enable it, so check if it's enabled and also check if we've requested it to | |
68 | * be enabled. | |
69 | */ | |
70 | static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, | |
71 | struct i915_power_well *power_well) | |
72 | { | |
73 | return I915_READ(HSW_PWR_WELL_DRIVER) == | |
74 | (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); | |
75 | } | |
76 | ||
e4e7684f DV |
77 | /** |
78 | * __intel_display_power_is_enabled - unlocked check for a power domain | |
79 | * @dev_priv: i915 device instance | |
80 | * @domain: power domain to check | |
81 | * | |
82 | * This is the unlocked version of intel_display_power_is_enabled() and should | |
83 | * only be used from error capture and recovery code where deadlocks are | |
84 | * possible. | |
85 | * | |
86 | * Returns: | |
87 | * True when the power domain is enabled, false otherwise. | |
88 | */ | |
f458ebbc DV |
89 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
90 | enum intel_display_power_domain domain) | |
9c065a7d DV |
91 | { |
92 | struct i915_power_domains *power_domains; | |
93 | struct i915_power_well *power_well; | |
94 | bool is_enabled; | |
95 | int i; | |
96 | ||
97 | if (dev_priv->pm.suspended) | |
98 | return false; | |
99 | ||
100 | power_domains = &dev_priv->power_domains; | |
101 | ||
102 | is_enabled = true; | |
103 | ||
104 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { | |
105 | if (power_well->always_on) | |
106 | continue; | |
107 | ||
108 | if (!power_well->hw_enabled) { | |
109 | is_enabled = false; | |
110 | break; | |
111 | } | |
112 | } | |
113 | ||
114 | return is_enabled; | |
115 | } | |
116 | ||
e4e7684f | 117 | /** |
f61ccae3 | 118 | * intel_display_power_is_enabled - check for a power domain |
e4e7684f DV |
119 | * @dev_priv: i915 device instance |
120 | * @domain: power domain to check | |
121 | * | |
122 | * This function can be used to check the hw power domain state. It is mostly | |
123 | * used in hardware state readout functions. Everywhere else code should rely | |
124 | * upon explicit power domain reference counting to ensure that the hardware | |
125 | * block is powered up before accessing it. | |
126 | * | |
127 | * Callers must hold the relevant modesetting locks to ensure that concurrent | |
128 | * threads can't disable the power well while the caller tries to read a few | |
129 | * registers. | |
130 | * | |
131 | * Returns: | |
132 | * True when the power domain is enabled, false otherwise. | |
133 | */ | |
f458ebbc DV |
134 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
135 | enum intel_display_power_domain domain) | |
9c065a7d DV |
136 | { |
137 | struct i915_power_domains *power_domains; | |
138 | bool ret; | |
139 | ||
140 | power_domains = &dev_priv->power_domains; | |
141 | ||
142 | mutex_lock(&power_domains->lock); | |
f458ebbc | 143 | ret = __intel_display_power_is_enabled(dev_priv, domain); |
9c065a7d DV |
144 | mutex_unlock(&power_domains->lock); |
145 | ||
146 | return ret; | |
147 | } | |
148 | ||
e4e7684f DV |
149 | /** |
150 | * intel_display_set_init_power - set the initial power domain state | |
151 | * @dev_priv: i915 device instance | |
152 | * @enable: whether to enable or disable the initial power domain state | |
153 | * | |
154 | * For simplicity our driver load/unload and system suspend/resume code assumes | |
155 | * that all power domains are always enabled. This functions controls the state | |
156 | * of this little hack. While the initial power domain state is enabled runtime | |
157 | * pm is effectively disabled. | |
158 | */ | |
d9bc89d9 DV |
159 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, |
160 | bool enable) | |
161 | { | |
162 | if (dev_priv->power_domains.init_power_on == enable) | |
163 | return; | |
164 | ||
165 | if (enable) | |
166 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
167 | else | |
168 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
169 | ||
170 | dev_priv->power_domains.init_power_on = enable; | |
171 | } | |
172 | ||
9c065a7d DV |
173 | /* |
174 | * Starting with Haswell, we have a "Power Down Well" that can be turned off | |
175 | * when not needed anymore. We have 4 registers that can request the power well | |
176 | * to be enabled, and it will only be disabled if none of the registers is | |
177 | * requesting it to be enabled. | |
178 | */ | |
179 | static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) | |
180 | { | |
181 | struct drm_device *dev = dev_priv->dev; | |
182 | ||
183 | /* | |
184 | * After we re-enable the power well, if we touch VGA register 0x3d5 | |
185 | * we'll get unclaimed register interrupts. This stops after we write | |
186 | * anything to the VGA MSR register. The vgacon module uses this | |
187 | * register all the time, so if we unbind our driver and, as a | |
188 | * consequence, bind vgacon, we'll get stuck in an infinite loop at | |
189 | * console_unlock(). So make here we touch the VGA MSR register, making | |
190 | * sure vgacon can keep working normally without triggering interrupts | |
191 | * and error messages. | |
192 | */ | |
193 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
194 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); | |
195 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
196 | ||
197 | if (IS_BROADWELL(dev) || (INTEL_INFO(dev)->gen >= 9)) | |
4c6c03be DL |
198 | gen8_irq_power_well_post_enable(dev_priv, |
199 | 1 << PIPE_C | 1 << PIPE_B); | |
9c065a7d DV |
200 | } |
201 | ||
202 | static void hsw_set_power_well(struct drm_i915_private *dev_priv, | |
203 | struct i915_power_well *power_well, bool enable) | |
204 | { | |
205 | bool is_enabled, enable_requested; | |
206 | uint32_t tmp; | |
207 | ||
208 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); | |
209 | is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; | |
210 | enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; | |
211 | ||
212 | if (enable) { | |
213 | if (!enable_requested) | |
214 | I915_WRITE(HSW_PWR_WELL_DRIVER, | |
215 | HSW_PWR_WELL_ENABLE_REQUEST); | |
216 | ||
217 | if (!is_enabled) { | |
218 | DRM_DEBUG_KMS("Enabling power well\n"); | |
219 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & | |
220 | HSW_PWR_WELL_STATE_ENABLED), 20)) | |
221 | DRM_ERROR("Timeout enabling power well\n"); | |
6d729bff | 222 | hsw_power_well_post_enable(dev_priv); |
9c065a7d DV |
223 | } |
224 | ||
9c065a7d DV |
225 | } else { |
226 | if (enable_requested) { | |
227 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); | |
228 | POSTING_READ(HSW_PWR_WELL_DRIVER); | |
229 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); | |
230 | } | |
231 | } | |
232 | } | |
233 | ||
94dd5138 S |
234 | #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ |
235 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ | |
236 | BIT(POWER_DOMAIN_PIPE_B) | \ | |
237 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ | |
238 | BIT(POWER_DOMAIN_PIPE_C) | \ | |
239 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ | |
240 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ | |
241 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ | |
242 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
243 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
244 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
245 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
246 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
247 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
248 | BIT(POWER_DOMAIN_AUX_B) | \ | |
249 | BIT(POWER_DOMAIN_AUX_C) | \ | |
250 | BIT(POWER_DOMAIN_AUX_D) | \ | |
251 | BIT(POWER_DOMAIN_AUDIO) | \ | |
252 | BIT(POWER_DOMAIN_VGA) | \ | |
253 | BIT(POWER_DOMAIN_INIT)) | |
254 | #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ | |
255 | SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ | |
256 | BIT(POWER_DOMAIN_PLLS) | \ | |
257 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
258 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ | |
259 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ | |
260 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ | |
261 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ | |
262 | BIT(POWER_DOMAIN_AUX_A) | \ | |
263 | BIT(POWER_DOMAIN_INIT)) | |
264 | #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \ | |
265 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ | |
266 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ | |
267 | BIT(POWER_DOMAIN_INIT)) | |
268 | #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \ | |
269 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
270 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
271 | BIT(POWER_DOMAIN_INIT)) | |
272 | #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \ | |
273 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
274 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
275 | BIT(POWER_DOMAIN_INIT)) | |
276 | #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \ | |
277 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
278 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
279 | BIT(POWER_DOMAIN_INIT)) | |
280 | #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \ | |
281 | SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS) | |
282 | #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ | |
283 | (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ | |
284 | SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ | |
285 | SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \ | |
286 | SKL_DISPLAY_DDI_B_POWER_DOMAINS | \ | |
287 | SKL_DISPLAY_DDI_C_POWER_DOMAINS | \ | |
288 | SKL_DISPLAY_DDI_D_POWER_DOMAINS | \ | |
289 | SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) | \ | |
290 | BIT(POWER_DOMAIN_INIT)) | |
291 | ||
292 | static void skl_set_power_well(struct drm_i915_private *dev_priv, | |
293 | struct i915_power_well *power_well, bool enable) | |
294 | { | |
295 | uint32_t tmp, fuse_status; | |
296 | uint32_t req_mask, state_mask; | |
2a51835f | 297 | bool is_enabled, enable_requested, check_fuse_status = false; |
94dd5138 S |
298 | |
299 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); | |
300 | fuse_status = I915_READ(SKL_FUSE_STATUS); | |
301 | ||
302 | switch (power_well->data) { | |
303 | case SKL_DISP_PW_1: | |
304 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & | |
305 | SKL_FUSE_PG0_DIST_STATUS), 1)) { | |
306 | DRM_ERROR("PG0 not enabled\n"); | |
307 | return; | |
308 | } | |
309 | break; | |
310 | case SKL_DISP_PW_2: | |
311 | if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { | |
312 | DRM_ERROR("PG1 in disabled state\n"); | |
313 | return; | |
314 | } | |
315 | break; | |
316 | case SKL_DISP_PW_DDI_A_E: | |
317 | case SKL_DISP_PW_DDI_B: | |
318 | case SKL_DISP_PW_DDI_C: | |
319 | case SKL_DISP_PW_DDI_D: | |
320 | case SKL_DISP_PW_MISC_IO: | |
321 | break; | |
322 | default: | |
323 | WARN(1, "Unknown power well %lu\n", power_well->data); | |
324 | return; | |
325 | } | |
326 | ||
327 | req_mask = SKL_POWER_WELL_REQ(power_well->data); | |
2a51835f | 328 | enable_requested = tmp & req_mask; |
94dd5138 | 329 | state_mask = SKL_POWER_WELL_STATE(power_well->data); |
2a51835f | 330 | is_enabled = tmp & state_mask; |
94dd5138 S |
331 | |
332 | if (enable) { | |
2a51835f | 333 | if (!enable_requested) { |
94dd5138 | 334 | I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); |
94dd5138 S |
335 | } |
336 | ||
2a51835f | 337 | if (!is_enabled) { |
510e6fdd | 338 | DRM_DEBUG_KMS("Enabling %s\n", power_well->name); |
94dd5138 S |
339 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & |
340 | state_mask), 1)) | |
341 | DRM_ERROR("%s enable timeout\n", | |
342 | power_well->name); | |
343 | check_fuse_status = true; | |
344 | } | |
345 | } else { | |
2a51835f | 346 | if (enable_requested) { |
94dd5138 S |
347 | I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); |
348 | POSTING_READ(HSW_PWR_WELL_DRIVER); | |
349 | DRM_DEBUG_KMS("Disabling %s\n", power_well->name); | |
350 | } | |
351 | } | |
352 | ||
353 | if (check_fuse_status) { | |
354 | if (power_well->data == SKL_DISP_PW_1) { | |
355 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & | |
356 | SKL_FUSE_PG1_DIST_STATUS), 1)) | |
357 | DRM_ERROR("PG1 distributing status timeout\n"); | |
358 | } else if (power_well->data == SKL_DISP_PW_2) { | |
359 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & | |
360 | SKL_FUSE_PG2_DIST_STATUS), 1)) | |
361 | DRM_ERROR("PG2 distributing status timeout\n"); | |
362 | } | |
363 | } | |
364 | } | |
365 | ||
9c065a7d DV |
366 | static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, |
367 | struct i915_power_well *power_well) | |
368 | { | |
369 | hsw_set_power_well(dev_priv, power_well, power_well->count > 0); | |
370 | ||
371 | /* | |
372 | * We're taking over the BIOS, so clear any requests made by it since | |
373 | * the driver is in charge now. | |
374 | */ | |
375 | if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) | |
376 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); | |
377 | } | |
378 | ||
379 | static void hsw_power_well_enable(struct drm_i915_private *dev_priv, | |
380 | struct i915_power_well *power_well) | |
381 | { | |
382 | hsw_set_power_well(dev_priv, power_well, true); | |
383 | } | |
384 | ||
385 | static void hsw_power_well_disable(struct drm_i915_private *dev_priv, | |
386 | struct i915_power_well *power_well) | |
387 | { | |
388 | hsw_set_power_well(dev_priv, power_well, false); | |
389 | } | |
390 | ||
94dd5138 S |
391 | static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, |
392 | struct i915_power_well *power_well) | |
393 | { | |
394 | uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) | | |
395 | SKL_POWER_WELL_STATE(power_well->data); | |
396 | ||
397 | return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; | |
398 | } | |
399 | ||
400 | static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
401 | struct i915_power_well *power_well) | |
402 | { | |
403 | skl_set_power_well(dev_priv, power_well, power_well->count > 0); | |
404 | ||
405 | /* Clear any request made by BIOS as driver is taking over */ | |
406 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); | |
407 | } | |
408 | ||
409 | static void skl_power_well_enable(struct drm_i915_private *dev_priv, | |
410 | struct i915_power_well *power_well) | |
411 | { | |
412 | skl_set_power_well(dev_priv, power_well, true); | |
413 | } | |
414 | ||
415 | static void skl_power_well_disable(struct drm_i915_private *dev_priv, | |
416 | struct i915_power_well *power_well) | |
417 | { | |
418 | skl_set_power_well(dev_priv, power_well, false); | |
419 | } | |
420 | ||
9c065a7d DV |
421 | static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, |
422 | struct i915_power_well *power_well) | |
423 | { | |
424 | } | |
425 | ||
426 | static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, | |
427 | struct i915_power_well *power_well) | |
428 | { | |
429 | return true; | |
430 | } | |
431 | ||
432 | static void vlv_set_power_well(struct drm_i915_private *dev_priv, | |
433 | struct i915_power_well *power_well, bool enable) | |
434 | { | |
435 | enum punit_power_well power_well_id = power_well->data; | |
436 | u32 mask; | |
437 | u32 state; | |
438 | u32 ctrl; | |
439 | ||
440 | mask = PUNIT_PWRGT_MASK(power_well_id); | |
441 | state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : | |
442 | PUNIT_PWRGT_PWR_GATE(power_well_id); | |
443 | ||
444 | mutex_lock(&dev_priv->rps.hw_lock); | |
445 | ||
446 | #define COND \ | |
447 | ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) | |
448 | ||
449 | if (COND) | |
450 | goto out; | |
451 | ||
452 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); | |
453 | ctrl &= ~mask; | |
454 | ctrl |= state; | |
455 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); | |
456 | ||
457 | if (wait_for(COND, 100)) | |
458 | DRM_ERROR("timout setting power well state %08x (%08x)\n", | |
459 | state, | |
460 | vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); | |
461 | ||
462 | #undef COND | |
463 | ||
464 | out: | |
465 | mutex_unlock(&dev_priv->rps.hw_lock); | |
466 | } | |
467 | ||
468 | static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
469 | struct i915_power_well *power_well) | |
470 | { | |
471 | vlv_set_power_well(dev_priv, power_well, power_well->count > 0); | |
472 | } | |
473 | ||
474 | static void vlv_power_well_enable(struct drm_i915_private *dev_priv, | |
475 | struct i915_power_well *power_well) | |
476 | { | |
477 | vlv_set_power_well(dev_priv, power_well, true); | |
478 | } | |
479 | ||
480 | static void vlv_power_well_disable(struct drm_i915_private *dev_priv, | |
481 | struct i915_power_well *power_well) | |
482 | { | |
483 | vlv_set_power_well(dev_priv, power_well, false); | |
484 | } | |
485 | ||
486 | static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, | |
487 | struct i915_power_well *power_well) | |
488 | { | |
489 | int power_well_id = power_well->data; | |
490 | bool enabled = false; | |
491 | u32 mask; | |
492 | u32 state; | |
493 | u32 ctrl; | |
494 | ||
495 | mask = PUNIT_PWRGT_MASK(power_well_id); | |
496 | ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); | |
497 | ||
498 | mutex_lock(&dev_priv->rps.hw_lock); | |
499 | ||
500 | state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; | |
501 | /* | |
502 | * We only ever set the power-on and power-gate states, anything | |
503 | * else is unexpected. | |
504 | */ | |
505 | WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && | |
506 | state != PUNIT_PWRGT_PWR_GATE(power_well_id)); | |
507 | if (state == ctrl) | |
508 | enabled = true; | |
509 | ||
510 | /* | |
511 | * A transient state at this point would mean some unexpected party | |
512 | * is poking at the power controls too. | |
513 | */ | |
514 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; | |
515 | WARN_ON(ctrl != state); | |
516 | ||
517 | mutex_unlock(&dev_priv->rps.hw_lock); | |
518 | ||
519 | return enabled; | |
520 | } | |
521 | ||
522 | static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, | |
523 | struct i915_power_well *power_well) | |
524 | { | |
525 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); | |
526 | ||
527 | vlv_set_power_well(dev_priv, power_well, true); | |
528 | ||
529 | spin_lock_irq(&dev_priv->irq_lock); | |
530 | valleyview_enable_display_irqs(dev_priv); | |
531 | spin_unlock_irq(&dev_priv->irq_lock); | |
532 | ||
533 | /* | |
534 | * During driver initialization/resume we can avoid restoring the | |
535 | * part of the HW/SW state that will be inited anyway explicitly. | |
536 | */ | |
537 | if (dev_priv->power_domains.initializing) | |
538 | return; | |
539 | ||
b963291c | 540 | intel_hpd_init(dev_priv); |
9c065a7d DV |
541 | |
542 | i915_redisable_vga_power_on(dev_priv->dev); | |
543 | } | |
544 | ||
545 | static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, | |
546 | struct i915_power_well *power_well) | |
547 | { | |
548 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); | |
549 | ||
550 | spin_lock_irq(&dev_priv->irq_lock); | |
551 | valleyview_disable_display_irqs(dev_priv); | |
552 | spin_unlock_irq(&dev_priv->irq_lock); | |
553 | ||
554 | vlv_set_power_well(dev_priv, power_well, false); | |
555 | ||
556 | vlv_power_sequencer_reset(dev_priv); | |
557 | } | |
558 | ||
559 | static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, | |
560 | struct i915_power_well *power_well) | |
561 | { | |
562 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); | |
563 | ||
564 | /* | |
565 | * Enable the CRI clock source so we can get at the | |
566 | * display and the reference clock for VGA | |
567 | * hotplug / manual detection. | |
568 | */ | |
569 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | | |
570 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); | |
571 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ | |
572 | ||
573 | vlv_set_power_well(dev_priv, power_well, true); | |
574 | ||
575 | /* | |
576 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
577 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
578 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
579 | * b. The other bits such as sfr settings / modesel may all | |
580 | * be set to 0. | |
581 | * | |
582 | * This should only be done on init and resume from S3 with | |
583 | * both PLLs disabled, or we risk losing DPIO and PLL | |
584 | * synchronization. | |
585 | */ | |
586 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
587 | } | |
588 | ||
589 | static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, | |
590 | struct i915_power_well *power_well) | |
591 | { | |
592 | enum pipe pipe; | |
593 | ||
594 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); | |
595 | ||
596 | for_each_pipe(dev_priv, pipe) | |
597 | assert_pll_disabled(dev_priv, pipe); | |
598 | ||
599 | /* Assert common reset */ | |
600 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); | |
601 | ||
602 | vlv_set_power_well(dev_priv, power_well, false); | |
603 | } | |
604 | ||
605 | static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, | |
606 | struct i915_power_well *power_well) | |
607 | { | |
608 | enum dpio_phy phy; | |
609 | ||
610 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && | |
611 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); | |
612 | ||
613 | /* | |
614 | * Enable the CRI clock source so we can get at the | |
615 | * display and the reference clock for VGA | |
616 | * hotplug / manual detection. | |
617 | */ | |
618 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { | |
619 | phy = DPIO_PHY0; | |
620 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | | |
621 | DPLL_REFA_CLK_ENABLE_VLV); | |
622 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | | |
623 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); | |
624 | } else { | |
625 | phy = DPIO_PHY1; | |
626 | I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | | |
627 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); | |
628 | } | |
629 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ | |
630 | vlv_set_power_well(dev_priv, power_well, true); | |
631 | ||
632 | /* Poll for phypwrgood signal */ | |
633 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) | |
634 | DRM_ERROR("Display PHY %d is not power up\n", phy); | |
635 | ||
636 | I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) | | |
637 | PHY_COM_LANE_RESET_DEASSERT(phy)); | |
638 | } | |
639 | ||
640 | static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, | |
641 | struct i915_power_well *power_well) | |
642 | { | |
643 | enum dpio_phy phy; | |
644 | ||
645 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && | |
646 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); | |
647 | ||
648 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { | |
649 | phy = DPIO_PHY0; | |
650 | assert_pll_disabled(dev_priv, PIPE_A); | |
651 | assert_pll_disabled(dev_priv, PIPE_B); | |
652 | } else { | |
653 | phy = DPIO_PHY1; | |
654 | assert_pll_disabled(dev_priv, PIPE_C); | |
655 | } | |
656 | ||
657 | I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) & | |
658 | ~PHY_COM_LANE_RESET_DEASSERT(phy)); | |
659 | ||
660 | vlv_set_power_well(dev_priv, power_well, false); | |
661 | } | |
662 | ||
663 | static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, | |
664 | struct i915_power_well *power_well) | |
665 | { | |
666 | enum pipe pipe = power_well->data; | |
667 | bool enabled; | |
668 | u32 state, ctrl; | |
669 | ||
670 | mutex_lock(&dev_priv->rps.hw_lock); | |
671 | ||
672 | state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); | |
673 | /* | |
674 | * We only ever set the power-on and power-gate states, anything | |
675 | * else is unexpected. | |
676 | */ | |
677 | WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); | |
678 | enabled = state == DP_SSS_PWR_ON(pipe); | |
679 | ||
680 | /* | |
681 | * A transient state at this point would mean some unexpected party | |
682 | * is poking at the power controls too. | |
683 | */ | |
684 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); | |
685 | WARN_ON(ctrl << 16 != state); | |
686 | ||
687 | mutex_unlock(&dev_priv->rps.hw_lock); | |
688 | ||
689 | return enabled; | |
690 | } | |
691 | ||
692 | static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, | |
693 | struct i915_power_well *power_well, | |
694 | bool enable) | |
695 | { | |
696 | enum pipe pipe = power_well->data; | |
697 | u32 state; | |
698 | u32 ctrl; | |
699 | ||
700 | state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); | |
701 | ||
702 | mutex_lock(&dev_priv->rps.hw_lock); | |
703 | ||
704 | #define COND \ | |
705 | ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) | |
706 | ||
707 | if (COND) | |
708 | goto out; | |
709 | ||
710 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
711 | ctrl &= ~DP_SSC_MASK(pipe); | |
712 | ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); | |
713 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); | |
714 | ||
715 | if (wait_for(COND, 100)) | |
716 | DRM_ERROR("timout setting power well state %08x (%08x)\n", | |
717 | state, | |
718 | vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); | |
719 | ||
720 | #undef COND | |
721 | ||
722 | out: | |
723 | mutex_unlock(&dev_priv->rps.hw_lock); | |
724 | } | |
725 | ||
726 | static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
727 | struct i915_power_well *power_well) | |
728 | { | |
729 | chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); | |
730 | } | |
731 | ||
732 | static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, | |
733 | struct i915_power_well *power_well) | |
734 | { | |
735 | WARN_ON_ONCE(power_well->data != PIPE_A && | |
736 | power_well->data != PIPE_B && | |
737 | power_well->data != PIPE_C); | |
738 | ||
739 | chv_set_pipe_power_well(dev_priv, power_well, true); | |
afd6275d VS |
740 | |
741 | if (power_well->data == PIPE_A) { | |
742 | spin_lock_irq(&dev_priv->irq_lock); | |
743 | valleyview_enable_display_irqs(dev_priv); | |
744 | spin_unlock_irq(&dev_priv->irq_lock); | |
745 | ||
746 | /* | |
747 | * During driver initialization/resume we can avoid restoring the | |
748 | * part of the HW/SW state that will be inited anyway explicitly. | |
749 | */ | |
750 | if (dev_priv->power_domains.initializing) | |
751 | return; | |
752 | ||
753 | intel_hpd_init(dev_priv); | |
754 | ||
755 | i915_redisable_vga_power_on(dev_priv->dev); | |
756 | } | |
9c065a7d DV |
757 | } |
758 | ||
759 | static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, | |
760 | struct i915_power_well *power_well) | |
761 | { | |
762 | WARN_ON_ONCE(power_well->data != PIPE_A && | |
763 | power_well->data != PIPE_B && | |
764 | power_well->data != PIPE_C); | |
765 | ||
afd6275d VS |
766 | if (power_well->data == PIPE_A) { |
767 | spin_lock_irq(&dev_priv->irq_lock); | |
768 | valleyview_disable_display_irqs(dev_priv); | |
769 | spin_unlock_irq(&dev_priv->irq_lock); | |
770 | } | |
771 | ||
9c065a7d | 772 | chv_set_pipe_power_well(dev_priv, power_well, false); |
baa4e575 VS |
773 | |
774 | if (power_well->data == PIPE_A) | |
775 | vlv_power_sequencer_reset(dev_priv); | |
9c065a7d DV |
776 | } |
777 | ||
e4e7684f DV |
778 | /** |
779 | * intel_display_power_get - grab a power domain reference | |
780 | * @dev_priv: i915 device instance | |
781 | * @domain: power domain to reference | |
782 | * | |
783 | * This function grabs a power domain reference for @domain and ensures that the | |
784 | * power domain and all its parents are powered up. Therefore users should only | |
785 | * grab a reference to the innermost power domain they need. | |
786 | * | |
787 | * Any power domain reference obtained by this function must have a symmetric | |
788 | * call to intel_display_power_put() to release the reference again. | |
789 | */ | |
9c065a7d DV |
790 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
791 | enum intel_display_power_domain domain) | |
792 | { | |
793 | struct i915_power_domains *power_domains; | |
794 | struct i915_power_well *power_well; | |
795 | int i; | |
796 | ||
797 | intel_runtime_pm_get(dev_priv); | |
798 | ||
799 | power_domains = &dev_priv->power_domains; | |
800 | ||
801 | mutex_lock(&power_domains->lock); | |
802 | ||
803 | for_each_power_well(i, power_well, BIT(domain), power_domains) { | |
804 | if (!power_well->count++) { | |
805 | DRM_DEBUG_KMS("enabling %s\n", power_well->name); | |
806 | power_well->ops->enable(dev_priv, power_well); | |
807 | power_well->hw_enabled = true; | |
808 | } | |
9c065a7d DV |
809 | } |
810 | ||
811 | power_domains->domain_use_count[domain]++; | |
812 | ||
813 | mutex_unlock(&power_domains->lock); | |
814 | } | |
815 | ||
e4e7684f DV |
816 | /** |
817 | * intel_display_power_put - release a power domain reference | |
818 | * @dev_priv: i915 device instance | |
819 | * @domain: power domain to reference | |
820 | * | |
821 | * This function drops the power domain reference obtained by | |
822 | * intel_display_power_get() and might power down the corresponding hardware | |
823 | * block right away if this is the last reference. | |
824 | */ | |
9c065a7d DV |
825 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
826 | enum intel_display_power_domain domain) | |
827 | { | |
828 | struct i915_power_domains *power_domains; | |
829 | struct i915_power_well *power_well; | |
830 | int i; | |
831 | ||
832 | power_domains = &dev_priv->power_domains; | |
833 | ||
834 | mutex_lock(&power_domains->lock); | |
835 | ||
836 | WARN_ON(!power_domains->domain_use_count[domain]); | |
837 | power_domains->domain_use_count[domain]--; | |
838 | ||
839 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { | |
840 | WARN_ON(!power_well->count); | |
841 | ||
842 | if (!--power_well->count && i915.disable_power_well) { | |
843 | DRM_DEBUG_KMS("disabling %s\n", power_well->name); | |
844 | power_well->hw_enabled = false; | |
845 | power_well->ops->disable(dev_priv, power_well); | |
846 | } | |
9c065a7d DV |
847 | } |
848 | ||
849 | mutex_unlock(&power_domains->lock); | |
850 | ||
851 | intel_runtime_pm_put(dev_priv); | |
852 | } | |
853 | ||
854 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) | |
855 | ||
856 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ | |
857 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
858 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ | |
859 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ | |
860 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ | |
861 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
862 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
863 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
864 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
865 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
866 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
867 | BIT(POWER_DOMAIN_PORT_CRT) | \ | |
868 | BIT(POWER_DOMAIN_PLLS) | \ | |
1407121a S |
869 | BIT(POWER_DOMAIN_AUX_A) | \ |
870 | BIT(POWER_DOMAIN_AUX_B) | \ | |
871 | BIT(POWER_DOMAIN_AUX_C) | \ | |
872 | BIT(POWER_DOMAIN_AUX_D) | \ | |
9c065a7d DV |
873 | BIT(POWER_DOMAIN_INIT)) |
874 | #define HSW_DISPLAY_POWER_DOMAINS ( \ | |
875 | (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ | |
876 | BIT(POWER_DOMAIN_INIT)) | |
877 | ||
878 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ | |
879 | HSW_ALWAYS_ON_POWER_DOMAINS | \ | |
880 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) | |
881 | #define BDW_DISPLAY_POWER_DOMAINS ( \ | |
882 | (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ | |
883 | BIT(POWER_DOMAIN_INIT)) | |
884 | ||
885 | #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) | |
886 | #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK | |
887 | ||
888 | #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ | |
889 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
890 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
891 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
892 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
893 | BIT(POWER_DOMAIN_PORT_CRT) | \ | |
1407121a S |
894 | BIT(POWER_DOMAIN_AUX_B) | \ |
895 | BIT(POWER_DOMAIN_AUX_C) | \ | |
9c065a7d DV |
896 | BIT(POWER_DOMAIN_INIT)) |
897 | ||
898 | #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ | |
899 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
900 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
1407121a | 901 | BIT(POWER_DOMAIN_AUX_B) | \ |
9c065a7d DV |
902 | BIT(POWER_DOMAIN_INIT)) |
903 | ||
904 | #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ | |
905 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
1407121a | 906 | BIT(POWER_DOMAIN_AUX_B) | \ |
9c065a7d DV |
907 | BIT(POWER_DOMAIN_INIT)) |
908 | ||
909 | #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ | |
910 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
911 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
1407121a | 912 | BIT(POWER_DOMAIN_AUX_C) | \ |
9c065a7d DV |
913 | BIT(POWER_DOMAIN_INIT)) |
914 | ||
915 | #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ | |
916 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
1407121a | 917 | BIT(POWER_DOMAIN_AUX_C) | \ |
9c065a7d DV |
918 | BIT(POWER_DOMAIN_INIT)) |
919 | ||
920 | #define CHV_PIPE_A_POWER_DOMAINS ( \ | |
921 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
922 | BIT(POWER_DOMAIN_INIT)) | |
923 | ||
924 | #define CHV_PIPE_B_POWER_DOMAINS ( \ | |
925 | BIT(POWER_DOMAIN_PIPE_B) | \ | |
926 | BIT(POWER_DOMAIN_INIT)) | |
927 | ||
928 | #define CHV_PIPE_C_POWER_DOMAINS ( \ | |
929 | BIT(POWER_DOMAIN_PIPE_C) | \ | |
930 | BIT(POWER_DOMAIN_INIT)) | |
931 | ||
932 | #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ | |
933 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
934 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
935 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
936 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
1407121a S |
937 | BIT(POWER_DOMAIN_AUX_B) | \ |
938 | BIT(POWER_DOMAIN_AUX_C) | \ | |
9c065a7d DV |
939 | BIT(POWER_DOMAIN_INIT)) |
940 | ||
941 | #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ | |
942 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
943 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
1407121a | 944 | BIT(POWER_DOMAIN_AUX_D) | \ |
9c065a7d DV |
945 | BIT(POWER_DOMAIN_INIT)) |
946 | ||
947 | #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \ | |
948 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
949 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
1407121a | 950 | BIT(POWER_DOMAIN_AUX_D) | \ |
9c065a7d DV |
951 | BIT(POWER_DOMAIN_INIT)) |
952 | ||
953 | #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \ | |
954 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
1407121a | 955 | BIT(POWER_DOMAIN_AUX_D) | \ |
9c065a7d DV |
956 | BIT(POWER_DOMAIN_INIT)) |
957 | ||
958 | static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { | |
959 | .sync_hw = i9xx_always_on_power_well_noop, | |
960 | .enable = i9xx_always_on_power_well_noop, | |
961 | .disable = i9xx_always_on_power_well_noop, | |
962 | .is_enabled = i9xx_always_on_power_well_enabled, | |
963 | }; | |
964 | ||
965 | static const struct i915_power_well_ops chv_pipe_power_well_ops = { | |
966 | .sync_hw = chv_pipe_power_well_sync_hw, | |
967 | .enable = chv_pipe_power_well_enable, | |
968 | .disable = chv_pipe_power_well_disable, | |
969 | .is_enabled = chv_pipe_power_well_enabled, | |
970 | }; | |
971 | ||
972 | static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { | |
973 | .sync_hw = vlv_power_well_sync_hw, | |
974 | .enable = chv_dpio_cmn_power_well_enable, | |
975 | .disable = chv_dpio_cmn_power_well_disable, | |
976 | .is_enabled = vlv_power_well_enabled, | |
977 | }; | |
978 | ||
979 | static struct i915_power_well i9xx_always_on_power_well[] = { | |
980 | { | |
981 | .name = "always-on", | |
982 | .always_on = 1, | |
983 | .domains = POWER_DOMAIN_MASK, | |
984 | .ops = &i9xx_always_on_power_well_ops, | |
985 | }, | |
986 | }; | |
987 | ||
988 | static const struct i915_power_well_ops hsw_power_well_ops = { | |
989 | .sync_hw = hsw_power_well_sync_hw, | |
990 | .enable = hsw_power_well_enable, | |
991 | .disable = hsw_power_well_disable, | |
992 | .is_enabled = hsw_power_well_enabled, | |
993 | }; | |
994 | ||
94dd5138 S |
995 | static const struct i915_power_well_ops skl_power_well_ops = { |
996 | .sync_hw = skl_power_well_sync_hw, | |
997 | .enable = skl_power_well_enable, | |
998 | .disable = skl_power_well_disable, | |
999 | .is_enabled = skl_power_well_enabled, | |
1000 | }; | |
1001 | ||
9c065a7d DV |
1002 | static struct i915_power_well hsw_power_wells[] = { |
1003 | { | |
1004 | .name = "always-on", | |
1005 | .always_on = 1, | |
1006 | .domains = HSW_ALWAYS_ON_POWER_DOMAINS, | |
1007 | .ops = &i9xx_always_on_power_well_ops, | |
1008 | }, | |
1009 | { | |
1010 | .name = "display", | |
1011 | .domains = HSW_DISPLAY_POWER_DOMAINS, | |
1012 | .ops = &hsw_power_well_ops, | |
1013 | }, | |
1014 | }; | |
1015 | ||
1016 | static struct i915_power_well bdw_power_wells[] = { | |
1017 | { | |
1018 | .name = "always-on", | |
1019 | .always_on = 1, | |
1020 | .domains = BDW_ALWAYS_ON_POWER_DOMAINS, | |
1021 | .ops = &i9xx_always_on_power_well_ops, | |
1022 | }, | |
1023 | { | |
1024 | .name = "display", | |
1025 | .domains = BDW_DISPLAY_POWER_DOMAINS, | |
1026 | .ops = &hsw_power_well_ops, | |
1027 | }, | |
1028 | }; | |
1029 | ||
1030 | static const struct i915_power_well_ops vlv_display_power_well_ops = { | |
1031 | .sync_hw = vlv_power_well_sync_hw, | |
1032 | .enable = vlv_display_power_well_enable, | |
1033 | .disable = vlv_display_power_well_disable, | |
1034 | .is_enabled = vlv_power_well_enabled, | |
1035 | }; | |
1036 | ||
1037 | static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { | |
1038 | .sync_hw = vlv_power_well_sync_hw, | |
1039 | .enable = vlv_dpio_cmn_power_well_enable, | |
1040 | .disable = vlv_dpio_cmn_power_well_disable, | |
1041 | .is_enabled = vlv_power_well_enabled, | |
1042 | }; | |
1043 | ||
1044 | static const struct i915_power_well_ops vlv_dpio_power_well_ops = { | |
1045 | .sync_hw = vlv_power_well_sync_hw, | |
1046 | .enable = vlv_power_well_enable, | |
1047 | .disable = vlv_power_well_disable, | |
1048 | .is_enabled = vlv_power_well_enabled, | |
1049 | }; | |
1050 | ||
1051 | static struct i915_power_well vlv_power_wells[] = { | |
1052 | { | |
1053 | .name = "always-on", | |
1054 | .always_on = 1, | |
1055 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, | |
1056 | .ops = &i9xx_always_on_power_well_ops, | |
1057 | }, | |
1058 | { | |
1059 | .name = "display", | |
1060 | .domains = VLV_DISPLAY_POWER_DOMAINS, | |
1061 | .data = PUNIT_POWER_WELL_DISP2D, | |
1062 | .ops = &vlv_display_power_well_ops, | |
1063 | }, | |
1064 | { | |
1065 | .name = "dpio-tx-b-01", | |
1066 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1067 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1068 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1069 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1070 | .ops = &vlv_dpio_power_well_ops, | |
1071 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, | |
1072 | }, | |
1073 | { | |
1074 | .name = "dpio-tx-b-23", | |
1075 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1076 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1077 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1078 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1079 | .ops = &vlv_dpio_power_well_ops, | |
1080 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, | |
1081 | }, | |
1082 | { | |
1083 | .name = "dpio-tx-c-01", | |
1084 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1085 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1086 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1087 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1088 | .ops = &vlv_dpio_power_well_ops, | |
1089 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, | |
1090 | }, | |
1091 | { | |
1092 | .name = "dpio-tx-c-23", | |
1093 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1094 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1095 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1096 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1097 | .ops = &vlv_dpio_power_well_ops, | |
1098 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, | |
1099 | }, | |
1100 | { | |
1101 | .name = "dpio-common", | |
1102 | .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, | |
1103 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, | |
1104 | .ops = &vlv_dpio_cmn_power_well_ops, | |
1105 | }, | |
1106 | }; | |
1107 | ||
1108 | static struct i915_power_well chv_power_wells[] = { | |
1109 | { | |
1110 | .name = "always-on", | |
1111 | .always_on = 1, | |
1112 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, | |
1113 | .ops = &i9xx_always_on_power_well_ops, | |
1114 | }, | |
1115 | #if 0 | |
1116 | { | |
1117 | .name = "display", | |
1118 | .domains = VLV_DISPLAY_POWER_DOMAINS, | |
1119 | .data = PUNIT_POWER_WELL_DISP2D, | |
1120 | .ops = &vlv_display_power_well_ops, | |
1121 | }, | |
baa4e575 | 1122 | #endif |
9c065a7d DV |
1123 | { |
1124 | .name = "pipe-a", | |
baa4e575 VS |
1125 | /* |
1126 | * FIXME: pipe A power well seems to be the new disp2d well. | |
1127 | * At least all registers seem to be housed there. Figure | |
1128 | * out if this a a temporary situation in pre-production | |
1129 | * hardware or a permanent state of affairs. | |
1130 | */ | |
1131 | .domains = CHV_PIPE_A_POWER_DOMAINS | VLV_DISPLAY_POWER_DOMAINS, | |
9c065a7d DV |
1132 | .data = PIPE_A, |
1133 | .ops = &chv_pipe_power_well_ops, | |
1134 | }, | |
baa4e575 | 1135 | #if 0 |
9c065a7d DV |
1136 | { |
1137 | .name = "pipe-b", | |
1138 | .domains = CHV_PIPE_B_POWER_DOMAINS, | |
1139 | .data = PIPE_B, | |
1140 | .ops = &chv_pipe_power_well_ops, | |
1141 | }, | |
1142 | { | |
1143 | .name = "pipe-c", | |
1144 | .domains = CHV_PIPE_C_POWER_DOMAINS, | |
1145 | .data = PIPE_C, | |
1146 | .ops = &chv_pipe_power_well_ops, | |
1147 | }, | |
1148 | #endif | |
1149 | { | |
1150 | .name = "dpio-common-bc", | |
1151 | /* | |
1152 | * XXX: cmnreset for one PHY seems to disturb the other. | |
1153 | * As a workaround keep both powered on at the same | |
1154 | * time for now. | |
1155 | */ | |
1156 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS, | |
1157 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, | |
1158 | .ops = &chv_dpio_cmn_power_well_ops, | |
1159 | }, | |
1160 | { | |
1161 | .name = "dpio-common-d", | |
1162 | /* | |
1163 | * XXX: cmnreset for one PHY seems to disturb the other. | |
1164 | * As a workaround keep both powered on at the same | |
1165 | * time for now. | |
1166 | */ | |
1167 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS, | |
1168 | .data = PUNIT_POWER_WELL_DPIO_CMN_D, | |
1169 | .ops = &chv_dpio_cmn_power_well_ops, | |
1170 | }, | |
1171 | #if 0 | |
1172 | { | |
1173 | .name = "dpio-tx-b-01", | |
1174 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1175 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, | |
1176 | .ops = &vlv_dpio_power_well_ops, | |
1177 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, | |
1178 | }, | |
1179 | { | |
1180 | .name = "dpio-tx-b-23", | |
1181 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1182 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, | |
1183 | .ops = &vlv_dpio_power_well_ops, | |
1184 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, | |
1185 | }, | |
1186 | { | |
1187 | .name = "dpio-tx-c-01", | |
1188 | .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1189 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1190 | .ops = &vlv_dpio_power_well_ops, | |
1191 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, | |
1192 | }, | |
1193 | { | |
1194 | .name = "dpio-tx-c-23", | |
1195 | .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1196 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1197 | .ops = &vlv_dpio_power_well_ops, | |
1198 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, | |
1199 | }, | |
1200 | { | |
1201 | .name = "dpio-tx-d-01", | |
1202 | .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | | |
1203 | CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, | |
1204 | .ops = &vlv_dpio_power_well_ops, | |
1205 | .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01, | |
1206 | }, | |
1207 | { | |
1208 | .name = "dpio-tx-d-23", | |
1209 | .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | | |
1210 | CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, | |
1211 | .ops = &vlv_dpio_power_well_ops, | |
1212 | .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23, | |
1213 | }, | |
1214 | #endif | |
1215 | }; | |
1216 | ||
1217 | static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, | |
1218 | enum punit_power_well power_well_id) | |
1219 | { | |
1220 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1221 | struct i915_power_well *power_well; | |
1222 | int i; | |
1223 | ||
1224 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { | |
1225 | if (power_well->data == power_well_id) | |
1226 | return power_well; | |
1227 | } | |
1228 | ||
1229 | return NULL; | |
1230 | } | |
1231 | ||
94dd5138 S |
1232 | static struct i915_power_well skl_power_wells[] = { |
1233 | { | |
1234 | .name = "always-on", | |
1235 | .always_on = 1, | |
1236 | .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS, | |
1237 | .ops = &i9xx_always_on_power_well_ops, | |
1238 | }, | |
1239 | { | |
1240 | .name = "power well 1", | |
1241 | .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS, | |
1242 | .ops = &skl_power_well_ops, | |
1243 | .data = SKL_DISP_PW_1, | |
1244 | }, | |
1245 | { | |
1246 | .name = "MISC IO power well", | |
1247 | .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS, | |
1248 | .ops = &skl_power_well_ops, | |
1249 | .data = SKL_DISP_PW_MISC_IO, | |
1250 | }, | |
1251 | { | |
1252 | .name = "power well 2", | |
1253 | .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, | |
1254 | .ops = &skl_power_well_ops, | |
1255 | .data = SKL_DISP_PW_2, | |
1256 | }, | |
1257 | { | |
1258 | .name = "DDI A/E power well", | |
1259 | .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS, | |
1260 | .ops = &skl_power_well_ops, | |
1261 | .data = SKL_DISP_PW_DDI_A_E, | |
1262 | }, | |
1263 | { | |
1264 | .name = "DDI B power well", | |
1265 | .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS, | |
1266 | .ops = &skl_power_well_ops, | |
1267 | .data = SKL_DISP_PW_DDI_B, | |
1268 | }, | |
1269 | { | |
1270 | .name = "DDI C power well", | |
1271 | .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS, | |
1272 | .ops = &skl_power_well_ops, | |
1273 | .data = SKL_DISP_PW_DDI_C, | |
1274 | }, | |
1275 | { | |
1276 | .name = "DDI D power well", | |
1277 | .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS, | |
1278 | .ops = &skl_power_well_ops, | |
1279 | .data = SKL_DISP_PW_DDI_D, | |
1280 | }, | |
1281 | }; | |
1282 | ||
9c065a7d DV |
1283 | #define set_power_wells(power_domains, __power_wells) ({ \ |
1284 | (power_domains)->power_wells = (__power_wells); \ | |
1285 | (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ | |
1286 | }) | |
1287 | ||
e4e7684f DV |
1288 | /** |
1289 | * intel_power_domains_init - initializes the power domain structures | |
1290 | * @dev_priv: i915 device instance | |
1291 | * | |
1292 | * Initializes the power domain structures for @dev_priv depending upon the | |
1293 | * supported platform. | |
1294 | */ | |
9c065a7d DV |
1295 | int intel_power_domains_init(struct drm_i915_private *dev_priv) |
1296 | { | |
1297 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1298 | ||
1299 | mutex_init(&power_domains->lock); | |
1300 | ||
1301 | /* | |
1302 | * The enabling order will be from lower to higher indexed wells, | |
1303 | * the disabling order is reversed. | |
1304 | */ | |
1305 | if (IS_HASWELL(dev_priv->dev)) { | |
1306 | set_power_wells(power_domains, hsw_power_wells); | |
9c065a7d DV |
1307 | } else if (IS_BROADWELL(dev_priv->dev)) { |
1308 | set_power_wells(power_domains, bdw_power_wells); | |
94dd5138 S |
1309 | } else if (IS_SKYLAKE(dev_priv->dev)) { |
1310 | set_power_wells(power_domains, skl_power_wells); | |
9c065a7d DV |
1311 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1312 | set_power_wells(power_domains, chv_power_wells); | |
1313 | } else if (IS_VALLEYVIEW(dev_priv->dev)) { | |
1314 | set_power_wells(power_domains, vlv_power_wells); | |
1315 | } else { | |
1316 | set_power_wells(power_domains, i9xx_always_on_power_well); | |
1317 | } | |
1318 | ||
1319 | return 0; | |
1320 | } | |
1321 | ||
41373cd5 DV |
1322 | static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv) |
1323 | { | |
1324 | struct drm_device *dev = dev_priv->dev; | |
1325 | struct device *device = &dev->pdev->dev; | |
1326 | ||
1327 | if (!HAS_RUNTIME_PM(dev)) | |
1328 | return; | |
1329 | ||
1330 | if (!intel_enable_rc6(dev)) | |
1331 | return; | |
1332 | ||
1333 | /* Make sure we're not suspended first. */ | |
1334 | pm_runtime_get_sync(device); | |
1335 | pm_runtime_disable(device); | |
1336 | } | |
1337 | ||
e4e7684f DV |
1338 | /** |
1339 | * intel_power_domains_fini - finalizes the power domain structures | |
1340 | * @dev_priv: i915 device instance | |
1341 | * | |
1342 | * Finalizes the power domain structures for @dev_priv depending upon the | |
1343 | * supported platform. This function also disables runtime pm and ensures that | |
1344 | * the device stays powered up so that the driver can be reloaded. | |
1345 | */ | |
f458ebbc | 1346 | void intel_power_domains_fini(struct drm_i915_private *dev_priv) |
9c065a7d | 1347 | { |
41373cd5 DV |
1348 | intel_runtime_pm_disable(dev_priv); |
1349 | ||
f458ebbc DV |
1350 | /* The i915.ko module is still not prepared to be loaded when |
1351 | * the power well is not enabled, so just enable it in case | |
1352 | * we're going to unload/reload. */ | |
1353 | intel_display_set_init_power(dev_priv, true); | |
9c065a7d DV |
1354 | } |
1355 | ||
1356 | static void intel_power_domains_resume(struct drm_i915_private *dev_priv) | |
1357 | { | |
1358 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1359 | struct i915_power_well *power_well; | |
1360 | int i; | |
1361 | ||
1362 | mutex_lock(&power_domains->lock); | |
1363 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { | |
1364 | power_well->ops->sync_hw(dev_priv, power_well); | |
1365 | power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, | |
1366 | power_well); | |
1367 | } | |
1368 | mutex_unlock(&power_domains->lock); | |
1369 | } | |
1370 | ||
1371 | static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) | |
1372 | { | |
1373 | struct i915_power_well *cmn = | |
1374 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); | |
1375 | struct i915_power_well *disp2d = | |
1376 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); | |
1377 | ||
9c065a7d | 1378 | /* If the display might be already active skip this */ |
5d93a6e5 VS |
1379 | if (cmn->ops->is_enabled(dev_priv, cmn) && |
1380 | disp2d->ops->is_enabled(dev_priv, disp2d) && | |
9c065a7d DV |
1381 | I915_READ(DPIO_CTL) & DPIO_CMNRST) |
1382 | return; | |
1383 | ||
1384 | DRM_DEBUG_KMS("toggling display PHY side reset\n"); | |
1385 | ||
1386 | /* cmnlane needs DPLL registers */ | |
1387 | disp2d->ops->enable(dev_priv, disp2d); | |
1388 | ||
1389 | /* | |
1390 | * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: | |
1391 | * Need to assert and de-assert PHY SB reset by gating the | |
1392 | * common lane power, then un-gating it. | |
1393 | * Simply ungating isn't enough to reset the PHY enough to get | |
1394 | * ports and lanes running. | |
1395 | */ | |
1396 | cmn->ops->disable(dev_priv, cmn); | |
1397 | } | |
1398 | ||
e4e7684f DV |
1399 | /** |
1400 | * intel_power_domains_init_hw - initialize hardware power domain state | |
1401 | * @dev_priv: i915 device instance | |
1402 | * | |
1403 | * This function initializes the hardware power domain state and enables all | |
1404 | * power domains using intel_display_set_init_power(). | |
1405 | */ | |
9c065a7d DV |
1406 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) |
1407 | { | |
1408 | struct drm_device *dev = dev_priv->dev; | |
1409 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1410 | ||
1411 | power_domains->initializing = true; | |
1412 | ||
1413 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { | |
1414 | mutex_lock(&power_domains->lock); | |
1415 | vlv_cmnlane_wa(dev_priv); | |
1416 | mutex_unlock(&power_domains->lock); | |
1417 | } | |
1418 | ||
1419 | /* For now, we need the power well to be always enabled. */ | |
1420 | intel_display_set_init_power(dev_priv, true); | |
1421 | intel_power_domains_resume(dev_priv); | |
1422 | power_domains->initializing = false; | |
1423 | } | |
1424 | ||
e4e7684f DV |
1425 | /** |
1426 | * intel_aux_display_runtime_get - grab an auxilliary power domain reference | |
1427 | * @dev_priv: i915 device instance | |
1428 | * | |
1429 | * This function grabs a power domain reference for the auxiliary power domain | |
1430 | * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its | |
1431 | * parents are powered up. Therefore users should only grab a reference to the | |
1432 | * innermost power domain they need. | |
1433 | * | |
1434 | * Any power domain reference obtained by this function must have a symmetric | |
1435 | * call to intel_aux_display_runtime_put() to release the reference again. | |
1436 | */ | |
9c065a7d DV |
1437 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) |
1438 | { | |
1439 | intel_runtime_pm_get(dev_priv); | |
1440 | } | |
1441 | ||
e4e7684f DV |
1442 | /** |
1443 | * intel_aux_display_runtime_put - release an auxilliary power domain reference | |
1444 | * @dev_priv: i915 device instance | |
1445 | * | |
1446 | * This function drops the auxilliary power domain reference obtained by | |
1447 | * intel_aux_display_runtime_get() and might power down the corresponding | |
1448 | * hardware block right away if this is the last reference. | |
1449 | */ | |
9c065a7d DV |
1450 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) |
1451 | { | |
1452 | intel_runtime_pm_put(dev_priv); | |
1453 | } | |
1454 | ||
e4e7684f DV |
1455 | /** |
1456 | * intel_runtime_pm_get - grab a runtime pm reference | |
1457 | * @dev_priv: i915 device instance | |
1458 | * | |
1459 | * This function grabs a device-level runtime pm reference (mostly used for GEM | |
1460 | * code to ensure the GTT or GT is on) and ensures that it is powered up. | |
1461 | * | |
1462 | * Any runtime pm reference obtained by this function must have a symmetric | |
1463 | * call to intel_runtime_pm_put() to release the reference again. | |
1464 | */ | |
9c065a7d DV |
1465 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv) |
1466 | { | |
1467 | struct drm_device *dev = dev_priv->dev; | |
1468 | struct device *device = &dev->pdev->dev; | |
1469 | ||
1470 | if (!HAS_RUNTIME_PM(dev)) | |
1471 | return; | |
1472 | ||
1473 | pm_runtime_get_sync(device); | |
1474 | WARN(dev_priv->pm.suspended, "Device still suspended.\n"); | |
1475 | } | |
1476 | ||
e4e7684f DV |
1477 | /** |
1478 | * intel_runtime_pm_get_noresume - grab a runtime pm reference | |
1479 | * @dev_priv: i915 device instance | |
1480 | * | |
1481 | * This function grabs a device-level runtime pm reference (mostly used for GEM | |
1482 | * code to ensure the GTT or GT is on). | |
1483 | * | |
1484 | * It will _not_ power up the device but instead only check that it's powered | |
1485 | * on. Therefore it is only valid to call this functions from contexts where | |
1486 | * the device is known to be powered up and where trying to power it up would | |
1487 | * result in hilarity and deadlocks. That pretty much means only the system | |
1488 | * suspend/resume code where this is used to grab runtime pm references for | |
1489 | * delayed setup down in work items. | |
1490 | * | |
1491 | * Any runtime pm reference obtained by this function must have a symmetric | |
1492 | * call to intel_runtime_pm_put() to release the reference again. | |
1493 | */ | |
9c065a7d DV |
1494 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) |
1495 | { | |
1496 | struct drm_device *dev = dev_priv->dev; | |
1497 | struct device *device = &dev->pdev->dev; | |
1498 | ||
1499 | if (!HAS_RUNTIME_PM(dev)) | |
1500 | return; | |
1501 | ||
1502 | WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n"); | |
1503 | pm_runtime_get_noresume(device); | |
1504 | } | |
1505 | ||
e4e7684f DV |
1506 | /** |
1507 | * intel_runtime_pm_put - release a runtime pm reference | |
1508 | * @dev_priv: i915 device instance | |
1509 | * | |
1510 | * This function drops the device-level runtime pm reference obtained by | |
1511 | * intel_runtime_pm_get() and might power down the corresponding | |
1512 | * hardware block right away if this is the last reference. | |
1513 | */ | |
9c065a7d DV |
1514 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv) |
1515 | { | |
1516 | struct drm_device *dev = dev_priv->dev; | |
1517 | struct device *device = &dev->pdev->dev; | |
1518 | ||
1519 | if (!HAS_RUNTIME_PM(dev)) | |
1520 | return; | |
1521 | ||
1522 | pm_runtime_mark_last_busy(device); | |
1523 | pm_runtime_put_autosuspend(device); | |
1524 | } | |
1525 | ||
e4e7684f DV |
1526 | /** |
1527 | * intel_runtime_pm_enable - enable runtime pm | |
1528 | * @dev_priv: i915 device instance | |
1529 | * | |
1530 | * This function enables runtime pm at the end of the driver load sequence. | |
1531 | * | |
1532 | * Note that this function does currently not enable runtime pm for the | |
1533 | * subordinate display power domains. That is only done on the first modeset | |
1534 | * using intel_display_set_init_power(). | |
1535 | */ | |
f458ebbc | 1536 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) |
9c065a7d DV |
1537 | { |
1538 | struct drm_device *dev = dev_priv->dev; | |
1539 | struct device *device = &dev->pdev->dev; | |
1540 | ||
1541 | if (!HAS_RUNTIME_PM(dev)) | |
1542 | return; | |
1543 | ||
1544 | pm_runtime_set_active(device); | |
1545 | ||
1546 | /* | |
1547 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a | |
1548 | * requirement. | |
1549 | */ | |
1550 | if (!intel_enable_rc6(dev)) { | |
1551 | DRM_INFO("RC6 disabled, disabling runtime PM support\n"); | |
1552 | return; | |
1553 | } | |
1554 | ||
1555 | pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ | |
1556 | pm_runtime_mark_last_busy(device); | |
1557 | pm_runtime_use_autosuspend(device); | |
1558 | ||
1559 | pm_runtime_put_autosuspend(device); | |
1560 | } | |
1561 |