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9c065a7d DV |
1 | /* |
2 | * Copyright © 2012-2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * Daniel Vetter <daniel.vetter@ffwll.ch> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/pm_runtime.h> | |
30 | #include <linux/vgaarb.h> | |
31 | ||
32 | #include "i915_drv.h" | |
33 | #include "intel_drv.h" | |
9c065a7d | 34 | |
e4e7684f DV |
35 | /** |
36 | * DOC: runtime pm | |
37 | * | |
38 | * The i915 driver supports dynamic enabling and disabling of entire hardware | |
39 | * blocks at runtime. This is especially important on the display side where | |
40 | * software is supposed to control many power gates manually on recent hardware, | |
41 | * since on the GT side a lot of the power management is done by the hardware. | |
42 | * But even there some manual control at the device level is required. | |
43 | * | |
44 | * Since i915 supports a diverse set of platforms with a unified codebase and | |
45 | * hardware engineers just love to shuffle functionality around between power | |
46 | * domains there's a sizeable amount of indirection required. This file provides | |
47 | * generic functions to the driver for grabbing and releasing references for | |
48 | * abstract power domains. It then maps those to the actual power wells | |
49 | * present for a given platform. | |
50 | */ | |
51 | ||
9c065a7d DV |
52 | #define for_each_power_well(i, power_well, domain_mask, power_domains) \ |
53 | for (i = 0; \ | |
54 | i < (power_domains)->power_well_count && \ | |
55 | ((power_well) = &(power_domains)->power_wells[i]); \ | |
56 | i++) \ | |
95150bdf | 57 | for_each_if ((power_well)->domains & (domain_mask)) |
9c065a7d DV |
58 | |
59 | #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ | |
60 | for (i = (power_domains)->power_well_count - 1; \ | |
61 | i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ | |
62 | i--) \ | |
95150bdf | 63 | for_each_if ((power_well)->domains & (domain_mask)) |
9c065a7d | 64 | |
5aefb239 SS |
65 | bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, |
66 | int power_well_id); | |
67 | ||
9895ad03 DS |
68 | const char * |
69 | intel_display_power_domain_str(enum intel_display_power_domain domain) | |
70 | { | |
71 | switch (domain) { | |
72 | case POWER_DOMAIN_PIPE_A: | |
73 | return "PIPE_A"; | |
74 | case POWER_DOMAIN_PIPE_B: | |
75 | return "PIPE_B"; | |
76 | case POWER_DOMAIN_PIPE_C: | |
77 | return "PIPE_C"; | |
78 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: | |
79 | return "PIPE_A_PANEL_FITTER"; | |
80 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: | |
81 | return "PIPE_B_PANEL_FITTER"; | |
82 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: | |
83 | return "PIPE_C_PANEL_FITTER"; | |
84 | case POWER_DOMAIN_TRANSCODER_A: | |
85 | return "TRANSCODER_A"; | |
86 | case POWER_DOMAIN_TRANSCODER_B: | |
87 | return "TRANSCODER_B"; | |
88 | case POWER_DOMAIN_TRANSCODER_C: | |
89 | return "TRANSCODER_C"; | |
90 | case POWER_DOMAIN_TRANSCODER_EDP: | |
91 | return "TRANSCODER_EDP"; | |
4d1de975 JN |
92 | case POWER_DOMAIN_TRANSCODER_DSI_A: |
93 | return "TRANSCODER_DSI_A"; | |
94 | case POWER_DOMAIN_TRANSCODER_DSI_C: | |
95 | return "TRANSCODER_DSI_C"; | |
9895ad03 DS |
96 | case POWER_DOMAIN_PORT_DDI_A_LANES: |
97 | return "PORT_DDI_A_LANES"; | |
98 | case POWER_DOMAIN_PORT_DDI_B_LANES: | |
99 | return "PORT_DDI_B_LANES"; | |
100 | case POWER_DOMAIN_PORT_DDI_C_LANES: | |
101 | return "PORT_DDI_C_LANES"; | |
102 | case POWER_DOMAIN_PORT_DDI_D_LANES: | |
103 | return "PORT_DDI_D_LANES"; | |
104 | case POWER_DOMAIN_PORT_DDI_E_LANES: | |
105 | return "PORT_DDI_E_LANES"; | |
106 | case POWER_DOMAIN_PORT_DSI: | |
107 | return "PORT_DSI"; | |
108 | case POWER_DOMAIN_PORT_CRT: | |
109 | return "PORT_CRT"; | |
110 | case POWER_DOMAIN_PORT_OTHER: | |
111 | return "PORT_OTHER"; | |
112 | case POWER_DOMAIN_VGA: | |
113 | return "VGA"; | |
114 | case POWER_DOMAIN_AUDIO: | |
115 | return "AUDIO"; | |
116 | case POWER_DOMAIN_PLLS: | |
117 | return "PLLS"; | |
118 | case POWER_DOMAIN_AUX_A: | |
119 | return "AUX_A"; | |
120 | case POWER_DOMAIN_AUX_B: | |
121 | return "AUX_B"; | |
122 | case POWER_DOMAIN_AUX_C: | |
123 | return "AUX_C"; | |
124 | case POWER_DOMAIN_AUX_D: | |
125 | return "AUX_D"; | |
126 | case POWER_DOMAIN_GMBUS: | |
127 | return "GMBUS"; | |
128 | case POWER_DOMAIN_INIT: | |
129 | return "INIT"; | |
130 | case POWER_DOMAIN_MODESET: | |
131 | return "MODESET"; | |
132 | default: | |
133 | MISSING_CASE(domain); | |
134 | return "?"; | |
135 | } | |
136 | } | |
137 | ||
e8ca9320 DL |
138 | static void intel_power_well_enable(struct drm_i915_private *dev_priv, |
139 | struct i915_power_well *power_well) | |
140 | { | |
141 | DRM_DEBUG_KMS("enabling %s\n", power_well->name); | |
142 | power_well->ops->enable(dev_priv, power_well); | |
143 | power_well->hw_enabled = true; | |
144 | } | |
145 | ||
dcddab3a DL |
146 | static void intel_power_well_disable(struct drm_i915_private *dev_priv, |
147 | struct i915_power_well *power_well) | |
148 | { | |
149 | DRM_DEBUG_KMS("disabling %s\n", power_well->name); | |
150 | power_well->hw_enabled = false; | |
151 | power_well->ops->disable(dev_priv, power_well); | |
152 | } | |
153 | ||
e4e7684f | 154 | /* |
9c065a7d DV |
155 | * We should only use the power well if we explicitly asked the hardware to |
156 | * enable it, so check if it's enabled and also check if we've requested it to | |
157 | * be enabled. | |
158 | */ | |
159 | static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, | |
160 | struct i915_power_well *power_well) | |
161 | { | |
162 | return I915_READ(HSW_PWR_WELL_DRIVER) == | |
163 | (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); | |
164 | } | |
165 | ||
e4e7684f DV |
166 | /** |
167 | * __intel_display_power_is_enabled - unlocked check for a power domain | |
168 | * @dev_priv: i915 device instance | |
169 | * @domain: power domain to check | |
170 | * | |
171 | * This is the unlocked version of intel_display_power_is_enabled() and should | |
172 | * only be used from error capture and recovery code where deadlocks are | |
173 | * possible. | |
174 | * | |
175 | * Returns: | |
176 | * True when the power domain is enabled, false otherwise. | |
177 | */ | |
f458ebbc DV |
178 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
179 | enum intel_display_power_domain domain) | |
9c065a7d DV |
180 | { |
181 | struct i915_power_domains *power_domains; | |
182 | struct i915_power_well *power_well; | |
183 | bool is_enabled; | |
184 | int i; | |
185 | ||
186 | if (dev_priv->pm.suspended) | |
187 | return false; | |
188 | ||
189 | power_domains = &dev_priv->power_domains; | |
190 | ||
191 | is_enabled = true; | |
192 | ||
193 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { | |
194 | if (power_well->always_on) | |
195 | continue; | |
196 | ||
197 | if (!power_well->hw_enabled) { | |
198 | is_enabled = false; | |
199 | break; | |
200 | } | |
201 | } | |
202 | ||
203 | return is_enabled; | |
204 | } | |
205 | ||
e4e7684f | 206 | /** |
f61ccae3 | 207 | * intel_display_power_is_enabled - check for a power domain |
e4e7684f DV |
208 | * @dev_priv: i915 device instance |
209 | * @domain: power domain to check | |
210 | * | |
211 | * This function can be used to check the hw power domain state. It is mostly | |
212 | * used in hardware state readout functions. Everywhere else code should rely | |
213 | * upon explicit power domain reference counting to ensure that the hardware | |
214 | * block is powered up before accessing it. | |
215 | * | |
216 | * Callers must hold the relevant modesetting locks to ensure that concurrent | |
217 | * threads can't disable the power well while the caller tries to read a few | |
218 | * registers. | |
219 | * | |
220 | * Returns: | |
221 | * True when the power domain is enabled, false otherwise. | |
222 | */ | |
f458ebbc DV |
223 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
224 | enum intel_display_power_domain domain) | |
9c065a7d DV |
225 | { |
226 | struct i915_power_domains *power_domains; | |
227 | bool ret; | |
228 | ||
229 | power_domains = &dev_priv->power_domains; | |
230 | ||
231 | mutex_lock(&power_domains->lock); | |
f458ebbc | 232 | ret = __intel_display_power_is_enabled(dev_priv, domain); |
9c065a7d DV |
233 | mutex_unlock(&power_domains->lock); |
234 | ||
235 | return ret; | |
236 | } | |
237 | ||
e4e7684f DV |
238 | /** |
239 | * intel_display_set_init_power - set the initial power domain state | |
240 | * @dev_priv: i915 device instance | |
241 | * @enable: whether to enable or disable the initial power domain state | |
242 | * | |
243 | * For simplicity our driver load/unload and system suspend/resume code assumes | |
244 | * that all power domains are always enabled. This functions controls the state | |
245 | * of this little hack. While the initial power domain state is enabled runtime | |
246 | * pm is effectively disabled. | |
247 | */ | |
d9bc89d9 DV |
248 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, |
249 | bool enable) | |
250 | { | |
251 | if (dev_priv->power_domains.init_power_on == enable) | |
252 | return; | |
253 | ||
254 | if (enable) | |
255 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
256 | else | |
257 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
258 | ||
259 | dev_priv->power_domains.init_power_on = enable; | |
260 | } | |
261 | ||
9c065a7d DV |
262 | /* |
263 | * Starting with Haswell, we have a "Power Down Well" that can be turned off | |
264 | * when not needed anymore. We have 4 registers that can request the power well | |
265 | * to be enabled, and it will only be disabled if none of the registers is | |
266 | * requesting it to be enabled. | |
267 | */ | |
268 | static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) | |
269 | { | |
270 | struct drm_device *dev = dev_priv->dev; | |
271 | ||
272 | /* | |
273 | * After we re-enable the power well, if we touch VGA register 0x3d5 | |
274 | * we'll get unclaimed register interrupts. This stops after we write | |
275 | * anything to the VGA MSR register. The vgacon module uses this | |
276 | * register all the time, so if we unbind our driver and, as a | |
277 | * consequence, bind vgacon, we'll get stuck in an infinite loop at | |
278 | * console_unlock(). So make here we touch the VGA MSR register, making | |
279 | * sure vgacon can keep working normally without triggering interrupts | |
280 | * and error messages. | |
281 | */ | |
282 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
283 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); | |
284 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
285 | ||
25400392 | 286 | if (IS_BROADWELL(dev)) |
4c6c03be DL |
287 | gen8_irq_power_well_post_enable(dev_priv, |
288 | 1 << PIPE_C | 1 << PIPE_B); | |
9c065a7d DV |
289 | } |
290 | ||
aae8ba84 VS |
291 | static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv) |
292 | { | |
293 | if (IS_BROADWELL(dev_priv)) | |
294 | gen8_irq_power_well_pre_disable(dev_priv, | |
295 | 1 << PIPE_C | 1 << PIPE_B); | |
296 | } | |
297 | ||
d14c0343 DL |
298 | static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, |
299 | struct i915_power_well *power_well) | |
300 | { | |
301 | struct drm_device *dev = dev_priv->dev; | |
302 | ||
303 | /* | |
304 | * After we re-enable the power well, if we touch VGA register 0x3d5 | |
305 | * we'll get unclaimed register interrupts. This stops after we write | |
306 | * anything to the VGA MSR register. The vgacon module uses this | |
307 | * register all the time, so if we unbind our driver and, as a | |
308 | * consequence, bind vgacon, we'll get stuck in an infinite loop at | |
309 | * console_unlock(). So make here we touch the VGA MSR register, making | |
310 | * sure vgacon can keep working normally without triggering interrupts | |
311 | * and error messages. | |
312 | */ | |
313 | if (power_well->data == SKL_DISP_PW_2) { | |
314 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
315 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); | |
316 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
317 | ||
318 | gen8_irq_power_well_post_enable(dev_priv, | |
319 | 1 << PIPE_C | 1 << PIPE_B); | |
320 | } | |
d14c0343 DL |
321 | } |
322 | ||
aae8ba84 VS |
323 | static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv, |
324 | struct i915_power_well *power_well) | |
325 | { | |
326 | if (power_well->data == SKL_DISP_PW_2) | |
327 | gen8_irq_power_well_pre_disable(dev_priv, | |
328 | 1 << PIPE_C | 1 << PIPE_B); | |
329 | } | |
330 | ||
9c065a7d DV |
331 | static void hsw_set_power_well(struct drm_i915_private *dev_priv, |
332 | struct i915_power_well *power_well, bool enable) | |
333 | { | |
334 | bool is_enabled, enable_requested; | |
335 | uint32_t tmp; | |
336 | ||
337 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); | |
338 | is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; | |
339 | enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; | |
340 | ||
341 | if (enable) { | |
342 | if (!enable_requested) | |
343 | I915_WRITE(HSW_PWR_WELL_DRIVER, | |
344 | HSW_PWR_WELL_ENABLE_REQUEST); | |
345 | ||
346 | if (!is_enabled) { | |
347 | DRM_DEBUG_KMS("Enabling power well\n"); | |
348 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & | |
349 | HSW_PWR_WELL_STATE_ENABLED), 20)) | |
350 | DRM_ERROR("Timeout enabling power well\n"); | |
6d729bff | 351 | hsw_power_well_post_enable(dev_priv); |
9c065a7d DV |
352 | } |
353 | ||
9c065a7d DV |
354 | } else { |
355 | if (enable_requested) { | |
aae8ba84 | 356 | hsw_power_well_pre_disable(dev_priv); |
9c065a7d DV |
357 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); |
358 | POSTING_READ(HSW_PWR_WELL_DRIVER); | |
359 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); | |
360 | } | |
361 | } | |
362 | } | |
363 | ||
94dd5138 S |
364 | #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ |
365 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ | |
366 | BIT(POWER_DOMAIN_PIPE_B) | \ | |
367 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ | |
368 | BIT(POWER_DOMAIN_PIPE_C) | \ | |
369 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ | |
370 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ | |
371 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ | |
6331a704 PJ |
372 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
373 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ | |
374 | BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ | |
375 | BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \ | |
94dd5138 S |
376 | BIT(POWER_DOMAIN_AUX_B) | \ |
377 | BIT(POWER_DOMAIN_AUX_C) | \ | |
378 | BIT(POWER_DOMAIN_AUX_D) | \ | |
379 | BIT(POWER_DOMAIN_AUDIO) | \ | |
380 | BIT(POWER_DOMAIN_VGA) | \ | |
381 | BIT(POWER_DOMAIN_INIT)) | |
94dd5138 | 382 | #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \ |
6331a704 PJ |
383 | BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \ |
384 | BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \ | |
94dd5138 S |
385 | BIT(POWER_DOMAIN_INIT)) |
386 | #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \ | |
6331a704 | 387 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
94dd5138 S |
388 | BIT(POWER_DOMAIN_INIT)) |
389 | #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \ | |
6331a704 | 390 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ |
94dd5138 S |
391 | BIT(POWER_DOMAIN_INIT)) |
392 | #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \ | |
6331a704 | 393 | BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ |
94dd5138 | 394 | BIT(POWER_DOMAIN_INIT)) |
9f836f90 PJ |
395 | #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \ |
396 | SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ | |
397 | BIT(POWER_DOMAIN_MODESET) | \ | |
398 | BIT(POWER_DOMAIN_AUX_A) | \ | |
399 | BIT(POWER_DOMAIN_INIT)) | |
94dd5138 | 400 | |
0b4a2a36 S |
401 | #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ |
402 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ | |
403 | BIT(POWER_DOMAIN_PIPE_B) | \ | |
404 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ | |
405 | BIT(POWER_DOMAIN_PIPE_C) | \ | |
406 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ | |
407 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ | |
408 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ | |
6331a704 PJ |
409 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
410 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ | |
0b4a2a36 S |
411 | BIT(POWER_DOMAIN_AUX_B) | \ |
412 | BIT(POWER_DOMAIN_AUX_C) | \ | |
413 | BIT(POWER_DOMAIN_AUDIO) | \ | |
414 | BIT(POWER_DOMAIN_VGA) | \ | |
f0ab43e6 | 415 | BIT(POWER_DOMAIN_GMBUS) | \ |
0b4a2a36 | 416 | BIT(POWER_DOMAIN_INIT)) |
9f836f90 PJ |
417 | #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \ |
418 | BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ | |
419 | BIT(POWER_DOMAIN_MODESET) | \ | |
420 | BIT(POWER_DOMAIN_AUX_A) | \ | |
421 | BIT(POWER_DOMAIN_INIT)) | |
0b4a2a36 | 422 | |
664326f8 SK |
423 | static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) |
424 | { | |
bfcdabe8 ID |
425 | WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), |
426 | "DC9 already programmed to be enabled.\n"); | |
427 | WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, | |
428 | "DC5 still not disabled to enable DC9.\n"); | |
429 | WARN_ONCE(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); | |
430 | WARN_ONCE(intel_irqs_enabled(dev_priv), | |
431 | "Interrupts not disabled yet.\n"); | |
664326f8 SK |
432 | |
433 | /* | |
434 | * TODO: check for the following to verify the conditions to enter DC9 | |
435 | * state are satisfied: | |
436 | * 1] Check relevant display engine registers to verify if mode set | |
437 | * disable sequence was followed. | |
438 | * 2] Check if display uninitialize sequence is initialized. | |
439 | */ | |
440 | } | |
441 | ||
442 | static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) | |
443 | { | |
bfcdabe8 ID |
444 | WARN_ONCE(intel_irqs_enabled(dev_priv), |
445 | "Interrupts not disabled yet.\n"); | |
446 | WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, | |
447 | "DC5 still not disabled.\n"); | |
664326f8 SK |
448 | |
449 | /* | |
450 | * TODO: check for the following to verify DC9 state was indeed | |
451 | * entered before programming to disable it: | |
452 | * 1] Check relevant display engine registers to verify if mode | |
453 | * set disable sequence was followed. | |
454 | * 2] Check if display uninitialize sequence is initialized. | |
455 | */ | |
456 | } | |
457 | ||
779cb5d3 MK |
458 | static void gen9_write_dc_state(struct drm_i915_private *dev_priv, |
459 | u32 state) | |
460 | { | |
461 | int rewrites = 0; | |
462 | int rereads = 0; | |
463 | u32 v; | |
464 | ||
465 | I915_WRITE(DC_STATE_EN, state); | |
466 | ||
467 | /* It has been observed that disabling the dc6 state sometimes | |
468 | * doesn't stick and dmc keeps returning old value. Make sure | |
469 | * the write really sticks enough times and also force rewrite until | |
470 | * we are confident that state is exactly what we want. | |
471 | */ | |
472 | do { | |
473 | v = I915_READ(DC_STATE_EN); | |
474 | ||
475 | if (v != state) { | |
476 | I915_WRITE(DC_STATE_EN, state); | |
477 | rewrites++; | |
478 | rereads = 0; | |
479 | } else if (rereads++ > 5) { | |
480 | break; | |
481 | } | |
482 | ||
483 | } while (rewrites < 100); | |
484 | ||
485 | if (v != state) | |
486 | DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n", | |
487 | state, v); | |
488 | ||
489 | /* Most of the times we need one retry, avoid spam */ | |
490 | if (rewrites > 1) | |
491 | DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n", | |
492 | state, rewrites); | |
493 | } | |
494 | ||
da2f41d1 | 495 | static u32 gen9_dc_mask(struct drm_i915_private *dev_priv) |
664326f8 | 496 | { |
da2f41d1 | 497 | u32 mask; |
664326f8 | 498 | |
13ae3a0d ID |
499 | mask = DC_STATE_EN_UPTO_DC5; |
500 | if (IS_BROXTON(dev_priv)) | |
501 | mask |= DC_STATE_EN_DC9; | |
502 | else | |
503 | mask |= DC_STATE_EN_UPTO_DC6; | |
664326f8 | 504 | |
da2f41d1 ID |
505 | return mask; |
506 | } | |
507 | ||
508 | void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv) | |
509 | { | |
510 | u32 val; | |
511 | ||
512 | val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv); | |
513 | ||
514 | DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n", | |
515 | dev_priv->csr.dc_state, val); | |
516 | dev_priv->csr.dc_state = val; | |
517 | } | |
518 | ||
519 | static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state) | |
520 | { | |
521 | uint32_t val; | |
522 | uint32_t mask; | |
523 | ||
a37baf3b ID |
524 | if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask)) |
525 | state &= dev_priv->csr.allowed_dc_mask; | |
443646c7 | 526 | |
664326f8 | 527 | val = I915_READ(DC_STATE_EN); |
da2f41d1 | 528 | mask = gen9_dc_mask(dev_priv); |
13ae3a0d ID |
529 | DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n", |
530 | val & mask, state); | |
832dba88 PJ |
531 | |
532 | /* Check if DMC is ignoring our DC state requests */ | |
533 | if ((val & mask) != dev_priv->csr.dc_state) | |
534 | DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n", | |
535 | dev_priv->csr.dc_state, val & mask); | |
536 | ||
13ae3a0d ID |
537 | val &= ~mask; |
538 | val |= state; | |
779cb5d3 MK |
539 | |
540 | gen9_write_dc_state(dev_priv, val); | |
832dba88 PJ |
541 | |
542 | dev_priv->csr.dc_state = val & mask; | |
664326f8 SK |
543 | } |
544 | ||
13ae3a0d | 545 | void bxt_enable_dc9(struct drm_i915_private *dev_priv) |
664326f8 | 546 | { |
13ae3a0d ID |
547 | assert_can_enable_dc9(dev_priv); |
548 | ||
549 | DRM_DEBUG_KMS("Enabling DC9\n"); | |
664326f8 | 550 | |
13ae3a0d ID |
551 | gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9); |
552 | } | |
553 | ||
554 | void bxt_disable_dc9(struct drm_i915_private *dev_priv) | |
555 | { | |
664326f8 SK |
556 | assert_can_disable_dc9(dev_priv); |
557 | ||
558 | DRM_DEBUG_KMS("Disabling DC9\n"); | |
559 | ||
13ae3a0d | 560 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); |
664326f8 SK |
561 | } |
562 | ||
af5fead2 DV |
563 | static void assert_csr_loaded(struct drm_i915_private *dev_priv) |
564 | { | |
565 | WARN_ONCE(!I915_READ(CSR_PROGRAM(0)), | |
566 | "CSR program storage start is NULL\n"); | |
567 | WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n"); | |
568 | WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n"); | |
569 | } | |
570 | ||
5aefb239 | 571 | static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) |
dc174300 | 572 | { |
5aefb239 SS |
573 | bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, |
574 | SKL_DISP_PW_2); | |
575 | ||
6ff8ab0d | 576 | WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n"); |
5aefb239 | 577 | |
6ff8ab0d JB |
578 | WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), |
579 | "DC5 already programmed to be enabled.\n"); | |
c9b8846a | 580 | assert_rpm_wakelock_held(dev_priv); |
5aefb239 SS |
581 | |
582 | assert_csr_loaded(dev_priv); | |
583 | } | |
584 | ||
f62c79b3 | 585 | void gen9_enable_dc5(struct drm_i915_private *dev_priv) |
5aefb239 | 586 | { |
5aefb239 | 587 | assert_can_enable_dc5(dev_priv); |
6b457d31 SK |
588 | |
589 | DRM_DEBUG_KMS("Enabling DC5\n"); | |
590 | ||
13ae3a0d | 591 | gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); |
dc174300 SS |
592 | } |
593 | ||
93c7cb6c | 594 | static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) |
f75a1985 | 595 | { |
6ff8ab0d JB |
596 | WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
597 | "Backlight is not disabled.\n"); | |
598 | WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), | |
599 | "DC6 already programmed to be enabled.\n"); | |
93c7cb6c SS |
600 | |
601 | assert_csr_loaded(dev_priv); | |
602 | } | |
603 | ||
0a9d2bed | 604 | void skl_enable_dc6(struct drm_i915_private *dev_priv) |
93c7cb6c | 605 | { |
93c7cb6c | 606 | assert_can_enable_dc6(dev_priv); |
74b4f371 SK |
607 | |
608 | DRM_DEBUG_KMS("Enabling DC6\n"); | |
609 | ||
13ae3a0d ID |
610 | gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6); |
611 | ||
f75a1985 SS |
612 | } |
613 | ||
0a9d2bed | 614 | void skl_disable_dc6(struct drm_i915_private *dev_priv) |
f75a1985 | 615 | { |
74b4f371 SK |
616 | DRM_DEBUG_KMS("Disabling DC6\n"); |
617 | ||
13ae3a0d | 618 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); |
f75a1985 SS |
619 | } |
620 | ||
c6782b76 ID |
621 | static void |
622 | gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv, | |
623 | struct i915_power_well *power_well) | |
624 | { | |
625 | enum skl_disp_power_wells power_well_id = power_well->data; | |
626 | u32 val; | |
627 | u32 mask; | |
628 | ||
629 | mask = SKL_POWER_WELL_REQ(power_well_id); | |
630 | ||
631 | val = I915_READ(HSW_PWR_WELL_KVMR); | |
632 | if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n", | |
633 | power_well->name)) | |
634 | I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask); | |
635 | ||
636 | val = I915_READ(HSW_PWR_WELL_BIOS); | |
637 | val |= I915_READ(HSW_PWR_WELL_DEBUG); | |
638 | ||
639 | if (!(val & mask)) | |
640 | return; | |
641 | ||
642 | /* | |
643 | * DMC is known to force on the request bits for power well 1 on SKL | |
644 | * and BXT and the misc IO power well on SKL but we don't expect any | |
645 | * other request bits to be set, so WARN for those. | |
646 | */ | |
647 | if (power_well_id == SKL_DISP_PW_1 || | |
80dbe997 ID |
648 | ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) && |
649 | power_well_id == SKL_DISP_PW_MISC_IO)) | |
c6782b76 ID |
650 | DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on " |
651 | "by DMC\n", power_well->name); | |
652 | else | |
653 | WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n", | |
654 | power_well->name); | |
655 | ||
656 | I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask); | |
657 | I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask); | |
658 | } | |
659 | ||
94dd5138 S |
660 | static void skl_set_power_well(struct drm_i915_private *dev_priv, |
661 | struct i915_power_well *power_well, bool enable) | |
662 | { | |
663 | uint32_t tmp, fuse_status; | |
664 | uint32_t req_mask, state_mask; | |
2a51835f | 665 | bool is_enabled, enable_requested, check_fuse_status = false; |
94dd5138 S |
666 | |
667 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); | |
668 | fuse_status = I915_READ(SKL_FUSE_STATUS); | |
669 | ||
670 | switch (power_well->data) { | |
671 | case SKL_DISP_PW_1: | |
672 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & | |
673 | SKL_FUSE_PG0_DIST_STATUS), 1)) { | |
674 | DRM_ERROR("PG0 not enabled\n"); | |
675 | return; | |
676 | } | |
677 | break; | |
678 | case SKL_DISP_PW_2: | |
679 | if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { | |
680 | DRM_ERROR("PG1 in disabled state\n"); | |
681 | return; | |
682 | } | |
683 | break; | |
684 | case SKL_DISP_PW_DDI_A_E: | |
685 | case SKL_DISP_PW_DDI_B: | |
686 | case SKL_DISP_PW_DDI_C: | |
687 | case SKL_DISP_PW_DDI_D: | |
688 | case SKL_DISP_PW_MISC_IO: | |
689 | break; | |
690 | default: | |
691 | WARN(1, "Unknown power well %lu\n", power_well->data); | |
692 | return; | |
693 | } | |
694 | ||
695 | req_mask = SKL_POWER_WELL_REQ(power_well->data); | |
2a51835f | 696 | enable_requested = tmp & req_mask; |
94dd5138 | 697 | state_mask = SKL_POWER_WELL_STATE(power_well->data); |
2a51835f | 698 | is_enabled = tmp & state_mask; |
94dd5138 | 699 | |
aae8ba84 VS |
700 | if (!enable && enable_requested) |
701 | skl_power_well_pre_disable(dev_priv, power_well); | |
702 | ||
94dd5138 | 703 | if (enable) { |
2a51835f | 704 | if (!enable_requested) { |
dc174300 SS |
705 | WARN((tmp & state_mask) && |
706 | !I915_READ(HSW_PWR_WELL_BIOS), | |
707 | "Invalid for power well status to be enabled, unless done by the BIOS, \ | |
708 | when request is to disable!\n"); | |
94dd5138 | 709 | I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); |
94dd5138 S |
710 | } |
711 | ||
2a51835f | 712 | if (!is_enabled) { |
510e6fdd | 713 | DRM_DEBUG_KMS("Enabling %s\n", power_well->name); |
94dd5138 S |
714 | check_fuse_status = true; |
715 | } | |
716 | } else { | |
2a51835f | 717 | if (enable_requested) { |
4a76f295 ID |
718 | I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); |
719 | POSTING_READ(HSW_PWR_WELL_DRIVER); | |
720 | DRM_DEBUG_KMS("Disabling %s\n", power_well->name); | |
94dd5138 | 721 | } |
c6782b76 | 722 | |
5f304c87 | 723 | if (IS_GEN9(dev_priv)) |
c6782b76 | 724 | gen9_sanitize_power_well_requests(dev_priv, power_well); |
94dd5138 S |
725 | } |
726 | ||
1d963afa ID |
727 | if (wait_for(!!(I915_READ(HSW_PWR_WELL_DRIVER) & state_mask) == enable, |
728 | 1)) | |
729 | DRM_ERROR("%s %s timeout\n", | |
730 | power_well->name, enable ? "enable" : "disable"); | |
731 | ||
94dd5138 S |
732 | if (check_fuse_status) { |
733 | if (power_well->data == SKL_DISP_PW_1) { | |
734 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & | |
735 | SKL_FUSE_PG1_DIST_STATUS), 1)) | |
736 | DRM_ERROR("PG1 distributing status timeout\n"); | |
737 | } else if (power_well->data == SKL_DISP_PW_2) { | |
738 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & | |
739 | SKL_FUSE_PG2_DIST_STATUS), 1)) | |
740 | DRM_ERROR("PG2 distributing status timeout\n"); | |
741 | } | |
742 | } | |
d14c0343 DL |
743 | |
744 | if (enable && !is_enabled) | |
745 | skl_power_well_post_enable(dev_priv, power_well); | |
94dd5138 S |
746 | } |
747 | ||
9c065a7d DV |
748 | static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, |
749 | struct i915_power_well *power_well) | |
750 | { | |
751 | hsw_set_power_well(dev_priv, power_well, power_well->count > 0); | |
752 | ||
753 | /* | |
754 | * We're taking over the BIOS, so clear any requests made by it since | |
755 | * the driver is in charge now. | |
756 | */ | |
757 | if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) | |
758 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); | |
759 | } | |
760 | ||
761 | static void hsw_power_well_enable(struct drm_i915_private *dev_priv, | |
762 | struct i915_power_well *power_well) | |
763 | { | |
764 | hsw_set_power_well(dev_priv, power_well, true); | |
765 | } | |
766 | ||
767 | static void hsw_power_well_disable(struct drm_i915_private *dev_priv, | |
768 | struct i915_power_well *power_well) | |
769 | { | |
770 | hsw_set_power_well(dev_priv, power_well, false); | |
771 | } | |
772 | ||
94dd5138 S |
773 | static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, |
774 | struct i915_power_well *power_well) | |
775 | { | |
776 | uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) | | |
777 | SKL_POWER_WELL_STATE(power_well->data); | |
778 | ||
779 | return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; | |
780 | } | |
781 | ||
782 | static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
783 | struct i915_power_well *power_well) | |
784 | { | |
785 | skl_set_power_well(dev_priv, power_well, power_well->count > 0); | |
786 | ||
787 | /* Clear any request made by BIOS as driver is taking over */ | |
788 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); | |
789 | } | |
790 | ||
791 | static void skl_power_well_enable(struct drm_i915_private *dev_priv, | |
792 | struct i915_power_well *power_well) | |
793 | { | |
794 | skl_set_power_well(dev_priv, power_well, true); | |
795 | } | |
796 | ||
797 | static void skl_power_well_disable(struct drm_i915_private *dev_priv, | |
798 | struct i915_power_well *power_well) | |
799 | { | |
800 | skl_set_power_well(dev_priv, power_well, false); | |
801 | } | |
802 | ||
9f836f90 PJ |
803 | static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv, |
804 | struct i915_power_well *power_well) | |
805 | { | |
806 | return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0; | |
807 | } | |
808 | ||
809 | static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv, | |
810 | struct i915_power_well *power_well) | |
811 | { | |
5b773eb4 | 812 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); |
adc7f04b ID |
813 | |
814 | if (IS_BROXTON(dev_priv)) { | |
815 | broxton_cdclk_verify_state(dev_priv); | |
816 | broxton_ddi_phy_verify_state(dev_priv); | |
817 | } | |
9f836f90 PJ |
818 | } |
819 | ||
820 | static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv, | |
821 | struct i915_power_well *power_well) | |
822 | { | |
f74ed08d ID |
823 | if (!dev_priv->csr.dmc_payload) |
824 | return; | |
825 | ||
a37baf3b | 826 | if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6) |
9f836f90 | 827 | skl_enable_dc6(dev_priv); |
a37baf3b | 828 | else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5) |
9f836f90 PJ |
829 | gen9_enable_dc5(dev_priv); |
830 | } | |
831 | ||
832 | static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
833 | struct i915_power_well *power_well) | |
834 | { | |
a37baf3b ID |
835 | if (power_well->count > 0) |
836 | gen9_dc_off_power_well_enable(dev_priv, power_well); | |
837 | else | |
838 | gen9_dc_off_power_well_disable(dev_priv, power_well); | |
9f836f90 PJ |
839 | } |
840 | ||
9c065a7d DV |
841 | static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, |
842 | struct i915_power_well *power_well) | |
843 | { | |
844 | } | |
845 | ||
846 | static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, | |
847 | struct i915_power_well *power_well) | |
848 | { | |
849 | return true; | |
850 | } | |
851 | ||
852 | static void vlv_set_power_well(struct drm_i915_private *dev_priv, | |
853 | struct i915_power_well *power_well, bool enable) | |
854 | { | |
855 | enum punit_power_well power_well_id = power_well->data; | |
856 | u32 mask; | |
857 | u32 state; | |
858 | u32 ctrl; | |
859 | ||
860 | mask = PUNIT_PWRGT_MASK(power_well_id); | |
861 | state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : | |
862 | PUNIT_PWRGT_PWR_GATE(power_well_id); | |
863 | ||
864 | mutex_lock(&dev_priv->rps.hw_lock); | |
865 | ||
866 | #define COND \ | |
867 | ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) | |
868 | ||
869 | if (COND) | |
870 | goto out; | |
871 | ||
872 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); | |
873 | ctrl &= ~mask; | |
874 | ctrl |= state; | |
875 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); | |
876 | ||
877 | if (wait_for(COND, 100)) | |
7e35ab88 | 878 | DRM_ERROR("timeout setting power well state %08x (%08x)\n", |
9c065a7d DV |
879 | state, |
880 | vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); | |
881 | ||
882 | #undef COND | |
883 | ||
884 | out: | |
885 | mutex_unlock(&dev_priv->rps.hw_lock); | |
886 | } | |
887 | ||
888 | static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
889 | struct i915_power_well *power_well) | |
890 | { | |
891 | vlv_set_power_well(dev_priv, power_well, power_well->count > 0); | |
892 | } | |
893 | ||
894 | static void vlv_power_well_enable(struct drm_i915_private *dev_priv, | |
895 | struct i915_power_well *power_well) | |
896 | { | |
897 | vlv_set_power_well(dev_priv, power_well, true); | |
898 | } | |
899 | ||
900 | static void vlv_power_well_disable(struct drm_i915_private *dev_priv, | |
901 | struct i915_power_well *power_well) | |
902 | { | |
903 | vlv_set_power_well(dev_priv, power_well, false); | |
904 | } | |
905 | ||
906 | static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, | |
907 | struct i915_power_well *power_well) | |
908 | { | |
909 | int power_well_id = power_well->data; | |
910 | bool enabled = false; | |
911 | u32 mask; | |
912 | u32 state; | |
913 | u32 ctrl; | |
914 | ||
915 | mask = PUNIT_PWRGT_MASK(power_well_id); | |
916 | ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); | |
917 | ||
918 | mutex_lock(&dev_priv->rps.hw_lock); | |
919 | ||
920 | state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; | |
921 | /* | |
922 | * We only ever set the power-on and power-gate states, anything | |
923 | * else is unexpected. | |
924 | */ | |
925 | WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && | |
926 | state != PUNIT_PWRGT_PWR_GATE(power_well_id)); | |
927 | if (state == ctrl) | |
928 | enabled = true; | |
929 | ||
930 | /* | |
931 | * A transient state at this point would mean some unexpected party | |
932 | * is poking at the power controls too. | |
933 | */ | |
934 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; | |
935 | WARN_ON(ctrl != state); | |
936 | ||
937 | mutex_unlock(&dev_priv->rps.hw_lock); | |
938 | ||
939 | return enabled; | |
940 | } | |
941 | ||
766078df VS |
942 | static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) |
943 | { | |
944 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); | |
945 | ||
946 | /* | |
947 | * Disable trickle feed and enable pnd deadline calculation | |
948 | */ | |
949 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); | |
950 | I915_WRITE(CBR1_VLV, 0); | |
19ab4ed3 VS |
951 | |
952 | WARN_ON(dev_priv->rawclk_freq == 0); | |
953 | ||
954 | I915_WRITE(RAWCLK_FREQ_VLV, | |
955 | DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 1000)); | |
766078df VS |
956 | } |
957 | ||
2be7d540 | 958 | static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) |
9c065a7d | 959 | { |
5a8fbb7d VS |
960 | enum pipe pipe; |
961 | ||
962 | /* | |
963 | * Enable the CRI clock source so we can get at the | |
964 | * display and the reference clock for VGA | |
965 | * hotplug / manual detection. Supposedly DSI also | |
966 | * needs the ref clock up and running. | |
967 | * | |
968 | * CHV DPLL B/C have some issues if VGA mode is enabled. | |
969 | */ | |
970 | for_each_pipe(dev_priv->dev, pipe) { | |
971 | u32 val = I915_READ(DPLL(pipe)); | |
972 | ||
973 | val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
974 | if (pipe != PIPE_A) | |
975 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
976 | ||
977 | I915_WRITE(DPLL(pipe), val); | |
978 | } | |
9c065a7d | 979 | |
766078df VS |
980 | vlv_init_display_clock_gating(dev_priv); |
981 | ||
9c065a7d DV |
982 | spin_lock_irq(&dev_priv->irq_lock); |
983 | valleyview_enable_display_irqs(dev_priv); | |
984 | spin_unlock_irq(&dev_priv->irq_lock); | |
985 | ||
986 | /* | |
987 | * During driver initialization/resume we can avoid restoring the | |
988 | * part of the HW/SW state that will be inited anyway explicitly. | |
989 | */ | |
990 | if (dev_priv->power_domains.initializing) | |
991 | return; | |
992 | ||
b963291c | 993 | intel_hpd_init(dev_priv); |
9c065a7d DV |
994 | |
995 | i915_redisable_vga_power_on(dev_priv->dev); | |
996 | } | |
997 | ||
2be7d540 VS |
998 | static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) |
999 | { | |
1000 | spin_lock_irq(&dev_priv->irq_lock); | |
1001 | valleyview_disable_display_irqs(dev_priv); | |
1002 | spin_unlock_irq(&dev_priv->irq_lock); | |
1003 | ||
2230fde8 VS |
1004 | /* make sure we're done processing display irqs */ |
1005 | synchronize_irq(dev_priv->dev->irq); | |
1006 | ||
2be7d540 VS |
1007 | vlv_power_sequencer_reset(dev_priv); |
1008 | } | |
1009 | ||
1010 | static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, | |
1011 | struct i915_power_well *power_well) | |
1012 | { | |
1013 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); | |
1014 | ||
1015 | vlv_set_power_well(dev_priv, power_well, true); | |
1016 | ||
1017 | vlv_display_power_well_init(dev_priv); | |
1018 | } | |
1019 | ||
9c065a7d DV |
1020 | static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, |
1021 | struct i915_power_well *power_well) | |
1022 | { | |
1023 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); | |
1024 | ||
2be7d540 | 1025 | vlv_display_power_well_deinit(dev_priv); |
9c065a7d DV |
1026 | |
1027 | vlv_set_power_well(dev_priv, power_well, false); | |
9c065a7d DV |
1028 | } |
1029 | ||
1030 | static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, | |
1031 | struct i915_power_well *power_well) | |
1032 | { | |
1033 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); | |
1034 | ||
5a8fbb7d | 1035 | /* since ref/cri clock was enabled */ |
9c065a7d DV |
1036 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |
1037 | ||
1038 | vlv_set_power_well(dev_priv, power_well, true); | |
1039 | ||
1040 | /* | |
1041 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
1042 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
1043 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
1044 | * b. The other bits such as sfr settings / modesel may all | |
1045 | * be set to 0. | |
1046 | * | |
1047 | * This should only be done on init and resume from S3 with | |
1048 | * both PLLs disabled, or we risk losing DPIO and PLL | |
1049 | * synchronization. | |
1050 | */ | |
1051 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
1052 | } | |
1053 | ||
1054 | static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, | |
1055 | struct i915_power_well *power_well) | |
1056 | { | |
1057 | enum pipe pipe; | |
1058 | ||
1059 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); | |
1060 | ||
1061 | for_each_pipe(dev_priv, pipe) | |
1062 | assert_pll_disabled(dev_priv, pipe); | |
1063 | ||
1064 | /* Assert common reset */ | |
1065 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); | |
1066 | ||
1067 | vlv_set_power_well(dev_priv, power_well, false); | |
1068 | } | |
1069 | ||
30142273 VS |
1070 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) |
1071 | ||
1072 | static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, | |
1073 | int power_well_id) | |
1074 | { | |
1075 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
30142273 VS |
1076 | int i; |
1077 | ||
fc17f227 ID |
1078 | for (i = 0; i < power_domains->power_well_count; i++) { |
1079 | struct i915_power_well *power_well; | |
1080 | ||
1081 | power_well = &power_domains->power_wells[i]; | |
30142273 VS |
1082 | if (power_well->data == power_well_id) |
1083 | return power_well; | |
1084 | } | |
1085 | ||
1086 | return NULL; | |
1087 | } | |
1088 | ||
1089 | #define BITS_SET(val, bits) (((val) & (bits)) == (bits)) | |
1090 | ||
1091 | static void assert_chv_phy_status(struct drm_i915_private *dev_priv) | |
1092 | { | |
1093 | struct i915_power_well *cmn_bc = | |
1094 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); | |
1095 | struct i915_power_well *cmn_d = | |
1096 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); | |
1097 | u32 phy_control = dev_priv->chv_phy_control; | |
1098 | u32 phy_status = 0; | |
3be60de9 | 1099 | u32 phy_status_mask = 0xffffffff; |
30142273 VS |
1100 | u32 tmp; |
1101 | ||
3be60de9 VS |
1102 | /* |
1103 | * The BIOS can leave the PHY is some weird state | |
1104 | * where it doesn't fully power down some parts. | |
1105 | * Disable the asserts until the PHY has been fully | |
1106 | * reset (ie. the power well has been disabled at | |
1107 | * least once). | |
1108 | */ | |
1109 | if (!dev_priv->chv_phy_assert[DPIO_PHY0]) | |
1110 | phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) | | |
1111 | PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) | | |
1112 | PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) | | |
1113 | PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) | | |
1114 | PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) | | |
1115 | PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1)); | |
1116 | ||
1117 | if (!dev_priv->chv_phy_assert[DPIO_PHY1]) | |
1118 | phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) | | |
1119 | PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) | | |
1120 | PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1)); | |
1121 | ||
30142273 VS |
1122 | if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { |
1123 | phy_status |= PHY_POWERGOOD(DPIO_PHY0); | |
1124 | ||
1125 | /* this assumes override is only used to enable lanes */ | |
1126 | if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) | |
1127 | phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); | |
1128 | ||
1129 | if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) | |
1130 | phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); | |
1131 | ||
1132 | /* CL1 is on whenever anything is on in either channel */ | |
1133 | if (BITS_SET(phy_control, | |
1134 | PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) | | |
1135 | PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1))) | |
1136 | phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0); | |
1137 | ||
1138 | /* | |
1139 | * The DPLLB check accounts for the pipe B + port A usage | |
1140 | * with CL2 powered up but all the lanes in the second channel | |
1141 | * powered down. | |
1142 | */ | |
1143 | if (BITS_SET(phy_control, | |
1144 | PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && | |
1145 | (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) | |
1146 | phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); | |
1147 | ||
1148 | if (BITS_SET(phy_control, | |
1149 | PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0))) | |
1150 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0); | |
1151 | if (BITS_SET(phy_control, | |
1152 | PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0))) | |
1153 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1); | |
1154 | ||
1155 | if (BITS_SET(phy_control, | |
1156 | PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1))) | |
1157 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0); | |
1158 | if (BITS_SET(phy_control, | |
1159 | PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1))) | |
1160 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1); | |
1161 | } | |
1162 | ||
1163 | if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { | |
1164 | phy_status |= PHY_POWERGOOD(DPIO_PHY1); | |
1165 | ||
1166 | /* this assumes override is only used to enable lanes */ | |
1167 | if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0) | |
1168 | phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0); | |
1169 | ||
1170 | if (BITS_SET(phy_control, | |
1171 | PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0))) | |
1172 | phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0); | |
1173 | ||
1174 | if (BITS_SET(phy_control, | |
1175 | PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0))) | |
1176 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0); | |
1177 | if (BITS_SET(phy_control, | |
1178 | PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0))) | |
1179 | phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1); | |
1180 | } | |
1181 | ||
3be60de9 VS |
1182 | phy_status &= phy_status_mask; |
1183 | ||
30142273 VS |
1184 | /* |
1185 | * The PHY may be busy with some initial calibration and whatnot, | |
1186 | * so the power state can take a while to actually change. | |
1187 | */ | |
3be60de9 | 1188 | if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10)) |
30142273 VS |
1189 | WARN(phy_status != tmp, |
1190 | "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n", | |
1191 | tmp, phy_status, dev_priv->chv_phy_control); | |
1192 | } | |
1193 | ||
1194 | #undef BITS_SET | |
1195 | ||
9c065a7d DV |
1196 | static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, |
1197 | struct i915_power_well *power_well) | |
1198 | { | |
1199 | enum dpio_phy phy; | |
e0fce78f VS |
1200 | enum pipe pipe; |
1201 | uint32_t tmp; | |
9c065a7d DV |
1202 | |
1203 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && | |
1204 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); | |
1205 | ||
e0fce78f VS |
1206 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { |
1207 | pipe = PIPE_A; | |
9c065a7d | 1208 | phy = DPIO_PHY0; |
e0fce78f VS |
1209 | } else { |
1210 | pipe = PIPE_C; | |
9c065a7d | 1211 | phy = DPIO_PHY1; |
e0fce78f | 1212 | } |
5a8fbb7d VS |
1213 | |
1214 | /* since ref/cri clock was enabled */ | |
9c065a7d DV |
1215 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |
1216 | vlv_set_power_well(dev_priv, power_well, true); | |
1217 | ||
1218 | /* Poll for phypwrgood signal */ | |
1219 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) | |
1220 | DRM_ERROR("Display PHY %d is not power up\n", phy); | |
1221 | ||
e0fce78f VS |
1222 | mutex_lock(&dev_priv->sb_lock); |
1223 | ||
1224 | /* Enable dynamic power down */ | |
1225 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); | |
ee279218 VS |
1226 | tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | |
1227 | DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; | |
e0fce78f VS |
1228 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); |
1229 | ||
1230 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { | |
1231 | tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); | |
1232 | tmp |= DPIO_DYNPWRDOWNEN_CH1; | |
1233 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); | |
3e288786 VS |
1234 | } else { |
1235 | /* | |
1236 | * Force the non-existing CL2 off. BXT does this | |
1237 | * too, so maybe it saves some power even though | |
1238 | * CL2 doesn't exist? | |
1239 | */ | |
1240 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30); | |
1241 | tmp |= DPIO_CL2_LDOFUSE_PWRENB; | |
1242 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp); | |
e0fce78f VS |
1243 | } |
1244 | ||
1245 | mutex_unlock(&dev_priv->sb_lock); | |
1246 | ||
70722468 VS |
1247 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); |
1248 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); | |
e0fce78f VS |
1249 | |
1250 | DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", | |
1251 | phy, dev_priv->chv_phy_control); | |
30142273 VS |
1252 | |
1253 | assert_chv_phy_status(dev_priv); | |
9c065a7d DV |
1254 | } |
1255 | ||
1256 | static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, | |
1257 | struct i915_power_well *power_well) | |
1258 | { | |
1259 | enum dpio_phy phy; | |
1260 | ||
1261 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && | |
1262 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); | |
1263 | ||
1264 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { | |
1265 | phy = DPIO_PHY0; | |
1266 | assert_pll_disabled(dev_priv, PIPE_A); | |
1267 | assert_pll_disabled(dev_priv, PIPE_B); | |
1268 | } else { | |
1269 | phy = DPIO_PHY1; | |
1270 | assert_pll_disabled(dev_priv, PIPE_C); | |
1271 | } | |
1272 | ||
70722468 VS |
1273 | dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); |
1274 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); | |
9c065a7d DV |
1275 | |
1276 | vlv_set_power_well(dev_priv, power_well, false); | |
e0fce78f VS |
1277 | |
1278 | DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", | |
1279 | phy, dev_priv->chv_phy_control); | |
30142273 | 1280 | |
3be60de9 VS |
1281 | /* PHY is fully reset now, so we can enable the PHY state asserts */ |
1282 | dev_priv->chv_phy_assert[phy] = true; | |
1283 | ||
30142273 | 1284 | assert_chv_phy_status(dev_priv); |
e0fce78f VS |
1285 | } |
1286 | ||
6669e39f VS |
1287 | static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
1288 | enum dpio_channel ch, bool override, unsigned int mask) | |
1289 | { | |
1290 | enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C; | |
1291 | u32 reg, val, expected, actual; | |
1292 | ||
3be60de9 VS |
1293 | /* |
1294 | * The BIOS can leave the PHY is some weird state | |
1295 | * where it doesn't fully power down some parts. | |
1296 | * Disable the asserts until the PHY has been fully | |
1297 | * reset (ie. the power well has been disabled at | |
1298 | * least once). | |
1299 | */ | |
1300 | if (!dev_priv->chv_phy_assert[phy]) | |
1301 | return; | |
1302 | ||
6669e39f VS |
1303 | if (ch == DPIO_CH0) |
1304 | reg = _CHV_CMN_DW0_CH0; | |
1305 | else | |
1306 | reg = _CHV_CMN_DW6_CH1; | |
1307 | ||
1308 | mutex_lock(&dev_priv->sb_lock); | |
1309 | val = vlv_dpio_read(dev_priv, pipe, reg); | |
1310 | mutex_unlock(&dev_priv->sb_lock); | |
1311 | ||
1312 | /* | |
1313 | * This assumes !override is only used when the port is disabled. | |
1314 | * All lanes should power down even without the override when | |
1315 | * the port is disabled. | |
1316 | */ | |
1317 | if (!override || mask == 0xf) { | |
1318 | expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; | |
1319 | /* | |
1320 | * If CH1 common lane is not active anymore | |
1321 | * (eg. for pipe B DPLL) the entire channel will | |
1322 | * shut down, which causes the common lane registers | |
1323 | * to read as 0. That means we can't actually check | |
1324 | * the lane power down status bits, but as the entire | |
1325 | * register reads as 0 it's a good indication that the | |
1326 | * channel is indeed entirely powered down. | |
1327 | */ | |
1328 | if (ch == DPIO_CH1 && val == 0) | |
1329 | expected = 0; | |
1330 | } else if (mask != 0x0) { | |
1331 | expected = DPIO_ANYDL_POWERDOWN; | |
1332 | } else { | |
1333 | expected = 0; | |
1334 | } | |
1335 | ||
1336 | if (ch == DPIO_CH0) | |
1337 | actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; | |
1338 | else | |
1339 | actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; | |
1340 | actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; | |
1341 | ||
1342 | WARN(actual != expected, | |
1343 | "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", | |
1344 | !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN), | |
1345 | !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN), | |
1346 | reg, val); | |
1347 | } | |
1348 | ||
b0b33846 VS |
1349 | bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
1350 | enum dpio_channel ch, bool override) | |
1351 | { | |
1352 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1353 | bool was_override; | |
1354 | ||
1355 | mutex_lock(&power_domains->lock); | |
1356 | ||
1357 | was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); | |
1358 | ||
1359 | if (override == was_override) | |
1360 | goto out; | |
1361 | ||
1362 | if (override) | |
1363 | dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); | |
1364 | else | |
1365 | dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); | |
1366 | ||
1367 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); | |
1368 | ||
1369 | DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", | |
1370 | phy, ch, dev_priv->chv_phy_control); | |
1371 | ||
30142273 VS |
1372 | assert_chv_phy_status(dev_priv); |
1373 | ||
b0b33846 VS |
1374 | out: |
1375 | mutex_unlock(&power_domains->lock); | |
1376 | ||
1377 | return was_override; | |
1378 | } | |
1379 | ||
e0fce78f VS |
1380 | void chv_phy_powergate_lanes(struct intel_encoder *encoder, |
1381 | bool override, unsigned int mask) | |
1382 | { | |
1383 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1384 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1385 | enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); | |
1386 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); | |
1387 | ||
1388 | mutex_lock(&power_domains->lock); | |
1389 | ||
1390 | dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); | |
1391 | dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); | |
1392 | ||
1393 | if (override) | |
1394 | dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); | |
1395 | else | |
1396 | dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); | |
1397 | ||
1398 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); | |
1399 | ||
1400 | DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", | |
1401 | phy, ch, mask, dev_priv->chv_phy_control); | |
1402 | ||
30142273 VS |
1403 | assert_chv_phy_status(dev_priv); |
1404 | ||
6669e39f VS |
1405 | assert_chv_phy_powergate(dev_priv, phy, ch, override, mask); |
1406 | ||
e0fce78f | 1407 | mutex_unlock(&power_domains->lock); |
9c065a7d DV |
1408 | } |
1409 | ||
1410 | static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, | |
1411 | struct i915_power_well *power_well) | |
1412 | { | |
1413 | enum pipe pipe = power_well->data; | |
1414 | bool enabled; | |
1415 | u32 state, ctrl; | |
1416 | ||
1417 | mutex_lock(&dev_priv->rps.hw_lock); | |
1418 | ||
1419 | state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); | |
1420 | /* | |
1421 | * We only ever set the power-on and power-gate states, anything | |
1422 | * else is unexpected. | |
1423 | */ | |
1424 | WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); | |
1425 | enabled = state == DP_SSS_PWR_ON(pipe); | |
1426 | ||
1427 | /* | |
1428 | * A transient state at this point would mean some unexpected party | |
1429 | * is poking at the power controls too. | |
1430 | */ | |
1431 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); | |
1432 | WARN_ON(ctrl << 16 != state); | |
1433 | ||
1434 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1435 | ||
1436 | return enabled; | |
1437 | } | |
1438 | ||
1439 | static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, | |
1440 | struct i915_power_well *power_well, | |
1441 | bool enable) | |
1442 | { | |
1443 | enum pipe pipe = power_well->data; | |
1444 | u32 state; | |
1445 | u32 ctrl; | |
1446 | ||
1447 | state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); | |
1448 | ||
1449 | mutex_lock(&dev_priv->rps.hw_lock); | |
1450 | ||
1451 | #define COND \ | |
1452 | ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) | |
1453 | ||
1454 | if (COND) | |
1455 | goto out; | |
1456 | ||
1457 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
1458 | ctrl &= ~DP_SSC_MASK(pipe); | |
1459 | ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); | |
1460 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); | |
1461 | ||
1462 | if (wait_for(COND, 100)) | |
7e35ab88 | 1463 | DRM_ERROR("timeout setting power well state %08x (%08x)\n", |
9c065a7d DV |
1464 | state, |
1465 | vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); | |
1466 | ||
1467 | #undef COND | |
1468 | ||
1469 | out: | |
1470 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1471 | } | |
1472 | ||
1473 | static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
1474 | struct i915_power_well *power_well) | |
1475 | { | |
8fcd5cd8 VS |
1476 | WARN_ON_ONCE(power_well->data != PIPE_A); |
1477 | ||
9c065a7d DV |
1478 | chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); |
1479 | } | |
1480 | ||
1481 | static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, | |
1482 | struct i915_power_well *power_well) | |
1483 | { | |
8fcd5cd8 | 1484 | WARN_ON_ONCE(power_well->data != PIPE_A); |
9c065a7d DV |
1485 | |
1486 | chv_set_pipe_power_well(dev_priv, power_well, true); | |
afd6275d | 1487 | |
2be7d540 | 1488 | vlv_display_power_well_init(dev_priv); |
9c065a7d DV |
1489 | } |
1490 | ||
1491 | static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, | |
1492 | struct i915_power_well *power_well) | |
1493 | { | |
8fcd5cd8 VS |
1494 | WARN_ON_ONCE(power_well->data != PIPE_A); |
1495 | ||
2be7d540 | 1496 | vlv_display_power_well_deinit(dev_priv); |
afd6275d | 1497 | |
9c065a7d DV |
1498 | chv_set_pipe_power_well(dev_priv, power_well, false); |
1499 | } | |
1500 | ||
09731280 ID |
1501 | static void |
1502 | __intel_display_power_get_domain(struct drm_i915_private *dev_priv, | |
1503 | enum intel_display_power_domain domain) | |
1504 | { | |
1505 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1506 | struct i915_power_well *power_well; | |
1507 | int i; | |
1508 | ||
1509 | for_each_power_well(i, power_well, BIT(domain), power_domains) { | |
1510 | if (!power_well->count++) | |
1511 | intel_power_well_enable(dev_priv, power_well); | |
1512 | } | |
1513 | ||
1514 | power_domains->domain_use_count[domain]++; | |
1515 | } | |
1516 | ||
e4e7684f DV |
1517 | /** |
1518 | * intel_display_power_get - grab a power domain reference | |
1519 | * @dev_priv: i915 device instance | |
1520 | * @domain: power domain to reference | |
1521 | * | |
1522 | * This function grabs a power domain reference for @domain and ensures that the | |
1523 | * power domain and all its parents are powered up. Therefore users should only | |
1524 | * grab a reference to the innermost power domain they need. | |
1525 | * | |
1526 | * Any power domain reference obtained by this function must have a symmetric | |
1527 | * call to intel_display_power_put() to release the reference again. | |
1528 | */ | |
9c065a7d DV |
1529 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
1530 | enum intel_display_power_domain domain) | |
1531 | { | |
09731280 | 1532 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
9c065a7d DV |
1533 | |
1534 | intel_runtime_pm_get(dev_priv); | |
1535 | ||
09731280 ID |
1536 | mutex_lock(&power_domains->lock); |
1537 | ||
1538 | __intel_display_power_get_domain(dev_priv, domain); | |
1539 | ||
1540 | mutex_unlock(&power_domains->lock); | |
1541 | } | |
1542 | ||
1543 | /** | |
1544 | * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain | |
1545 | * @dev_priv: i915 device instance | |
1546 | * @domain: power domain to reference | |
1547 | * | |
1548 | * This function grabs a power domain reference for @domain and ensures that the | |
1549 | * power domain and all its parents are powered up. Therefore users should only | |
1550 | * grab a reference to the innermost power domain they need. | |
1551 | * | |
1552 | * Any power domain reference obtained by this function must have a symmetric | |
1553 | * call to intel_display_power_put() to release the reference again. | |
1554 | */ | |
1555 | bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv, | |
1556 | enum intel_display_power_domain domain) | |
1557 | { | |
1558 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1559 | bool is_enabled; | |
1560 | ||
1561 | if (!intel_runtime_pm_get_if_in_use(dev_priv)) | |
1562 | return false; | |
9c065a7d DV |
1563 | |
1564 | mutex_lock(&power_domains->lock); | |
1565 | ||
09731280 ID |
1566 | if (__intel_display_power_is_enabled(dev_priv, domain)) { |
1567 | __intel_display_power_get_domain(dev_priv, domain); | |
1568 | is_enabled = true; | |
1569 | } else { | |
1570 | is_enabled = false; | |
9c065a7d DV |
1571 | } |
1572 | ||
9c065a7d | 1573 | mutex_unlock(&power_domains->lock); |
09731280 ID |
1574 | |
1575 | if (!is_enabled) | |
1576 | intel_runtime_pm_put(dev_priv); | |
1577 | ||
1578 | return is_enabled; | |
9c065a7d DV |
1579 | } |
1580 | ||
e4e7684f DV |
1581 | /** |
1582 | * intel_display_power_put - release a power domain reference | |
1583 | * @dev_priv: i915 device instance | |
1584 | * @domain: power domain to reference | |
1585 | * | |
1586 | * This function drops the power domain reference obtained by | |
1587 | * intel_display_power_get() and might power down the corresponding hardware | |
1588 | * block right away if this is the last reference. | |
1589 | */ | |
9c065a7d DV |
1590 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
1591 | enum intel_display_power_domain domain) | |
1592 | { | |
1593 | struct i915_power_domains *power_domains; | |
1594 | struct i915_power_well *power_well; | |
1595 | int i; | |
1596 | ||
1597 | power_domains = &dev_priv->power_domains; | |
1598 | ||
1599 | mutex_lock(&power_domains->lock); | |
1600 | ||
11c86db8 DS |
1601 | WARN(!power_domains->domain_use_count[domain], |
1602 | "Use count on domain %s is already zero\n", | |
1603 | intel_display_power_domain_str(domain)); | |
9c065a7d DV |
1604 | power_domains->domain_use_count[domain]--; |
1605 | ||
1606 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { | |
11c86db8 DS |
1607 | WARN(!power_well->count, |
1608 | "Use count on power well %s is already zero", | |
1609 | power_well->name); | |
9c065a7d | 1610 | |
d314cd43 | 1611 | if (!--power_well->count) |
dcddab3a | 1612 | intel_power_well_disable(dev_priv, power_well); |
9c065a7d DV |
1613 | } |
1614 | ||
1615 | mutex_unlock(&power_domains->lock); | |
1616 | ||
1617 | intel_runtime_pm_put(dev_priv); | |
1618 | } | |
1619 | ||
9d0996b5 VS |
1620 | #define HSW_DISPLAY_POWER_DOMAINS ( \ |
1621 | BIT(POWER_DOMAIN_PIPE_B) | \ | |
1622 | BIT(POWER_DOMAIN_PIPE_C) | \ | |
1623 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ | |
1624 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ | |
1625 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ | |
1626 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ | |
1627 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ | |
1628 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ | |
6331a704 PJ |
1629 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
1630 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ | |
1631 | BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ | |
9d0996b5 VS |
1632 | BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ |
1633 | BIT(POWER_DOMAIN_VGA) | \ | |
1634 | BIT(POWER_DOMAIN_AUDIO) | \ | |
9c065a7d DV |
1635 | BIT(POWER_DOMAIN_INIT)) |
1636 | ||
9d0996b5 VS |
1637 | #define BDW_DISPLAY_POWER_DOMAINS ( \ |
1638 | BIT(POWER_DOMAIN_PIPE_B) | \ | |
1639 | BIT(POWER_DOMAIN_PIPE_C) | \ | |
1640 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ | |
1641 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ | |
1642 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ | |
1643 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ | |
1644 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ | |
1645 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ | |
1646 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ | |
1647 | BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ | |
1648 | BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \ | |
1649 | BIT(POWER_DOMAIN_VGA) | \ | |
1650 | BIT(POWER_DOMAIN_AUDIO) | \ | |
9c065a7d DV |
1651 | BIT(POWER_DOMAIN_INIT)) |
1652 | ||
465ac0c6 VS |
1653 | #define VLV_DISPLAY_POWER_DOMAINS ( \ |
1654 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
1655 | BIT(POWER_DOMAIN_PIPE_B) | \ | |
1656 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ | |
1657 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ | |
1658 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ | |
1659 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ | |
1660 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ | |
1661 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ | |
1662 | BIT(POWER_DOMAIN_PORT_DSI) | \ | |
1663 | BIT(POWER_DOMAIN_PORT_CRT) | \ | |
1664 | BIT(POWER_DOMAIN_VGA) | \ | |
1665 | BIT(POWER_DOMAIN_AUDIO) | \ | |
1666 | BIT(POWER_DOMAIN_AUX_B) | \ | |
1667 | BIT(POWER_DOMAIN_AUX_C) | \ | |
1668 | BIT(POWER_DOMAIN_GMBUS) | \ | |
1669 | BIT(POWER_DOMAIN_INIT)) | |
9c065a7d DV |
1670 | |
1671 | #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ | |
6331a704 PJ |
1672 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
1673 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ | |
9c065a7d | 1674 | BIT(POWER_DOMAIN_PORT_CRT) | \ |
1407121a S |
1675 | BIT(POWER_DOMAIN_AUX_B) | \ |
1676 | BIT(POWER_DOMAIN_AUX_C) | \ | |
9c065a7d DV |
1677 | BIT(POWER_DOMAIN_INIT)) |
1678 | ||
1679 | #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ | |
6331a704 | 1680 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
1407121a | 1681 | BIT(POWER_DOMAIN_AUX_B) | \ |
9c065a7d DV |
1682 | BIT(POWER_DOMAIN_INIT)) |
1683 | ||
1684 | #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ | |
6331a704 | 1685 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
1407121a | 1686 | BIT(POWER_DOMAIN_AUX_B) | \ |
9c065a7d DV |
1687 | BIT(POWER_DOMAIN_INIT)) |
1688 | ||
1689 | #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ | |
6331a704 | 1690 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ |
1407121a | 1691 | BIT(POWER_DOMAIN_AUX_C) | \ |
9c065a7d DV |
1692 | BIT(POWER_DOMAIN_INIT)) |
1693 | ||
1694 | #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ | |
6331a704 | 1695 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ |
1407121a | 1696 | BIT(POWER_DOMAIN_AUX_C) | \ |
9c065a7d DV |
1697 | BIT(POWER_DOMAIN_INIT)) |
1698 | ||
465ac0c6 VS |
1699 | #define CHV_DISPLAY_POWER_DOMAINS ( \ |
1700 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
1701 | BIT(POWER_DOMAIN_PIPE_B) | \ | |
1702 | BIT(POWER_DOMAIN_PIPE_C) | \ | |
1703 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ | |
1704 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ | |
1705 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ | |
1706 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ | |
1707 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ | |
1708 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ | |
1709 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ | |
1710 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ | |
1711 | BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ | |
1712 | BIT(POWER_DOMAIN_PORT_DSI) | \ | |
1713 | BIT(POWER_DOMAIN_VGA) | \ | |
1714 | BIT(POWER_DOMAIN_AUDIO) | \ | |
1715 | BIT(POWER_DOMAIN_AUX_B) | \ | |
1716 | BIT(POWER_DOMAIN_AUX_C) | \ | |
1717 | BIT(POWER_DOMAIN_AUX_D) | \ | |
1718 | BIT(POWER_DOMAIN_GMBUS) | \ | |
1719 | BIT(POWER_DOMAIN_INIT)) | |
1720 | ||
9c065a7d | 1721 | #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ |
6331a704 PJ |
1722 | BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \ |
1723 | BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \ | |
1407121a S |
1724 | BIT(POWER_DOMAIN_AUX_B) | \ |
1725 | BIT(POWER_DOMAIN_AUX_C) | \ | |
9c065a7d DV |
1726 | BIT(POWER_DOMAIN_INIT)) |
1727 | ||
1728 | #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ | |
6331a704 | 1729 | BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \ |
1407121a | 1730 | BIT(POWER_DOMAIN_AUX_D) | \ |
9c065a7d DV |
1731 | BIT(POWER_DOMAIN_INIT)) |
1732 | ||
9c065a7d DV |
1733 | static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { |
1734 | .sync_hw = i9xx_always_on_power_well_noop, | |
1735 | .enable = i9xx_always_on_power_well_noop, | |
1736 | .disable = i9xx_always_on_power_well_noop, | |
1737 | .is_enabled = i9xx_always_on_power_well_enabled, | |
1738 | }; | |
1739 | ||
1740 | static const struct i915_power_well_ops chv_pipe_power_well_ops = { | |
1741 | .sync_hw = chv_pipe_power_well_sync_hw, | |
1742 | .enable = chv_pipe_power_well_enable, | |
1743 | .disable = chv_pipe_power_well_disable, | |
1744 | .is_enabled = chv_pipe_power_well_enabled, | |
1745 | }; | |
1746 | ||
1747 | static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { | |
1748 | .sync_hw = vlv_power_well_sync_hw, | |
1749 | .enable = chv_dpio_cmn_power_well_enable, | |
1750 | .disable = chv_dpio_cmn_power_well_disable, | |
1751 | .is_enabled = vlv_power_well_enabled, | |
1752 | }; | |
1753 | ||
1754 | static struct i915_power_well i9xx_always_on_power_well[] = { | |
1755 | { | |
1756 | .name = "always-on", | |
1757 | .always_on = 1, | |
1758 | .domains = POWER_DOMAIN_MASK, | |
1759 | .ops = &i9xx_always_on_power_well_ops, | |
1760 | }, | |
1761 | }; | |
1762 | ||
1763 | static const struct i915_power_well_ops hsw_power_well_ops = { | |
1764 | .sync_hw = hsw_power_well_sync_hw, | |
1765 | .enable = hsw_power_well_enable, | |
1766 | .disable = hsw_power_well_disable, | |
1767 | .is_enabled = hsw_power_well_enabled, | |
1768 | }; | |
1769 | ||
94dd5138 S |
1770 | static const struct i915_power_well_ops skl_power_well_ops = { |
1771 | .sync_hw = skl_power_well_sync_hw, | |
1772 | .enable = skl_power_well_enable, | |
1773 | .disable = skl_power_well_disable, | |
1774 | .is_enabled = skl_power_well_enabled, | |
1775 | }; | |
1776 | ||
9f836f90 PJ |
1777 | static const struct i915_power_well_ops gen9_dc_off_power_well_ops = { |
1778 | .sync_hw = gen9_dc_off_power_well_sync_hw, | |
1779 | .enable = gen9_dc_off_power_well_enable, | |
1780 | .disable = gen9_dc_off_power_well_disable, | |
1781 | .is_enabled = gen9_dc_off_power_well_enabled, | |
1782 | }; | |
1783 | ||
9c065a7d DV |
1784 | static struct i915_power_well hsw_power_wells[] = { |
1785 | { | |
1786 | .name = "always-on", | |
1787 | .always_on = 1, | |
998bd66a | 1788 | .domains = POWER_DOMAIN_MASK, |
9c065a7d DV |
1789 | .ops = &i9xx_always_on_power_well_ops, |
1790 | }, | |
1791 | { | |
1792 | .name = "display", | |
1793 | .domains = HSW_DISPLAY_POWER_DOMAINS, | |
1794 | .ops = &hsw_power_well_ops, | |
1795 | }, | |
1796 | }; | |
1797 | ||
1798 | static struct i915_power_well bdw_power_wells[] = { | |
1799 | { | |
1800 | .name = "always-on", | |
1801 | .always_on = 1, | |
998bd66a | 1802 | .domains = POWER_DOMAIN_MASK, |
9c065a7d DV |
1803 | .ops = &i9xx_always_on_power_well_ops, |
1804 | }, | |
1805 | { | |
1806 | .name = "display", | |
1807 | .domains = BDW_DISPLAY_POWER_DOMAINS, | |
1808 | .ops = &hsw_power_well_ops, | |
1809 | }, | |
1810 | }; | |
1811 | ||
1812 | static const struct i915_power_well_ops vlv_display_power_well_ops = { | |
1813 | .sync_hw = vlv_power_well_sync_hw, | |
1814 | .enable = vlv_display_power_well_enable, | |
1815 | .disable = vlv_display_power_well_disable, | |
1816 | .is_enabled = vlv_power_well_enabled, | |
1817 | }; | |
1818 | ||
1819 | static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { | |
1820 | .sync_hw = vlv_power_well_sync_hw, | |
1821 | .enable = vlv_dpio_cmn_power_well_enable, | |
1822 | .disable = vlv_dpio_cmn_power_well_disable, | |
1823 | .is_enabled = vlv_power_well_enabled, | |
1824 | }; | |
1825 | ||
1826 | static const struct i915_power_well_ops vlv_dpio_power_well_ops = { | |
1827 | .sync_hw = vlv_power_well_sync_hw, | |
1828 | .enable = vlv_power_well_enable, | |
1829 | .disable = vlv_power_well_disable, | |
1830 | .is_enabled = vlv_power_well_enabled, | |
1831 | }; | |
1832 | ||
1833 | static struct i915_power_well vlv_power_wells[] = { | |
1834 | { | |
1835 | .name = "always-on", | |
1836 | .always_on = 1, | |
998bd66a | 1837 | .domains = POWER_DOMAIN_MASK, |
9c065a7d | 1838 | .ops = &i9xx_always_on_power_well_ops, |
56fcfd63 | 1839 | .data = PUNIT_POWER_WELL_ALWAYS_ON, |
9c065a7d DV |
1840 | }, |
1841 | { | |
1842 | .name = "display", | |
1843 | .domains = VLV_DISPLAY_POWER_DOMAINS, | |
1844 | .data = PUNIT_POWER_WELL_DISP2D, | |
1845 | .ops = &vlv_display_power_well_ops, | |
1846 | }, | |
1847 | { | |
1848 | .name = "dpio-tx-b-01", | |
1849 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1850 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1851 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1852 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1853 | .ops = &vlv_dpio_power_well_ops, | |
1854 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, | |
1855 | }, | |
1856 | { | |
1857 | .name = "dpio-tx-b-23", | |
1858 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1859 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1860 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1861 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1862 | .ops = &vlv_dpio_power_well_ops, | |
1863 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, | |
1864 | }, | |
1865 | { | |
1866 | .name = "dpio-tx-c-01", | |
1867 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1868 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1869 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1870 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1871 | .ops = &vlv_dpio_power_well_ops, | |
1872 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, | |
1873 | }, | |
1874 | { | |
1875 | .name = "dpio-tx-c-23", | |
1876 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1877 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1878 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1879 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1880 | .ops = &vlv_dpio_power_well_ops, | |
1881 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, | |
1882 | }, | |
1883 | { | |
1884 | .name = "dpio-common", | |
1885 | .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, | |
1886 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, | |
1887 | .ops = &vlv_dpio_cmn_power_well_ops, | |
1888 | }, | |
1889 | }; | |
1890 | ||
1891 | static struct i915_power_well chv_power_wells[] = { | |
1892 | { | |
1893 | .name = "always-on", | |
1894 | .always_on = 1, | |
998bd66a | 1895 | .domains = POWER_DOMAIN_MASK, |
9c065a7d DV |
1896 | .ops = &i9xx_always_on_power_well_ops, |
1897 | }, | |
9c065a7d DV |
1898 | { |
1899 | .name = "display", | |
baa4e575 | 1900 | /* |
fde61e4b VS |
1901 | * Pipe A power well is the new disp2d well. Pipe B and C |
1902 | * power wells don't actually exist. Pipe A power well is | |
1903 | * required for any pipe to work. | |
baa4e575 | 1904 | */ |
465ac0c6 | 1905 | .domains = CHV_DISPLAY_POWER_DOMAINS, |
9c065a7d DV |
1906 | .data = PIPE_A, |
1907 | .ops = &chv_pipe_power_well_ops, | |
1908 | }, | |
9c065a7d DV |
1909 | { |
1910 | .name = "dpio-common-bc", | |
71849b67 | 1911 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, |
9c065a7d DV |
1912 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, |
1913 | .ops = &chv_dpio_cmn_power_well_ops, | |
1914 | }, | |
1915 | { | |
1916 | .name = "dpio-common-d", | |
71849b67 | 1917 | .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, |
9c065a7d DV |
1918 | .data = PUNIT_POWER_WELL_DPIO_CMN_D, |
1919 | .ops = &chv_dpio_cmn_power_well_ops, | |
1920 | }, | |
9c065a7d DV |
1921 | }; |
1922 | ||
5aefb239 SS |
1923 | bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, |
1924 | int power_well_id) | |
1925 | { | |
1926 | struct i915_power_well *power_well; | |
1927 | bool ret; | |
1928 | ||
1929 | power_well = lookup_power_well(dev_priv, power_well_id); | |
1930 | ret = power_well->ops->is_enabled(dev_priv, power_well); | |
1931 | ||
1932 | return ret; | |
1933 | } | |
1934 | ||
94dd5138 S |
1935 | static struct i915_power_well skl_power_wells[] = { |
1936 | { | |
1937 | .name = "always-on", | |
1938 | .always_on = 1, | |
998bd66a | 1939 | .domains = POWER_DOMAIN_MASK, |
94dd5138 | 1940 | .ops = &i9xx_always_on_power_well_ops, |
56fcfd63 | 1941 | .data = SKL_DISP_PW_ALWAYS_ON, |
94dd5138 S |
1942 | }, |
1943 | { | |
1944 | .name = "power well 1", | |
4a76f295 ID |
1945 | /* Handled by the DMC firmware */ |
1946 | .domains = 0, | |
94dd5138 S |
1947 | .ops = &skl_power_well_ops, |
1948 | .data = SKL_DISP_PW_1, | |
1949 | }, | |
1950 | { | |
1951 | .name = "MISC IO power well", | |
4a76f295 ID |
1952 | /* Handled by the DMC firmware */ |
1953 | .domains = 0, | |
94dd5138 S |
1954 | .ops = &skl_power_well_ops, |
1955 | .data = SKL_DISP_PW_MISC_IO, | |
1956 | }, | |
9f836f90 PJ |
1957 | { |
1958 | .name = "DC off", | |
1959 | .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS, | |
1960 | .ops = &gen9_dc_off_power_well_ops, | |
1961 | .data = SKL_DISP_PW_DC_OFF, | |
1962 | }, | |
94dd5138 S |
1963 | { |
1964 | .name = "power well 2", | |
1965 | .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, | |
1966 | .ops = &skl_power_well_ops, | |
1967 | .data = SKL_DISP_PW_2, | |
1968 | }, | |
1969 | { | |
1970 | .name = "DDI A/E power well", | |
1971 | .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS, | |
1972 | .ops = &skl_power_well_ops, | |
1973 | .data = SKL_DISP_PW_DDI_A_E, | |
1974 | }, | |
1975 | { | |
1976 | .name = "DDI B power well", | |
1977 | .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS, | |
1978 | .ops = &skl_power_well_ops, | |
1979 | .data = SKL_DISP_PW_DDI_B, | |
1980 | }, | |
1981 | { | |
1982 | .name = "DDI C power well", | |
1983 | .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS, | |
1984 | .ops = &skl_power_well_ops, | |
1985 | .data = SKL_DISP_PW_DDI_C, | |
1986 | }, | |
1987 | { | |
1988 | .name = "DDI D power well", | |
1989 | .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS, | |
1990 | .ops = &skl_power_well_ops, | |
1991 | .data = SKL_DISP_PW_DDI_D, | |
1992 | }, | |
1993 | }; | |
1994 | ||
0b4a2a36 S |
1995 | static struct i915_power_well bxt_power_wells[] = { |
1996 | { | |
1997 | .name = "always-on", | |
1998 | .always_on = 1, | |
998bd66a | 1999 | .domains = POWER_DOMAIN_MASK, |
0b4a2a36 S |
2000 | .ops = &i9xx_always_on_power_well_ops, |
2001 | }, | |
2002 | { | |
2003 | .name = "power well 1", | |
d7d7c9ee | 2004 | .domains = 0, |
0b4a2a36 S |
2005 | .ops = &skl_power_well_ops, |
2006 | .data = SKL_DISP_PW_1, | |
2007 | }, | |
9f836f90 PJ |
2008 | { |
2009 | .name = "DC off", | |
2010 | .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS, | |
2011 | .ops = &gen9_dc_off_power_well_ops, | |
2012 | .data = SKL_DISP_PW_DC_OFF, | |
2013 | }, | |
0b4a2a36 S |
2014 | { |
2015 | .name = "power well 2", | |
2016 | .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, | |
2017 | .ops = &skl_power_well_ops, | |
2018 | .data = SKL_DISP_PW_2, | |
9f836f90 | 2019 | }, |
0b4a2a36 S |
2020 | }; |
2021 | ||
1b0e3a04 ID |
2022 | static int |
2023 | sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv, | |
2024 | int disable_power_well) | |
2025 | { | |
2026 | if (disable_power_well >= 0) | |
2027 | return !!disable_power_well; | |
2028 | ||
1b0e3a04 ID |
2029 | return 1; |
2030 | } | |
2031 | ||
a37baf3b ID |
2032 | static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv, |
2033 | int enable_dc) | |
2034 | { | |
2035 | uint32_t mask; | |
2036 | int requested_dc; | |
2037 | int max_dc; | |
2038 | ||
2039 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { | |
2040 | max_dc = 2; | |
2041 | mask = 0; | |
2042 | } else if (IS_BROXTON(dev_priv)) { | |
2043 | max_dc = 1; | |
2044 | /* | |
2045 | * DC9 has a separate HW flow from the rest of the DC states, | |
2046 | * not depending on the DMC firmware. It's needed by system | |
2047 | * suspend/resume, so allow it unconditionally. | |
2048 | */ | |
2049 | mask = DC_STATE_EN_DC9; | |
2050 | } else { | |
2051 | max_dc = 0; | |
2052 | mask = 0; | |
2053 | } | |
2054 | ||
66e2c4c3 ID |
2055 | if (!i915.disable_power_well) |
2056 | max_dc = 0; | |
2057 | ||
a37baf3b ID |
2058 | if (enable_dc >= 0 && enable_dc <= max_dc) { |
2059 | requested_dc = enable_dc; | |
2060 | } else if (enable_dc == -1) { | |
2061 | requested_dc = max_dc; | |
2062 | } else if (enable_dc > max_dc && enable_dc <= 2) { | |
2063 | DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n", | |
2064 | enable_dc, max_dc); | |
2065 | requested_dc = max_dc; | |
2066 | } else { | |
2067 | DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc); | |
2068 | requested_dc = max_dc; | |
2069 | } | |
2070 | ||
2071 | if (requested_dc > 1) | |
2072 | mask |= DC_STATE_EN_UPTO_DC6; | |
2073 | if (requested_dc > 0) | |
2074 | mask |= DC_STATE_EN_UPTO_DC5; | |
2075 | ||
2076 | DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask); | |
2077 | ||
2078 | return mask; | |
2079 | } | |
2080 | ||
9c065a7d DV |
2081 | #define set_power_wells(power_domains, __power_wells) ({ \ |
2082 | (power_domains)->power_wells = (__power_wells); \ | |
2083 | (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ | |
2084 | }) | |
2085 | ||
e4e7684f DV |
2086 | /** |
2087 | * intel_power_domains_init - initializes the power domain structures | |
2088 | * @dev_priv: i915 device instance | |
2089 | * | |
2090 | * Initializes the power domain structures for @dev_priv depending upon the | |
2091 | * supported platform. | |
2092 | */ | |
9c065a7d DV |
2093 | int intel_power_domains_init(struct drm_i915_private *dev_priv) |
2094 | { | |
2095 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2096 | ||
1b0e3a04 ID |
2097 | i915.disable_power_well = sanitize_disable_power_well_option(dev_priv, |
2098 | i915.disable_power_well); | |
a37baf3b ID |
2099 | dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv, |
2100 | i915.enable_dc); | |
1b0e3a04 | 2101 | |
f0ab43e6 VS |
2102 | BUILD_BUG_ON(POWER_DOMAIN_NUM > 31); |
2103 | ||
9c065a7d DV |
2104 | mutex_init(&power_domains->lock); |
2105 | ||
2106 | /* | |
2107 | * The enabling order will be from lower to higher indexed wells, | |
2108 | * the disabling order is reversed. | |
2109 | */ | |
2d1fe073 | 2110 | if (IS_HASWELL(dev_priv)) { |
9c065a7d | 2111 | set_power_wells(power_domains, hsw_power_wells); |
2d1fe073 | 2112 | } else if (IS_BROADWELL(dev_priv)) { |
9c065a7d | 2113 | set_power_wells(power_domains, bdw_power_wells); |
2d1fe073 | 2114 | } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) { |
94dd5138 | 2115 | set_power_wells(power_domains, skl_power_wells); |
2d1fe073 | 2116 | } else if (IS_BROXTON(dev_priv)) { |
0b4a2a36 | 2117 | set_power_wells(power_domains, bxt_power_wells); |
2d1fe073 | 2118 | } else if (IS_CHERRYVIEW(dev_priv)) { |
9c065a7d | 2119 | set_power_wells(power_domains, chv_power_wells); |
2d1fe073 | 2120 | } else if (IS_VALLEYVIEW(dev_priv)) { |
9c065a7d DV |
2121 | set_power_wells(power_domains, vlv_power_wells); |
2122 | } else { | |
2123 | set_power_wells(power_domains, i9xx_always_on_power_well); | |
2124 | } | |
2125 | ||
2126 | return 0; | |
2127 | } | |
2128 | ||
e4e7684f DV |
2129 | /** |
2130 | * intel_power_domains_fini - finalizes the power domain structures | |
2131 | * @dev_priv: i915 device instance | |
2132 | * | |
2133 | * Finalizes the power domain structures for @dev_priv depending upon the | |
2134 | * supported platform. This function also disables runtime pm and ensures that | |
2135 | * the device stays powered up so that the driver can be reloaded. | |
2136 | */ | |
f458ebbc | 2137 | void intel_power_domains_fini(struct drm_i915_private *dev_priv) |
9c065a7d | 2138 | { |
25b181b4 ID |
2139 | struct device *device = &dev_priv->dev->pdev->dev; |
2140 | ||
aabee1bb ID |
2141 | /* |
2142 | * The i915.ko module is still not prepared to be loaded when | |
f458ebbc | 2143 | * the power well is not enabled, so just enable it in case |
aabee1bb ID |
2144 | * we're going to unload/reload. |
2145 | * The following also reacquires the RPM reference the core passed | |
2146 | * to the driver during loading, which is dropped in | |
2147 | * intel_runtime_pm_enable(). We have to hand back the control of the | |
2148 | * device to the core with this reference held. | |
2149 | */ | |
f458ebbc | 2150 | intel_display_set_init_power(dev_priv, true); |
d314cd43 ID |
2151 | |
2152 | /* Remove the refcount we took to keep power well support disabled. */ | |
2153 | if (!i915.disable_power_well) | |
2154 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
25b181b4 ID |
2155 | |
2156 | /* | |
2157 | * Remove the refcount we took in intel_runtime_pm_enable() in case | |
2158 | * the platform doesn't support runtime PM. | |
2159 | */ | |
2160 | if (!HAS_RUNTIME_PM(dev_priv)) | |
2161 | pm_runtime_put(device); | |
9c065a7d DV |
2162 | } |
2163 | ||
30eade12 | 2164 | static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv) |
9c065a7d DV |
2165 | { |
2166 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2167 | struct i915_power_well *power_well; | |
2168 | int i; | |
2169 | ||
2170 | mutex_lock(&power_domains->lock); | |
2171 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { | |
2172 | power_well->ops->sync_hw(dev_priv, power_well); | |
2173 | power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, | |
2174 | power_well); | |
2175 | } | |
2176 | mutex_unlock(&power_domains->lock); | |
2177 | } | |
2178 | ||
70c2c184 VS |
2179 | static void gen9_dbuf_enable(struct drm_i915_private *dev_priv) |
2180 | { | |
2181 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
2182 | POSTING_READ(DBUF_CTL); | |
2183 | ||
2184 | udelay(10); | |
2185 | ||
2186 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
2187 | DRM_ERROR("DBuf power enable timeout\n"); | |
2188 | } | |
2189 | ||
2190 | static void gen9_dbuf_disable(struct drm_i915_private *dev_priv) | |
2191 | { | |
2192 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
2193 | POSTING_READ(DBUF_CTL); | |
2194 | ||
2195 | udelay(10); | |
2196 | ||
2197 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
2198 | DRM_ERROR("DBuf power disable timeout!\n"); | |
2199 | } | |
2200 | ||
73dfc227 | 2201 | static void skl_display_core_init(struct drm_i915_private *dev_priv, |
443a93ac | 2202 | bool resume) |
73dfc227 ID |
2203 | { |
2204 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
443a93ac | 2205 | struct i915_power_well *well; |
73dfc227 ID |
2206 | uint32_t val; |
2207 | ||
d26fa1d5 ID |
2208 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); |
2209 | ||
73dfc227 ID |
2210 | /* enable PCH reset handshake */ |
2211 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
2212 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE); | |
2213 | ||
2214 | /* enable PG1 and Misc I/O */ | |
2215 | mutex_lock(&power_domains->lock); | |
443a93ac ID |
2216 | |
2217 | well = lookup_power_well(dev_priv, SKL_DISP_PW_1); | |
2218 | intel_power_well_enable(dev_priv, well); | |
2219 | ||
2220 | well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); | |
2221 | intel_power_well_enable(dev_priv, well); | |
2222 | ||
73dfc227 ID |
2223 | mutex_unlock(&power_domains->lock); |
2224 | ||
73dfc227 ID |
2225 | skl_init_cdclk(dev_priv); |
2226 | ||
70c2c184 VS |
2227 | gen9_dbuf_enable(dev_priv); |
2228 | ||
9f7eb31a | 2229 | if (resume && dev_priv->csr.dmc_payload) |
2abc525b | 2230 | intel_csr_load_program(dev_priv); |
73dfc227 ID |
2231 | } |
2232 | ||
2233 | static void skl_display_core_uninit(struct drm_i915_private *dev_priv) | |
2234 | { | |
2235 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
443a93ac | 2236 | struct i915_power_well *well; |
73dfc227 | 2237 | |
d26fa1d5 ID |
2238 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); |
2239 | ||
70c2c184 VS |
2240 | gen9_dbuf_disable(dev_priv); |
2241 | ||
73dfc227 ID |
2242 | skl_uninit_cdclk(dev_priv); |
2243 | ||
2244 | /* The spec doesn't call for removing the reset handshake flag */ | |
2245 | /* disable PG1 and Misc I/O */ | |
443a93ac | 2246 | |
73dfc227 | 2247 | mutex_lock(&power_domains->lock); |
443a93ac ID |
2248 | |
2249 | well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO); | |
2250 | intel_power_well_disable(dev_priv, well); | |
2251 | ||
2252 | well = lookup_power_well(dev_priv, SKL_DISP_PW_1); | |
2253 | intel_power_well_disable(dev_priv, well); | |
2254 | ||
73dfc227 ID |
2255 | mutex_unlock(&power_domains->lock); |
2256 | } | |
2257 | ||
d7d7c9ee ID |
2258 | void bxt_display_core_init(struct drm_i915_private *dev_priv, |
2259 | bool resume) | |
2260 | { | |
2261 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2262 | struct i915_power_well *well; | |
2263 | uint32_t val; | |
2264 | ||
2265 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); | |
2266 | ||
2267 | /* | |
2268 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
2269 | * or else the reset will hang because there is no PCH to respond. | |
2270 | * Move the handshake programming to initialization sequence. | |
2271 | * Previously was left up to BIOS. | |
2272 | */ | |
2273 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
2274 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
2275 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
2276 | ||
2277 | /* Enable PG1 */ | |
2278 | mutex_lock(&power_domains->lock); | |
2279 | ||
2280 | well = lookup_power_well(dev_priv, SKL_DISP_PW_1); | |
2281 | intel_power_well_enable(dev_priv, well); | |
2282 | ||
2283 | mutex_unlock(&power_domains->lock); | |
2284 | ||
2285 | broxton_init_cdclk(dev_priv); | |
70c2c184 VS |
2286 | |
2287 | gen9_dbuf_enable(dev_priv); | |
2288 | ||
d7d7c9ee ID |
2289 | broxton_ddi_phy_init(dev_priv); |
2290 | ||
adc7f04b ID |
2291 | broxton_cdclk_verify_state(dev_priv); |
2292 | broxton_ddi_phy_verify_state(dev_priv); | |
2293 | ||
d7d7c9ee ID |
2294 | if (resume && dev_priv->csr.dmc_payload) |
2295 | intel_csr_load_program(dev_priv); | |
2296 | } | |
2297 | ||
2298 | void bxt_display_core_uninit(struct drm_i915_private *dev_priv) | |
2299 | { | |
2300 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2301 | struct i915_power_well *well; | |
2302 | ||
2303 | gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); | |
2304 | ||
2305 | broxton_ddi_phy_uninit(dev_priv); | |
70c2c184 VS |
2306 | |
2307 | gen9_dbuf_disable(dev_priv); | |
2308 | ||
d7d7c9ee ID |
2309 | broxton_uninit_cdclk(dev_priv); |
2310 | ||
2311 | /* The spec doesn't call for removing the reset handshake flag */ | |
2312 | ||
2313 | /* Disable PG1 */ | |
2314 | mutex_lock(&power_domains->lock); | |
2315 | ||
2316 | well = lookup_power_well(dev_priv, SKL_DISP_PW_1); | |
2317 | intel_power_well_disable(dev_priv, well); | |
2318 | ||
2319 | mutex_unlock(&power_domains->lock); | |
2320 | } | |
2321 | ||
70722468 VS |
2322 | static void chv_phy_control_init(struct drm_i915_private *dev_priv) |
2323 | { | |
2324 | struct i915_power_well *cmn_bc = | |
2325 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); | |
2326 | struct i915_power_well *cmn_d = | |
2327 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); | |
2328 | ||
2329 | /* | |
2330 | * DISPLAY_PHY_CONTROL can get corrupted if read. As a | |
2331 | * workaround never ever read DISPLAY_PHY_CONTROL, and | |
2332 | * instead maintain a shadow copy ourselves. Use the actual | |
e0fce78f VS |
2333 | * power well state and lane status to reconstruct the |
2334 | * expected initial value. | |
70722468 VS |
2335 | */ |
2336 | dev_priv->chv_phy_control = | |
bc284542 VS |
2337 | PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | |
2338 | PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | | |
e0fce78f VS |
2339 | PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | |
2340 | PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | | |
2341 | PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); | |
2342 | ||
2343 | /* | |
2344 | * If all lanes are disabled we leave the override disabled | |
2345 | * with all power down bits cleared to match the state we | |
2346 | * would use after disabling the port. Otherwise enable the | |
2347 | * override and set the lane powerdown bits accding to the | |
2348 | * current lane status. | |
2349 | */ | |
2350 | if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { | |
2351 | uint32_t status = I915_READ(DPLL(PIPE_A)); | |
2352 | unsigned int mask; | |
2353 | ||
2354 | mask = status & DPLL_PORTB_READY_MASK; | |
2355 | if (mask == 0xf) | |
2356 | mask = 0x0; | |
2357 | else | |
2358 | dev_priv->chv_phy_control |= | |
2359 | PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); | |
2360 | ||
2361 | dev_priv->chv_phy_control |= | |
2362 | PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); | |
2363 | ||
2364 | mask = (status & DPLL_PORTC_READY_MASK) >> 4; | |
2365 | if (mask == 0xf) | |
2366 | mask = 0x0; | |
2367 | else | |
2368 | dev_priv->chv_phy_control |= | |
2369 | PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); | |
2370 | ||
2371 | dev_priv->chv_phy_control |= | |
2372 | PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); | |
2373 | ||
70722468 | 2374 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); |
3be60de9 VS |
2375 | |
2376 | dev_priv->chv_phy_assert[DPIO_PHY0] = false; | |
2377 | } else { | |
2378 | dev_priv->chv_phy_assert[DPIO_PHY0] = true; | |
e0fce78f VS |
2379 | } |
2380 | ||
2381 | if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { | |
2382 | uint32_t status = I915_READ(DPIO_PHY_STATUS); | |
2383 | unsigned int mask; | |
2384 | ||
2385 | mask = status & DPLL_PORTD_READY_MASK; | |
2386 | ||
2387 | if (mask == 0xf) | |
2388 | mask = 0x0; | |
2389 | else | |
2390 | dev_priv->chv_phy_control |= | |
2391 | PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); | |
2392 | ||
2393 | dev_priv->chv_phy_control |= | |
2394 | PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); | |
2395 | ||
70722468 | 2396 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); |
3be60de9 VS |
2397 | |
2398 | dev_priv->chv_phy_assert[DPIO_PHY1] = false; | |
2399 | } else { | |
2400 | dev_priv->chv_phy_assert[DPIO_PHY1] = true; | |
e0fce78f VS |
2401 | } |
2402 | ||
2403 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); | |
2404 | ||
2405 | DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", | |
2406 | dev_priv->chv_phy_control); | |
70722468 VS |
2407 | } |
2408 | ||
9c065a7d DV |
2409 | static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) |
2410 | { | |
2411 | struct i915_power_well *cmn = | |
2412 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); | |
2413 | struct i915_power_well *disp2d = | |
2414 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); | |
2415 | ||
9c065a7d | 2416 | /* If the display might be already active skip this */ |
5d93a6e5 VS |
2417 | if (cmn->ops->is_enabled(dev_priv, cmn) && |
2418 | disp2d->ops->is_enabled(dev_priv, disp2d) && | |
9c065a7d DV |
2419 | I915_READ(DPIO_CTL) & DPIO_CMNRST) |
2420 | return; | |
2421 | ||
2422 | DRM_DEBUG_KMS("toggling display PHY side reset\n"); | |
2423 | ||
2424 | /* cmnlane needs DPLL registers */ | |
2425 | disp2d->ops->enable(dev_priv, disp2d); | |
2426 | ||
2427 | /* | |
2428 | * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: | |
2429 | * Need to assert and de-assert PHY SB reset by gating the | |
2430 | * common lane power, then un-gating it. | |
2431 | * Simply ungating isn't enough to reset the PHY enough to get | |
2432 | * ports and lanes running. | |
2433 | */ | |
2434 | cmn->ops->disable(dev_priv, cmn); | |
2435 | } | |
2436 | ||
e4e7684f DV |
2437 | /** |
2438 | * intel_power_domains_init_hw - initialize hardware power domain state | |
2439 | * @dev_priv: i915 device instance | |
2440 | * | |
2441 | * This function initializes the hardware power domain state and enables all | |
2442 | * power domains using intel_display_set_init_power(). | |
2443 | */ | |
73dfc227 | 2444 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume) |
9c065a7d DV |
2445 | { |
2446 | struct drm_device *dev = dev_priv->dev; | |
2447 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
2448 | ||
2449 | power_domains->initializing = true; | |
2450 | ||
73dfc227 ID |
2451 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
2452 | skl_display_core_init(dev_priv, resume); | |
d7d7c9ee ID |
2453 | } else if (IS_BROXTON(dev)) { |
2454 | bxt_display_core_init(dev_priv, resume); | |
73dfc227 | 2455 | } else if (IS_CHERRYVIEW(dev)) { |
770effb1 | 2456 | mutex_lock(&power_domains->lock); |
70722468 | 2457 | chv_phy_control_init(dev_priv); |
770effb1 | 2458 | mutex_unlock(&power_domains->lock); |
70722468 | 2459 | } else if (IS_VALLEYVIEW(dev)) { |
9c065a7d DV |
2460 | mutex_lock(&power_domains->lock); |
2461 | vlv_cmnlane_wa(dev_priv); | |
2462 | mutex_unlock(&power_domains->lock); | |
2463 | } | |
2464 | ||
2465 | /* For now, we need the power well to be always enabled. */ | |
2466 | intel_display_set_init_power(dev_priv, true); | |
d314cd43 ID |
2467 | /* Disable power support if the user asked so. */ |
2468 | if (!i915.disable_power_well) | |
2469 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
30eade12 | 2470 | intel_power_domains_sync_hw(dev_priv); |
9c065a7d DV |
2471 | power_domains->initializing = false; |
2472 | } | |
2473 | ||
73dfc227 ID |
2474 | /** |
2475 | * intel_power_domains_suspend - suspend power domain state | |
2476 | * @dev_priv: i915 device instance | |
2477 | * | |
2478 | * This function prepares the hardware power domain state before entering | |
2479 | * system suspend. It must be paired with intel_power_domains_init_hw(). | |
2480 | */ | |
2481 | void intel_power_domains_suspend(struct drm_i915_private *dev_priv) | |
2482 | { | |
d314cd43 ID |
2483 | /* |
2484 | * Even if power well support was disabled we still want to disable | |
2485 | * power wells while we are system suspended. | |
2486 | */ | |
2487 | if (!i915.disable_power_well) | |
2488 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
2622d79b ID |
2489 | |
2490 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) | |
2491 | skl_display_core_uninit(dev_priv); | |
d7d7c9ee ID |
2492 | else if (IS_BROXTON(dev_priv)) |
2493 | bxt_display_core_uninit(dev_priv); | |
73dfc227 ID |
2494 | } |
2495 | ||
e4e7684f DV |
2496 | /** |
2497 | * intel_runtime_pm_get - grab a runtime pm reference | |
2498 | * @dev_priv: i915 device instance | |
2499 | * | |
2500 | * This function grabs a device-level runtime pm reference (mostly used for GEM | |
2501 | * code to ensure the GTT or GT is on) and ensures that it is powered up. | |
2502 | * | |
2503 | * Any runtime pm reference obtained by this function must have a symmetric | |
2504 | * call to intel_runtime_pm_put() to release the reference again. | |
2505 | */ | |
9c065a7d DV |
2506 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv) |
2507 | { | |
2508 | struct drm_device *dev = dev_priv->dev; | |
2509 | struct device *device = &dev->pdev->dev; | |
2510 | ||
9c065a7d | 2511 | pm_runtime_get_sync(device); |
1f814dac ID |
2512 | |
2513 | atomic_inc(&dev_priv->pm.wakeref_count); | |
c9b8846a | 2514 | assert_rpm_wakelock_held(dev_priv); |
9c065a7d DV |
2515 | } |
2516 | ||
09731280 ID |
2517 | /** |
2518 | * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use | |
2519 | * @dev_priv: i915 device instance | |
2520 | * | |
2521 | * This function grabs a device-level runtime pm reference if the device is | |
2522 | * already in use and ensures that it is powered up. | |
2523 | * | |
2524 | * Any runtime pm reference obtained by this function must have a symmetric | |
2525 | * call to intel_runtime_pm_put() to release the reference again. | |
2526 | */ | |
2527 | bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv) | |
2528 | { | |
2529 | struct drm_device *dev = dev_priv->dev; | |
2530 | struct device *device = &dev->pdev->dev; | |
09731280 | 2531 | |
135dc79e CW |
2532 | if (IS_ENABLED(CONFIG_PM)) { |
2533 | int ret = pm_runtime_get_if_in_use(device); | |
09731280 | 2534 | |
135dc79e CW |
2535 | /* |
2536 | * In cases runtime PM is disabled by the RPM core and we get | |
2537 | * an -EINVAL return value we are not supposed to call this | |
2538 | * function, since the power state is undefined. This applies | |
2539 | * atm to the late/early system suspend/resume handlers. | |
2540 | */ | |
2541 | WARN_ON_ONCE(ret < 0); | |
2542 | if (ret <= 0) | |
2543 | return false; | |
2544 | } | |
09731280 ID |
2545 | |
2546 | atomic_inc(&dev_priv->pm.wakeref_count); | |
2547 | assert_rpm_wakelock_held(dev_priv); | |
2548 | ||
2549 | return true; | |
2550 | } | |
2551 | ||
e4e7684f DV |
2552 | /** |
2553 | * intel_runtime_pm_get_noresume - grab a runtime pm reference | |
2554 | * @dev_priv: i915 device instance | |
2555 | * | |
2556 | * This function grabs a device-level runtime pm reference (mostly used for GEM | |
2557 | * code to ensure the GTT or GT is on). | |
2558 | * | |
2559 | * It will _not_ power up the device but instead only check that it's powered | |
2560 | * on. Therefore it is only valid to call this functions from contexts where | |
2561 | * the device is known to be powered up and where trying to power it up would | |
2562 | * result in hilarity and deadlocks. That pretty much means only the system | |
2563 | * suspend/resume code where this is used to grab runtime pm references for | |
2564 | * delayed setup down in work items. | |
2565 | * | |
2566 | * Any runtime pm reference obtained by this function must have a symmetric | |
2567 | * call to intel_runtime_pm_put() to release the reference again. | |
2568 | */ | |
9c065a7d DV |
2569 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) |
2570 | { | |
2571 | struct drm_device *dev = dev_priv->dev; | |
2572 | struct device *device = &dev->pdev->dev; | |
2573 | ||
c9b8846a | 2574 | assert_rpm_wakelock_held(dev_priv); |
9c065a7d | 2575 | pm_runtime_get_noresume(device); |
1f814dac ID |
2576 | |
2577 | atomic_inc(&dev_priv->pm.wakeref_count); | |
9c065a7d DV |
2578 | } |
2579 | ||
e4e7684f DV |
2580 | /** |
2581 | * intel_runtime_pm_put - release a runtime pm reference | |
2582 | * @dev_priv: i915 device instance | |
2583 | * | |
2584 | * This function drops the device-level runtime pm reference obtained by | |
2585 | * intel_runtime_pm_get() and might power down the corresponding | |
2586 | * hardware block right away if this is the last reference. | |
2587 | */ | |
9c065a7d DV |
2588 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv) |
2589 | { | |
2590 | struct drm_device *dev = dev_priv->dev; | |
2591 | struct device *device = &dev->pdev->dev; | |
2592 | ||
542db3cd | 2593 | assert_rpm_wakelock_held(dev_priv); |
2b19efeb ID |
2594 | if (atomic_dec_and_test(&dev_priv->pm.wakeref_count)) |
2595 | atomic_inc(&dev_priv->pm.atomic_seq); | |
1f814dac | 2596 | |
9c065a7d DV |
2597 | pm_runtime_mark_last_busy(device); |
2598 | pm_runtime_put_autosuspend(device); | |
2599 | } | |
2600 | ||
e4e7684f DV |
2601 | /** |
2602 | * intel_runtime_pm_enable - enable runtime pm | |
2603 | * @dev_priv: i915 device instance | |
2604 | * | |
2605 | * This function enables runtime pm at the end of the driver load sequence. | |
2606 | * | |
2607 | * Note that this function does currently not enable runtime pm for the | |
2608 | * subordinate display power domains. That is only done on the first modeset | |
2609 | * using intel_display_set_init_power(). | |
2610 | */ | |
f458ebbc | 2611 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) |
9c065a7d DV |
2612 | { |
2613 | struct drm_device *dev = dev_priv->dev; | |
2614 | struct device *device = &dev->pdev->dev; | |
2615 | ||
cbc68dc9 ID |
2616 | pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ |
2617 | pm_runtime_mark_last_busy(device); | |
2618 | ||
25b181b4 ID |
2619 | /* |
2620 | * Take a permanent reference to disable the RPM functionality and drop | |
2621 | * it only when unloading the driver. Use the low level get/put helpers, | |
2622 | * so the driver's own RPM reference tracking asserts also work on | |
2623 | * platforms without RPM support. | |
2624 | */ | |
cbc68dc9 ID |
2625 | if (!HAS_RUNTIME_PM(dev)) { |
2626 | pm_runtime_dont_use_autosuspend(device); | |
25b181b4 | 2627 | pm_runtime_get_sync(device); |
cbc68dc9 ID |
2628 | } else { |
2629 | pm_runtime_use_autosuspend(device); | |
2630 | } | |
9c065a7d | 2631 | |
aabee1bb ID |
2632 | /* |
2633 | * The core calls the driver load handler with an RPM reference held. | |
2634 | * We drop that here and will reacquire it during unloading in | |
2635 | * intel_power_domains_fini(). | |
2636 | */ | |
9c065a7d DV |
2637 | pm_runtime_put_autosuspend(device); |
2638 | } | |
2639 |