]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/gpu/drm/i915/intel_runtime_pm.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915/gen9: Verify and enforce dc6 state writes
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_runtime_pm.c
CommitLineData
9c065a7d
DV		 1/*
2 * Copyright © 2012-2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 * Daniel Vetter <daniel.vetter@ffwll.ch>
26 *
27 */
28
29#include <linux/pm_runtime.h>
30#include <linux/vgaarb.h>
31
32#include "i915_drv.h"
33#include "intel_drv.h"
9c065a7d 34
e4e7684f
DV		 35/**
36 * DOC: runtime pm
37 *
38 * The i915 driver supports dynamic enabling and disabling of entire hardware
39 * blocks at runtime. This is especially important on the display side where
40 * software is supposed to control many power gates manually on recent hardware,
41 * since on the GT side a lot of the power management is done by the hardware.
42 * But even there some manual control at the device level is required.
43 *
44 * Since i915 supports a diverse set of platforms with a unified codebase and
45 * hardware engineers just love to shuffle functionality around between power
46 * domains there's a sizeable amount of indirection required. This file provides
47 * generic functions to the driver for grabbing and releasing references for
48 * abstract power domains. It then maps those to the actual power wells
49 * present for a given platform.
50 */
51
9c065a7d
DV		 52#define for_each_power_well(i, power_well, domain_mask, power_domains) \
53 for (i = 0; \
54 i < (power_domains)->power_well_count && \
55 ((power_well) = &(power_domains)->power_wells[i]); \
56 i++) \
95150bdf 57 for_each_if ((power_well)->domains & (domain_mask))
9c065a7d
DV		 58
59#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
60 for (i = (power_domains)->power_well_count - 1; \
61 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
62 i--) \
95150bdf 63 for_each_if ((power_well)->domains & (domain_mask))
9c065a7d 64
5aefb239
SS		 65bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
66 int power_well_id);
67
9895ad03
DS		 68const char *
69intel_display_power_domain_str(enum intel_display_power_domain domain)
70{
71 switch (domain) {
72 case POWER_DOMAIN_PIPE_A:
73 return "PIPE_A";
74 case POWER_DOMAIN_PIPE_B:
75 return "PIPE_B";
76 case POWER_DOMAIN_PIPE_C:
77 return "PIPE_C";
78 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
79 return "PIPE_A_PANEL_FITTER";
80 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
81 return "PIPE_B_PANEL_FITTER";
82 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
83 return "PIPE_C_PANEL_FITTER";
84 case POWER_DOMAIN_TRANSCODER_A:
85 return "TRANSCODER_A";
86 case POWER_DOMAIN_TRANSCODER_B:
87 return "TRANSCODER_B";
88 case POWER_DOMAIN_TRANSCODER_C:
89 return "TRANSCODER_C";
90 case POWER_DOMAIN_TRANSCODER_EDP:
91 return "TRANSCODER_EDP";
92 case POWER_DOMAIN_PORT_DDI_A_LANES:
93 return "PORT_DDI_A_LANES";
94 case POWER_DOMAIN_PORT_DDI_B_LANES:
95 return "PORT_DDI_B_LANES";
96 case POWER_DOMAIN_PORT_DDI_C_LANES:
97 return "PORT_DDI_C_LANES";
98 case POWER_DOMAIN_PORT_DDI_D_LANES:
99 return "PORT_DDI_D_LANES";
100 case POWER_DOMAIN_PORT_DDI_E_LANES:
101 return "PORT_DDI_E_LANES";
102 case POWER_DOMAIN_PORT_DSI:
103 return "PORT_DSI";
104 case POWER_DOMAIN_PORT_CRT:
105 return "PORT_CRT";
106 case POWER_DOMAIN_PORT_OTHER:
107 return "PORT_OTHER";
108 case POWER_DOMAIN_VGA:
109 return "VGA";
110 case POWER_DOMAIN_AUDIO:
111 return "AUDIO";
112 case POWER_DOMAIN_PLLS:
113 return "PLLS";
114 case POWER_DOMAIN_AUX_A:
115 return "AUX_A";
116 case POWER_DOMAIN_AUX_B:
117 return "AUX_B";
118 case POWER_DOMAIN_AUX_C:
119 return "AUX_C";
120 case POWER_DOMAIN_AUX_D:
121 return "AUX_D";
122 case POWER_DOMAIN_GMBUS:
123 return "GMBUS";
124 case POWER_DOMAIN_INIT:
125 return "INIT";
126 case POWER_DOMAIN_MODESET:
127 return "MODESET";
128 default:
129 MISSING_CASE(domain);
130 return "?";
131 }
132}
133
e8ca9320
DL		 134static void intel_power_well_enable(struct drm_i915_private *dev_priv,
135 struct i915_power_well *power_well)
136{
137 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
138 power_well->ops->enable(dev_priv, power_well);
139 power_well->hw_enabled = true;
140}
141
dcddab3a
DL		 142static void intel_power_well_disable(struct drm_i915_private *dev_priv,
143 struct i915_power_well *power_well)
144{
145 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
146 power_well->hw_enabled = false;
147 power_well->ops->disable(dev_priv, power_well);
148}
149
e4e7684f 150/*
9c065a7d
DV		 151 * We should only use the power well if we explicitly asked the hardware to
152 * enable it, so check if it's enabled and also check if we've requested it to
153 * be enabled.
154 */
155static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
156 struct i915_power_well *power_well)
157{
158 return I915_READ(HSW_PWR_WELL_DRIVER) ==
159 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
160}
161
e4e7684f
DV		 162/**
163 * __intel_display_power_is_enabled - unlocked check for a power domain
164 * @dev_priv: i915 device instance
165 * @domain: power domain to check
166 *
167 * This is the unlocked version of intel_display_power_is_enabled() and should
168 * only be used from error capture and recovery code where deadlocks are
169 * possible.
170 *
171 * Returns:
172 * True when the power domain is enabled, false otherwise.
173 */
f458ebbc
DV		 174bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
175 enum intel_display_power_domain domain)
9c065a7d
DV		 176{
177 struct i915_power_domains *power_domains;
178 struct i915_power_well *power_well;
179 bool is_enabled;
180 int i;
181
182 if (dev_priv->pm.suspended)
183 return false;
184
185 power_domains = &dev_priv->power_domains;
186
187 is_enabled = true;
188
189 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
190 if (power_well->always_on)
191 continue;
192
193 if (!power_well->hw_enabled) {
194 is_enabled = false;
195 break;
196 }
197 }
198
199 return is_enabled;
200}
201
e4e7684f 202/**
f61ccae3 203 * intel_display_power_is_enabled - check for a power domain
e4e7684f
DV		 204 * @dev_priv: i915 device instance
205 * @domain: power domain to check
206 *
207 * This function can be used to check the hw power domain state. It is mostly
208 * used in hardware state readout functions. Everywhere else code should rely
209 * upon explicit power domain reference counting to ensure that the hardware
210 * block is powered up before accessing it.
211 *
212 * Callers must hold the relevant modesetting locks to ensure that concurrent
213 * threads can't disable the power well while the caller tries to read a few
214 * registers.
215 *
216 * Returns:
217 * True when the power domain is enabled, false otherwise.
218 */
f458ebbc
DV		 219bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
220 enum intel_display_power_domain domain)
9c065a7d
DV		 221{
222 struct i915_power_domains *power_domains;
223 bool ret;
224
225 power_domains = &dev_priv->power_domains;
226
227 mutex_lock(&power_domains->lock);
f458ebbc 228 ret = __intel_display_power_is_enabled(dev_priv, domain);
9c065a7d
DV		 229 mutex_unlock(&power_domains->lock);
230
231 return ret;
232}
233
e4e7684f
DV		 234/**
235 * intel_display_set_init_power - set the initial power domain state
236 * @dev_priv: i915 device instance
237 * @enable: whether to enable or disable the initial power domain state
238 *
239 * For simplicity our driver load/unload and system suspend/resume code assumes
240 * that all power domains are always enabled. This functions controls the state
241 * of this little hack. While the initial power domain state is enabled runtime
242 * pm is effectively disabled.
243 */
d9bc89d9
DV		 244void intel_display_set_init_power(struct drm_i915_private *dev_priv,
245 bool enable)
246{
247 if (dev_priv->power_domains.init_power_on == enable)
248 return;
249
250 if (enable)
251 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
252 else
253 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
254
255 dev_priv->power_domains.init_power_on = enable;
256}
257
9c065a7d
DV		 258/*
259 * Starting with Haswell, we have a "Power Down Well" that can be turned off
260 * when not needed anymore. We have 4 registers that can request the power well
261 * to be enabled, and it will only be disabled if none of the registers is
262 * requesting it to be enabled.
263 */
264static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
265{
266 struct drm_device *dev = dev_priv->dev;
267
268 /*
269 * After we re-enable the power well, if we touch VGA register 0x3d5
270 * we'll get unclaimed register interrupts. This stops after we write
271 * anything to the VGA MSR register. The vgacon module uses this
272 * register all the time, so if we unbind our driver and, as a
273 * consequence, bind vgacon, we'll get stuck in an infinite loop at
274 * console_unlock(). So make here we touch the VGA MSR register, making
275 * sure vgacon can keep working normally without triggering interrupts
276 * and error messages.
277 */
278 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
279 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
280 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
281
25400392 282 if (IS_BROADWELL(dev))
4c6c03be
DL		 283 gen8_irq_power_well_post_enable(dev_priv,
284 1 << PIPE_C | 1 << PIPE_B);
9c065a7d
DV		 285}
286
d14c0343
DL		 287static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
288 struct i915_power_well *power_well)
289{
290 struct drm_device *dev = dev_priv->dev;
291
292 /*
293 * After we re-enable the power well, if we touch VGA register 0x3d5
294 * we'll get unclaimed register interrupts. This stops after we write
295 * anything to the VGA MSR register. The vgacon module uses this
296 * register all the time, so if we unbind our driver and, as a
297 * consequence, bind vgacon, we'll get stuck in an infinite loop at
298 * console_unlock(). So make here we touch the VGA MSR register, making
299 * sure vgacon can keep working normally without triggering interrupts
300 * and error messages.
301 */
302 if (power_well->data == SKL_DISP_PW_2) {
303 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
304 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
305 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
306
307 gen8_irq_power_well_post_enable(dev_priv,
308 1 << PIPE_C | 1 << PIPE_B);
309 }
d14c0343
DL		 310}
311
9c065a7d
DV		 312static void hsw_set_power_well(struct drm_i915_private *dev_priv,
313 struct i915_power_well *power_well, bool enable)
314{
315 bool is_enabled, enable_requested;
316 uint32_t tmp;
317
318 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
319 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
320 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
321
322 if (enable) {
323 if (!enable_requested)
324 I915_WRITE(HSW_PWR_WELL_DRIVER,
325 HSW_PWR_WELL_ENABLE_REQUEST);
326
327 if (!is_enabled) {
328 DRM_DEBUG_KMS("Enabling power well\n");
329 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
330 HSW_PWR_WELL_STATE_ENABLED), 20))
331 DRM_ERROR("Timeout enabling power well\n");
6d729bff 332 hsw_power_well_post_enable(dev_priv);
9c065a7d
DV		 333 }
334
9c065a7d
DV		 335 } else {
336 if (enable_requested) {
337 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
338 POSTING_READ(HSW_PWR_WELL_DRIVER);
339 DRM_DEBUG_KMS("Requesting to disable the power well\n");
340 }
341 }
342}
343
94dd5138
S		 344#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
345 BIT(POWER_DOMAIN_TRANSCODER_A) | \
346 BIT(POWER_DOMAIN_PIPE_B) | \
347 BIT(POWER_DOMAIN_TRANSCODER_B) | \
348 BIT(POWER_DOMAIN_PIPE_C) | \
349 BIT(POWER_DOMAIN_TRANSCODER_C) | \
350 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
351 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
6331a704
PJ		 352 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
353 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
354 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
355 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
94dd5138
S		 356 BIT(POWER_DOMAIN_AUX_B) | \
357 BIT(POWER_DOMAIN_AUX_C) | \
358 BIT(POWER_DOMAIN_AUX_D) | \
359 BIT(POWER_DOMAIN_AUDIO) | \
360 BIT(POWER_DOMAIN_VGA) | \
361 BIT(POWER_DOMAIN_INIT))
94dd5138 362#define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
6331a704
PJ		 363 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
364 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
94dd5138
S		 365 BIT(POWER_DOMAIN_INIT))
366#define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
6331a704 367 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
94dd5138
S		 368 BIT(POWER_DOMAIN_INIT))
369#define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
6331a704 370 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
94dd5138
S		 371 BIT(POWER_DOMAIN_INIT))
372#define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
6331a704 373 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
94dd5138 374 BIT(POWER_DOMAIN_INIT))
9f836f90
PJ		 375#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
376 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
377 BIT(POWER_DOMAIN_MODESET) | \
378 BIT(POWER_DOMAIN_AUX_A) | \
379 BIT(POWER_DOMAIN_INIT))
94dd5138 380#define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
4a76f295 381 (POWER_DOMAIN_MASK & ~( \
9f836f90
PJ		 382 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
383 SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
94dd5138
S		 384 BIT(POWER_DOMAIN_INIT))
385
0b4a2a36
S		 386#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
387 BIT(POWER_DOMAIN_TRANSCODER_A) | \
388 BIT(POWER_DOMAIN_PIPE_B) | \
389 BIT(POWER_DOMAIN_TRANSCODER_B) | \
390 BIT(POWER_DOMAIN_PIPE_C) | \
391 BIT(POWER_DOMAIN_TRANSCODER_C) | \
392 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
393 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
6331a704
PJ		 394 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
395 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
0b4a2a36
S		 396 BIT(POWER_DOMAIN_AUX_B) | \
397 BIT(POWER_DOMAIN_AUX_C) | \
398 BIT(POWER_DOMAIN_AUDIO) | \
399 BIT(POWER_DOMAIN_VGA) | \
f0ab43e6 400 BIT(POWER_DOMAIN_GMBUS) | \
0b4a2a36
S		 401 BIT(POWER_DOMAIN_INIT))
402#define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
403 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
404 BIT(POWER_DOMAIN_PIPE_A) | \
405 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
406 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
6331a704 407 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
0b4a2a36
S		 408 BIT(POWER_DOMAIN_AUX_A) | \
409 BIT(POWER_DOMAIN_PLLS) | \
410 BIT(POWER_DOMAIN_INIT))
9f836f90
PJ		 411#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
412 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
413 BIT(POWER_DOMAIN_MODESET) | \
414 BIT(POWER_DOMAIN_AUX_A) | \
415 BIT(POWER_DOMAIN_INIT))
0b4a2a36
S		 416#define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
417 (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
418 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
419 BIT(POWER_DOMAIN_INIT))
420
664326f8
SK		 421static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
422{
423 struct drm_device *dev = dev_priv->dev;
424
425 WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
426 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
427 "DC9 already programmed to be enabled.\n");
428 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
429 "DC5 still not disabled to enable DC9.\n");
430 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
431 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
432
433 /*
434 * TODO: check for the following to verify the conditions to enter DC9
435 * state are satisfied:
436 * 1] Check relevant display engine registers to verify if mode set
437 * disable sequence was followed.
438 * 2] Check if display uninitialize sequence is initialized.
439 */
440}
441
442static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
443{
444 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
445 WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
446 "DC9 already programmed to be disabled.\n");
447 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
448 "DC5 still not disabled.\n");
449
450 /*
451 * TODO: check for the following to verify DC9 state was indeed
452 * entered before programming to disable it:
453 * 1] Check relevant display engine registers to verify if mode
454 * set disable sequence was followed.
455 * 2] Check if display uninitialize sequence is initialized.
456 */
457}
458
4deccbb2
PJ		 459static void gen9_set_dc_state_debugmask_memory_up(
460 struct drm_i915_private *dev_priv)
461{
462 uint32_t val;
463
464 /* The below bit doesn't need to be cleared ever afterwards */
465 val = I915_READ(DC_STATE_DEBUG);
466 if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
467 val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
468 I915_WRITE(DC_STATE_DEBUG, val);
469 POSTING_READ(DC_STATE_DEBUG);
470 }
471}
472
779cb5d3
MK		 473static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
474 u32 state)
475{
476 int rewrites = 0;
477 int rereads = 0;
478 u32 v;
479
480 I915_WRITE(DC_STATE_EN, state);
481
482 /* It has been observed that disabling the dc6 state sometimes
483 * doesn't stick and dmc keeps returning old value. Make sure
484 * the write really sticks enough times and also force rewrite until
485 * we are confident that state is exactly what we want.
486 */
487 do {
488 v = I915_READ(DC_STATE_EN);
489
490 if (v != state) {
491 I915_WRITE(DC_STATE_EN, state);
492 rewrites++;
493 rereads = 0;
494 } else if (rereads++ > 5) {
495 break;
496 }
497
498 } while (rewrites < 100);
499
500 if (v != state)
501 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
502 state, v);
503
504 /* Most of the times we need one retry, avoid spam */
505 if (rewrites > 1)
506 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
507 state, rewrites);
508}
509
13ae3a0d 510static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
664326f8
SK		 511{
512 uint32_t val;
13ae3a0d 513 uint32_t mask;
664326f8 514
13ae3a0d
ID		 515 mask = DC_STATE_EN_UPTO_DC5;
516 if (IS_BROXTON(dev_priv))
517 mask |= DC_STATE_EN_DC9;
518 else
519 mask |= DC_STATE_EN_UPTO_DC6;
664326f8 520
13ae3a0d 521 WARN_ON_ONCE(state & ~mask);
664326f8 522
443646c7
PJ		 523 if (i915.enable_dc == 0)
524 state = DC_STATE_DISABLE;
525 else if (i915.enable_dc == 1 && state > DC_STATE_EN_UPTO_DC5)
526 state = DC_STATE_EN_UPTO_DC5;
527
4deccbb2
PJ		 528 if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
529 gen9_set_dc_state_debugmask_memory_up(dev_priv);
530
664326f8 531 val = I915_READ(DC_STATE_EN);
13ae3a0d
ID		 532 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
533 val & mask, state);
832dba88
PJ		 534
535 /* Check if DMC is ignoring our DC state requests */
536 if ((val & mask) != dev_priv->csr.dc_state)
537 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
538 dev_priv->csr.dc_state, val & mask);
539
13ae3a0d
ID		 540 val &= ~mask;
541 val |= state;
779cb5d3
MK		 542
543 gen9_write_dc_state(dev_priv, val);
832dba88
PJ		 544
545 dev_priv->csr.dc_state = val & mask;
664326f8
SK		 546}
547
13ae3a0d 548void bxt_enable_dc9(struct drm_i915_private *dev_priv)
664326f8 549{
13ae3a0d
ID		 550 assert_can_enable_dc9(dev_priv);
551
552 DRM_DEBUG_KMS("Enabling DC9\n");
664326f8 553
13ae3a0d
ID		 554 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
555}
556
557void bxt_disable_dc9(struct drm_i915_private *dev_priv)
558{
664326f8
SK		 559 assert_can_disable_dc9(dev_priv);
560
561 DRM_DEBUG_KMS("Disabling DC9\n");
562
13ae3a0d 563 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
664326f8
SK		 564}
565
af5fead2
DV		 566static void assert_csr_loaded(struct drm_i915_private *dev_priv)
567{
568 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
569 "CSR program storage start is NULL\n");
570 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
571 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
572}
573
5aefb239 574static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
dc174300 575{
6b457d31 576 struct drm_device *dev = dev_priv->dev;
5aefb239
SS		 577 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
578 SKL_DISP_PW_2);
579
8d7a1c4a
RV		 580 WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
581 "Platform doesn't support DC5.\n");
6ff8ab0d
JB		 582 WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
583 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
5aefb239 584
6ff8ab0d
JB		 585 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
586 "DC5 already programmed to be enabled.\n");
c9b8846a 587 assert_rpm_wakelock_held(dev_priv);
5aefb239
SS		 588
589 assert_csr_loaded(dev_priv);
590}
591
592static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
593{
93c7cb6c
SS		 594 /*
595 * During initialization, the firmware may not be loaded yet.
596 * We still want to make sure that the DC enabling flag is cleared.
597 */
598 if (dev_priv->power_domains.initializing)
599 return;
5aefb239 600
c9b8846a 601 assert_rpm_wakelock_held(dev_priv);
5aefb239
SS		 602}
603
604static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
605{
5aefb239 606 assert_can_enable_dc5(dev_priv);
6b457d31
SK		 607
608 DRM_DEBUG_KMS("Enabling DC5\n");
609
13ae3a0d 610 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
dc174300
SS		 611}
612
93c7cb6c 613static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
f75a1985 614{
74b4f371 615 struct drm_device *dev = dev_priv->dev;
93c7cb6c 616
8d7a1c4a
RV		 617 WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
618 "Platform doesn't support DC6.\n");
6ff8ab0d
JB		 619 WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
620 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
621 "Backlight is not disabled.\n");
622 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
623 "DC6 already programmed to be enabled.\n");
93c7cb6c
SS		 624
625 assert_csr_loaded(dev_priv);
626}
627
628static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
629{
630 /*
631 * During initialization, the firmware may not be loaded yet.
632 * We still want to make sure that the DC enabling flag is cleared.
633 */
634 if (dev_priv->power_domains.initializing)
635 return;
636
6ff8ab0d
JB		 637 WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
638 "DC6 already programmed to be disabled.\n");
93c7cb6c
SS		 639}
640
9f836f90
PJ		 641static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
642{
643 assert_can_disable_dc5(dev_priv);
443646c7 644
8d7a1c4a
RV		 645 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
646 i915.enable_dc != 0 && i915.enable_dc != 1)
443646c7 647 assert_can_disable_dc6(dev_priv);
9f836f90
PJ		 648
649 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
650}
651
0a9d2bed 652void skl_enable_dc6(struct drm_i915_private *dev_priv)
93c7cb6c 653{
93c7cb6c 654 assert_can_enable_dc6(dev_priv);
74b4f371
SK		 655
656 DRM_DEBUG_KMS("Enabling DC6\n");
657
13ae3a0d
ID		 658 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
659
f75a1985
SS		 660}
661
0a9d2bed 662void skl_disable_dc6(struct drm_i915_private *dev_priv)
f75a1985 663{
93c7cb6c 664 assert_can_disable_dc6(dev_priv);
74b4f371
SK		 665
666 DRM_DEBUG_KMS("Disabling DC6\n");
667
13ae3a0d 668 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
f75a1985
SS		 669}
670
94dd5138
S		 671static void skl_set_power_well(struct drm_i915_private *dev_priv,
672 struct i915_power_well *power_well, bool enable)
673{
674 uint32_t tmp, fuse_status;
675 uint32_t req_mask, state_mask;
2a51835f 676 bool is_enabled, enable_requested, check_fuse_status = false;
94dd5138
S		 677
678 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
679 fuse_status = I915_READ(SKL_FUSE_STATUS);
680
681 switch (power_well->data) {
682 case SKL_DISP_PW_1:
683 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
684 SKL_FUSE_PG0_DIST_STATUS), 1)) {
685 DRM_ERROR("PG0 not enabled\n");
686 return;
687 }
688 break;
689 case SKL_DISP_PW_2:
690 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
691 DRM_ERROR("PG1 in disabled state\n");
692 return;
693 }
694 break;
695 case SKL_DISP_PW_DDI_A_E:
696 case SKL_DISP_PW_DDI_B:
697 case SKL_DISP_PW_DDI_C:
698 case SKL_DISP_PW_DDI_D:
699 case SKL_DISP_PW_MISC_IO:
700 break;
701 default:
702 WARN(1, "Unknown power well %lu\n", power_well->data);
703 return;
704 }
705
706 req_mask = SKL_POWER_WELL_REQ(power_well->data);
2a51835f 707 enable_requested = tmp & req_mask;
94dd5138 708 state_mask = SKL_POWER_WELL_STATE(power_well->data);
2a51835f 709 is_enabled = tmp & state_mask;
94dd5138
S		 710
711 if (enable) {
2a51835f 712 if (!enable_requested) {
dc174300
SS		 713 WARN((tmp & state_mask) &&
714 !I915_READ(HSW_PWR_WELL_BIOS),
715 "Invalid for power well status to be enabled, unless done by the BIOS, \
716 when request is to disable!\n");
94dd5138 717 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
94dd5138
S		 718 }
719
2a51835f 720 if (!is_enabled) {
510e6fdd 721 DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
94dd5138
S		 722 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
723 state_mask), 1))
724 DRM_ERROR("%s enable timeout\n",
725 power_well->name);
726 check_fuse_status = true;
727 }
728 } else {
2a51835f 729 if (enable_requested) {
4a76f295
ID		 730 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
731 POSTING_READ(HSW_PWR_WELL_DRIVER);
732 DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
94dd5138
S		 733 }
734 }
735
736 if (check_fuse_status) {
737 if (power_well->data == SKL_DISP_PW_1) {
738 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
739 SKL_FUSE_PG1_DIST_STATUS), 1))
740 DRM_ERROR("PG1 distributing status timeout\n");
741 } else if (power_well->data == SKL_DISP_PW_2) {
742 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
743 SKL_FUSE_PG2_DIST_STATUS), 1))
744 DRM_ERROR("PG2 distributing status timeout\n");
745 }
746 }
d14c0343
DL		 747
748 if (enable && !is_enabled)
749 skl_power_well_post_enable(dev_priv, power_well);
94dd5138
S		 750}
751
9c065a7d
DV		 752static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
753 struct i915_power_well *power_well)
754{
755 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
756
757 /*
758 * We're taking over the BIOS, so clear any requests made by it since
759 * the driver is in charge now.
760 */
761 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
762 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
763}
764
765static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
766 struct i915_power_well *power_well)
767{
768 hsw_set_power_well(dev_priv, power_well, true);
769}
770
771static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
772 struct i915_power_well *power_well)
773{
774 hsw_set_power_well(dev_priv, power_well, false);
775}
776
94dd5138
S		 777static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
778 struct i915_power_well *power_well)
779{
780 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
781 SKL_POWER_WELL_STATE(power_well->data);
782
783 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
784}
785
786static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
787 struct i915_power_well *power_well)
788{
789 skl_set_power_well(dev_priv, power_well, power_well->count > 0);
790
791 /* Clear any request made by BIOS as driver is taking over */
792 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
793}
794
795static void skl_power_well_enable(struct drm_i915_private *dev_priv,
796 struct i915_power_well *power_well)
797{
798 skl_set_power_well(dev_priv, power_well, true);
799}
800
801static void skl_power_well_disable(struct drm_i915_private *dev_priv,
802 struct i915_power_well *power_well)
803{
804 skl_set_power_well(dev_priv, power_well, false);
805}
806
9f836f90
PJ		 807static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
808 struct i915_power_well *power_well)
809{
810 return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
811}
812
813static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
814 struct i915_power_well *power_well)
815{
816 gen9_disable_dc5_dc6(dev_priv);
817}
818
819static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
820 struct i915_power_well *power_well)
821{
8d7a1c4a
RV		 822 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
823 i915.enable_dc != 0 && i915.enable_dc != 1)
9f836f90
PJ		 824 skl_enable_dc6(dev_priv);
825 else
826 gen9_enable_dc5(dev_priv);
827}
828
829static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
830 struct i915_power_well *power_well)
831{
832 if (power_well->count > 0) {
833 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
834 } else {
8d7a1c4a
RV		 835 if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
836 i915.enable_dc != 0 &&
443646c7 837 i915.enable_dc != 1)
9f836f90
PJ		 838 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
839 else
840 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
841 }
842}
843
9c065a7d
DV		 844static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
845 struct i915_power_well *power_well)
846{
847}
848
849static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
850 struct i915_power_well *power_well)
851{
852 return true;
853}
854
855static void vlv_set_power_well(struct drm_i915_private *dev_priv,
856 struct i915_power_well *power_well, bool enable)
857{
858 enum punit_power_well power_well_id = power_well->data;
859 u32 mask;
860 u32 state;
861 u32 ctrl;
862
863 mask = PUNIT_PWRGT_MASK(power_well_id);
864 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
865 PUNIT_PWRGT_PWR_GATE(power_well_id);
866
867 mutex_lock(&dev_priv->rps.hw_lock);
868
869#define COND \
870 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
871
872 if (COND)
873 goto out;
874
875 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
876 ctrl &= ~mask;
877 ctrl |= state;
878 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
879
880 if (wait_for(COND, 100))
7e35ab88 881 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
9c065a7d
DV		 882 state,
883 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
884
885#undef COND
886
887out:
888 mutex_unlock(&dev_priv->rps.hw_lock);
889}
890
891static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
892 struct i915_power_well *power_well)
893{
894 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
895}
896
897static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
898 struct i915_power_well *power_well)
899{
900 vlv_set_power_well(dev_priv, power_well, true);
901}
902
903static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
904 struct i915_power_well *power_well)
905{
906 vlv_set_power_well(dev_priv, power_well, false);
907}
908
909static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
910 struct i915_power_well *power_well)
911{
912 int power_well_id = power_well->data;
913 bool enabled = false;
914 u32 mask;
915 u32 state;
916 u32 ctrl;
917
918 mask = PUNIT_PWRGT_MASK(power_well_id);
919 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
920
921 mutex_lock(&dev_priv->rps.hw_lock);
922
923 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
924 /*
925 * We only ever set the power-on and power-gate states, anything
926 * else is unexpected.
927 */
928 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
929 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
930 if (state == ctrl)
931 enabled = true;
932
933 /*
934 * A transient state at this point would mean some unexpected party
935 * is poking at the power controls too.
936 */
937 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
938 WARN_ON(ctrl != state);
939
940 mutex_unlock(&dev_priv->rps.hw_lock);
941
942 return enabled;
943}
944
2be7d540 945static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
9c065a7d 946{
5a8fbb7d
VS		 947 enum pipe pipe;
948
949 /*
950 * Enable the CRI clock source so we can get at the
951 * display and the reference clock for VGA
952 * hotplug / manual detection. Supposedly DSI also
953 * needs the ref clock up and running.
954 *
955 * CHV DPLL B/C have some issues if VGA mode is enabled.
956 */
957 for_each_pipe(dev_priv->dev, pipe) {
958 u32 val = I915_READ(DPLL(pipe));
959
960 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
961 if (pipe != PIPE_A)
962 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
963
964 I915_WRITE(DPLL(pipe), val);
965 }
9c065a7d
DV		 966
967 spin_lock_irq(&dev_priv->irq_lock);
968 valleyview_enable_display_irqs(dev_priv);
969 spin_unlock_irq(&dev_priv->irq_lock);
970
971 /*
972 * During driver initialization/resume we can avoid restoring the
973 * part of the HW/SW state that will be inited anyway explicitly.
974 */
975 if (dev_priv->power_domains.initializing)
976 return;
977
b963291c 978 intel_hpd_init(dev_priv);
9c065a7d
DV		 979
980 i915_redisable_vga_power_on(dev_priv->dev);
981}
982
2be7d540
VS		 983static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
984{
985 spin_lock_irq(&dev_priv->irq_lock);
986 valleyview_disable_display_irqs(dev_priv);
987 spin_unlock_irq(&dev_priv->irq_lock);
988
989 vlv_power_sequencer_reset(dev_priv);
990}
991
992static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
993 struct i915_power_well *power_well)
994{
995 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
996
997 vlv_set_power_well(dev_priv, power_well, true);
998
999 vlv_display_power_well_init(dev_priv);
1000}
1001
9c065a7d
DV		 1002static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1003 struct i915_power_well *power_well)
1004{
1005 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1006
2be7d540 1007 vlv_display_power_well_deinit(dev_priv);
9c065a7d
DV		 1008
1009 vlv_set_power_well(dev_priv, power_well, false);
9c065a7d
DV		 1010}
1011
1012static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1013 struct i915_power_well *power_well)
1014{
1015 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1016
5a8fbb7d 1017 /* since ref/cri clock was enabled */
9c065a7d
DV		 1018 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1019
1020 vlv_set_power_well(dev_priv, power_well, true);
1021
1022 /*
1023 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1024 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1025 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1026 * b. The other bits such as sfr settings / modesel may all
1027 * be set to 0.
1028 *
1029 * This should only be done on init and resume from S3 with
1030 * both PLLs disabled, or we risk losing DPIO and PLL
1031 * synchronization.
1032 */
1033 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1034}
1035
1036static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1037 struct i915_power_well *power_well)
1038{
1039 enum pipe pipe;
1040
1041 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1042
1043 for_each_pipe(dev_priv, pipe)
1044 assert_pll_disabled(dev_priv, pipe);
1045
1046 /* Assert common reset */
1047 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1048
1049 vlv_set_power_well(dev_priv, power_well, false);
1050}
1051
30142273
VS		 1052#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1053
1054static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1055 int power_well_id)
1056{
1057 struct i915_power_domains *power_domains = &dev_priv->power_domains;
30142273
VS		 1058 int i;
1059
fc17f227
ID		 1060 for (i = 0; i < power_domains->power_well_count; i++) {
1061 struct i915_power_well *power_well;
1062
1063 power_well = &power_domains->power_wells[i];
30142273
VS		 1064 if (power_well->data == power_well_id)
1065 return power_well;
1066 }
1067
1068 return NULL;
1069}
1070
1071#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1072
1073static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1074{
1075 struct i915_power_well *cmn_bc =
1076 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1077 struct i915_power_well *cmn_d =
1078 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1079 u32 phy_control = dev_priv->chv_phy_control;
1080 u32 phy_status = 0;
3be60de9 1081 u32 phy_status_mask = 0xffffffff;
30142273
VS		 1082 u32 tmp;
1083
3be60de9
VS		 1084 /*
1085 * The BIOS can leave the PHY is some weird state
1086 * where it doesn't fully power down some parts.
1087 * Disable the asserts until the PHY has been fully
1088 * reset (ie. the power well has been disabled at
1089 * least once).
1090 */
1091 if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1092 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1093 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1094 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1095 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1096 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1097 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1098
1099 if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1100 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1101 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1102 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1103
30142273
VS		 1104 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1105 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1106
1107 /* this assumes override is only used to enable lanes */
1108 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1109 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1110
1111 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1112 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1113
1114 /* CL1 is on whenever anything is on in either channel */
1115 if (BITS_SET(phy_control,
1116 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1117 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1118 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1119
1120 /*
1121 * The DPLLB check accounts for the pipe B + port A usage
1122 * with CL2 powered up but all the lanes in the second channel
1123 * powered down.
1124 */
1125 if (BITS_SET(phy_control,
1126 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1127 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1128 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1129
1130 if (BITS_SET(phy_control,
1131 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1132 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1133 if (BITS_SET(phy_control,
1134 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1135 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1136
1137 if (BITS_SET(phy_control,
1138 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1139 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1140 if (BITS_SET(phy_control,
1141 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1142 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1143 }
1144
1145 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1146 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1147
1148 /* this assumes override is only used to enable lanes */
1149 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1150 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1151
1152 if (BITS_SET(phy_control,
1153 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1154 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1155
1156 if (BITS_SET(phy_control,
1157 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1158 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1159 if (BITS_SET(phy_control,
1160 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1161 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1162 }
1163
3be60de9
VS		 1164 phy_status &= phy_status_mask;
1165
30142273
VS		 1166 /*
1167 * The PHY may be busy with some initial calibration and whatnot,
1168 * so the power state can take a while to actually change.
1169 */
3be60de9 1170 if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
30142273
VS		 1171 WARN(phy_status != tmp,
1172 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1173 tmp, phy_status, dev_priv->chv_phy_control);
1174}
1175
1176#undef BITS_SET
1177
9c065a7d
DV		 1178static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1179 struct i915_power_well *power_well)
1180{
1181 enum dpio_phy phy;
e0fce78f
VS		 1182 enum pipe pipe;
1183 uint32_t tmp;
9c065a7d
DV		 1184
1185 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1186 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1187
e0fce78f
VS		 1188 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1189 pipe = PIPE_A;
9c065a7d 1190 phy = DPIO_PHY0;
e0fce78f
VS		 1191 } else {
1192 pipe = PIPE_C;
9c065a7d 1193 phy = DPIO_PHY1;
e0fce78f 1194 }
5a8fbb7d
VS		 1195
1196 /* since ref/cri clock was enabled */
9c065a7d
DV		 1197 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1198 vlv_set_power_well(dev_priv, power_well, true);
1199
1200 /* Poll for phypwrgood signal */
1201 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1202 DRM_ERROR("Display PHY %d is not power up\n", phy);
1203
e0fce78f
VS		 1204 mutex_lock(&dev_priv->sb_lock);
1205
1206 /* Enable dynamic power down */
1207 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
ee279218
VS		 1208 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1209 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
e0fce78f
VS		 1210 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1211
1212 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1213 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1214 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1215 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
3e288786
VS		 1216 } else {
1217 /*
1218 * Force the non-existing CL2 off. BXT does this
1219 * too, so maybe it saves some power even though
1220 * CL2 doesn't exist?
1221 */
1222 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1223 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1224 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
e0fce78f
VS		 1225 }
1226
1227 mutex_unlock(&dev_priv->sb_lock);
1228
70722468
VS		 1229 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1230 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
e0fce78f
VS		 1231
1232 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1233 phy, dev_priv->chv_phy_control);
30142273
VS		 1234
1235 assert_chv_phy_status(dev_priv);
9c065a7d
DV		 1236}
1237
1238static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1239 struct i915_power_well *power_well)
1240{
1241 enum dpio_phy phy;
1242
1243 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1244 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1245
1246 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1247 phy = DPIO_PHY0;
1248 assert_pll_disabled(dev_priv, PIPE_A);
1249 assert_pll_disabled(dev_priv, PIPE_B);
1250 } else {
1251 phy = DPIO_PHY1;
1252 assert_pll_disabled(dev_priv, PIPE_C);
1253 }
1254
70722468
VS		 1255 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1256 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
9c065a7d
DV		 1257
1258 vlv_set_power_well(dev_priv, power_well, false);
e0fce78f
VS		 1259
1260 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1261 phy, dev_priv->chv_phy_control);
30142273 1262
3be60de9
VS		 1263 /* PHY is fully reset now, so we can enable the PHY state asserts */
1264 dev_priv->chv_phy_assert[phy] = true;
1265
30142273 1266 assert_chv_phy_status(dev_priv);
e0fce78f
VS		 1267}
1268
6669e39f
VS		 1269static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1270 enum dpio_channel ch, bool override, unsigned int mask)
1271{
1272 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1273 u32 reg, val, expected, actual;
1274
3be60de9
VS		 1275 /*
1276 * The BIOS can leave the PHY is some weird state
1277 * where it doesn't fully power down some parts.
1278 * Disable the asserts until the PHY has been fully
1279 * reset (ie. the power well has been disabled at
1280 * least once).
1281 */
1282 if (!dev_priv->chv_phy_assert[phy])
1283 return;
1284
6669e39f
VS		 1285 if (ch == DPIO_CH0)
1286 reg = _CHV_CMN_DW0_CH0;
1287 else
1288 reg = _CHV_CMN_DW6_CH1;
1289
1290 mutex_lock(&dev_priv->sb_lock);
1291 val = vlv_dpio_read(dev_priv, pipe, reg);
1292 mutex_unlock(&dev_priv->sb_lock);
1293
1294 /*
1295 * This assumes !override is only used when the port is disabled.
1296 * All lanes should power down even without the override when
1297 * the port is disabled.
1298 */
1299 if (!override || mask == 0xf) {
1300 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1301 /*
1302 * If CH1 common lane is not active anymore
1303 * (eg. for pipe B DPLL) the entire channel will
1304 * shut down, which causes the common lane registers
1305 * to read as 0. That means we can't actually check
1306 * the lane power down status bits, but as the entire
1307 * register reads as 0 it's a good indication that the
1308 * channel is indeed entirely powered down.
1309 */
1310 if (ch == DPIO_CH1 && val == 0)
1311 expected = 0;
1312 } else if (mask != 0x0) {
1313 expected = DPIO_ANYDL_POWERDOWN;
1314 } else {
1315 expected = 0;
1316 }
1317
1318 if (ch == DPIO_CH0)
1319 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1320 else
1321 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1322 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1323
1324 WARN(actual != expected,
1325 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1326 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1327 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1328 reg, val);
1329}
1330
b0b33846
VS		 1331bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1332 enum dpio_channel ch, bool override)
1333{
1334 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1335 bool was_override;
1336
1337 mutex_lock(&power_domains->lock);
1338
1339 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1340
1341 if (override == was_override)
1342 goto out;
1343
1344 if (override)
1345 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1346 else
1347 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1348
1349 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1350
1351 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1352 phy, ch, dev_priv->chv_phy_control);
1353
30142273
VS		 1354 assert_chv_phy_status(dev_priv);
1355
b0b33846
VS		 1356out:
1357 mutex_unlock(&power_domains->lock);
1358
1359 return was_override;
1360}
1361
e0fce78f
VS		 1362void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1363 bool override, unsigned int mask)
1364{
1365 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1366 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1367 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1368 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1369
1370 mutex_lock(&power_domains->lock);
1371
1372 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1373 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1374
1375 if (override)
1376 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1377 else
1378 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1379
1380 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1381
1382 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1383 phy, ch, mask, dev_priv->chv_phy_control);
1384
30142273
VS		 1385 assert_chv_phy_status(dev_priv);
1386
6669e39f
VS		 1387 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1388
e0fce78f 1389 mutex_unlock(&power_domains->lock);
9c065a7d
DV		 1390}
1391
1392static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1393 struct i915_power_well *power_well)
1394{
1395 enum pipe pipe = power_well->data;
1396 bool enabled;
1397 u32 state, ctrl;
1398
1399 mutex_lock(&dev_priv->rps.hw_lock);
1400
1401 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1402 /*
1403 * We only ever set the power-on and power-gate states, anything
1404 * else is unexpected.
1405 */
1406 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1407 enabled = state == DP_SSS_PWR_ON(pipe);
1408
1409 /*
1410 * A transient state at this point would mean some unexpected party
1411 * is poking at the power controls too.
1412 */
1413 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1414 WARN_ON(ctrl << 16 != state);
1415
1416 mutex_unlock(&dev_priv->rps.hw_lock);
1417
1418 return enabled;
1419}
1420
1421static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1422 struct i915_power_well *power_well,
1423 bool enable)
1424{
1425 enum pipe pipe = power_well->data;
1426 u32 state;
1427 u32 ctrl;
1428
1429 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1430
1431 mutex_lock(&dev_priv->rps.hw_lock);
1432
1433#define COND \
1434 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1435
1436 if (COND)
1437 goto out;
1438
1439 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1440 ctrl &= ~DP_SSC_MASK(pipe);
1441 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1442 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1443
1444 if (wait_for(COND, 100))
7e35ab88 1445 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
9c065a7d
DV		 1446 state,
1447 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1448
1449#undef COND
1450
1451out:
1452 mutex_unlock(&dev_priv->rps.hw_lock);
1453}
1454
1455static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1456 struct i915_power_well *power_well)
1457{
8fcd5cd8
VS		 1458 WARN_ON_ONCE(power_well->data != PIPE_A);
1459
9c065a7d
DV		 1460 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1461}
1462
1463static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1464 struct i915_power_well *power_well)
1465{
8fcd5cd8 1466 WARN_ON_ONCE(power_well->data != PIPE_A);
9c065a7d
DV		 1467
1468 chv_set_pipe_power_well(dev_priv, power_well, true);
afd6275d 1469
2be7d540 1470 vlv_display_power_well_init(dev_priv);
9c065a7d
DV		 1471}
1472
1473static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1474 struct i915_power_well *power_well)
1475{
8fcd5cd8
VS		 1476 WARN_ON_ONCE(power_well->data != PIPE_A);
1477
2be7d540 1478 vlv_display_power_well_deinit(dev_priv);
afd6275d 1479
9c065a7d
DV		 1480 chv_set_pipe_power_well(dev_priv, power_well, false);
1481}
1482
09731280
ID		 1483static void
1484__intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1485 enum intel_display_power_domain domain)
1486{
1487 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1488 struct i915_power_well *power_well;
1489 int i;
1490
1491 for_each_power_well(i, power_well, BIT(domain), power_domains) {
1492 if (!power_well->count++)
1493 intel_power_well_enable(dev_priv, power_well);
1494 }
1495
1496 power_domains->domain_use_count[domain]++;
1497}
1498
e4e7684f
DV		 1499/**
1500 * intel_display_power_get - grab a power domain reference
1501 * @dev_priv: i915 device instance
1502 * @domain: power domain to reference
1503 *
1504 * This function grabs a power domain reference for @domain and ensures that the
1505 * power domain and all its parents are powered up. Therefore users should only
1506 * grab a reference to the innermost power domain they need.
1507 *
1508 * Any power domain reference obtained by this function must have a symmetric
1509 * call to intel_display_power_put() to release the reference again.
1510 */
9c065a7d
DV		 1511void intel_display_power_get(struct drm_i915_private *dev_priv,
1512 enum intel_display_power_domain domain)
1513{
09731280 1514 struct i915_power_domains *power_domains = &dev_priv->power_domains;
9c065a7d
DV		 1515
1516 intel_runtime_pm_get(dev_priv);
1517
09731280
ID		 1518 mutex_lock(&power_domains->lock);
1519
1520 __intel_display_power_get_domain(dev_priv, domain);
1521
1522 mutex_unlock(&power_domains->lock);
1523}
1524
1525/**
1526 * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1527 * @dev_priv: i915 device instance
1528 * @domain: power domain to reference
1529 *
1530 * This function grabs a power domain reference for @domain and ensures that the
1531 * power domain and all its parents are powered up. Therefore users should only
1532 * grab a reference to the innermost power domain they need.
1533 *
1534 * Any power domain reference obtained by this function must have a symmetric
1535 * call to intel_display_power_put() to release the reference again.
1536 */
1537bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1538 enum intel_display_power_domain domain)
1539{
1540 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1541 bool is_enabled;
1542
1543 if (!intel_runtime_pm_get_if_in_use(dev_priv))
1544 return false;
9c065a7d
DV		 1545
1546 mutex_lock(&power_domains->lock);
1547
09731280
ID		 1548 if (__intel_display_power_is_enabled(dev_priv, domain)) {
1549 __intel_display_power_get_domain(dev_priv, domain);
1550 is_enabled = true;
1551 } else {
1552 is_enabled = false;
9c065a7d
DV		 1553 }
1554
9c065a7d 1555 mutex_unlock(&power_domains->lock);
09731280
ID		 1556
1557 if (!is_enabled)
1558 intel_runtime_pm_put(dev_priv);
1559
1560 return is_enabled;
9c065a7d
DV		 1561}
1562
e4e7684f
DV		 1563/**
1564 * intel_display_power_put - release a power domain reference
1565 * @dev_priv: i915 device instance
1566 * @domain: power domain to reference
1567 *
1568 * This function drops the power domain reference obtained by
1569 * intel_display_power_get() and might power down the corresponding hardware
1570 * block right away if this is the last reference.
1571 */
9c065a7d
DV		 1572void intel_display_power_put(struct drm_i915_private *dev_priv,
1573 enum intel_display_power_domain domain)
1574{
1575 struct i915_power_domains *power_domains;
1576 struct i915_power_well *power_well;
1577 int i;
1578
1579 power_domains = &dev_priv->power_domains;
1580
1581 mutex_lock(&power_domains->lock);
1582
11c86db8
DS		 1583 WARN(!power_domains->domain_use_count[domain],
1584 "Use count on domain %s is already zero\n",
1585 intel_display_power_domain_str(domain));
9c065a7d
DV		 1586 power_domains->domain_use_count[domain]--;
1587
1588 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
11c86db8
DS		 1589 WARN(!power_well->count,
1590 "Use count on power well %s is already zero",
1591 power_well->name);
9c065a7d 1592
d314cd43 1593 if (!--power_well->count)
dcddab3a 1594 intel_power_well_disable(dev_priv, power_well);
9c065a7d
DV		 1595 }
1596
1597 mutex_unlock(&power_domains->lock);
1598
1599 intel_runtime_pm_put(dev_priv);
1600}
1601
9c065a7d
DV		 1602#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
1603 BIT(POWER_DOMAIN_PIPE_A) | \
1604 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
6331a704
PJ		 1605 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
1606 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1607 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1608 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
9c065a7d
DV		 1609 BIT(POWER_DOMAIN_PORT_CRT) | \
1610 BIT(POWER_DOMAIN_PLLS) | \
1407121a
S		 1611 BIT(POWER_DOMAIN_AUX_A) | \
1612 BIT(POWER_DOMAIN_AUX_B) | \
1613 BIT(POWER_DOMAIN_AUX_C) | \
1614 BIT(POWER_DOMAIN_AUX_D) | \
f0ab43e6 1615 BIT(POWER_DOMAIN_GMBUS) | \
9c065a7d
DV		 1616 BIT(POWER_DOMAIN_INIT))
1617#define HSW_DISPLAY_POWER_DOMAINS ( \
1618 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
1619 BIT(POWER_DOMAIN_INIT))
1620
1621#define BDW_ALWAYS_ON_POWER_DOMAINS ( \
1622 HSW_ALWAYS_ON_POWER_DOMAINS | \
1623 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1624#define BDW_DISPLAY_POWER_DOMAINS ( \
1625 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
1626 BIT(POWER_DOMAIN_INIT))
1627
1628#define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
1629#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
1630
1631#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6331a704
PJ		 1632 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1633 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
9c065a7d 1634 BIT(POWER_DOMAIN_PORT_CRT) | \
1407121a
S		 1635 BIT(POWER_DOMAIN_AUX_B) | \
1636 BIT(POWER_DOMAIN_AUX_C) | \
9c065a7d
DV		 1637 BIT(POWER_DOMAIN_INIT))
1638
1639#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6331a704 1640 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1407121a 1641 BIT(POWER_DOMAIN_AUX_B) | \
9c065a7d
DV		 1642 BIT(POWER_DOMAIN_INIT))
1643
1644#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6331a704 1645 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1407121a 1646 BIT(POWER_DOMAIN_AUX_B) | \
9c065a7d
DV		 1647 BIT(POWER_DOMAIN_INIT))
1648
1649#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6331a704 1650 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1407121a 1651 BIT(POWER_DOMAIN_AUX_C) | \
9c065a7d
DV		 1652 BIT(POWER_DOMAIN_INIT))
1653
1654#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6331a704 1655 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1407121a 1656 BIT(POWER_DOMAIN_AUX_C) | \
9c065a7d
DV		 1657 BIT(POWER_DOMAIN_INIT))
1658
9c065a7d 1659#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
6331a704
PJ		 1660 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1661 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1407121a
S		 1662 BIT(POWER_DOMAIN_AUX_B) | \
1663 BIT(POWER_DOMAIN_AUX_C) | \
9c065a7d
DV		 1664 BIT(POWER_DOMAIN_INIT))
1665
1666#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
6331a704 1667 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1407121a 1668 BIT(POWER_DOMAIN_AUX_D) | \
9c065a7d
DV		 1669 BIT(POWER_DOMAIN_INIT))
1670
9c065a7d
DV		 1671static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1672 .sync_hw = i9xx_always_on_power_well_noop,
1673 .enable = i9xx_always_on_power_well_noop,
1674 .disable = i9xx_always_on_power_well_noop,
1675 .is_enabled = i9xx_always_on_power_well_enabled,
1676};
1677
1678static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1679 .sync_hw = chv_pipe_power_well_sync_hw,
1680 .enable = chv_pipe_power_well_enable,
1681 .disable = chv_pipe_power_well_disable,
1682 .is_enabled = chv_pipe_power_well_enabled,
1683};
1684
1685static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1686 .sync_hw = vlv_power_well_sync_hw,
1687 .enable = chv_dpio_cmn_power_well_enable,
1688 .disable = chv_dpio_cmn_power_well_disable,
1689 .is_enabled = vlv_power_well_enabled,
1690};
1691
1692static struct i915_power_well i9xx_always_on_power_well[] = {
1693 {
1694 .name = "always-on",
1695 .always_on = 1,
1696 .domains = POWER_DOMAIN_MASK,
1697 .ops = &i9xx_always_on_power_well_ops,
1698 },
1699};
1700
1701static const struct i915_power_well_ops hsw_power_well_ops = {
1702 .sync_hw = hsw_power_well_sync_hw,
1703 .enable = hsw_power_well_enable,
1704 .disable = hsw_power_well_disable,
1705 .is_enabled = hsw_power_well_enabled,
1706};
1707
94dd5138
S		 1708static const struct i915_power_well_ops skl_power_well_ops = {
1709 .sync_hw = skl_power_well_sync_hw,
1710 .enable = skl_power_well_enable,
1711 .disable = skl_power_well_disable,
1712 .is_enabled = skl_power_well_enabled,
1713};
1714
9f836f90
PJ		 1715static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1716 .sync_hw = gen9_dc_off_power_well_sync_hw,
1717 .enable = gen9_dc_off_power_well_enable,
1718 .disable = gen9_dc_off_power_well_disable,
1719 .is_enabled = gen9_dc_off_power_well_enabled,
1720};
1721
9c065a7d
DV		 1722static struct i915_power_well hsw_power_wells[] = {
1723 {
1724 .name = "always-on",
1725 .always_on = 1,
1726 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1727 .ops = &i9xx_always_on_power_well_ops,
1728 },
1729 {
1730 .name = "display",
1731 .domains = HSW_DISPLAY_POWER_DOMAINS,
1732 .ops = &hsw_power_well_ops,
1733 },
1734};
1735
1736static struct i915_power_well bdw_power_wells[] = {
1737 {
1738 .name = "always-on",
1739 .always_on = 1,
1740 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1741 .ops = &i9xx_always_on_power_well_ops,
1742 },
1743 {
1744 .name = "display",
1745 .domains = BDW_DISPLAY_POWER_DOMAINS,
1746 .ops = &hsw_power_well_ops,
1747 },
1748};
1749
1750static const struct i915_power_well_ops vlv_display_power_well_ops = {
1751 .sync_hw = vlv_power_well_sync_hw,
1752 .enable = vlv_display_power_well_enable,
1753 .disable = vlv_display_power_well_disable,
1754 .is_enabled = vlv_power_well_enabled,
1755};
1756
1757static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1758 .sync_hw = vlv_power_well_sync_hw,
1759 .enable = vlv_dpio_cmn_power_well_enable,
1760 .disable = vlv_dpio_cmn_power_well_disable,
1761 .is_enabled = vlv_power_well_enabled,
1762};
1763
1764static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1765 .sync_hw = vlv_power_well_sync_hw,
1766 .enable = vlv_power_well_enable,
1767 .disable = vlv_power_well_disable,
1768 .is_enabled = vlv_power_well_enabled,
1769};
1770
1771static struct i915_power_well vlv_power_wells[] = {
1772 {
1773 .name = "always-on",
1774 .always_on = 1,
1775 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1776 .ops = &i9xx_always_on_power_well_ops,
56fcfd63 1777 .data = PUNIT_POWER_WELL_ALWAYS_ON,
9c065a7d
DV		 1778 },
1779 {
1780 .name = "display",
1781 .domains = VLV_DISPLAY_POWER_DOMAINS,
1782 .data = PUNIT_POWER_WELL_DISP2D,
1783 .ops = &vlv_display_power_well_ops,
1784 },
1785 {
1786 .name = "dpio-tx-b-01",
1787 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1788 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1789 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1790 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1791 .ops = &vlv_dpio_power_well_ops,
1792 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1793 },
1794 {
1795 .name = "dpio-tx-b-23",
1796 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1797 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1798 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1799 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1800 .ops = &vlv_dpio_power_well_ops,
1801 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1802 },
1803 {
1804 .name = "dpio-tx-c-01",
1805 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1806 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1807 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1808 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1809 .ops = &vlv_dpio_power_well_ops,
1810 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1811 },
1812 {
1813 .name = "dpio-tx-c-23",
1814 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1815 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1816 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1817 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1818 .ops = &vlv_dpio_power_well_ops,
1819 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1820 },
1821 {
1822 .name = "dpio-common",
1823 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1824 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1825 .ops = &vlv_dpio_cmn_power_well_ops,
1826 },
1827};
1828
1829static struct i915_power_well chv_power_wells[] = {
1830 {
1831 .name = "always-on",
1832 .always_on = 1,
1833 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1834 .ops = &i9xx_always_on_power_well_ops,
1835 },
9c065a7d
DV		 1836 {
1837 .name = "display",
baa4e575 1838 /*
fde61e4b
VS		 1839 * Pipe A power well is the new disp2d well. Pipe B and C
1840 * power wells don't actually exist. Pipe A power well is
1841 * required for any pipe to work.
baa4e575 1842 */
fde61e4b 1843 .domains = VLV_DISPLAY_POWER_DOMAINS,
9c065a7d
DV		 1844 .data = PIPE_A,
1845 .ops = &chv_pipe_power_well_ops,
1846 },
9c065a7d
DV		 1847 {
1848 .name = "dpio-common-bc",
71849b67 1849 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
9c065a7d
DV		 1850 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1851 .ops = &chv_dpio_cmn_power_well_ops,
1852 },
1853 {
1854 .name = "dpio-common-d",
71849b67 1855 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
9c065a7d
DV		 1856 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1857 .ops = &chv_dpio_cmn_power_well_ops,
1858 },
9c065a7d
DV		 1859};
1860
5aefb239
SS		 1861bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1862 int power_well_id)
1863{
1864 struct i915_power_well *power_well;
1865 bool ret;
1866
1867 power_well = lookup_power_well(dev_priv, power_well_id);
1868 ret = power_well->ops->is_enabled(dev_priv, power_well);
1869
1870 return ret;
1871}
1872
94dd5138
S		 1873static struct i915_power_well skl_power_wells[] = {
1874 {
1875 .name = "always-on",
1876 .always_on = 1,
1877 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1878 .ops = &i9xx_always_on_power_well_ops,
56fcfd63 1879 .data = SKL_DISP_PW_ALWAYS_ON,
94dd5138
S		 1880 },
1881 {
1882 .name = "power well 1",
4a76f295
ID		 1883 /* Handled by the DMC firmware */
1884 .domains = 0,
94dd5138
S		 1885 .ops = &skl_power_well_ops,
1886 .data = SKL_DISP_PW_1,
1887 },
1888 {
1889 .name = "MISC IO power well",
4a76f295
ID		 1890 /* Handled by the DMC firmware */
1891 .domains = 0,
94dd5138
S		 1892 .ops = &skl_power_well_ops,
1893 .data = SKL_DISP_PW_MISC_IO,
1894 },
9f836f90
PJ		 1895 {
1896 .name = "DC off",
1897 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
1898 .ops = &gen9_dc_off_power_well_ops,
1899 .data = SKL_DISP_PW_DC_OFF,
1900 },
94dd5138
S		 1901 {
1902 .name = "power well 2",
1903 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1904 .ops = &skl_power_well_ops,
1905 .data = SKL_DISP_PW_2,
1906 },
1907 {
1908 .name = "DDI A/E power well",
1909 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1910 .ops = &skl_power_well_ops,
1911 .data = SKL_DISP_PW_DDI_A_E,
1912 },
1913 {
1914 .name = "DDI B power well",
1915 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1916 .ops = &skl_power_well_ops,
1917 .data = SKL_DISP_PW_DDI_B,
1918 },
1919 {
1920 .name = "DDI C power well",
1921 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1922 .ops = &skl_power_well_ops,
1923 .data = SKL_DISP_PW_DDI_C,
1924 },
1925 {
1926 .name = "DDI D power well",
1927 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1928 .ops = &skl_power_well_ops,
1929 .data = SKL_DISP_PW_DDI_D,
1930 },
1931};
1932
2f693e28
DL		 1933void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
1934{
1935 struct i915_power_well *well;
1936
16fbc291 1937 if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
2f693e28
DL		 1938 return;
1939
1940 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1941 intel_power_well_enable(dev_priv, well);
1942
1943 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1944 intel_power_well_enable(dev_priv, well);
1945}
1946
1947void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
1948{
1949 struct i915_power_well *well;
1950
16fbc291 1951 if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
2f693e28
DL		 1952 return;
1953
1954 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1955 intel_power_well_disable(dev_priv, well);
1956
1957 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1958 intel_power_well_disable(dev_priv, well);
1959}
1960
0b4a2a36
S		 1961static struct i915_power_well bxt_power_wells[] = {
1962 {
1963 .name = "always-on",
1964 .always_on = 1,
1965 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1966 .ops = &i9xx_always_on_power_well_ops,
1967 },
1968 {
1969 .name = "power well 1",
1970 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1971 .ops = &skl_power_well_ops,
1972 .data = SKL_DISP_PW_1,
1973 },
9f836f90
PJ		 1974 {
1975 .name = "DC off",
1976 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
1977 .ops = &gen9_dc_off_power_well_ops,
1978 .data = SKL_DISP_PW_DC_OFF,
1979 },
0b4a2a36
S		 1980 {
1981 .name = "power well 2",
1982 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1983 .ops = &skl_power_well_ops,
1984 .data = SKL_DISP_PW_2,
9f836f90 1985 },
0b4a2a36
S		 1986};
1987
1b0e3a04
ID		 1988static int
1989sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
1990 int disable_power_well)
1991{
1992 if (disable_power_well >= 0)
1993 return !!disable_power_well;
1994
18024199
MR		 1995 if (IS_BROXTON(dev_priv)) {
1996 DRM_DEBUG_KMS("Disabling display power well support\n");
1997 return 0;
1998 }
1999
1b0e3a04
ID		 2000 return 1;
2001}
2002
9c065a7d
DV		 2003#define set_power_wells(power_domains, __power_wells) ({ \
2004 (power_domains)->power_wells = (__power_wells); \
2005 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
2006})
2007
e4e7684f
DV		 2008/**
2009 * intel_power_domains_init - initializes the power domain structures
2010 * @dev_priv: i915 device instance
2011 *
2012 * Initializes the power domain structures for @dev_priv depending upon the
2013 * supported platform.
2014 */
9c065a7d
DV		 2015int intel_power_domains_init(struct drm_i915_private *dev_priv)
2016{
2017 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2018
1b0e3a04
ID		 2019 i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
2020 i915.disable_power_well);
2021
f0ab43e6
VS		 2022 BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
2023
9c065a7d
DV		 2024 mutex_init(&power_domains->lock);
2025
2026 /*
2027 * The enabling order will be from lower to higher indexed wells,
2028 * the disabling order is reversed.
2029 */
2030 if (IS_HASWELL(dev_priv->dev)) {
2031 set_power_wells(power_domains, hsw_power_wells);
9c065a7d
DV		 2032 } else if (IS_BROADWELL(dev_priv->dev)) {
2033 set_power_wells(power_domains, bdw_power_wells);
ef11bdb3 2034 } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) {
94dd5138 2035 set_power_wells(power_domains, skl_power_wells);
0b4a2a36
S		 2036 } else if (IS_BROXTON(dev_priv->dev)) {
2037 set_power_wells(power_domains, bxt_power_wells);
9c065a7d
DV		 2038 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
2039 set_power_wells(power_domains, chv_power_wells);
2040 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
2041 set_power_wells(power_domains, vlv_power_wells);
2042 } else {
2043 set_power_wells(power_domains, i9xx_always_on_power_well);
2044 }
2045
2046 return 0;
2047}
2048
e4e7684f
DV		 2049/**
2050 * intel_power_domains_fini - finalizes the power domain structures
2051 * @dev_priv: i915 device instance
2052 *
2053 * Finalizes the power domain structures for @dev_priv depending upon the
2054 * supported platform. This function also disables runtime pm and ensures that
2055 * the device stays powered up so that the driver can be reloaded.
2056 */
f458ebbc 2057void intel_power_domains_fini(struct drm_i915_private *dev_priv)
9c065a7d 2058{
25b181b4
ID		 2059 struct device *device = &dev_priv->dev->pdev->dev;
2060
aabee1bb
ID		 2061 /*
2062 * The i915.ko module is still not prepared to be loaded when
f458ebbc 2063 * the power well is not enabled, so just enable it in case
aabee1bb
ID		 2064 * we're going to unload/reload.
2065 * The following also reacquires the RPM reference the core passed
2066 * to the driver during loading, which is dropped in
2067 * intel_runtime_pm_enable(). We have to hand back the control of the
2068 * device to the core with this reference held.
2069 */
f458ebbc 2070 intel_display_set_init_power(dev_priv, true);
d314cd43
ID		 2071
2072 /* Remove the refcount we took to keep power well support disabled. */
2073 if (!i915.disable_power_well)
2074 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
25b181b4
ID		 2075
2076 /*
2077 * Remove the refcount we took in intel_runtime_pm_enable() in case
2078 * the platform doesn't support runtime PM.
2079 */
2080 if (!HAS_RUNTIME_PM(dev_priv))
2081 pm_runtime_put(device);
9c065a7d
DV		 2082}
2083
30eade12 2084static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
9c065a7d
DV		 2085{
2086 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2087 struct i915_power_well *power_well;
2088 int i;
2089
2090 mutex_lock(&power_domains->lock);
2091 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2092 power_well->ops->sync_hw(dev_priv, power_well);
2093 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2094 power_well);
2095 }
2096 mutex_unlock(&power_domains->lock);
2097}
2098
73dfc227
ID		 2099static void skl_display_core_init(struct drm_i915_private *dev_priv,
2100 bool resume)
2101{
2102 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2103 uint32_t val;
2104
d26fa1d5
ID		 2105 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2106
73dfc227
ID		 2107 /* enable PCH reset handshake */
2108 val = I915_READ(HSW_NDE_RSTWRN_OPT);
2109 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2110
2111 /* enable PG1 and Misc I/O */
2112 mutex_lock(&power_domains->lock);
2113 skl_pw1_misc_io_init(dev_priv);
2114 mutex_unlock(&power_domains->lock);
2115
2116 if (!resume)
2117 return;
2118
2119 skl_init_cdclk(dev_priv);
2120
2121 if (dev_priv->csr.dmc_payload)
2122 intel_csr_load_program(dev_priv);
2123}
2124
2125static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2126{
2127 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2128
d26fa1d5
ID		 2129 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2130
73dfc227
ID		 2131 skl_uninit_cdclk(dev_priv);
2132
2133 /* The spec doesn't call for removing the reset handshake flag */
2134 /* disable PG1 and Misc I/O */
2135 mutex_lock(&power_domains->lock);
2136 skl_pw1_misc_io_fini(dev_priv);
2137 mutex_unlock(&power_domains->lock);
2138}
2139
70722468
VS		 2140static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2141{
2142 struct i915_power_well *cmn_bc =
2143 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2144 struct i915_power_well *cmn_d =
2145 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2146
2147 /*
2148 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2149 * workaround never ever read DISPLAY_PHY_CONTROL, and
2150 * instead maintain a shadow copy ourselves. Use the actual
e0fce78f
VS		 2151 * power well state and lane status to reconstruct the
2152 * expected initial value.
70722468
VS		 2153 */
2154 dev_priv->chv_phy_control =
bc284542
VS		 2155 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2156 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
e0fce78f
VS		 2157 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2158 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2159 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2160
2161 /*
2162 * If all lanes are disabled we leave the override disabled
2163 * with all power down bits cleared to match the state we
2164 * would use after disabling the port. Otherwise enable the
2165 * override and set the lane powerdown bits accding to the
2166 * current lane status.
2167 */
2168 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2169 uint32_t status = I915_READ(DPLL(PIPE_A));
2170 unsigned int mask;
2171
2172 mask = status & DPLL_PORTB_READY_MASK;
2173 if (mask == 0xf)
2174 mask = 0x0;
2175 else
2176 dev_priv->chv_phy_control |=
2177 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2178
2179 dev_priv->chv_phy_control |=
2180 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2181
2182 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2183 if (mask == 0xf)
2184 mask = 0x0;
2185 else
2186 dev_priv->chv_phy_control |=
2187 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2188
2189 dev_priv->chv_phy_control |=
2190 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2191
70722468 2192 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
3be60de9
VS		 2193
2194 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2195 } else {
2196 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
e0fce78f
VS		 2197 }
2198
2199 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2200 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2201 unsigned int mask;
2202
2203 mask = status & DPLL_PORTD_READY_MASK;
2204
2205 if (mask == 0xf)
2206 mask = 0x0;
2207 else
2208 dev_priv->chv_phy_control |=
2209 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2210
2211 dev_priv->chv_phy_control |=
2212 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2213
70722468 2214 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
3be60de9
VS		 2215
2216 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2217 } else {
2218 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
e0fce78f
VS		 2219 }
2220
2221 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2222
2223 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2224 dev_priv->chv_phy_control);
70722468
VS		 2225}
2226
9c065a7d
DV		 2227static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2228{
2229 struct i915_power_well *cmn =
2230 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2231 struct i915_power_well *disp2d =
2232 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2233
9c065a7d 2234 /* If the display might be already active skip this */
5d93a6e5
VS		 2235 if (cmn->ops->is_enabled(dev_priv, cmn) &&
2236 disp2d->ops->is_enabled(dev_priv, disp2d) &&
9c065a7d
DV		 2237 I915_READ(DPIO_CTL) & DPIO_CMNRST)
2238 return;
2239
2240 DRM_DEBUG_KMS("toggling display PHY side reset\n");
2241
2242 /* cmnlane needs DPLL registers */
2243 disp2d->ops->enable(dev_priv, disp2d);
2244
2245 /*
2246 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2247 * Need to assert and de-assert PHY SB reset by gating the
2248 * common lane power, then un-gating it.
2249 * Simply ungating isn't enough to reset the PHY enough to get
2250 * ports and lanes running.
2251 */
2252 cmn->ops->disable(dev_priv, cmn);
2253}
2254
e4e7684f
DV		 2255/**
2256 * intel_power_domains_init_hw - initialize hardware power domain state
2257 * @dev_priv: i915 device instance
2258 *
2259 * This function initializes the hardware power domain state and enables all
2260 * power domains using intel_display_set_init_power().
2261 */
73dfc227 2262void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
9c065a7d
DV		 2263{
2264 struct drm_device *dev = dev_priv->dev;
2265 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2266
2267 power_domains->initializing = true;
2268
73dfc227
ID		 2269 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2270 skl_display_core_init(dev_priv, resume);
2271 } else if (IS_CHERRYVIEW(dev)) {
770effb1 2272 mutex_lock(&power_domains->lock);
70722468 2273 chv_phy_control_init(dev_priv);
770effb1 2274 mutex_unlock(&power_domains->lock);
70722468 2275 } else if (IS_VALLEYVIEW(dev)) {
9c065a7d
DV		 2276 mutex_lock(&power_domains->lock);
2277 vlv_cmnlane_wa(dev_priv);
2278 mutex_unlock(&power_domains->lock);
2279 }
2280
2281 /* For now, we need the power well to be always enabled. */
2282 intel_display_set_init_power(dev_priv, true);
d314cd43
ID		 2283 /* Disable power support if the user asked so. */
2284 if (!i915.disable_power_well)
2285 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
30eade12 2286 intel_power_domains_sync_hw(dev_priv);
9c065a7d
DV		 2287 power_domains->initializing = false;
2288}
2289
73dfc227
ID		 2290/**
2291 * intel_power_domains_suspend - suspend power domain state
2292 * @dev_priv: i915 device instance
2293 *
2294 * This function prepares the hardware power domain state before entering
2295 * system suspend. It must be paired with intel_power_domains_init_hw().
2296 */
2297void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2298{
2299 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2300 skl_display_core_uninit(dev_priv);
d314cd43
ID		 2301
2302 /*
2303 * Even if power well support was disabled we still want to disable
2304 * power wells while we are system suspended.
2305 */
2306 if (!i915.disable_power_well)
2307 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
73dfc227
ID		 2308}
2309
e4e7684f
DV		 2310/**
2311 * intel_runtime_pm_get - grab a runtime pm reference
2312 * @dev_priv: i915 device instance
2313 *
2314 * This function grabs a device-level runtime pm reference (mostly used for GEM
2315 * code to ensure the GTT or GT is on) and ensures that it is powered up.
2316 *
2317 * Any runtime pm reference obtained by this function must have a symmetric
2318 * call to intel_runtime_pm_put() to release the reference again.
2319 */
9c065a7d
DV		 2320void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2321{
2322 struct drm_device *dev = dev_priv->dev;
2323 struct device *device = &dev->pdev->dev;
2324
9c065a7d 2325 pm_runtime_get_sync(device);
1f814dac
ID		 2326
2327 atomic_inc(&dev_priv->pm.wakeref_count);
c9b8846a 2328 assert_rpm_wakelock_held(dev_priv);
9c065a7d
DV		 2329}
2330
09731280
ID		 2331/**
2332 * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2333 * @dev_priv: i915 device instance
2334 *
2335 * This function grabs a device-level runtime pm reference if the device is
2336 * already in use and ensures that it is powered up.
2337 *
2338 * Any runtime pm reference obtained by this function must have a symmetric
2339 * call to intel_runtime_pm_put() to release the reference again.
2340 */
2341bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2342{
2343 struct drm_device *dev = dev_priv->dev;
2344 struct device *device = &dev->pdev->dev;
2345 int ret;
2346
2347 if (!IS_ENABLED(CONFIG_PM))
2348 return true;
2349
2350 ret = pm_runtime_get_if_in_use(device);
2351
2352 /*
2353 * In cases runtime PM is disabled by the RPM core and we get an
2354 * -EINVAL return value we are not supposed to call this function,
2355 * since the power state is undefined. This applies atm to the
2356 * late/early system suspend/resume handlers.
2357 */
2358 WARN_ON_ONCE(ret < 0);
2359 if (ret <= 0)
2360 return false;
2361
2362 atomic_inc(&dev_priv->pm.wakeref_count);
2363 assert_rpm_wakelock_held(dev_priv);
2364
2365 return true;
2366}
2367
e4e7684f
DV		 2368/**
2369 * intel_runtime_pm_get_noresume - grab a runtime pm reference
2370 * @dev_priv: i915 device instance
2371 *
2372 * This function grabs a device-level runtime pm reference (mostly used for GEM
2373 * code to ensure the GTT or GT is on).
2374 *
2375 * It will _not_ power up the device but instead only check that it's powered
2376 * on. Therefore it is only valid to call this functions from contexts where
2377 * the device is known to be powered up and where trying to power it up would
2378 * result in hilarity and deadlocks. That pretty much means only the system
2379 * suspend/resume code where this is used to grab runtime pm references for
2380 * delayed setup down in work items.
2381 *
2382 * Any runtime pm reference obtained by this function must have a symmetric
2383 * call to intel_runtime_pm_put() to release the reference again.
2384 */
9c065a7d
DV		 2385void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2386{
2387 struct drm_device *dev = dev_priv->dev;
2388 struct device *device = &dev->pdev->dev;
2389
c9b8846a 2390 assert_rpm_wakelock_held(dev_priv);
9c065a7d 2391 pm_runtime_get_noresume(device);
1f814dac
ID		 2392
2393 atomic_inc(&dev_priv->pm.wakeref_count);
9c065a7d
DV		 2394}
2395
e4e7684f
DV		 2396/**
2397 * intel_runtime_pm_put - release a runtime pm reference
2398 * @dev_priv: i915 device instance
2399 *
2400 * This function drops the device-level runtime pm reference obtained by
2401 * intel_runtime_pm_get() and might power down the corresponding
2402 * hardware block right away if this is the last reference.
2403 */
9c065a7d
DV		 2404void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2405{
2406 struct drm_device *dev = dev_priv->dev;
2407 struct device *device = &dev->pdev->dev;
2408
542db3cd 2409 assert_rpm_wakelock_held(dev_priv);
2b19efeb
ID		 2410 if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2411 atomic_inc(&dev_priv->pm.atomic_seq);
1f814dac 2412
9c065a7d
DV		 2413 pm_runtime_mark_last_busy(device);
2414 pm_runtime_put_autosuspend(device);
2415}
2416
e4e7684f
DV		 2417/**
2418 * intel_runtime_pm_enable - enable runtime pm
2419 * @dev_priv: i915 device instance
2420 *
2421 * This function enables runtime pm at the end of the driver load sequence.
2422 *
2423 * Note that this function does currently not enable runtime pm for the
2424 * subordinate display power domains. That is only done on the first modeset
2425 * using intel_display_set_init_power().
2426 */
f458ebbc 2427void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
9c065a7d
DV		 2428{
2429 struct drm_device *dev = dev_priv->dev;
2430 struct device *device = &dev->pdev->dev;
2431
cbc68dc9
ID		 2432 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2433 pm_runtime_mark_last_busy(device);
2434
25b181b4
ID		 2435 /*
2436 * Take a permanent reference to disable the RPM functionality and drop
2437 * it only when unloading the driver. Use the low level get/put helpers,
2438 * so the driver's own RPM reference tracking asserts also work on
2439 * platforms without RPM support.
2440 */
cbc68dc9
ID		 2441 if (!HAS_RUNTIME_PM(dev)) {
2442 pm_runtime_dont_use_autosuspend(device);
25b181b4 2443 pm_runtime_get_sync(device);
cbc68dc9
ID		 2444 } else {
2445 pm_runtime_use_autosuspend(device);
2446 }
9c065a7d 2447
aabee1bb
ID		 2448 /*
2449 * The core calls the driver load handler with an RPM reference held.
2450 * We drop that here and will reacquire it during unloading in
2451 * intel_power_domains_fini().
2452 */
9c065a7d
DV		 2453 pm_runtime_put_autosuspend(device);
2454}
2455
Ubuntu Artful kernel mirror