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drm/i915/gen9: Turn DC handling into a power well
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_runtime_pm.c
CommitLineData
9c065a7d
DV		 1/*
2 * Copyright © 2012-2014 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 * Daniel Vetter <daniel.vetter@ffwll.ch>
26 *
27 */
28
29#include <linux/pm_runtime.h>
30#include <linux/vgaarb.h>
31
32#include "i915_drv.h"
33#include "intel_drv.h"
9c065a7d 34
e4e7684f
DV		 35/**
36 * DOC: runtime pm
37 *
38 * The i915 driver supports dynamic enabling and disabling of entire hardware
39 * blocks at runtime. This is especially important on the display side where
40 * software is supposed to control many power gates manually on recent hardware,
41 * since on the GT side a lot of the power management is done by the hardware.
42 * But even there some manual control at the device level is required.
43 *
44 * Since i915 supports a diverse set of platforms with a unified codebase and
45 * hardware engineers just love to shuffle functionality around between power
46 * domains there's a sizeable amount of indirection required. This file provides
47 * generic functions to the driver for grabbing and releasing references for
48 * abstract power domains. It then maps those to the actual power wells
49 * present for a given platform.
50 */
51
9c065a7d
DV		 52#define for_each_power_well(i, power_well, domain_mask, power_domains) \
53 for (i = 0; \
54 i < (power_domains)->power_well_count && \
55 ((power_well) = &(power_domains)->power_wells[i]); \
56 i++) \
57 if ((power_well)->domains & (domain_mask))
58
59#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
60 for (i = (power_domains)->power_well_count - 1; \
61 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
62 i--) \
63 if ((power_well)->domains & (domain_mask))
64
5aefb239
SS		 65bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
66 int power_well_id);
67
e8ca9320
DL		 68static void intel_power_well_enable(struct drm_i915_private *dev_priv,
69 struct i915_power_well *power_well)
70{
71 DRM_DEBUG_KMS("enabling %s\n", power_well->name);
72 power_well->ops->enable(dev_priv, power_well);
73 power_well->hw_enabled = true;
74}
75
dcddab3a
DL		 76static void intel_power_well_disable(struct drm_i915_private *dev_priv,
77 struct i915_power_well *power_well)
78{
79 DRM_DEBUG_KMS("disabling %s\n", power_well->name);
80 power_well->hw_enabled = false;
81 power_well->ops->disable(dev_priv, power_well);
82}
83
e4e7684f 84/*
9c065a7d
DV		 85 * We should only use the power well if we explicitly asked the hardware to
86 * enable it, so check if it's enabled and also check if we've requested it to
87 * be enabled.
88 */
89static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
90 struct i915_power_well *power_well)
91{
92 return I915_READ(HSW_PWR_WELL_DRIVER) ==
93 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
94}
95
e4e7684f
DV		 96/**
97 * __intel_display_power_is_enabled - unlocked check for a power domain
98 * @dev_priv: i915 device instance
99 * @domain: power domain to check
100 *
101 * This is the unlocked version of intel_display_power_is_enabled() and should
102 * only be used from error capture and recovery code where deadlocks are
103 * possible.
104 *
105 * Returns:
106 * True when the power domain is enabled, false otherwise.
107 */
f458ebbc
DV		 108bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
109 enum intel_display_power_domain domain)
9c065a7d
DV		 110{
111 struct i915_power_domains *power_domains;
112 struct i915_power_well *power_well;
113 bool is_enabled;
114 int i;
115
116 if (dev_priv->pm.suspended)
117 return false;
118
119 power_domains = &dev_priv->power_domains;
120
121 is_enabled = true;
122
123 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
124 if (power_well->always_on)
125 continue;
126
127 if (!power_well->hw_enabled) {
128 is_enabled = false;
129 break;
130 }
131 }
132
133 return is_enabled;
134}
135
e4e7684f 136/**
f61ccae3 137 * intel_display_power_is_enabled - check for a power domain
e4e7684f
DV		 138 * @dev_priv: i915 device instance
139 * @domain: power domain to check
140 *
141 * This function can be used to check the hw power domain state. It is mostly
142 * used in hardware state readout functions. Everywhere else code should rely
143 * upon explicit power domain reference counting to ensure that the hardware
144 * block is powered up before accessing it.
145 *
146 * Callers must hold the relevant modesetting locks to ensure that concurrent
147 * threads can't disable the power well while the caller tries to read a few
148 * registers.
149 *
150 * Returns:
151 * True when the power domain is enabled, false otherwise.
152 */
f458ebbc
DV		 153bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
154 enum intel_display_power_domain domain)
9c065a7d
DV		 155{
156 struct i915_power_domains *power_domains;
157 bool ret;
158
159 power_domains = &dev_priv->power_domains;
160
161 mutex_lock(&power_domains->lock);
f458ebbc 162 ret = __intel_display_power_is_enabled(dev_priv, domain);
9c065a7d
DV		 163 mutex_unlock(&power_domains->lock);
164
165 return ret;
166}
167
e4e7684f
DV		 168/**
169 * intel_display_set_init_power - set the initial power domain state
170 * @dev_priv: i915 device instance
171 * @enable: whether to enable or disable the initial power domain state
172 *
173 * For simplicity our driver load/unload and system suspend/resume code assumes
174 * that all power domains are always enabled. This functions controls the state
175 * of this little hack. While the initial power domain state is enabled runtime
176 * pm is effectively disabled.
177 */
d9bc89d9
DV		 178void intel_display_set_init_power(struct drm_i915_private *dev_priv,
179 bool enable)
180{
181 if (dev_priv->power_domains.init_power_on == enable)
182 return;
183
184 if (enable)
185 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
186 else
187 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
188
189 dev_priv->power_domains.init_power_on = enable;
190}
191
9c065a7d
DV		 192/*
193 * Starting with Haswell, we have a "Power Down Well" that can be turned off
194 * when not needed anymore. We have 4 registers that can request the power well
195 * to be enabled, and it will only be disabled if none of the registers is
196 * requesting it to be enabled.
197 */
198static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
199{
200 struct drm_device *dev = dev_priv->dev;
201
202 /*
203 * After we re-enable the power well, if we touch VGA register 0x3d5
204 * we'll get unclaimed register interrupts. This stops after we write
205 * anything to the VGA MSR register. The vgacon module uses this
206 * register all the time, so if we unbind our driver and, as a
207 * consequence, bind vgacon, we'll get stuck in an infinite loop at
208 * console_unlock(). So make here we touch the VGA MSR register, making
209 * sure vgacon can keep working normally without triggering interrupts
210 * and error messages.
211 */
212 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
213 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
214 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
215
25400392 216 if (IS_BROADWELL(dev))
4c6c03be
DL		 217 gen8_irq_power_well_post_enable(dev_priv,
218 1 << PIPE_C | 1 << PIPE_B);
9c065a7d
DV		 219}
220
d14c0343
DL		 221static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
222 struct i915_power_well *power_well)
223{
224 struct drm_device *dev = dev_priv->dev;
225
226 /*
227 * After we re-enable the power well, if we touch VGA register 0x3d5
228 * we'll get unclaimed register interrupts. This stops after we write
229 * anything to the VGA MSR register. The vgacon module uses this
230 * register all the time, so if we unbind our driver and, as a
231 * consequence, bind vgacon, we'll get stuck in an infinite loop at
232 * console_unlock(). So make here we touch the VGA MSR register, making
233 * sure vgacon can keep working normally without triggering interrupts
234 * and error messages.
235 */
236 if (power_well->data == SKL_DISP_PW_2) {
237 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
238 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
239 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
240
241 gen8_irq_power_well_post_enable(dev_priv,
242 1 << PIPE_C | 1 << PIPE_B);
243 }
d14c0343
DL		 244}
245
9c065a7d
DV		 246static void hsw_set_power_well(struct drm_i915_private *dev_priv,
247 struct i915_power_well *power_well, bool enable)
248{
249 bool is_enabled, enable_requested;
250 uint32_t tmp;
251
252 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
253 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
254 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
255
256 if (enable) {
257 if (!enable_requested)
258 I915_WRITE(HSW_PWR_WELL_DRIVER,
259 HSW_PWR_WELL_ENABLE_REQUEST);
260
261 if (!is_enabled) {
262 DRM_DEBUG_KMS("Enabling power well\n");
263 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
264 HSW_PWR_WELL_STATE_ENABLED), 20))
265 DRM_ERROR("Timeout enabling power well\n");
6d729bff 266 hsw_power_well_post_enable(dev_priv);
9c065a7d
DV		 267 }
268
9c065a7d
DV		 269 } else {
270 if (enable_requested) {
271 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
272 POSTING_READ(HSW_PWR_WELL_DRIVER);
273 DRM_DEBUG_KMS("Requesting to disable the power well\n");
274 }
275 }
276}
277
94dd5138
S		 278#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
279 BIT(POWER_DOMAIN_TRANSCODER_A) | \
280 BIT(POWER_DOMAIN_PIPE_B) | \
281 BIT(POWER_DOMAIN_TRANSCODER_B) | \
282 BIT(POWER_DOMAIN_PIPE_C) | \
283 BIT(POWER_DOMAIN_TRANSCODER_C) | \
284 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
285 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
6331a704
PJ		 286 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
287 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
288 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
289 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
94dd5138
S		 290 BIT(POWER_DOMAIN_AUX_B) | \
291 BIT(POWER_DOMAIN_AUX_C) | \
292 BIT(POWER_DOMAIN_AUX_D) | \
293 BIT(POWER_DOMAIN_AUDIO) | \
294 BIT(POWER_DOMAIN_VGA) | \
295 BIT(POWER_DOMAIN_INIT))
94dd5138 296#define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
6331a704
PJ		 297 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
298 BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
94dd5138
S		 299 BIT(POWER_DOMAIN_INIT))
300#define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
6331a704 301 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
94dd5138
S		 302 BIT(POWER_DOMAIN_INIT))
303#define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
6331a704 304 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
94dd5138
S		 305 BIT(POWER_DOMAIN_INIT))
306#define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
6331a704 307 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
94dd5138 308 BIT(POWER_DOMAIN_INIT))
9f836f90
PJ		 309#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
310 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
311 BIT(POWER_DOMAIN_MODESET) | \
312 BIT(POWER_DOMAIN_AUX_A) | \
313 BIT(POWER_DOMAIN_INIT))
94dd5138 314#define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
4a76f295 315 (POWER_DOMAIN_MASK & ~( \
9f836f90
PJ		 316 SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
317 SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) | \
94dd5138
S		 318 BIT(POWER_DOMAIN_INIT))
319
0b4a2a36
S		 320#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
321 BIT(POWER_DOMAIN_TRANSCODER_A) | \
322 BIT(POWER_DOMAIN_PIPE_B) | \
323 BIT(POWER_DOMAIN_TRANSCODER_B) | \
324 BIT(POWER_DOMAIN_PIPE_C) | \
325 BIT(POWER_DOMAIN_TRANSCODER_C) | \
326 BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
327 BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
6331a704
PJ		 328 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
329 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
0b4a2a36
S		 330 BIT(POWER_DOMAIN_AUX_B) | \
331 BIT(POWER_DOMAIN_AUX_C) | \
332 BIT(POWER_DOMAIN_AUDIO) | \
333 BIT(POWER_DOMAIN_VGA) | \
f0ab43e6 334 BIT(POWER_DOMAIN_GMBUS) | \
0b4a2a36
S		 335 BIT(POWER_DOMAIN_INIT))
336#define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \
337 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
338 BIT(POWER_DOMAIN_PIPE_A) | \
339 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
340 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
6331a704 341 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
0b4a2a36
S		 342 BIT(POWER_DOMAIN_AUX_A) | \
343 BIT(POWER_DOMAIN_PLLS) | \
344 BIT(POWER_DOMAIN_INIT))
9f836f90
PJ		 345#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
346 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
347 BIT(POWER_DOMAIN_MODESET) | \
348 BIT(POWER_DOMAIN_AUX_A) | \
349 BIT(POWER_DOMAIN_INIT))
0b4a2a36
S		 350#define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
351 (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \
352 BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \
353 BIT(POWER_DOMAIN_INIT))
354
664326f8
SK		 355static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
356{
357 struct drm_device *dev = dev_priv->dev;
358
359 WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
360 WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
361 "DC9 already programmed to be enabled.\n");
362 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
363 "DC5 still not disabled to enable DC9.\n");
364 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
365 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
366
367 /*
368 * TODO: check for the following to verify the conditions to enter DC9
369 * state are satisfied:
370 * 1] Check relevant display engine registers to verify if mode set
371 * disable sequence was followed.
372 * 2] Check if display uninitialize sequence is initialized.
373 */
374}
375
376static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
377{
378 WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
379 WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
380 "DC9 already programmed to be disabled.\n");
381 WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
382 "DC5 still not disabled.\n");
383
384 /*
385 * TODO: check for the following to verify DC9 state was indeed
386 * entered before programming to disable it:
387 * 1] Check relevant display engine registers to verify if mode
388 * set disable sequence was followed.
389 * 2] Check if display uninitialize sequence is initialized.
390 */
391}
392
4deccbb2
PJ		 393static void gen9_set_dc_state_debugmask_memory_up(
394 struct drm_i915_private *dev_priv)
395{
396 uint32_t val;
397
398 /* The below bit doesn't need to be cleared ever afterwards */
399 val = I915_READ(DC_STATE_DEBUG);
400 if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
401 val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
402 I915_WRITE(DC_STATE_DEBUG, val);
403 POSTING_READ(DC_STATE_DEBUG);
404 }
405}
406
13ae3a0d 407static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
664326f8
SK		 408{
409 uint32_t val;
13ae3a0d 410 uint32_t mask;
664326f8 411
13ae3a0d
ID		 412 mask = DC_STATE_EN_UPTO_DC5;
413 if (IS_BROXTON(dev_priv))
414 mask |= DC_STATE_EN_DC9;
415 else
416 mask |= DC_STATE_EN_UPTO_DC6;
664326f8 417
13ae3a0d 418 WARN_ON_ONCE(state & ~mask);
664326f8 419
4deccbb2
PJ		 420 if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
421 gen9_set_dc_state_debugmask_memory_up(dev_priv);
422
664326f8 423 val = I915_READ(DC_STATE_EN);
13ae3a0d
ID		 424 DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
425 val & mask, state);
426 val &= ~mask;
427 val |= state;
664326f8
SK		 428 I915_WRITE(DC_STATE_EN, val);
429 POSTING_READ(DC_STATE_EN);
430}
431
13ae3a0d 432void bxt_enable_dc9(struct drm_i915_private *dev_priv)
664326f8 433{
13ae3a0d
ID		 434 assert_can_enable_dc9(dev_priv);
435
436 DRM_DEBUG_KMS("Enabling DC9\n");
664326f8 437
13ae3a0d
ID		 438 gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
439}
440
441void bxt_disable_dc9(struct drm_i915_private *dev_priv)
442{
664326f8
SK		 443 assert_can_disable_dc9(dev_priv);
444
445 DRM_DEBUG_KMS("Disabling DC9\n");
446
13ae3a0d 447 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
664326f8
SK		 448}
449
af5fead2
DV		 450static void assert_csr_loaded(struct drm_i915_private *dev_priv)
451{
452 WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
453 "CSR program storage start is NULL\n");
454 WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
455 WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
456}
457
5aefb239 458static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
dc174300 459{
6b457d31 460 struct drm_device *dev = dev_priv->dev;
5aefb239
SS		 461 bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
462 SKL_DISP_PW_2);
463
6ff8ab0d
JB		 464 WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n");
465 WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
466 WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
5aefb239 467
6ff8ab0d
JB		 468 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
469 "DC5 already programmed to be enabled.\n");
470 WARN_ONCE(dev_priv->pm.suspended,
471 "DC5 cannot be enabled, if platform is runtime-suspended.\n");
5aefb239
SS		 472
473 assert_csr_loaded(dev_priv);
474}
475
476static void assert_can_disable_dc5(struct drm_i915_private *dev_priv)
477{
93c7cb6c
SS		 478 /*
479 * During initialization, the firmware may not be loaded yet.
480 * We still want to make sure that the DC enabling flag is cleared.
481 */
482 if (dev_priv->power_domains.initializing)
483 return;
5aefb239 484
6ff8ab0d 485 WARN_ONCE(dev_priv->pm.suspended,
5aefb239
SS		 486 "Disabling of DC5 while platform is runtime-suspended should never happen.\n");
487}
488
489static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
490{
5aefb239 491 assert_can_enable_dc5(dev_priv);
6b457d31
SK		 492
493 DRM_DEBUG_KMS("Enabling DC5\n");
494
13ae3a0d 495 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
dc174300
SS		 496}
497
93c7cb6c 498static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
f75a1985 499{
74b4f371 500 struct drm_device *dev = dev_priv->dev;
93c7cb6c 501
6ff8ab0d
JB		 502 WARN_ONCE(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n");
503 WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
504 WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
505 "Backlight is not disabled.\n");
506 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
507 "DC6 already programmed to be enabled.\n");
93c7cb6c
SS		 508
509 assert_csr_loaded(dev_priv);
510}
511
512static void assert_can_disable_dc6(struct drm_i915_private *dev_priv)
513{
514 /*
515 * During initialization, the firmware may not be loaded yet.
516 * We still want to make sure that the DC enabling flag is cleared.
517 */
518 if (dev_priv->power_domains.initializing)
519 return;
520
6ff8ab0d
JB		 521 WARN_ONCE(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
522 "DC6 already programmed to be disabled.\n");
93c7cb6c
SS		 523}
524
9f836f90
PJ		 525static void gen9_disable_dc5_dc6(struct drm_i915_private *dev_priv)
526{
527 assert_can_disable_dc5(dev_priv);
528 assert_can_disable_dc6(dev_priv);
529
530 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
531}
532
0a9d2bed 533void skl_enable_dc6(struct drm_i915_private *dev_priv)
93c7cb6c 534{
93c7cb6c 535 assert_can_enable_dc6(dev_priv);
74b4f371
SK		 536
537 DRM_DEBUG_KMS("Enabling DC6\n");
538
13ae3a0d
ID		 539 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
540
f75a1985
SS		 541}
542
0a9d2bed 543void skl_disable_dc6(struct drm_i915_private *dev_priv)
f75a1985 544{
93c7cb6c 545 assert_can_disable_dc6(dev_priv);
74b4f371
SK		 546
547 DRM_DEBUG_KMS("Disabling DC6\n");
548
13ae3a0d 549 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
f75a1985
SS		 550}
551
94dd5138
S		 552static void skl_set_power_well(struct drm_i915_private *dev_priv,
553 struct i915_power_well *power_well, bool enable)
554{
dc174300 555 struct drm_device *dev = dev_priv->dev;
94dd5138
S		 556 uint32_t tmp, fuse_status;
557 uint32_t req_mask, state_mask;
2a51835f 558 bool is_enabled, enable_requested, check_fuse_status = false;
94dd5138
S		 559
560 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
561 fuse_status = I915_READ(SKL_FUSE_STATUS);
562
563 switch (power_well->data) {
564 case SKL_DISP_PW_1:
565 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
566 SKL_FUSE_PG0_DIST_STATUS), 1)) {
567 DRM_ERROR("PG0 not enabled\n");
568 return;
569 }
570 break;
571 case SKL_DISP_PW_2:
572 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
573 DRM_ERROR("PG1 in disabled state\n");
574 return;
575 }
576 break;
577 case SKL_DISP_PW_DDI_A_E:
578 case SKL_DISP_PW_DDI_B:
579 case SKL_DISP_PW_DDI_C:
580 case SKL_DISP_PW_DDI_D:
581 case SKL_DISP_PW_MISC_IO:
582 break;
583 default:
584 WARN(1, "Unknown power well %lu\n", power_well->data);
585 return;
586 }
587
588 req_mask = SKL_POWER_WELL_REQ(power_well->data);
2a51835f 589 enable_requested = tmp & req_mask;
94dd5138 590 state_mask = SKL_POWER_WELL_STATE(power_well->data);
2a51835f 591 is_enabled = tmp & state_mask;
94dd5138
S		 592
593 if (enable) {
2a51835f 594 if (!enable_requested) {
dc174300
SS		 595 WARN((tmp & state_mask) &&
596 !I915_READ(HSW_PWR_WELL_BIOS),
597 "Invalid for power well status to be enabled, unless done by the BIOS, \
598 when request is to disable!\n");
0a9d2bed 599 if (power_well->data == SKL_DISP_PW_2) {
9f836f90
PJ		 600 /*
601 * DDI buffer programming unnecessary during
602 * driver-load/resume as it's already done
603 * during modeset initialization then. It's
604 * also invalid here as encoder list is still
605 * uninitialized.
606 */
607 if (!dev_priv->power_domains.initializing)
608 intel_prepare_ddi(dev);
f75a1985 609 }
94dd5138 610 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
94dd5138
S		 611 }
612
2a51835f 613 if (!is_enabled) {
510e6fdd 614 DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
94dd5138
S		 615 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
616 state_mask), 1))
617 DRM_ERROR("%s enable timeout\n",
618 power_well->name);
619 check_fuse_status = true;
620 }
621 } else {
2a51835f 622 if (enable_requested) {
4a76f295
ID		 623 I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
624 POSTING_READ(HSW_PWR_WELL_DRIVER);
625 DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
94dd5138
S		 626 }
627 }
628
629 if (check_fuse_status) {
630 if (power_well->data == SKL_DISP_PW_1) {
631 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
632 SKL_FUSE_PG1_DIST_STATUS), 1))
633 DRM_ERROR("PG1 distributing status timeout\n");
634 } else if (power_well->data == SKL_DISP_PW_2) {
635 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
636 SKL_FUSE_PG2_DIST_STATUS), 1))
637 DRM_ERROR("PG2 distributing status timeout\n");
638 }
639 }
d14c0343
DL		 640
641 if (enable && !is_enabled)
642 skl_power_well_post_enable(dev_priv, power_well);
94dd5138
S		 643}
644
9c065a7d
DV		 645static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
646 struct i915_power_well *power_well)
647{
648 hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
649
650 /*
651 * We're taking over the BIOS, so clear any requests made by it since
652 * the driver is in charge now.
653 */
654 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
655 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
656}
657
658static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
659 struct i915_power_well *power_well)
660{
661 hsw_set_power_well(dev_priv, power_well, true);
662}
663
664static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
665 struct i915_power_well *power_well)
666{
667 hsw_set_power_well(dev_priv, power_well, false);
668}
669
94dd5138
S		 670static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
671 struct i915_power_well *power_well)
672{
673 uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
674 SKL_POWER_WELL_STATE(power_well->data);
675
676 return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
677}
678
679static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
680 struct i915_power_well *power_well)
681{
682 skl_set_power_well(dev_priv, power_well, power_well->count > 0);
683
684 /* Clear any request made by BIOS as driver is taking over */
685 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
686}
687
688static void skl_power_well_enable(struct drm_i915_private *dev_priv,
689 struct i915_power_well *power_well)
690{
691 skl_set_power_well(dev_priv, power_well, true);
692}
693
694static void skl_power_well_disable(struct drm_i915_private *dev_priv,
695 struct i915_power_well *power_well)
696{
697 skl_set_power_well(dev_priv, power_well, false);
698}
699
9f836f90
PJ		 700static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
701 struct i915_power_well *power_well)
702{
703 return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
704}
705
706static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
707 struct i915_power_well *power_well)
708{
709 gen9_disable_dc5_dc6(dev_priv);
710}
711
712static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
713 struct i915_power_well *power_well)
714{
715 if (IS_SKYLAKE(dev_priv))
716 skl_enable_dc6(dev_priv);
717 else
718 gen9_enable_dc5(dev_priv);
719}
720
721static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
722 struct i915_power_well *power_well)
723{
724 if (power_well->count > 0) {
725 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
726 } else {
727 if (IS_SKYLAKE(dev_priv))
728 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
729 else
730 gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
731 }
732}
733
9c065a7d
DV		 734static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
735 struct i915_power_well *power_well)
736{
737}
738
739static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
740 struct i915_power_well *power_well)
741{
742 return true;
743}
744
745static void vlv_set_power_well(struct drm_i915_private *dev_priv,
746 struct i915_power_well *power_well, bool enable)
747{
748 enum punit_power_well power_well_id = power_well->data;
749 u32 mask;
750 u32 state;
751 u32 ctrl;
752
753 mask = PUNIT_PWRGT_MASK(power_well_id);
754 state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
755 PUNIT_PWRGT_PWR_GATE(power_well_id);
756
757 mutex_lock(&dev_priv->rps.hw_lock);
758
759#define COND \
760 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
761
762 if (COND)
763 goto out;
764
765 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
766 ctrl &= ~mask;
767 ctrl |= state;
768 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
769
770 if (wait_for(COND, 100))
7e35ab88 771 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
9c065a7d
DV		 772 state,
773 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
774
775#undef COND
776
777out:
778 mutex_unlock(&dev_priv->rps.hw_lock);
779}
780
781static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
782 struct i915_power_well *power_well)
783{
784 vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
785}
786
787static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
788 struct i915_power_well *power_well)
789{
790 vlv_set_power_well(dev_priv, power_well, true);
791}
792
793static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
794 struct i915_power_well *power_well)
795{
796 vlv_set_power_well(dev_priv, power_well, false);
797}
798
799static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
800 struct i915_power_well *power_well)
801{
802 int power_well_id = power_well->data;
803 bool enabled = false;
804 u32 mask;
805 u32 state;
806 u32 ctrl;
807
808 mask = PUNIT_PWRGT_MASK(power_well_id);
809 ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
810
811 mutex_lock(&dev_priv->rps.hw_lock);
812
813 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
814 /*
815 * We only ever set the power-on and power-gate states, anything
816 * else is unexpected.
817 */
818 WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
819 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
820 if (state == ctrl)
821 enabled = true;
822
823 /*
824 * A transient state at this point would mean some unexpected party
825 * is poking at the power controls too.
826 */
827 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
828 WARN_ON(ctrl != state);
829
830 mutex_unlock(&dev_priv->rps.hw_lock);
831
832 return enabled;
833}
834
2be7d540 835static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
9c065a7d 836{
5a8fbb7d
VS		 837 enum pipe pipe;
838
839 /*
840 * Enable the CRI clock source so we can get at the
841 * display and the reference clock for VGA
842 * hotplug / manual detection. Supposedly DSI also
843 * needs the ref clock up and running.
844 *
845 * CHV DPLL B/C have some issues if VGA mode is enabled.
846 */
847 for_each_pipe(dev_priv->dev, pipe) {
848 u32 val = I915_READ(DPLL(pipe));
849
850 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
851 if (pipe != PIPE_A)
852 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
853
854 I915_WRITE(DPLL(pipe), val);
855 }
9c065a7d
DV		 856
857 spin_lock_irq(&dev_priv->irq_lock);
858 valleyview_enable_display_irqs(dev_priv);
859 spin_unlock_irq(&dev_priv->irq_lock);
860
861 /*
862 * During driver initialization/resume we can avoid restoring the
863 * part of the HW/SW state that will be inited anyway explicitly.
864 */
865 if (dev_priv->power_domains.initializing)
866 return;
867
b963291c 868 intel_hpd_init(dev_priv);
9c065a7d
DV		 869
870 i915_redisable_vga_power_on(dev_priv->dev);
871}
872
2be7d540
VS		 873static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
874{
875 spin_lock_irq(&dev_priv->irq_lock);
876 valleyview_disable_display_irqs(dev_priv);
877 spin_unlock_irq(&dev_priv->irq_lock);
878
879 vlv_power_sequencer_reset(dev_priv);
880}
881
882static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
883 struct i915_power_well *power_well)
884{
885 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
886
887 vlv_set_power_well(dev_priv, power_well, true);
888
889 vlv_display_power_well_init(dev_priv);
890}
891
9c065a7d
DV		 892static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
893 struct i915_power_well *power_well)
894{
895 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
896
2be7d540 897 vlv_display_power_well_deinit(dev_priv);
9c065a7d
DV		 898
899 vlv_set_power_well(dev_priv, power_well, false);
9c065a7d
DV		 900}
901
902static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
903 struct i915_power_well *power_well)
904{
905 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
906
5a8fbb7d 907 /* since ref/cri clock was enabled */
9c065a7d
DV		 908 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
909
910 vlv_set_power_well(dev_priv, power_well, true);
911
912 /*
913 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
914 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
915 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
916 * b. The other bits such as sfr settings / modesel may all
917 * be set to 0.
918 *
919 * This should only be done on init and resume from S3 with
920 * both PLLs disabled, or we risk losing DPIO and PLL
921 * synchronization.
922 */
923 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
924}
925
926static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
927 struct i915_power_well *power_well)
928{
929 enum pipe pipe;
930
931 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
932
933 for_each_pipe(dev_priv, pipe)
934 assert_pll_disabled(dev_priv, pipe);
935
936 /* Assert common reset */
937 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
938
939 vlv_set_power_well(dev_priv, power_well, false);
940}
941
30142273
VS		 942#define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
943
944static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
945 int power_well_id)
946{
947 struct i915_power_domains *power_domains = &dev_priv->power_domains;
30142273
VS		 948 int i;
949
fc17f227
ID		 950 for (i = 0; i < power_domains->power_well_count; i++) {
951 struct i915_power_well *power_well;
952
953 power_well = &power_domains->power_wells[i];
30142273
VS		 954 if (power_well->data == power_well_id)
955 return power_well;
956 }
957
958 return NULL;
959}
960
961#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
962
963static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
964{
965 struct i915_power_well *cmn_bc =
966 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
967 struct i915_power_well *cmn_d =
968 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
969 u32 phy_control = dev_priv->chv_phy_control;
970 u32 phy_status = 0;
3be60de9 971 u32 phy_status_mask = 0xffffffff;
30142273
VS		 972 u32 tmp;
973
3be60de9
VS		 974 /*
975 * The BIOS can leave the PHY is some weird state
976 * where it doesn't fully power down some parts.
977 * Disable the asserts until the PHY has been fully
978 * reset (ie. the power well has been disabled at
979 * least once).
980 */
981 if (!dev_priv->chv_phy_assert[DPIO_PHY0])
982 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
983 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
984 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
985 PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
986 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
987 PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
988
989 if (!dev_priv->chv_phy_assert[DPIO_PHY1])
990 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
991 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
992 PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
993
30142273
VS		 994 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
995 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
996
997 /* this assumes override is only used to enable lanes */
998 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
999 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1000
1001 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1002 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1003
1004 /* CL1 is on whenever anything is on in either channel */
1005 if (BITS_SET(phy_control,
1006 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1007 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1008 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1009
1010 /*
1011 * The DPLLB check accounts for the pipe B + port A usage
1012 * with CL2 powered up but all the lanes in the second channel
1013 * powered down.
1014 */
1015 if (BITS_SET(phy_control,
1016 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1017 (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1018 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1019
1020 if (BITS_SET(phy_control,
1021 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1022 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1023 if (BITS_SET(phy_control,
1024 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1025 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1026
1027 if (BITS_SET(phy_control,
1028 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1029 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1030 if (BITS_SET(phy_control,
1031 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1032 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1033 }
1034
1035 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1036 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1037
1038 /* this assumes override is only used to enable lanes */
1039 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1040 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1041
1042 if (BITS_SET(phy_control,
1043 PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1044 phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1045
1046 if (BITS_SET(phy_control,
1047 PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1048 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1049 if (BITS_SET(phy_control,
1050 PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1051 phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1052 }
1053
3be60de9
VS		 1054 phy_status &= phy_status_mask;
1055
30142273
VS		 1056 /*
1057 * The PHY may be busy with some initial calibration and whatnot,
1058 * so the power state can take a while to actually change.
1059 */
3be60de9 1060 if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
30142273
VS		 1061 WARN(phy_status != tmp,
1062 "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1063 tmp, phy_status, dev_priv->chv_phy_control);
1064}
1065
1066#undef BITS_SET
1067
9c065a7d
DV		 1068static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1069 struct i915_power_well *power_well)
1070{
1071 enum dpio_phy phy;
e0fce78f
VS		 1072 enum pipe pipe;
1073 uint32_t tmp;
9c065a7d
DV		 1074
1075 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1076 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1077
e0fce78f
VS		 1078 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1079 pipe = PIPE_A;
9c065a7d 1080 phy = DPIO_PHY0;
e0fce78f
VS		 1081 } else {
1082 pipe = PIPE_C;
9c065a7d 1083 phy = DPIO_PHY1;
e0fce78f 1084 }
5a8fbb7d
VS		 1085
1086 /* since ref/cri clock was enabled */
9c065a7d
DV		 1087 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1088 vlv_set_power_well(dev_priv, power_well, true);
1089
1090 /* Poll for phypwrgood signal */
1091 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1092 DRM_ERROR("Display PHY %d is not power up\n", phy);
1093
e0fce78f
VS		 1094 mutex_lock(&dev_priv->sb_lock);
1095
1096 /* Enable dynamic power down */
1097 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
ee279218
VS		 1098 tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1099 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
e0fce78f
VS		 1100 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1101
1102 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1103 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1104 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1105 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
3e288786
VS		 1106 } else {
1107 /*
1108 * Force the non-existing CL2 off. BXT does this
1109 * too, so maybe it saves some power even though
1110 * CL2 doesn't exist?
1111 */
1112 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1113 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1114 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
e0fce78f
VS		 1115 }
1116
1117 mutex_unlock(&dev_priv->sb_lock);
1118
70722468
VS		 1119 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1120 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
e0fce78f
VS		 1121
1122 DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1123 phy, dev_priv->chv_phy_control);
30142273
VS		 1124
1125 assert_chv_phy_status(dev_priv);
9c065a7d
DV		 1126}
1127
1128static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1129 struct i915_power_well *power_well)
1130{
1131 enum dpio_phy phy;
1132
1133 WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1134 power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1135
1136 if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1137 phy = DPIO_PHY0;
1138 assert_pll_disabled(dev_priv, PIPE_A);
1139 assert_pll_disabled(dev_priv, PIPE_B);
1140 } else {
1141 phy = DPIO_PHY1;
1142 assert_pll_disabled(dev_priv, PIPE_C);
1143 }
1144
70722468
VS		 1145 dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1146 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
9c065a7d
DV		 1147
1148 vlv_set_power_well(dev_priv, power_well, false);
e0fce78f
VS		 1149
1150 DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1151 phy, dev_priv->chv_phy_control);
30142273 1152
3be60de9
VS		 1153 /* PHY is fully reset now, so we can enable the PHY state asserts */
1154 dev_priv->chv_phy_assert[phy] = true;
1155
30142273 1156 assert_chv_phy_status(dev_priv);
e0fce78f
VS		 1157}
1158
6669e39f
VS		 1159static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1160 enum dpio_channel ch, bool override, unsigned int mask)
1161{
1162 enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1163 u32 reg, val, expected, actual;
1164
3be60de9
VS		 1165 /*
1166 * The BIOS can leave the PHY is some weird state
1167 * where it doesn't fully power down some parts.
1168 * Disable the asserts until the PHY has been fully
1169 * reset (ie. the power well has been disabled at
1170 * least once).
1171 */
1172 if (!dev_priv->chv_phy_assert[phy])
1173 return;
1174
6669e39f
VS		 1175 if (ch == DPIO_CH0)
1176 reg = _CHV_CMN_DW0_CH0;
1177 else
1178 reg = _CHV_CMN_DW6_CH1;
1179
1180 mutex_lock(&dev_priv->sb_lock);
1181 val = vlv_dpio_read(dev_priv, pipe, reg);
1182 mutex_unlock(&dev_priv->sb_lock);
1183
1184 /*
1185 * This assumes !override is only used when the port is disabled.
1186 * All lanes should power down even without the override when
1187 * the port is disabled.
1188 */
1189 if (!override || mask == 0xf) {
1190 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1191 /*
1192 * If CH1 common lane is not active anymore
1193 * (eg. for pipe B DPLL) the entire channel will
1194 * shut down, which causes the common lane registers
1195 * to read as 0. That means we can't actually check
1196 * the lane power down status bits, but as the entire
1197 * register reads as 0 it's a good indication that the
1198 * channel is indeed entirely powered down.
1199 */
1200 if (ch == DPIO_CH1 && val == 0)
1201 expected = 0;
1202 } else if (mask != 0x0) {
1203 expected = DPIO_ANYDL_POWERDOWN;
1204 } else {
1205 expected = 0;
1206 }
1207
1208 if (ch == DPIO_CH0)
1209 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1210 else
1211 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1212 actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1213
1214 WARN(actual != expected,
1215 "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1216 !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1217 !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1218 reg, val);
1219}
1220
b0b33846
VS		 1221bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1222 enum dpio_channel ch, bool override)
1223{
1224 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1225 bool was_override;
1226
1227 mutex_lock(&power_domains->lock);
1228
1229 was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1230
1231 if (override == was_override)
1232 goto out;
1233
1234 if (override)
1235 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1236 else
1237 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1238
1239 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1240
1241 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1242 phy, ch, dev_priv->chv_phy_control);
1243
30142273
VS		 1244 assert_chv_phy_status(dev_priv);
1245
b0b33846
VS		 1246out:
1247 mutex_unlock(&power_domains->lock);
1248
1249 return was_override;
1250}
1251
e0fce78f
VS		 1252void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1253 bool override, unsigned int mask)
1254{
1255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1256 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1257 enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1258 enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1259
1260 mutex_lock(&power_domains->lock);
1261
1262 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1263 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1264
1265 if (override)
1266 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1267 else
1268 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1269
1270 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1271
1272 DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1273 phy, ch, mask, dev_priv->chv_phy_control);
1274
30142273
VS		 1275 assert_chv_phy_status(dev_priv);
1276
6669e39f
VS		 1277 assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1278
e0fce78f 1279 mutex_unlock(&power_domains->lock);
9c065a7d
DV		 1280}
1281
1282static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1283 struct i915_power_well *power_well)
1284{
1285 enum pipe pipe = power_well->data;
1286 bool enabled;
1287 u32 state, ctrl;
1288
1289 mutex_lock(&dev_priv->rps.hw_lock);
1290
1291 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1292 /*
1293 * We only ever set the power-on and power-gate states, anything
1294 * else is unexpected.
1295 */
1296 WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1297 enabled = state == DP_SSS_PWR_ON(pipe);
1298
1299 /*
1300 * A transient state at this point would mean some unexpected party
1301 * is poking at the power controls too.
1302 */
1303 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1304 WARN_ON(ctrl << 16 != state);
1305
1306 mutex_unlock(&dev_priv->rps.hw_lock);
1307
1308 return enabled;
1309}
1310
1311static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1312 struct i915_power_well *power_well,
1313 bool enable)
1314{
1315 enum pipe pipe = power_well->data;
1316 u32 state;
1317 u32 ctrl;
1318
1319 state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1320
1321 mutex_lock(&dev_priv->rps.hw_lock);
1322
1323#define COND \
1324 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1325
1326 if (COND)
1327 goto out;
1328
1329 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1330 ctrl &= ~DP_SSC_MASK(pipe);
1331 ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1332 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1333
1334 if (wait_for(COND, 100))
7e35ab88 1335 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
9c065a7d
DV		 1336 state,
1337 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1338
1339#undef COND
1340
1341out:
1342 mutex_unlock(&dev_priv->rps.hw_lock);
1343}
1344
1345static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1346 struct i915_power_well *power_well)
1347{
8fcd5cd8
VS		 1348 WARN_ON_ONCE(power_well->data != PIPE_A);
1349
9c065a7d
DV		 1350 chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1351}
1352
1353static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1354 struct i915_power_well *power_well)
1355{
8fcd5cd8 1356 WARN_ON_ONCE(power_well->data != PIPE_A);
9c065a7d
DV		 1357
1358 chv_set_pipe_power_well(dev_priv, power_well, true);
afd6275d 1359
2be7d540 1360 vlv_display_power_well_init(dev_priv);
9c065a7d
DV		 1361}
1362
1363static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1364 struct i915_power_well *power_well)
1365{
8fcd5cd8
VS		 1366 WARN_ON_ONCE(power_well->data != PIPE_A);
1367
2be7d540 1368 vlv_display_power_well_deinit(dev_priv);
afd6275d 1369
9c065a7d
DV		 1370 chv_set_pipe_power_well(dev_priv, power_well, false);
1371}
1372
e4e7684f
DV		 1373/**
1374 * intel_display_power_get - grab a power domain reference
1375 * @dev_priv: i915 device instance
1376 * @domain: power domain to reference
1377 *
1378 * This function grabs a power domain reference for @domain and ensures that the
1379 * power domain and all its parents are powered up. Therefore users should only
1380 * grab a reference to the innermost power domain they need.
1381 *
1382 * Any power domain reference obtained by this function must have a symmetric
1383 * call to intel_display_power_put() to release the reference again.
1384 */
9c065a7d
DV		 1385void intel_display_power_get(struct drm_i915_private *dev_priv,
1386 enum intel_display_power_domain domain)
1387{
1388 struct i915_power_domains *power_domains;
1389 struct i915_power_well *power_well;
1390 int i;
1391
1392 intel_runtime_pm_get(dev_priv);
1393
1394 power_domains = &dev_priv->power_domains;
1395
1396 mutex_lock(&power_domains->lock);
1397
1398 for_each_power_well(i, power_well, BIT(domain), power_domains) {
e8ca9320
DL		 1399 if (!power_well->count++)
1400 intel_power_well_enable(dev_priv, power_well);
9c065a7d
DV		 1401 }
1402
1403 power_domains->domain_use_count[domain]++;
1404
1405 mutex_unlock(&power_domains->lock);
1406}
1407
e4e7684f
DV		 1408/**
1409 * intel_display_power_put - release a power domain reference
1410 * @dev_priv: i915 device instance
1411 * @domain: power domain to reference
1412 *
1413 * This function drops the power domain reference obtained by
1414 * intel_display_power_get() and might power down the corresponding hardware
1415 * block right away if this is the last reference.
1416 */
9c065a7d
DV		 1417void intel_display_power_put(struct drm_i915_private *dev_priv,
1418 enum intel_display_power_domain domain)
1419{
1420 struct i915_power_domains *power_domains;
1421 struct i915_power_well *power_well;
1422 int i;
1423
1424 power_domains = &dev_priv->power_domains;
1425
1426 mutex_lock(&power_domains->lock);
1427
1428 WARN_ON(!power_domains->domain_use_count[domain]);
1429 power_domains->domain_use_count[domain]--;
1430
1431 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1432 WARN_ON(!power_well->count);
1433
d314cd43 1434 if (!--power_well->count)
dcddab3a 1435 intel_power_well_disable(dev_priv, power_well);
9c065a7d
DV		 1436 }
1437
1438 mutex_unlock(&power_domains->lock);
1439
1440 intel_runtime_pm_put(dev_priv);
1441}
1442
9c065a7d
DV		 1443#define HSW_ALWAYS_ON_POWER_DOMAINS ( \
1444 BIT(POWER_DOMAIN_PIPE_A) | \
1445 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
6331a704
PJ		 1446 BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
1447 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1448 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1449 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
9c065a7d
DV		 1450 BIT(POWER_DOMAIN_PORT_CRT) | \
1451 BIT(POWER_DOMAIN_PLLS) | \
1407121a
S		 1452 BIT(POWER_DOMAIN_AUX_A) | \
1453 BIT(POWER_DOMAIN_AUX_B) | \
1454 BIT(POWER_DOMAIN_AUX_C) | \
1455 BIT(POWER_DOMAIN_AUX_D) | \
f0ab43e6 1456 BIT(POWER_DOMAIN_GMBUS) | \
9c065a7d
DV		 1457 BIT(POWER_DOMAIN_INIT))
1458#define HSW_DISPLAY_POWER_DOMAINS ( \
1459 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
1460 BIT(POWER_DOMAIN_INIT))
1461
1462#define BDW_ALWAYS_ON_POWER_DOMAINS ( \
1463 HSW_ALWAYS_ON_POWER_DOMAINS | \
1464 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1465#define BDW_DISPLAY_POWER_DOMAINS ( \
1466 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
1467 BIT(POWER_DOMAIN_INIT))
1468
1469#define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
1470#define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
1471
1472#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6331a704
PJ		 1473 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1474 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
9c065a7d 1475 BIT(POWER_DOMAIN_PORT_CRT) | \
1407121a
S		 1476 BIT(POWER_DOMAIN_AUX_B) | \
1477 BIT(POWER_DOMAIN_AUX_C) | \
9c065a7d
DV		 1478 BIT(POWER_DOMAIN_INIT))
1479
1480#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6331a704 1481 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1407121a 1482 BIT(POWER_DOMAIN_AUX_B) | \
9c065a7d
DV		 1483 BIT(POWER_DOMAIN_INIT))
1484
1485#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6331a704 1486 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1407121a 1487 BIT(POWER_DOMAIN_AUX_B) | \
9c065a7d
DV		 1488 BIT(POWER_DOMAIN_INIT))
1489
1490#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6331a704 1491 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1407121a 1492 BIT(POWER_DOMAIN_AUX_C) | \
9c065a7d
DV		 1493 BIT(POWER_DOMAIN_INIT))
1494
1495#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6331a704 1496 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1407121a 1497 BIT(POWER_DOMAIN_AUX_C) | \
9c065a7d
DV		 1498 BIT(POWER_DOMAIN_INIT))
1499
9c065a7d 1500#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
6331a704
PJ		 1501 BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
1502 BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
1407121a
S		 1503 BIT(POWER_DOMAIN_AUX_B) | \
1504 BIT(POWER_DOMAIN_AUX_C) | \
9c065a7d
DV		 1505 BIT(POWER_DOMAIN_INIT))
1506
1507#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
6331a704 1508 BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
1407121a 1509 BIT(POWER_DOMAIN_AUX_D) | \
9c065a7d
DV		 1510 BIT(POWER_DOMAIN_INIT))
1511
9c065a7d
DV		 1512static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1513 .sync_hw = i9xx_always_on_power_well_noop,
1514 .enable = i9xx_always_on_power_well_noop,
1515 .disable = i9xx_always_on_power_well_noop,
1516 .is_enabled = i9xx_always_on_power_well_enabled,
1517};
1518
1519static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1520 .sync_hw = chv_pipe_power_well_sync_hw,
1521 .enable = chv_pipe_power_well_enable,
1522 .disable = chv_pipe_power_well_disable,
1523 .is_enabled = chv_pipe_power_well_enabled,
1524};
1525
1526static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1527 .sync_hw = vlv_power_well_sync_hw,
1528 .enable = chv_dpio_cmn_power_well_enable,
1529 .disable = chv_dpio_cmn_power_well_disable,
1530 .is_enabled = vlv_power_well_enabled,
1531};
1532
1533static struct i915_power_well i9xx_always_on_power_well[] = {
1534 {
1535 .name = "always-on",
1536 .always_on = 1,
1537 .domains = POWER_DOMAIN_MASK,
1538 .ops = &i9xx_always_on_power_well_ops,
1539 },
1540};
1541
1542static const struct i915_power_well_ops hsw_power_well_ops = {
1543 .sync_hw = hsw_power_well_sync_hw,
1544 .enable = hsw_power_well_enable,
1545 .disable = hsw_power_well_disable,
1546 .is_enabled = hsw_power_well_enabled,
1547};
1548
94dd5138
S		 1549static const struct i915_power_well_ops skl_power_well_ops = {
1550 .sync_hw = skl_power_well_sync_hw,
1551 .enable = skl_power_well_enable,
1552 .disable = skl_power_well_disable,
1553 .is_enabled = skl_power_well_enabled,
1554};
1555
9f836f90
PJ		 1556static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1557 .sync_hw = gen9_dc_off_power_well_sync_hw,
1558 .enable = gen9_dc_off_power_well_enable,
1559 .disable = gen9_dc_off_power_well_disable,
1560 .is_enabled = gen9_dc_off_power_well_enabled,
1561};
1562
9c065a7d
DV		 1563static struct i915_power_well hsw_power_wells[] = {
1564 {
1565 .name = "always-on",
1566 .always_on = 1,
1567 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1568 .ops = &i9xx_always_on_power_well_ops,
1569 },
1570 {
1571 .name = "display",
1572 .domains = HSW_DISPLAY_POWER_DOMAINS,
1573 .ops = &hsw_power_well_ops,
1574 },
1575};
1576
1577static struct i915_power_well bdw_power_wells[] = {
1578 {
1579 .name = "always-on",
1580 .always_on = 1,
1581 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1582 .ops = &i9xx_always_on_power_well_ops,
1583 },
1584 {
1585 .name = "display",
1586 .domains = BDW_DISPLAY_POWER_DOMAINS,
1587 .ops = &hsw_power_well_ops,
1588 },
1589};
1590
1591static const struct i915_power_well_ops vlv_display_power_well_ops = {
1592 .sync_hw = vlv_power_well_sync_hw,
1593 .enable = vlv_display_power_well_enable,
1594 .disable = vlv_display_power_well_disable,
1595 .is_enabled = vlv_power_well_enabled,
1596};
1597
1598static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1599 .sync_hw = vlv_power_well_sync_hw,
1600 .enable = vlv_dpio_cmn_power_well_enable,
1601 .disable = vlv_dpio_cmn_power_well_disable,
1602 .is_enabled = vlv_power_well_enabled,
1603};
1604
1605static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1606 .sync_hw = vlv_power_well_sync_hw,
1607 .enable = vlv_power_well_enable,
1608 .disable = vlv_power_well_disable,
1609 .is_enabled = vlv_power_well_enabled,
1610};
1611
1612static struct i915_power_well vlv_power_wells[] = {
1613 {
1614 .name = "always-on",
1615 .always_on = 1,
1616 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1617 .ops = &i9xx_always_on_power_well_ops,
56fcfd63 1618 .data = PUNIT_POWER_WELL_ALWAYS_ON,
9c065a7d
DV		 1619 },
1620 {
1621 .name = "display",
1622 .domains = VLV_DISPLAY_POWER_DOMAINS,
1623 .data = PUNIT_POWER_WELL_DISP2D,
1624 .ops = &vlv_display_power_well_ops,
1625 },
1626 {
1627 .name = "dpio-tx-b-01",
1628 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1629 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1630 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1631 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1632 .ops = &vlv_dpio_power_well_ops,
1633 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1634 },
1635 {
1636 .name = "dpio-tx-b-23",
1637 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1638 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1639 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1640 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1641 .ops = &vlv_dpio_power_well_ops,
1642 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1643 },
1644 {
1645 .name = "dpio-tx-c-01",
1646 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1647 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1648 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1649 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1650 .ops = &vlv_dpio_power_well_ops,
1651 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1652 },
1653 {
1654 .name = "dpio-tx-c-23",
1655 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1656 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1657 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1658 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1659 .ops = &vlv_dpio_power_well_ops,
1660 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1661 },
1662 {
1663 .name = "dpio-common",
1664 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1665 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1666 .ops = &vlv_dpio_cmn_power_well_ops,
1667 },
1668};
1669
1670static struct i915_power_well chv_power_wells[] = {
1671 {
1672 .name = "always-on",
1673 .always_on = 1,
1674 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1675 .ops = &i9xx_always_on_power_well_ops,
1676 },
9c065a7d
DV		 1677 {
1678 .name = "display",
baa4e575 1679 /*
fde61e4b
VS		 1680 * Pipe A power well is the new disp2d well. Pipe B and C
1681 * power wells don't actually exist. Pipe A power well is
1682 * required for any pipe to work.
baa4e575 1683 */
fde61e4b 1684 .domains = VLV_DISPLAY_POWER_DOMAINS,
9c065a7d
DV		 1685 .data = PIPE_A,
1686 .ops = &chv_pipe_power_well_ops,
1687 },
9c065a7d
DV		 1688 {
1689 .name = "dpio-common-bc",
71849b67 1690 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
9c065a7d
DV		 1691 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1692 .ops = &chv_dpio_cmn_power_well_ops,
1693 },
1694 {
1695 .name = "dpio-common-d",
71849b67 1696 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
9c065a7d
DV		 1697 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1698 .ops = &chv_dpio_cmn_power_well_ops,
1699 },
9c065a7d
DV		 1700};
1701
5aefb239
SS		 1702bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1703 int power_well_id)
1704{
1705 struct i915_power_well *power_well;
1706 bool ret;
1707
1708 power_well = lookup_power_well(dev_priv, power_well_id);
1709 ret = power_well->ops->is_enabled(dev_priv, power_well);
1710
1711 return ret;
1712}
1713
94dd5138
S		 1714static struct i915_power_well skl_power_wells[] = {
1715 {
1716 .name = "always-on",
1717 .always_on = 1,
1718 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1719 .ops = &i9xx_always_on_power_well_ops,
56fcfd63 1720 .data = SKL_DISP_PW_ALWAYS_ON,
94dd5138
S		 1721 },
1722 {
1723 .name = "power well 1",
4a76f295
ID		 1724 /* Handled by the DMC firmware */
1725 .domains = 0,
94dd5138
S		 1726 .ops = &skl_power_well_ops,
1727 .data = SKL_DISP_PW_1,
1728 },
1729 {
1730 .name = "MISC IO power well",
4a76f295
ID		 1731 /* Handled by the DMC firmware */
1732 .domains = 0,
94dd5138
S		 1733 .ops = &skl_power_well_ops,
1734 .data = SKL_DISP_PW_MISC_IO,
1735 },
9f836f90
PJ		 1736 {
1737 .name = "DC off",
1738 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
1739 .ops = &gen9_dc_off_power_well_ops,
1740 .data = SKL_DISP_PW_DC_OFF,
1741 },
94dd5138
S		 1742 {
1743 .name = "power well 2",
1744 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1745 .ops = &skl_power_well_ops,
1746 .data = SKL_DISP_PW_2,
1747 },
1748 {
1749 .name = "DDI A/E power well",
1750 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1751 .ops = &skl_power_well_ops,
1752 .data = SKL_DISP_PW_DDI_A_E,
1753 },
1754 {
1755 .name = "DDI B power well",
1756 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1757 .ops = &skl_power_well_ops,
1758 .data = SKL_DISP_PW_DDI_B,
1759 },
1760 {
1761 .name = "DDI C power well",
1762 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1763 .ops = &skl_power_well_ops,
1764 .data = SKL_DISP_PW_DDI_C,
1765 },
1766 {
1767 .name = "DDI D power well",
1768 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1769 .ops = &skl_power_well_ops,
1770 .data = SKL_DISP_PW_DDI_D,
1771 },
1772};
1773
2f693e28
DL		 1774void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
1775{
1776 struct i915_power_well *well;
1777
1778 if (!IS_SKYLAKE(dev_priv))
1779 return;
1780
1781 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1782 intel_power_well_enable(dev_priv, well);
1783
1784 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1785 intel_power_well_enable(dev_priv, well);
1786}
1787
1788void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
1789{
1790 struct i915_power_well *well;
1791
1792 if (!IS_SKYLAKE(dev_priv))
1793 return;
1794
1795 well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1796 intel_power_well_disable(dev_priv, well);
1797
1798 well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1799 intel_power_well_disable(dev_priv, well);
1800}
1801
0b4a2a36
S		 1802static struct i915_power_well bxt_power_wells[] = {
1803 {
1804 .name = "always-on",
1805 .always_on = 1,
1806 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1807 .ops = &i9xx_always_on_power_well_ops,
1808 },
1809 {
1810 .name = "power well 1",
1811 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1812 .ops = &skl_power_well_ops,
1813 .data = SKL_DISP_PW_1,
1814 },
9f836f90
PJ		 1815 {
1816 .name = "DC off",
1817 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
1818 .ops = &gen9_dc_off_power_well_ops,
1819 .data = SKL_DISP_PW_DC_OFF,
1820 },
0b4a2a36
S		 1821 {
1822 .name = "power well 2",
1823 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1824 .ops = &skl_power_well_ops,
1825 .data = SKL_DISP_PW_2,
9f836f90 1826 },
0b4a2a36
S		 1827};
1828
9c065a7d
DV		 1829#define set_power_wells(power_domains, __power_wells) ({ \
1830 (power_domains)->power_wells = (__power_wells); \
1831 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
1832})
1833
e4e7684f
DV		 1834/**
1835 * intel_power_domains_init - initializes the power domain structures
1836 * @dev_priv: i915 device instance
1837 *
1838 * Initializes the power domain structures for @dev_priv depending upon the
1839 * supported platform.
1840 */
9c065a7d
DV		 1841int intel_power_domains_init(struct drm_i915_private *dev_priv)
1842{
1843 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1844
f0ab43e6
VS		 1845 BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
1846
9c065a7d
DV		 1847 mutex_init(&power_domains->lock);
1848
1849 /*
1850 * The enabling order will be from lower to higher indexed wells,
1851 * the disabling order is reversed.
1852 */
1853 if (IS_HASWELL(dev_priv->dev)) {
1854 set_power_wells(power_domains, hsw_power_wells);
9c065a7d
DV		 1855 } else if (IS_BROADWELL(dev_priv->dev)) {
1856 set_power_wells(power_domains, bdw_power_wells);
ef11bdb3 1857 } else if (IS_SKYLAKE(dev_priv->dev) || IS_KABYLAKE(dev_priv->dev)) {
94dd5138 1858 set_power_wells(power_domains, skl_power_wells);
0b4a2a36
S		 1859 } else if (IS_BROXTON(dev_priv->dev)) {
1860 set_power_wells(power_domains, bxt_power_wells);
9c065a7d
DV		 1861 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1862 set_power_wells(power_domains, chv_power_wells);
1863 } else if (IS_VALLEYVIEW(dev_priv->dev)) {
1864 set_power_wells(power_domains, vlv_power_wells);
1865 } else {
1866 set_power_wells(power_domains, i9xx_always_on_power_well);
1867 }
1868
1869 return 0;
1870}
1871
e4e7684f
DV		 1872/**
1873 * intel_power_domains_fini - finalizes the power domain structures
1874 * @dev_priv: i915 device instance
1875 *
1876 * Finalizes the power domain structures for @dev_priv depending upon the
1877 * supported platform. This function also disables runtime pm and ensures that
1878 * the device stays powered up so that the driver can be reloaded.
1879 */
f458ebbc 1880void intel_power_domains_fini(struct drm_i915_private *dev_priv)
9c065a7d 1881{
f458ebbc
DV		 1882 /* The i915.ko module is still not prepared to be loaded when
1883 * the power well is not enabled, so just enable it in case
1884 * we're going to unload/reload. */
1885 intel_display_set_init_power(dev_priv, true);
d314cd43
ID		 1886
1887 /* Remove the refcount we took to keep power well support disabled. */
1888 if (!i915.disable_power_well)
1889 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
9c065a7d
DV		 1890}
1891
30eade12 1892static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
9c065a7d
DV		 1893{
1894 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1895 struct i915_power_well *power_well;
1896 int i;
1897
1898 mutex_lock(&power_domains->lock);
1899 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
1900 power_well->ops->sync_hw(dev_priv, power_well);
1901 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
1902 power_well);
1903 }
1904 mutex_unlock(&power_domains->lock);
1905}
1906
73dfc227
ID		 1907static void skl_display_core_init(struct drm_i915_private *dev_priv,
1908 bool resume)
1909{
1910 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1911 uint32_t val;
1912
d26fa1d5
ID		 1913 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
1914
73dfc227
ID		 1915 /* enable PCH reset handshake */
1916 val = I915_READ(HSW_NDE_RSTWRN_OPT);
1917 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
1918
1919 /* enable PG1 and Misc I/O */
1920 mutex_lock(&power_domains->lock);
1921 skl_pw1_misc_io_init(dev_priv);
1922 mutex_unlock(&power_domains->lock);
1923
1924 if (!resume)
1925 return;
1926
1927 skl_init_cdclk(dev_priv);
1928
1929 if (dev_priv->csr.dmc_payload)
1930 intel_csr_load_program(dev_priv);
1931}
1932
1933static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
1934{
1935 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1936
d26fa1d5
ID		 1937 gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
1938
73dfc227
ID		 1939 skl_uninit_cdclk(dev_priv);
1940
1941 /* The spec doesn't call for removing the reset handshake flag */
1942 /* disable PG1 and Misc I/O */
1943 mutex_lock(&power_domains->lock);
1944 skl_pw1_misc_io_fini(dev_priv);
1945 mutex_unlock(&power_domains->lock);
1946}
1947
70722468
VS		 1948static void chv_phy_control_init(struct drm_i915_private *dev_priv)
1949{
1950 struct i915_power_well *cmn_bc =
1951 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1952 struct i915_power_well *cmn_d =
1953 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1954
1955 /*
1956 * DISPLAY_PHY_CONTROL can get corrupted if read. As a
1957 * workaround never ever read DISPLAY_PHY_CONTROL, and
1958 * instead maintain a shadow copy ourselves. Use the actual
e0fce78f
VS		 1959 * power well state and lane status to reconstruct the
1960 * expected initial value.
70722468
VS		 1961 */
1962 dev_priv->chv_phy_control =
bc284542
VS		 1963 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
1964 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
e0fce78f
VS		 1965 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
1966 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
1967 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
1968
1969 /*
1970 * If all lanes are disabled we leave the override disabled
1971 * with all power down bits cleared to match the state we
1972 * would use after disabling the port. Otherwise enable the
1973 * override and set the lane powerdown bits accding to the
1974 * current lane status.
1975 */
1976 if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1977 uint32_t status = I915_READ(DPLL(PIPE_A));
1978 unsigned int mask;
1979
1980 mask = status & DPLL_PORTB_READY_MASK;
1981 if (mask == 0xf)
1982 mask = 0x0;
1983 else
1984 dev_priv->chv_phy_control |=
1985 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
1986
1987 dev_priv->chv_phy_control |=
1988 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
1989
1990 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
1991 if (mask == 0xf)
1992 mask = 0x0;
1993 else
1994 dev_priv->chv_phy_control |=
1995 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
1996
1997 dev_priv->chv_phy_control |=
1998 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
1999
70722468 2000 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
3be60de9
VS		 2001
2002 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2003 } else {
2004 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
e0fce78f
VS		 2005 }
2006
2007 if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2008 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2009 unsigned int mask;
2010
2011 mask = status & DPLL_PORTD_READY_MASK;
2012
2013 if (mask == 0xf)
2014 mask = 0x0;
2015 else
2016 dev_priv->chv_phy_control |=
2017 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2018
2019 dev_priv->chv_phy_control |=
2020 PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2021
70722468 2022 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
3be60de9
VS		 2023
2024 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2025 } else {
2026 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
e0fce78f
VS		 2027 }
2028
2029 I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2030
2031 DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2032 dev_priv->chv_phy_control);
70722468
VS		 2033}
2034
9c065a7d
DV		 2035static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2036{
2037 struct i915_power_well *cmn =
2038 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2039 struct i915_power_well *disp2d =
2040 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2041
9c065a7d 2042 /* If the display might be already active skip this */
5d93a6e5
VS		 2043 if (cmn->ops->is_enabled(dev_priv, cmn) &&
2044 disp2d->ops->is_enabled(dev_priv, disp2d) &&
9c065a7d
DV		 2045 I915_READ(DPIO_CTL) & DPIO_CMNRST)
2046 return;
2047
2048 DRM_DEBUG_KMS("toggling display PHY side reset\n");
2049
2050 /* cmnlane needs DPLL registers */
2051 disp2d->ops->enable(dev_priv, disp2d);
2052
2053 /*
2054 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2055 * Need to assert and de-assert PHY SB reset by gating the
2056 * common lane power, then un-gating it.
2057 * Simply ungating isn't enough to reset the PHY enough to get
2058 * ports and lanes running.
2059 */
2060 cmn->ops->disable(dev_priv, cmn);
2061}
2062
e4e7684f
DV		 2063/**
2064 * intel_power_domains_init_hw - initialize hardware power domain state
2065 * @dev_priv: i915 device instance
2066 *
2067 * This function initializes the hardware power domain state and enables all
2068 * power domains using intel_display_set_init_power().
2069 */
73dfc227 2070void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
9c065a7d
DV		 2071{
2072 struct drm_device *dev = dev_priv->dev;
2073 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2074
2075 power_domains->initializing = true;
2076
73dfc227
ID		 2077 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2078 skl_display_core_init(dev_priv, resume);
2079 } else if (IS_CHERRYVIEW(dev)) {
770effb1 2080 mutex_lock(&power_domains->lock);
70722468 2081 chv_phy_control_init(dev_priv);
770effb1 2082 mutex_unlock(&power_domains->lock);
70722468 2083 } else if (IS_VALLEYVIEW(dev)) {
9c065a7d
DV		 2084 mutex_lock(&power_domains->lock);
2085 vlv_cmnlane_wa(dev_priv);
2086 mutex_unlock(&power_domains->lock);
2087 }
2088
2089 /* For now, we need the power well to be always enabled. */
2090 intel_display_set_init_power(dev_priv, true);
d314cd43
ID		 2091 /* Disable power support if the user asked so. */
2092 if (!i915.disable_power_well)
2093 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
30eade12 2094 intel_power_domains_sync_hw(dev_priv);
9c065a7d
DV		 2095 power_domains->initializing = false;
2096}
2097
73dfc227
ID		 2098/**
2099 * intel_power_domains_suspend - suspend power domain state
2100 * @dev_priv: i915 device instance
2101 *
2102 * This function prepares the hardware power domain state before entering
2103 * system suspend. It must be paired with intel_power_domains_init_hw().
2104 */
2105void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2106{
2107 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2108 skl_display_core_uninit(dev_priv);
d314cd43
ID		 2109
2110 /*
2111 * Even if power well support was disabled we still want to disable
2112 * power wells while we are system suspended.
2113 */
2114 if (!i915.disable_power_well)
2115 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
73dfc227
ID		 2116}
2117
e4e7684f
DV		 2118/**
2119 * intel_runtime_pm_get - grab a runtime pm reference
2120 * @dev_priv: i915 device instance
2121 *
2122 * This function grabs a device-level runtime pm reference (mostly used for GEM
2123 * code to ensure the GTT or GT is on) and ensures that it is powered up.
2124 *
2125 * Any runtime pm reference obtained by this function must have a symmetric
2126 * call to intel_runtime_pm_put() to release the reference again.
2127 */
9c065a7d
DV		 2128void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2129{
2130 struct drm_device *dev = dev_priv->dev;
2131 struct device *device = &dev->pdev->dev;
2132
2133 if (!HAS_RUNTIME_PM(dev))
2134 return;
2135
2136 pm_runtime_get_sync(device);
2137 WARN(dev_priv->pm.suspended, "Device still suspended.\n");
2138}
2139
e4e7684f
DV		 2140/**
2141 * intel_runtime_pm_get_noresume - grab a runtime pm reference
2142 * @dev_priv: i915 device instance
2143 *
2144 * This function grabs a device-level runtime pm reference (mostly used for GEM
2145 * code to ensure the GTT or GT is on).
2146 *
2147 * It will _not_ power up the device but instead only check that it's powered
2148 * on. Therefore it is only valid to call this functions from contexts where
2149 * the device is known to be powered up and where trying to power it up would
2150 * result in hilarity and deadlocks. That pretty much means only the system
2151 * suspend/resume code where this is used to grab runtime pm references for
2152 * delayed setup down in work items.
2153 *
2154 * Any runtime pm reference obtained by this function must have a symmetric
2155 * call to intel_runtime_pm_put() to release the reference again.
2156 */
9c065a7d
DV		 2157void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2158{
2159 struct drm_device *dev = dev_priv->dev;
2160 struct device *device = &dev->pdev->dev;
2161
2162 if (!HAS_RUNTIME_PM(dev))
2163 return;
2164
2165 WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n");
2166 pm_runtime_get_noresume(device);
2167}
2168
e4e7684f
DV		 2169/**
2170 * intel_runtime_pm_put - release a runtime pm reference
2171 * @dev_priv: i915 device instance
2172 *
2173 * This function drops the device-level runtime pm reference obtained by
2174 * intel_runtime_pm_get() and might power down the corresponding
2175 * hardware block right away if this is the last reference.
2176 */
9c065a7d
DV		 2177void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2178{
2179 struct drm_device *dev = dev_priv->dev;
2180 struct device *device = &dev->pdev->dev;
2181
2182 if (!HAS_RUNTIME_PM(dev))
2183 return;
2184
2185 pm_runtime_mark_last_busy(device);
2186 pm_runtime_put_autosuspend(device);
2187}
2188
e4e7684f
DV		 2189/**
2190 * intel_runtime_pm_enable - enable runtime pm
2191 * @dev_priv: i915 device instance
2192 *
2193 * This function enables runtime pm at the end of the driver load sequence.
2194 *
2195 * Note that this function does currently not enable runtime pm for the
2196 * subordinate display power domains. That is only done on the first modeset
2197 * using intel_display_set_init_power().
2198 */
f458ebbc 2199void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
9c065a7d
DV		 2200{
2201 struct drm_device *dev = dev_priv->dev;
2202 struct device *device = &dev->pdev->dev;
2203
2204 if (!HAS_RUNTIME_PM(dev))
2205 return;
2206
9c065a7d
DV		 2207 /*
2208 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
2209 * requirement.
2210 */
2211 if (!intel_enable_rc6(dev)) {
2212 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
2213 return;
2214 }
2215
2216 pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2217 pm_runtime_mark_last_busy(device);
2218 pm_runtime_use_autosuspend(device);
2219
2220 pm_runtime_put_autosuspend(device);
2221}
2222
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