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9c065a7d DV |
1 | /* |
2 | * Copyright © 2012-2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * Daniel Vetter <daniel.vetter@ffwll.ch> | |
26 | * | |
27 | */ | |
28 | ||
29 | #include <linux/pm_runtime.h> | |
30 | #include <linux/vgaarb.h> | |
31 | ||
32 | #include "i915_drv.h" | |
33 | #include "intel_drv.h" | |
9c065a7d | 34 | |
e4e7684f DV |
35 | /** |
36 | * DOC: runtime pm | |
37 | * | |
38 | * The i915 driver supports dynamic enabling and disabling of entire hardware | |
39 | * blocks at runtime. This is especially important on the display side where | |
40 | * software is supposed to control many power gates manually on recent hardware, | |
41 | * since on the GT side a lot of the power management is done by the hardware. | |
42 | * But even there some manual control at the device level is required. | |
43 | * | |
44 | * Since i915 supports a diverse set of platforms with a unified codebase and | |
45 | * hardware engineers just love to shuffle functionality around between power | |
46 | * domains there's a sizeable amount of indirection required. This file provides | |
47 | * generic functions to the driver for grabbing and releasing references for | |
48 | * abstract power domains. It then maps those to the actual power wells | |
49 | * present for a given platform. | |
50 | */ | |
51 | ||
f75a1985 SS |
52 | #define GEN9_ENABLE_DC5(dev) 0 |
53 | #define SKL_ENABLE_DC6(dev) IS_SKYLAKE(dev) | |
dc174300 | 54 | |
9c065a7d DV |
55 | #define for_each_power_well(i, power_well, domain_mask, power_domains) \ |
56 | for (i = 0; \ | |
57 | i < (power_domains)->power_well_count && \ | |
58 | ((power_well) = &(power_domains)->power_wells[i]); \ | |
59 | i++) \ | |
60 | if ((power_well)->domains & (domain_mask)) | |
61 | ||
62 | #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ | |
63 | for (i = (power_domains)->power_well_count - 1; \ | |
64 | i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ | |
65 | i--) \ | |
66 | if ((power_well)->domains & (domain_mask)) | |
67 | ||
5aefb239 SS |
68 | bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, |
69 | int power_well_id); | |
70 | ||
e8ca9320 DL |
71 | static void intel_power_well_enable(struct drm_i915_private *dev_priv, |
72 | struct i915_power_well *power_well) | |
73 | { | |
74 | DRM_DEBUG_KMS("enabling %s\n", power_well->name); | |
75 | power_well->ops->enable(dev_priv, power_well); | |
76 | power_well->hw_enabled = true; | |
77 | } | |
78 | ||
dcddab3a DL |
79 | static void intel_power_well_disable(struct drm_i915_private *dev_priv, |
80 | struct i915_power_well *power_well) | |
81 | { | |
82 | DRM_DEBUG_KMS("disabling %s\n", power_well->name); | |
83 | power_well->hw_enabled = false; | |
84 | power_well->ops->disable(dev_priv, power_well); | |
85 | } | |
86 | ||
e4e7684f | 87 | /* |
9c065a7d DV |
88 | * We should only use the power well if we explicitly asked the hardware to |
89 | * enable it, so check if it's enabled and also check if we've requested it to | |
90 | * be enabled. | |
91 | */ | |
92 | static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, | |
93 | struct i915_power_well *power_well) | |
94 | { | |
95 | return I915_READ(HSW_PWR_WELL_DRIVER) == | |
96 | (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); | |
97 | } | |
98 | ||
e4e7684f DV |
99 | /** |
100 | * __intel_display_power_is_enabled - unlocked check for a power domain | |
101 | * @dev_priv: i915 device instance | |
102 | * @domain: power domain to check | |
103 | * | |
104 | * This is the unlocked version of intel_display_power_is_enabled() and should | |
105 | * only be used from error capture and recovery code where deadlocks are | |
106 | * possible. | |
107 | * | |
108 | * Returns: | |
109 | * True when the power domain is enabled, false otherwise. | |
110 | */ | |
f458ebbc DV |
111 | bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
112 | enum intel_display_power_domain domain) | |
9c065a7d DV |
113 | { |
114 | struct i915_power_domains *power_domains; | |
115 | struct i915_power_well *power_well; | |
116 | bool is_enabled; | |
117 | int i; | |
118 | ||
119 | if (dev_priv->pm.suspended) | |
120 | return false; | |
121 | ||
122 | power_domains = &dev_priv->power_domains; | |
123 | ||
124 | is_enabled = true; | |
125 | ||
126 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { | |
127 | if (power_well->always_on) | |
128 | continue; | |
129 | ||
130 | if (!power_well->hw_enabled) { | |
131 | is_enabled = false; | |
132 | break; | |
133 | } | |
134 | } | |
135 | ||
136 | return is_enabled; | |
137 | } | |
138 | ||
e4e7684f | 139 | /** |
f61ccae3 | 140 | * intel_display_power_is_enabled - check for a power domain |
e4e7684f DV |
141 | * @dev_priv: i915 device instance |
142 | * @domain: power domain to check | |
143 | * | |
144 | * This function can be used to check the hw power domain state. It is mostly | |
145 | * used in hardware state readout functions. Everywhere else code should rely | |
146 | * upon explicit power domain reference counting to ensure that the hardware | |
147 | * block is powered up before accessing it. | |
148 | * | |
149 | * Callers must hold the relevant modesetting locks to ensure that concurrent | |
150 | * threads can't disable the power well while the caller tries to read a few | |
151 | * registers. | |
152 | * | |
153 | * Returns: | |
154 | * True when the power domain is enabled, false otherwise. | |
155 | */ | |
f458ebbc DV |
156 | bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, |
157 | enum intel_display_power_domain domain) | |
9c065a7d DV |
158 | { |
159 | struct i915_power_domains *power_domains; | |
160 | bool ret; | |
161 | ||
162 | power_domains = &dev_priv->power_domains; | |
163 | ||
164 | mutex_lock(&power_domains->lock); | |
f458ebbc | 165 | ret = __intel_display_power_is_enabled(dev_priv, domain); |
9c065a7d DV |
166 | mutex_unlock(&power_domains->lock); |
167 | ||
168 | return ret; | |
169 | } | |
170 | ||
e4e7684f DV |
171 | /** |
172 | * intel_display_set_init_power - set the initial power domain state | |
173 | * @dev_priv: i915 device instance | |
174 | * @enable: whether to enable or disable the initial power domain state | |
175 | * | |
176 | * For simplicity our driver load/unload and system suspend/resume code assumes | |
177 | * that all power domains are always enabled. This functions controls the state | |
178 | * of this little hack. While the initial power domain state is enabled runtime | |
179 | * pm is effectively disabled. | |
180 | */ | |
d9bc89d9 DV |
181 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, |
182 | bool enable) | |
183 | { | |
184 | if (dev_priv->power_domains.init_power_on == enable) | |
185 | return; | |
186 | ||
187 | if (enable) | |
188 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
189 | else | |
190 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
191 | ||
192 | dev_priv->power_domains.init_power_on = enable; | |
193 | } | |
194 | ||
9c065a7d DV |
195 | /* |
196 | * Starting with Haswell, we have a "Power Down Well" that can be turned off | |
197 | * when not needed anymore. We have 4 registers that can request the power well | |
198 | * to be enabled, and it will only be disabled if none of the registers is | |
199 | * requesting it to be enabled. | |
200 | */ | |
201 | static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) | |
202 | { | |
203 | struct drm_device *dev = dev_priv->dev; | |
204 | ||
205 | /* | |
206 | * After we re-enable the power well, if we touch VGA register 0x3d5 | |
207 | * we'll get unclaimed register interrupts. This stops after we write | |
208 | * anything to the VGA MSR register. The vgacon module uses this | |
209 | * register all the time, so if we unbind our driver and, as a | |
210 | * consequence, bind vgacon, we'll get stuck in an infinite loop at | |
211 | * console_unlock(). So make here we touch the VGA MSR register, making | |
212 | * sure vgacon can keep working normally without triggering interrupts | |
213 | * and error messages. | |
214 | */ | |
215 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
216 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); | |
217 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
218 | ||
25400392 | 219 | if (IS_BROADWELL(dev)) |
4c6c03be DL |
220 | gen8_irq_power_well_post_enable(dev_priv, |
221 | 1 << PIPE_C | 1 << PIPE_B); | |
9c065a7d DV |
222 | } |
223 | ||
d14c0343 DL |
224 | static void skl_power_well_post_enable(struct drm_i915_private *dev_priv, |
225 | struct i915_power_well *power_well) | |
226 | { | |
227 | struct drm_device *dev = dev_priv->dev; | |
228 | ||
229 | /* | |
230 | * After we re-enable the power well, if we touch VGA register 0x3d5 | |
231 | * we'll get unclaimed register interrupts. This stops after we write | |
232 | * anything to the VGA MSR register. The vgacon module uses this | |
233 | * register all the time, so if we unbind our driver and, as a | |
234 | * consequence, bind vgacon, we'll get stuck in an infinite loop at | |
235 | * console_unlock(). So make here we touch the VGA MSR register, making | |
236 | * sure vgacon can keep working normally without triggering interrupts | |
237 | * and error messages. | |
238 | */ | |
239 | if (power_well->data == SKL_DISP_PW_2) { | |
240 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); | |
241 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); | |
242 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
243 | ||
244 | gen8_irq_power_well_post_enable(dev_priv, | |
245 | 1 << PIPE_C | 1 << PIPE_B); | |
246 | } | |
247 | ||
1d2b9526 DL |
248 | if (power_well->data == SKL_DISP_PW_1) { |
249 | intel_prepare_ddi(dev); | |
d14c0343 | 250 | gen8_irq_power_well_post_enable(dev_priv, 1 << PIPE_A); |
1d2b9526 | 251 | } |
d14c0343 DL |
252 | } |
253 | ||
9c065a7d DV |
254 | static void hsw_set_power_well(struct drm_i915_private *dev_priv, |
255 | struct i915_power_well *power_well, bool enable) | |
256 | { | |
257 | bool is_enabled, enable_requested; | |
258 | uint32_t tmp; | |
259 | ||
260 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); | |
261 | is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; | |
262 | enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; | |
263 | ||
264 | if (enable) { | |
265 | if (!enable_requested) | |
266 | I915_WRITE(HSW_PWR_WELL_DRIVER, | |
267 | HSW_PWR_WELL_ENABLE_REQUEST); | |
268 | ||
269 | if (!is_enabled) { | |
270 | DRM_DEBUG_KMS("Enabling power well\n"); | |
271 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & | |
272 | HSW_PWR_WELL_STATE_ENABLED), 20)) | |
273 | DRM_ERROR("Timeout enabling power well\n"); | |
6d729bff | 274 | hsw_power_well_post_enable(dev_priv); |
9c065a7d DV |
275 | } |
276 | ||
9c065a7d DV |
277 | } else { |
278 | if (enable_requested) { | |
279 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); | |
280 | POSTING_READ(HSW_PWR_WELL_DRIVER); | |
281 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); | |
282 | } | |
283 | } | |
284 | } | |
285 | ||
94dd5138 S |
286 | #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ |
287 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ | |
288 | BIT(POWER_DOMAIN_PIPE_B) | \ | |
289 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ | |
290 | BIT(POWER_DOMAIN_PIPE_C) | \ | |
291 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ | |
292 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ | |
293 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ | |
294 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
295 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
296 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
297 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
298 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
299 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
300 | BIT(POWER_DOMAIN_AUX_B) | \ | |
301 | BIT(POWER_DOMAIN_AUX_C) | \ | |
302 | BIT(POWER_DOMAIN_AUX_D) | \ | |
303 | BIT(POWER_DOMAIN_AUDIO) | \ | |
304 | BIT(POWER_DOMAIN_VGA) | \ | |
305 | BIT(POWER_DOMAIN_INIT)) | |
306 | #define SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ | |
307 | SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ | |
308 | BIT(POWER_DOMAIN_PLLS) | \ | |
309 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
310 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ | |
311 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ | |
312 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ | |
313 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ | |
314 | BIT(POWER_DOMAIN_AUX_A) | \ | |
315 | BIT(POWER_DOMAIN_INIT)) | |
316 | #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \ | |
317 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ | |
318 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ | |
319 | BIT(POWER_DOMAIN_INIT)) | |
320 | #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \ | |
321 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
322 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
323 | BIT(POWER_DOMAIN_INIT)) | |
324 | #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \ | |
325 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
326 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
327 | BIT(POWER_DOMAIN_INIT)) | |
328 | #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \ | |
329 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
330 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
331 | BIT(POWER_DOMAIN_INIT)) | |
332 | #define SKL_DISPLAY_MISC_IO_POWER_DOMAINS ( \ | |
aeaa2122 | 333 | SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ |
6222709d | 334 | BIT(POWER_DOMAIN_PLLS) | \ |
aeaa2122 | 335 | BIT(POWER_DOMAIN_INIT)) |
94dd5138 S |
336 | #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ |
337 | (POWER_DOMAIN_MASK & ~(SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ | |
338 | SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ | |
339 | SKL_DISPLAY_DDI_A_E_POWER_DOMAINS | \ | |
340 | SKL_DISPLAY_DDI_B_POWER_DOMAINS | \ | |
341 | SKL_DISPLAY_DDI_C_POWER_DOMAINS | \ | |
342 | SKL_DISPLAY_DDI_D_POWER_DOMAINS | \ | |
343 | SKL_DISPLAY_MISC_IO_POWER_DOMAINS)) | \ | |
344 | BIT(POWER_DOMAIN_INIT)) | |
345 | ||
0b4a2a36 S |
346 | #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \ |
347 | BIT(POWER_DOMAIN_TRANSCODER_A) | \ | |
348 | BIT(POWER_DOMAIN_PIPE_B) | \ | |
349 | BIT(POWER_DOMAIN_TRANSCODER_B) | \ | |
350 | BIT(POWER_DOMAIN_PIPE_C) | \ | |
351 | BIT(POWER_DOMAIN_TRANSCODER_C) | \ | |
352 | BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \ | |
353 | BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \ | |
354 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
355 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
356 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
357 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
358 | BIT(POWER_DOMAIN_AUX_B) | \ | |
359 | BIT(POWER_DOMAIN_AUX_C) | \ | |
360 | BIT(POWER_DOMAIN_AUDIO) | \ | |
361 | BIT(POWER_DOMAIN_VGA) | \ | |
362 | BIT(POWER_DOMAIN_INIT)) | |
363 | #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS ( \ | |
364 | BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \ | |
365 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
366 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ | |
367 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \ | |
368 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ | |
369 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ | |
370 | BIT(POWER_DOMAIN_AUX_A) | \ | |
371 | BIT(POWER_DOMAIN_PLLS) | \ | |
372 | BIT(POWER_DOMAIN_INIT)) | |
373 | #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \ | |
374 | (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS | \ | |
375 | BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) | \ | |
376 | BIT(POWER_DOMAIN_INIT)) | |
377 | ||
664326f8 SK |
378 | static void assert_can_enable_dc9(struct drm_i915_private *dev_priv) |
379 | { | |
380 | struct drm_device *dev = dev_priv->dev; | |
381 | ||
382 | WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n"); | |
383 | WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), | |
384 | "DC9 already programmed to be enabled.\n"); | |
385 | WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, | |
386 | "DC5 still not disabled to enable DC9.\n"); | |
387 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n"); | |
388 | WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); | |
389 | ||
390 | /* | |
391 | * TODO: check for the following to verify the conditions to enter DC9 | |
392 | * state are satisfied: | |
393 | * 1] Check relevant display engine registers to verify if mode set | |
394 | * disable sequence was followed. | |
395 | * 2] Check if display uninitialize sequence is initialized. | |
396 | */ | |
397 | } | |
398 | ||
399 | static void assert_can_disable_dc9(struct drm_i915_private *dev_priv) | |
400 | { | |
401 | WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n"); | |
402 | WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), | |
403 | "DC9 already programmed to be disabled.\n"); | |
404 | WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, | |
405 | "DC5 still not disabled.\n"); | |
406 | ||
407 | /* | |
408 | * TODO: check for the following to verify DC9 state was indeed | |
409 | * entered before programming to disable it: | |
410 | * 1] Check relevant display engine registers to verify if mode | |
411 | * set disable sequence was followed. | |
412 | * 2] Check if display uninitialize sequence is initialized. | |
413 | */ | |
414 | } | |
415 | ||
416 | void bxt_enable_dc9(struct drm_i915_private *dev_priv) | |
417 | { | |
418 | uint32_t val; | |
419 | ||
420 | assert_can_enable_dc9(dev_priv); | |
421 | ||
422 | DRM_DEBUG_KMS("Enabling DC9\n"); | |
423 | ||
424 | val = I915_READ(DC_STATE_EN); | |
425 | val |= DC_STATE_EN_DC9; | |
426 | I915_WRITE(DC_STATE_EN, val); | |
427 | POSTING_READ(DC_STATE_EN); | |
428 | } | |
429 | ||
430 | void bxt_disable_dc9(struct drm_i915_private *dev_priv) | |
431 | { | |
432 | uint32_t val; | |
433 | ||
434 | assert_can_disable_dc9(dev_priv); | |
435 | ||
436 | DRM_DEBUG_KMS("Disabling DC9\n"); | |
437 | ||
438 | val = I915_READ(DC_STATE_EN); | |
439 | val &= ~DC_STATE_EN_DC9; | |
440 | I915_WRITE(DC_STATE_EN, val); | |
441 | POSTING_READ(DC_STATE_EN); | |
442 | } | |
443 | ||
6b457d31 SK |
444 | static void gen9_set_dc_state_debugmask_memory_up( |
445 | struct drm_i915_private *dev_priv) | |
446 | { | |
447 | uint32_t val; | |
448 | ||
449 | /* The below bit doesn't need to be cleared ever afterwards */ | |
450 | val = I915_READ(DC_STATE_DEBUG); | |
451 | if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) { | |
452 | val |= DC_STATE_DEBUG_MASK_MEMORY_UP; | |
453 | I915_WRITE(DC_STATE_DEBUG, val); | |
454 | POSTING_READ(DC_STATE_DEBUG); | |
455 | } | |
456 | } | |
457 | ||
5aefb239 | 458 | static void assert_can_enable_dc5(struct drm_i915_private *dev_priv) |
dc174300 | 459 | { |
6b457d31 | 460 | struct drm_device *dev = dev_priv->dev; |
5aefb239 SS |
461 | bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, |
462 | SKL_DISP_PW_2); | |
463 | ||
464 | WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC5.\n"); | |
465 | WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); | |
466 | WARN(pg2_enabled, "PG2 not disabled to enable DC5.\n"); | |
467 | ||
468 | WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5), | |
469 | "DC5 already programmed to be enabled.\n"); | |
470 | WARN(dev_priv->pm.suspended, | |
471 | "DC5 cannot be enabled, if platform is runtime-suspended.\n"); | |
472 | ||
473 | assert_csr_loaded(dev_priv); | |
474 | } | |
475 | ||
476 | static void assert_can_disable_dc5(struct drm_i915_private *dev_priv) | |
477 | { | |
478 | bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv, | |
479 | SKL_DISP_PW_2); | |
93c7cb6c SS |
480 | /* |
481 | * During initialization, the firmware may not be loaded yet. | |
482 | * We still want to make sure that the DC enabling flag is cleared. | |
483 | */ | |
484 | if (dev_priv->power_domains.initializing) | |
485 | return; | |
5aefb239 SS |
486 | |
487 | WARN(!pg2_enabled, "PG2 not enabled to disable DC5.\n"); | |
488 | WARN(dev_priv->pm.suspended, | |
489 | "Disabling of DC5 while platform is runtime-suspended should never happen.\n"); | |
490 | } | |
491 | ||
492 | static void gen9_enable_dc5(struct drm_i915_private *dev_priv) | |
493 | { | |
6b457d31 SK |
494 | uint32_t val; |
495 | ||
5aefb239 | 496 | assert_can_enable_dc5(dev_priv); |
6b457d31 SK |
497 | |
498 | DRM_DEBUG_KMS("Enabling DC5\n"); | |
499 | ||
500 | gen9_set_dc_state_debugmask_memory_up(dev_priv); | |
501 | ||
502 | val = I915_READ(DC_STATE_EN); | |
503 | val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK; | |
504 | val |= DC_STATE_EN_UPTO_DC5; | |
505 | I915_WRITE(DC_STATE_EN, val); | |
506 | POSTING_READ(DC_STATE_EN); | |
dc174300 SS |
507 | } |
508 | ||
509 | static void gen9_disable_dc5(struct drm_i915_private *dev_priv) | |
510 | { | |
6b457d31 SK |
511 | uint32_t val; |
512 | ||
5aefb239 | 513 | assert_can_disable_dc5(dev_priv); |
6b457d31 SK |
514 | |
515 | DRM_DEBUG_KMS("Disabling DC5\n"); | |
516 | ||
517 | val = I915_READ(DC_STATE_EN); | |
518 | val &= ~DC_STATE_EN_UPTO_DC5; | |
519 | I915_WRITE(DC_STATE_EN, val); | |
520 | POSTING_READ(DC_STATE_EN); | |
dc174300 SS |
521 | } |
522 | ||
93c7cb6c | 523 | static void assert_can_enable_dc6(struct drm_i915_private *dev_priv) |
f75a1985 | 524 | { |
74b4f371 | 525 | struct drm_device *dev = dev_priv->dev; |
93c7cb6c SS |
526 | |
527 | WARN(!IS_SKYLAKE(dev), "Platform doesn't support DC6.\n"); | |
528 | WARN(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n"); | |
529 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
530 | "Backlight is not disabled.\n"); | |
531 | WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), | |
532 | "DC6 already programmed to be enabled.\n"); | |
533 | ||
534 | assert_csr_loaded(dev_priv); | |
535 | } | |
536 | ||
537 | static void assert_can_disable_dc6(struct drm_i915_private *dev_priv) | |
538 | { | |
539 | /* | |
540 | * During initialization, the firmware may not be loaded yet. | |
541 | * We still want to make sure that the DC enabling flag is cleared. | |
542 | */ | |
543 | if (dev_priv->power_domains.initializing) | |
544 | return; | |
545 | ||
546 | assert_csr_loaded(dev_priv); | |
547 | WARN(!(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6), | |
548 | "DC6 already programmed to be disabled.\n"); | |
549 | } | |
550 | ||
551 | static void skl_enable_dc6(struct drm_i915_private *dev_priv) | |
552 | { | |
74b4f371 SK |
553 | uint32_t val; |
554 | ||
93c7cb6c | 555 | assert_can_enable_dc6(dev_priv); |
74b4f371 SK |
556 | |
557 | DRM_DEBUG_KMS("Enabling DC6\n"); | |
558 | ||
559 | gen9_set_dc_state_debugmask_memory_up(dev_priv); | |
560 | ||
561 | val = I915_READ(DC_STATE_EN); | |
562 | val &= ~DC_STATE_EN_UPTO_DC5_DC6_MASK; | |
563 | val |= DC_STATE_EN_UPTO_DC6; | |
564 | I915_WRITE(DC_STATE_EN, val); | |
565 | POSTING_READ(DC_STATE_EN); | |
f75a1985 SS |
566 | } |
567 | ||
568 | static void skl_disable_dc6(struct drm_i915_private *dev_priv) | |
569 | { | |
74b4f371 SK |
570 | uint32_t val; |
571 | ||
93c7cb6c | 572 | assert_can_disable_dc6(dev_priv); |
74b4f371 SK |
573 | |
574 | DRM_DEBUG_KMS("Disabling DC6\n"); | |
575 | ||
576 | val = I915_READ(DC_STATE_EN); | |
577 | val &= ~DC_STATE_EN_UPTO_DC6; | |
578 | I915_WRITE(DC_STATE_EN, val); | |
579 | POSTING_READ(DC_STATE_EN); | |
f75a1985 SS |
580 | } |
581 | ||
94dd5138 S |
582 | static void skl_set_power_well(struct drm_i915_private *dev_priv, |
583 | struct i915_power_well *power_well, bool enable) | |
584 | { | |
dc174300 | 585 | struct drm_device *dev = dev_priv->dev; |
94dd5138 S |
586 | uint32_t tmp, fuse_status; |
587 | uint32_t req_mask, state_mask; | |
2a51835f | 588 | bool is_enabled, enable_requested, check_fuse_status = false; |
94dd5138 S |
589 | |
590 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); | |
591 | fuse_status = I915_READ(SKL_FUSE_STATUS); | |
592 | ||
593 | switch (power_well->data) { | |
594 | case SKL_DISP_PW_1: | |
595 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & | |
596 | SKL_FUSE_PG0_DIST_STATUS), 1)) { | |
597 | DRM_ERROR("PG0 not enabled\n"); | |
598 | return; | |
599 | } | |
600 | break; | |
601 | case SKL_DISP_PW_2: | |
602 | if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) { | |
603 | DRM_ERROR("PG1 in disabled state\n"); | |
604 | return; | |
605 | } | |
606 | break; | |
607 | case SKL_DISP_PW_DDI_A_E: | |
608 | case SKL_DISP_PW_DDI_B: | |
609 | case SKL_DISP_PW_DDI_C: | |
610 | case SKL_DISP_PW_DDI_D: | |
611 | case SKL_DISP_PW_MISC_IO: | |
612 | break; | |
613 | default: | |
614 | WARN(1, "Unknown power well %lu\n", power_well->data); | |
615 | return; | |
616 | } | |
617 | ||
618 | req_mask = SKL_POWER_WELL_REQ(power_well->data); | |
2a51835f | 619 | enable_requested = tmp & req_mask; |
94dd5138 | 620 | state_mask = SKL_POWER_WELL_STATE(power_well->data); |
2a51835f | 621 | is_enabled = tmp & state_mask; |
94dd5138 S |
622 | |
623 | if (enable) { | |
2a51835f | 624 | if (!enable_requested) { |
dc174300 SS |
625 | WARN((tmp & state_mask) && |
626 | !I915_READ(HSW_PWR_WELL_BIOS), | |
627 | "Invalid for power well status to be enabled, unless done by the BIOS, \ | |
628 | when request is to disable!\n"); | |
f75a1985 SS |
629 | if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) && |
630 | power_well->data == SKL_DISP_PW_2) { | |
631 | if (SKL_ENABLE_DC6(dev)) { | |
632 | skl_disable_dc6(dev_priv); | |
633 | /* | |
634 | * DDI buffer programming unnecessary during driver-load/resume | |
635 | * as it's already done during modeset initialization then. | |
636 | * It's also invalid here as encoder list is still uninitialized. | |
637 | */ | |
638 | if (!dev_priv->power_domains.initializing) | |
639 | intel_prepare_ddi(dev); | |
640 | } else { | |
641 | gen9_disable_dc5(dev_priv); | |
642 | } | |
643 | } | |
94dd5138 | 644 | I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask); |
94dd5138 S |
645 | } |
646 | ||
2a51835f | 647 | if (!is_enabled) { |
510e6fdd | 648 | DRM_DEBUG_KMS("Enabling %s\n", power_well->name); |
94dd5138 S |
649 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & |
650 | state_mask), 1)) | |
651 | DRM_ERROR("%s enable timeout\n", | |
652 | power_well->name); | |
653 | check_fuse_status = true; | |
654 | } | |
655 | } else { | |
2a51835f | 656 | if (enable_requested) { |
94dd5138 S |
657 | I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask); |
658 | POSTING_READ(HSW_PWR_WELL_DRIVER); | |
659 | DRM_DEBUG_KMS("Disabling %s\n", power_well->name); | |
dc174300 | 660 | |
f75a1985 | 661 | if ((GEN9_ENABLE_DC5(dev) || SKL_ENABLE_DC6(dev)) && |
dc174300 SS |
662 | power_well->data == SKL_DISP_PW_2) { |
663 | enum csr_state state; | |
f75a1985 SS |
664 | /* TODO: wait for a completion event or |
665 | * similar here instead of busy | |
666 | * waiting using wait_for function. | |
667 | */ | |
dc174300 SS |
668 | wait_for((state = intel_csr_load_status_get(dev_priv)) != |
669 | FW_UNINITIALIZED, 1000); | |
670 | if (state != FW_LOADED) | |
671 | DRM_ERROR("CSR firmware not ready (%d)\n", | |
672 | state); | |
673 | else | |
f75a1985 SS |
674 | if (SKL_ENABLE_DC6(dev)) |
675 | skl_enable_dc6(dev_priv); | |
676 | else | |
677 | gen9_enable_dc5(dev_priv); | |
dc174300 | 678 | } |
94dd5138 S |
679 | } |
680 | } | |
681 | ||
682 | if (check_fuse_status) { | |
683 | if (power_well->data == SKL_DISP_PW_1) { | |
684 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & | |
685 | SKL_FUSE_PG1_DIST_STATUS), 1)) | |
686 | DRM_ERROR("PG1 distributing status timeout\n"); | |
687 | } else if (power_well->data == SKL_DISP_PW_2) { | |
688 | if (wait_for((I915_READ(SKL_FUSE_STATUS) & | |
689 | SKL_FUSE_PG2_DIST_STATUS), 1)) | |
690 | DRM_ERROR("PG2 distributing status timeout\n"); | |
691 | } | |
692 | } | |
d14c0343 DL |
693 | |
694 | if (enable && !is_enabled) | |
695 | skl_power_well_post_enable(dev_priv, power_well); | |
94dd5138 S |
696 | } |
697 | ||
9c065a7d DV |
698 | static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, |
699 | struct i915_power_well *power_well) | |
700 | { | |
701 | hsw_set_power_well(dev_priv, power_well, power_well->count > 0); | |
702 | ||
703 | /* | |
704 | * We're taking over the BIOS, so clear any requests made by it since | |
705 | * the driver is in charge now. | |
706 | */ | |
707 | if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) | |
708 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); | |
709 | } | |
710 | ||
711 | static void hsw_power_well_enable(struct drm_i915_private *dev_priv, | |
712 | struct i915_power_well *power_well) | |
713 | { | |
714 | hsw_set_power_well(dev_priv, power_well, true); | |
715 | } | |
716 | ||
717 | static void hsw_power_well_disable(struct drm_i915_private *dev_priv, | |
718 | struct i915_power_well *power_well) | |
719 | { | |
720 | hsw_set_power_well(dev_priv, power_well, false); | |
721 | } | |
722 | ||
94dd5138 S |
723 | static bool skl_power_well_enabled(struct drm_i915_private *dev_priv, |
724 | struct i915_power_well *power_well) | |
725 | { | |
726 | uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) | | |
727 | SKL_POWER_WELL_STATE(power_well->data); | |
728 | ||
729 | return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask; | |
730 | } | |
731 | ||
732 | static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
733 | struct i915_power_well *power_well) | |
734 | { | |
735 | skl_set_power_well(dev_priv, power_well, power_well->count > 0); | |
736 | ||
737 | /* Clear any request made by BIOS as driver is taking over */ | |
738 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); | |
739 | } | |
740 | ||
741 | static void skl_power_well_enable(struct drm_i915_private *dev_priv, | |
742 | struct i915_power_well *power_well) | |
743 | { | |
744 | skl_set_power_well(dev_priv, power_well, true); | |
745 | } | |
746 | ||
747 | static void skl_power_well_disable(struct drm_i915_private *dev_priv, | |
748 | struct i915_power_well *power_well) | |
749 | { | |
750 | skl_set_power_well(dev_priv, power_well, false); | |
751 | } | |
752 | ||
9c065a7d DV |
753 | static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, |
754 | struct i915_power_well *power_well) | |
755 | { | |
756 | } | |
757 | ||
758 | static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, | |
759 | struct i915_power_well *power_well) | |
760 | { | |
761 | return true; | |
762 | } | |
763 | ||
764 | static void vlv_set_power_well(struct drm_i915_private *dev_priv, | |
765 | struct i915_power_well *power_well, bool enable) | |
766 | { | |
767 | enum punit_power_well power_well_id = power_well->data; | |
768 | u32 mask; | |
769 | u32 state; | |
770 | u32 ctrl; | |
771 | ||
772 | mask = PUNIT_PWRGT_MASK(power_well_id); | |
773 | state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : | |
774 | PUNIT_PWRGT_PWR_GATE(power_well_id); | |
775 | ||
776 | mutex_lock(&dev_priv->rps.hw_lock); | |
777 | ||
778 | #define COND \ | |
779 | ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) | |
780 | ||
781 | if (COND) | |
782 | goto out; | |
783 | ||
784 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); | |
785 | ctrl &= ~mask; | |
786 | ctrl |= state; | |
787 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); | |
788 | ||
789 | if (wait_for(COND, 100)) | |
7e35ab88 | 790 | DRM_ERROR("timeout setting power well state %08x (%08x)\n", |
9c065a7d DV |
791 | state, |
792 | vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); | |
793 | ||
794 | #undef COND | |
795 | ||
796 | out: | |
797 | mutex_unlock(&dev_priv->rps.hw_lock); | |
798 | } | |
799 | ||
800 | static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
801 | struct i915_power_well *power_well) | |
802 | { | |
803 | vlv_set_power_well(dev_priv, power_well, power_well->count > 0); | |
804 | } | |
805 | ||
806 | static void vlv_power_well_enable(struct drm_i915_private *dev_priv, | |
807 | struct i915_power_well *power_well) | |
808 | { | |
809 | vlv_set_power_well(dev_priv, power_well, true); | |
810 | } | |
811 | ||
812 | static void vlv_power_well_disable(struct drm_i915_private *dev_priv, | |
813 | struct i915_power_well *power_well) | |
814 | { | |
815 | vlv_set_power_well(dev_priv, power_well, false); | |
816 | } | |
817 | ||
818 | static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, | |
819 | struct i915_power_well *power_well) | |
820 | { | |
821 | int power_well_id = power_well->data; | |
822 | bool enabled = false; | |
823 | u32 mask; | |
824 | u32 state; | |
825 | u32 ctrl; | |
826 | ||
827 | mask = PUNIT_PWRGT_MASK(power_well_id); | |
828 | ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); | |
829 | ||
830 | mutex_lock(&dev_priv->rps.hw_lock); | |
831 | ||
832 | state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; | |
833 | /* | |
834 | * We only ever set the power-on and power-gate states, anything | |
835 | * else is unexpected. | |
836 | */ | |
837 | WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && | |
838 | state != PUNIT_PWRGT_PWR_GATE(power_well_id)); | |
839 | if (state == ctrl) | |
840 | enabled = true; | |
841 | ||
842 | /* | |
843 | * A transient state at this point would mean some unexpected party | |
844 | * is poking at the power controls too. | |
845 | */ | |
846 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; | |
847 | WARN_ON(ctrl != state); | |
848 | ||
849 | mutex_unlock(&dev_priv->rps.hw_lock); | |
850 | ||
851 | return enabled; | |
852 | } | |
853 | ||
2be7d540 | 854 | static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) |
9c065a7d | 855 | { |
5a8fbb7d VS |
856 | enum pipe pipe; |
857 | ||
858 | /* | |
859 | * Enable the CRI clock source so we can get at the | |
860 | * display and the reference clock for VGA | |
861 | * hotplug / manual detection. Supposedly DSI also | |
862 | * needs the ref clock up and running. | |
863 | * | |
864 | * CHV DPLL B/C have some issues if VGA mode is enabled. | |
865 | */ | |
866 | for_each_pipe(dev_priv->dev, pipe) { | |
867 | u32 val = I915_READ(DPLL(pipe)); | |
868 | ||
869 | val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
870 | if (pipe != PIPE_A) | |
871 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
872 | ||
873 | I915_WRITE(DPLL(pipe), val); | |
874 | } | |
9c065a7d DV |
875 | |
876 | spin_lock_irq(&dev_priv->irq_lock); | |
877 | valleyview_enable_display_irqs(dev_priv); | |
878 | spin_unlock_irq(&dev_priv->irq_lock); | |
879 | ||
880 | /* | |
881 | * During driver initialization/resume we can avoid restoring the | |
882 | * part of the HW/SW state that will be inited anyway explicitly. | |
883 | */ | |
884 | if (dev_priv->power_domains.initializing) | |
885 | return; | |
886 | ||
b963291c | 887 | intel_hpd_init(dev_priv); |
9c065a7d DV |
888 | |
889 | i915_redisable_vga_power_on(dev_priv->dev); | |
890 | } | |
891 | ||
2be7d540 VS |
892 | static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv) |
893 | { | |
894 | spin_lock_irq(&dev_priv->irq_lock); | |
895 | valleyview_disable_display_irqs(dev_priv); | |
896 | spin_unlock_irq(&dev_priv->irq_lock); | |
897 | ||
898 | vlv_power_sequencer_reset(dev_priv); | |
899 | } | |
900 | ||
901 | static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, | |
902 | struct i915_power_well *power_well) | |
903 | { | |
904 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); | |
905 | ||
906 | vlv_set_power_well(dev_priv, power_well, true); | |
907 | ||
908 | vlv_display_power_well_init(dev_priv); | |
909 | } | |
910 | ||
9c065a7d DV |
911 | static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, |
912 | struct i915_power_well *power_well) | |
913 | { | |
914 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); | |
915 | ||
2be7d540 | 916 | vlv_display_power_well_deinit(dev_priv); |
9c065a7d DV |
917 | |
918 | vlv_set_power_well(dev_priv, power_well, false); | |
9c065a7d DV |
919 | } |
920 | ||
921 | static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, | |
922 | struct i915_power_well *power_well) | |
923 | { | |
924 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); | |
925 | ||
5a8fbb7d | 926 | /* since ref/cri clock was enabled */ |
9c065a7d DV |
927 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |
928 | ||
929 | vlv_set_power_well(dev_priv, power_well, true); | |
930 | ||
931 | /* | |
932 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - | |
933 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. | |
934 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) | |
935 | * b. The other bits such as sfr settings / modesel may all | |
936 | * be set to 0. | |
937 | * | |
938 | * This should only be done on init and resume from S3 with | |
939 | * both PLLs disabled, or we risk losing DPIO and PLL | |
940 | * synchronization. | |
941 | */ | |
942 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); | |
943 | } | |
944 | ||
945 | static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, | |
946 | struct i915_power_well *power_well) | |
947 | { | |
948 | enum pipe pipe; | |
949 | ||
950 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); | |
951 | ||
952 | for_each_pipe(dev_priv, pipe) | |
953 | assert_pll_disabled(dev_priv, pipe); | |
954 | ||
955 | /* Assert common reset */ | |
956 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); | |
957 | ||
958 | vlv_set_power_well(dev_priv, power_well, false); | |
959 | } | |
960 | ||
961 | static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, | |
962 | struct i915_power_well *power_well) | |
963 | { | |
964 | enum dpio_phy phy; | |
e0fce78f VS |
965 | enum pipe pipe; |
966 | uint32_t tmp; | |
9c065a7d DV |
967 | |
968 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && | |
969 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); | |
970 | ||
e0fce78f VS |
971 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { |
972 | pipe = PIPE_A; | |
9c065a7d | 973 | phy = DPIO_PHY0; |
e0fce78f VS |
974 | } else { |
975 | pipe = PIPE_C; | |
9c065a7d | 976 | phy = DPIO_PHY1; |
e0fce78f | 977 | } |
5a8fbb7d VS |
978 | |
979 | /* since ref/cri clock was enabled */ | |
9c065a7d DV |
980 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |
981 | vlv_set_power_well(dev_priv, power_well, true); | |
982 | ||
983 | /* Poll for phypwrgood signal */ | |
984 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) | |
985 | DRM_ERROR("Display PHY %d is not power up\n", phy); | |
986 | ||
e0fce78f VS |
987 | mutex_lock(&dev_priv->sb_lock); |
988 | ||
989 | /* Enable dynamic power down */ | |
990 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28); | |
ee279218 VS |
991 | tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN | |
992 | DPIO_SUS_CLK_CONFIG_GATE_CLKREQ; | |
e0fce78f VS |
993 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp); |
994 | ||
995 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { | |
996 | tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1); | |
997 | tmp |= DPIO_DYNPWRDOWNEN_CH1; | |
998 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp); | |
999 | } | |
1000 | ||
1001 | mutex_unlock(&dev_priv->sb_lock); | |
1002 | ||
70722468 VS |
1003 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy); |
1004 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); | |
e0fce78f VS |
1005 | |
1006 | DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", | |
1007 | phy, dev_priv->chv_phy_control); | |
9c065a7d DV |
1008 | } |
1009 | ||
1010 | static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, | |
1011 | struct i915_power_well *power_well) | |
1012 | { | |
1013 | enum dpio_phy phy; | |
1014 | ||
1015 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && | |
1016 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); | |
1017 | ||
1018 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { | |
1019 | phy = DPIO_PHY0; | |
1020 | assert_pll_disabled(dev_priv, PIPE_A); | |
1021 | assert_pll_disabled(dev_priv, PIPE_B); | |
1022 | } else { | |
1023 | phy = DPIO_PHY1; | |
1024 | assert_pll_disabled(dev_priv, PIPE_C); | |
1025 | } | |
1026 | ||
70722468 VS |
1027 | dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy); |
1028 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); | |
9c065a7d DV |
1029 | |
1030 | vlv_set_power_well(dev_priv, power_well, false); | |
e0fce78f VS |
1031 | |
1032 | DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n", | |
1033 | phy, dev_priv->chv_phy_control); | |
1034 | } | |
1035 | ||
b0b33846 VS |
1036 | bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy, |
1037 | enum dpio_channel ch, bool override) | |
1038 | { | |
1039 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1040 | bool was_override; | |
1041 | ||
1042 | mutex_lock(&power_domains->lock); | |
1043 | ||
1044 | was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); | |
1045 | ||
1046 | if (override == was_override) | |
1047 | goto out; | |
1048 | ||
1049 | if (override) | |
1050 | dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); | |
1051 | else | |
1052 | dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); | |
1053 | ||
1054 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); | |
1055 | ||
1056 | DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n", | |
1057 | phy, ch, dev_priv->chv_phy_control); | |
1058 | ||
1059 | out: | |
1060 | mutex_unlock(&power_domains->lock); | |
1061 | ||
1062 | return was_override; | |
1063 | } | |
1064 | ||
e0fce78f VS |
1065 | void chv_phy_powergate_lanes(struct intel_encoder *encoder, |
1066 | bool override, unsigned int mask) | |
1067 | { | |
1068 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); | |
1069 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1070 | enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base)); | |
1071 | enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base)); | |
1072 | ||
1073 | mutex_lock(&power_domains->lock); | |
1074 | ||
1075 | dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch); | |
1076 | dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch); | |
1077 | ||
1078 | if (override) | |
1079 | dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); | |
1080 | else | |
1081 | dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch); | |
1082 | ||
1083 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); | |
1084 | ||
1085 | DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n", | |
1086 | phy, ch, mask, dev_priv->chv_phy_control); | |
1087 | ||
1088 | mutex_unlock(&power_domains->lock); | |
9c065a7d DV |
1089 | } |
1090 | ||
1091 | static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, | |
1092 | struct i915_power_well *power_well) | |
1093 | { | |
1094 | enum pipe pipe = power_well->data; | |
1095 | bool enabled; | |
1096 | u32 state, ctrl; | |
1097 | ||
1098 | mutex_lock(&dev_priv->rps.hw_lock); | |
1099 | ||
1100 | state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); | |
1101 | /* | |
1102 | * We only ever set the power-on and power-gate states, anything | |
1103 | * else is unexpected. | |
1104 | */ | |
1105 | WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); | |
1106 | enabled = state == DP_SSS_PWR_ON(pipe); | |
1107 | ||
1108 | /* | |
1109 | * A transient state at this point would mean some unexpected party | |
1110 | * is poking at the power controls too. | |
1111 | */ | |
1112 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); | |
1113 | WARN_ON(ctrl << 16 != state); | |
1114 | ||
1115 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1116 | ||
1117 | return enabled; | |
1118 | } | |
1119 | ||
1120 | static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, | |
1121 | struct i915_power_well *power_well, | |
1122 | bool enable) | |
1123 | { | |
1124 | enum pipe pipe = power_well->data; | |
1125 | u32 state; | |
1126 | u32 ctrl; | |
1127 | ||
1128 | state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); | |
1129 | ||
1130 | mutex_lock(&dev_priv->rps.hw_lock); | |
1131 | ||
1132 | #define COND \ | |
1133 | ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) | |
1134 | ||
1135 | if (COND) | |
1136 | goto out; | |
1137 | ||
1138 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
1139 | ctrl &= ~DP_SSC_MASK(pipe); | |
1140 | ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); | |
1141 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); | |
1142 | ||
1143 | if (wait_for(COND, 100)) | |
7e35ab88 | 1144 | DRM_ERROR("timeout setting power well state %08x (%08x)\n", |
9c065a7d DV |
1145 | state, |
1146 | vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); | |
1147 | ||
1148 | #undef COND | |
1149 | ||
1150 | out: | |
1151 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1152 | } | |
1153 | ||
1154 | static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, | |
1155 | struct i915_power_well *power_well) | |
1156 | { | |
8fcd5cd8 VS |
1157 | WARN_ON_ONCE(power_well->data != PIPE_A); |
1158 | ||
9c065a7d DV |
1159 | chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); |
1160 | } | |
1161 | ||
1162 | static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, | |
1163 | struct i915_power_well *power_well) | |
1164 | { | |
8fcd5cd8 | 1165 | WARN_ON_ONCE(power_well->data != PIPE_A); |
9c065a7d DV |
1166 | |
1167 | chv_set_pipe_power_well(dev_priv, power_well, true); | |
afd6275d | 1168 | |
2be7d540 | 1169 | vlv_display_power_well_init(dev_priv); |
9c065a7d DV |
1170 | } |
1171 | ||
1172 | static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, | |
1173 | struct i915_power_well *power_well) | |
1174 | { | |
8fcd5cd8 VS |
1175 | WARN_ON_ONCE(power_well->data != PIPE_A); |
1176 | ||
2be7d540 | 1177 | vlv_display_power_well_deinit(dev_priv); |
afd6275d | 1178 | |
9c065a7d DV |
1179 | chv_set_pipe_power_well(dev_priv, power_well, false); |
1180 | } | |
1181 | ||
e4e7684f DV |
1182 | /** |
1183 | * intel_display_power_get - grab a power domain reference | |
1184 | * @dev_priv: i915 device instance | |
1185 | * @domain: power domain to reference | |
1186 | * | |
1187 | * This function grabs a power domain reference for @domain and ensures that the | |
1188 | * power domain and all its parents are powered up. Therefore users should only | |
1189 | * grab a reference to the innermost power domain they need. | |
1190 | * | |
1191 | * Any power domain reference obtained by this function must have a symmetric | |
1192 | * call to intel_display_power_put() to release the reference again. | |
1193 | */ | |
9c065a7d DV |
1194 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
1195 | enum intel_display_power_domain domain) | |
1196 | { | |
1197 | struct i915_power_domains *power_domains; | |
1198 | struct i915_power_well *power_well; | |
1199 | int i; | |
1200 | ||
1201 | intel_runtime_pm_get(dev_priv); | |
1202 | ||
1203 | power_domains = &dev_priv->power_domains; | |
1204 | ||
1205 | mutex_lock(&power_domains->lock); | |
1206 | ||
1207 | for_each_power_well(i, power_well, BIT(domain), power_domains) { | |
e8ca9320 DL |
1208 | if (!power_well->count++) |
1209 | intel_power_well_enable(dev_priv, power_well); | |
9c065a7d DV |
1210 | } |
1211 | ||
1212 | power_domains->domain_use_count[domain]++; | |
1213 | ||
1214 | mutex_unlock(&power_domains->lock); | |
1215 | } | |
1216 | ||
e4e7684f DV |
1217 | /** |
1218 | * intel_display_power_put - release a power domain reference | |
1219 | * @dev_priv: i915 device instance | |
1220 | * @domain: power domain to reference | |
1221 | * | |
1222 | * This function drops the power domain reference obtained by | |
1223 | * intel_display_power_get() and might power down the corresponding hardware | |
1224 | * block right away if this is the last reference. | |
1225 | */ | |
9c065a7d DV |
1226 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
1227 | enum intel_display_power_domain domain) | |
1228 | { | |
1229 | struct i915_power_domains *power_domains; | |
1230 | struct i915_power_well *power_well; | |
1231 | int i; | |
1232 | ||
1233 | power_domains = &dev_priv->power_domains; | |
1234 | ||
1235 | mutex_lock(&power_domains->lock); | |
1236 | ||
1237 | WARN_ON(!power_domains->domain_use_count[domain]); | |
1238 | power_domains->domain_use_count[domain]--; | |
1239 | ||
1240 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { | |
1241 | WARN_ON(!power_well->count); | |
1242 | ||
dcddab3a DL |
1243 | if (!--power_well->count && i915.disable_power_well) |
1244 | intel_power_well_disable(dev_priv, power_well); | |
9c065a7d DV |
1245 | } |
1246 | ||
1247 | mutex_unlock(&power_domains->lock); | |
1248 | ||
1249 | intel_runtime_pm_put(dev_priv); | |
1250 | } | |
1251 | ||
1252 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) | |
1253 | ||
1254 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ | |
1255 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
1256 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ | |
1257 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ | |
1258 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ | |
1259 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
1260 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
1261 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
1262 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
1263 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
1264 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
1265 | BIT(POWER_DOMAIN_PORT_CRT) | \ | |
1266 | BIT(POWER_DOMAIN_PLLS) | \ | |
1407121a S |
1267 | BIT(POWER_DOMAIN_AUX_A) | \ |
1268 | BIT(POWER_DOMAIN_AUX_B) | \ | |
1269 | BIT(POWER_DOMAIN_AUX_C) | \ | |
1270 | BIT(POWER_DOMAIN_AUX_D) | \ | |
9c065a7d DV |
1271 | BIT(POWER_DOMAIN_INIT)) |
1272 | #define HSW_DISPLAY_POWER_DOMAINS ( \ | |
1273 | (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ | |
1274 | BIT(POWER_DOMAIN_INIT)) | |
1275 | ||
1276 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ | |
1277 | HSW_ALWAYS_ON_POWER_DOMAINS | \ | |
1278 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) | |
1279 | #define BDW_DISPLAY_POWER_DOMAINS ( \ | |
1280 | (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ | |
1281 | BIT(POWER_DOMAIN_INIT)) | |
1282 | ||
1283 | #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) | |
1284 | #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK | |
1285 | ||
1286 | #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ | |
1287 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
1288 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
1289 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
1290 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
1291 | BIT(POWER_DOMAIN_PORT_CRT) | \ | |
1407121a S |
1292 | BIT(POWER_DOMAIN_AUX_B) | \ |
1293 | BIT(POWER_DOMAIN_AUX_C) | \ | |
9c065a7d DV |
1294 | BIT(POWER_DOMAIN_INIT)) |
1295 | ||
1296 | #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ | |
1297 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
1298 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
1407121a | 1299 | BIT(POWER_DOMAIN_AUX_B) | \ |
9c065a7d DV |
1300 | BIT(POWER_DOMAIN_INIT)) |
1301 | ||
1302 | #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ | |
1303 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
1407121a | 1304 | BIT(POWER_DOMAIN_AUX_B) | \ |
9c065a7d DV |
1305 | BIT(POWER_DOMAIN_INIT)) |
1306 | ||
1307 | #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ | |
1308 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
1309 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
1407121a | 1310 | BIT(POWER_DOMAIN_AUX_C) | \ |
9c065a7d DV |
1311 | BIT(POWER_DOMAIN_INIT)) |
1312 | ||
1313 | #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ | |
1314 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
1407121a | 1315 | BIT(POWER_DOMAIN_AUX_C) | \ |
9c065a7d DV |
1316 | BIT(POWER_DOMAIN_INIT)) |
1317 | ||
9c065a7d DV |
1318 | #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ |
1319 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ | |
1320 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ | |
1321 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ | |
1322 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ | |
1407121a S |
1323 | BIT(POWER_DOMAIN_AUX_B) | \ |
1324 | BIT(POWER_DOMAIN_AUX_C) | \ | |
9c065a7d DV |
1325 | BIT(POWER_DOMAIN_INIT)) |
1326 | ||
1327 | #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ | |
1328 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ | |
1329 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ | |
1407121a | 1330 | BIT(POWER_DOMAIN_AUX_D) | \ |
9c065a7d DV |
1331 | BIT(POWER_DOMAIN_INIT)) |
1332 | ||
9c065a7d DV |
1333 | static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { |
1334 | .sync_hw = i9xx_always_on_power_well_noop, | |
1335 | .enable = i9xx_always_on_power_well_noop, | |
1336 | .disable = i9xx_always_on_power_well_noop, | |
1337 | .is_enabled = i9xx_always_on_power_well_enabled, | |
1338 | }; | |
1339 | ||
1340 | static const struct i915_power_well_ops chv_pipe_power_well_ops = { | |
1341 | .sync_hw = chv_pipe_power_well_sync_hw, | |
1342 | .enable = chv_pipe_power_well_enable, | |
1343 | .disable = chv_pipe_power_well_disable, | |
1344 | .is_enabled = chv_pipe_power_well_enabled, | |
1345 | }; | |
1346 | ||
1347 | static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { | |
1348 | .sync_hw = vlv_power_well_sync_hw, | |
1349 | .enable = chv_dpio_cmn_power_well_enable, | |
1350 | .disable = chv_dpio_cmn_power_well_disable, | |
1351 | .is_enabled = vlv_power_well_enabled, | |
1352 | }; | |
1353 | ||
1354 | static struct i915_power_well i9xx_always_on_power_well[] = { | |
1355 | { | |
1356 | .name = "always-on", | |
1357 | .always_on = 1, | |
1358 | .domains = POWER_DOMAIN_MASK, | |
1359 | .ops = &i9xx_always_on_power_well_ops, | |
1360 | }, | |
1361 | }; | |
1362 | ||
1363 | static const struct i915_power_well_ops hsw_power_well_ops = { | |
1364 | .sync_hw = hsw_power_well_sync_hw, | |
1365 | .enable = hsw_power_well_enable, | |
1366 | .disable = hsw_power_well_disable, | |
1367 | .is_enabled = hsw_power_well_enabled, | |
1368 | }; | |
1369 | ||
94dd5138 S |
1370 | static const struct i915_power_well_ops skl_power_well_ops = { |
1371 | .sync_hw = skl_power_well_sync_hw, | |
1372 | .enable = skl_power_well_enable, | |
1373 | .disable = skl_power_well_disable, | |
1374 | .is_enabled = skl_power_well_enabled, | |
1375 | }; | |
1376 | ||
9c065a7d DV |
1377 | static struct i915_power_well hsw_power_wells[] = { |
1378 | { | |
1379 | .name = "always-on", | |
1380 | .always_on = 1, | |
1381 | .domains = HSW_ALWAYS_ON_POWER_DOMAINS, | |
1382 | .ops = &i9xx_always_on_power_well_ops, | |
1383 | }, | |
1384 | { | |
1385 | .name = "display", | |
1386 | .domains = HSW_DISPLAY_POWER_DOMAINS, | |
1387 | .ops = &hsw_power_well_ops, | |
1388 | }, | |
1389 | }; | |
1390 | ||
1391 | static struct i915_power_well bdw_power_wells[] = { | |
1392 | { | |
1393 | .name = "always-on", | |
1394 | .always_on = 1, | |
1395 | .domains = BDW_ALWAYS_ON_POWER_DOMAINS, | |
1396 | .ops = &i9xx_always_on_power_well_ops, | |
1397 | }, | |
1398 | { | |
1399 | .name = "display", | |
1400 | .domains = BDW_DISPLAY_POWER_DOMAINS, | |
1401 | .ops = &hsw_power_well_ops, | |
1402 | }, | |
1403 | }; | |
1404 | ||
1405 | static const struct i915_power_well_ops vlv_display_power_well_ops = { | |
1406 | .sync_hw = vlv_power_well_sync_hw, | |
1407 | .enable = vlv_display_power_well_enable, | |
1408 | .disable = vlv_display_power_well_disable, | |
1409 | .is_enabled = vlv_power_well_enabled, | |
1410 | }; | |
1411 | ||
1412 | static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { | |
1413 | .sync_hw = vlv_power_well_sync_hw, | |
1414 | .enable = vlv_dpio_cmn_power_well_enable, | |
1415 | .disable = vlv_dpio_cmn_power_well_disable, | |
1416 | .is_enabled = vlv_power_well_enabled, | |
1417 | }; | |
1418 | ||
1419 | static const struct i915_power_well_ops vlv_dpio_power_well_ops = { | |
1420 | .sync_hw = vlv_power_well_sync_hw, | |
1421 | .enable = vlv_power_well_enable, | |
1422 | .disable = vlv_power_well_disable, | |
1423 | .is_enabled = vlv_power_well_enabled, | |
1424 | }; | |
1425 | ||
1426 | static struct i915_power_well vlv_power_wells[] = { | |
1427 | { | |
1428 | .name = "always-on", | |
1429 | .always_on = 1, | |
1430 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, | |
1431 | .ops = &i9xx_always_on_power_well_ops, | |
1432 | }, | |
1433 | { | |
1434 | .name = "display", | |
1435 | .domains = VLV_DISPLAY_POWER_DOMAINS, | |
1436 | .data = PUNIT_POWER_WELL_DISP2D, | |
1437 | .ops = &vlv_display_power_well_ops, | |
1438 | }, | |
1439 | { | |
1440 | .name = "dpio-tx-b-01", | |
1441 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1442 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1443 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1444 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1445 | .ops = &vlv_dpio_power_well_ops, | |
1446 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, | |
1447 | }, | |
1448 | { | |
1449 | .name = "dpio-tx-b-23", | |
1450 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1451 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1452 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1453 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1454 | .ops = &vlv_dpio_power_well_ops, | |
1455 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, | |
1456 | }, | |
1457 | { | |
1458 | .name = "dpio-tx-c-01", | |
1459 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1460 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1461 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1462 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1463 | .ops = &vlv_dpio_power_well_ops, | |
1464 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, | |
1465 | }, | |
1466 | { | |
1467 | .name = "dpio-tx-c-23", | |
1468 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | | |
1469 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | | |
1470 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | | |
1471 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, | |
1472 | .ops = &vlv_dpio_power_well_ops, | |
1473 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, | |
1474 | }, | |
1475 | { | |
1476 | .name = "dpio-common", | |
1477 | .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, | |
1478 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, | |
1479 | .ops = &vlv_dpio_cmn_power_well_ops, | |
1480 | }, | |
1481 | }; | |
1482 | ||
1483 | static struct i915_power_well chv_power_wells[] = { | |
1484 | { | |
1485 | .name = "always-on", | |
1486 | .always_on = 1, | |
1487 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, | |
1488 | .ops = &i9xx_always_on_power_well_ops, | |
1489 | }, | |
9c065a7d DV |
1490 | { |
1491 | .name = "display", | |
baa4e575 | 1492 | /* |
fde61e4b VS |
1493 | * Pipe A power well is the new disp2d well. Pipe B and C |
1494 | * power wells don't actually exist. Pipe A power well is | |
1495 | * required for any pipe to work. | |
baa4e575 | 1496 | */ |
fde61e4b | 1497 | .domains = VLV_DISPLAY_POWER_DOMAINS, |
9c065a7d DV |
1498 | .data = PIPE_A, |
1499 | .ops = &chv_pipe_power_well_ops, | |
1500 | }, | |
9c065a7d DV |
1501 | { |
1502 | .name = "dpio-common-bc", | |
71849b67 | 1503 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS, |
9c065a7d DV |
1504 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, |
1505 | .ops = &chv_dpio_cmn_power_well_ops, | |
1506 | }, | |
1507 | { | |
1508 | .name = "dpio-common-d", | |
71849b67 | 1509 | .domains = CHV_DPIO_CMN_D_POWER_DOMAINS, |
9c065a7d DV |
1510 | .data = PUNIT_POWER_WELL_DPIO_CMN_D, |
1511 | .ops = &chv_dpio_cmn_power_well_ops, | |
1512 | }, | |
9c065a7d DV |
1513 | }; |
1514 | ||
1515 | static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, | |
5aefb239 | 1516 | int power_well_id) |
9c065a7d DV |
1517 | { |
1518 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1519 | struct i915_power_well *power_well; | |
1520 | int i; | |
1521 | ||
1522 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { | |
1523 | if (power_well->data == power_well_id) | |
1524 | return power_well; | |
1525 | } | |
1526 | ||
1527 | return NULL; | |
1528 | } | |
1529 | ||
5aefb239 SS |
1530 | bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv, |
1531 | int power_well_id) | |
1532 | { | |
1533 | struct i915_power_well *power_well; | |
1534 | bool ret; | |
1535 | ||
1536 | power_well = lookup_power_well(dev_priv, power_well_id); | |
1537 | ret = power_well->ops->is_enabled(dev_priv, power_well); | |
1538 | ||
1539 | return ret; | |
1540 | } | |
1541 | ||
94dd5138 S |
1542 | static struct i915_power_well skl_power_wells[] = { |
1543 | { | |
1544 | .name = "always-on", | |
1545 | .always_on = 1, | |
1546 | .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS, | |
1547 | .ops = &i9xx_always_on_power_well_ops, | |
1548 | }, | |
1549 | { | |
1550 | .name = "power well 1", | |
1551 | .domains = SKL_DISPLAY_POWERWELL_1_POWER_DOMAINS, | |
1552 | .ops = &skl_power_well_ops, | |
1553 | .data = SKL_DISP_PW_1, | |
1554 | }, | |
1555 | { | |
1556 | .name = "MISC IO power well", | |
1557 | .domains = SKL_DISPLAY_MISC_IO_POWER_DOMAINS, | |
1558 | .ops = &skl_power_well_ops, | |
1559 | .data = SKL_DISP_PW_MISC_IO, | |
1560 | }, | |
1561 | { | |
1562 | .name = "power well 2", | |
1563 | .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS, | |
1564 | .ops = &skl_power_well_ops, | |
1565 | .data = SKL_DISP_PW_2, | |
1566 | }, | |
1567 | { | |
1568 | .name = "DDI A/E power well", | |
1569 | .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS, | |
1570 | .ops = &skl_power_well_ops, | |
1571 | .data = SKL_DISP_PW_DDI_A_E, | |
1572 | }, | |
1573 | { | |
1574 | .name = "DDI B power well", | |
1575 | .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS, | |
1576 | .ops = &skl_power_well_ops, | |
1577 | .data = SKL_DISP_PW_DDI_B, | |
1578 | }, | |
1579 | { | |
1580 | .name = "DDI C power well", | |
1581 | .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS, | |
1582 | .ops = &skl_power_well_ops, | |
1583 | .data = SKL_DISP_PW_DDI_C, | |
1584 | }, | |
1585 | { | |
1586 | .name = "DDI D power well", | |
1587 | .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS, | |
1588 | .ops = &skl_power_well_ops, | |
1589 | .data = SKL_DISP_PW_DDI_D, | |
1590 | }, | |
1591 | }; | |
1592 | ||
0b4a2a36 S |
1593 | static struct i915_power_well bxt_power_wells[] = { |
1594 | { | |
1595 | .name = "always-on", | |
1596 | .always_on = 1, | |
1597 | .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS, | |
1598 | .ops = &i9xx_always_on_power_well_ops, | |
1599 | }, | |
1600 | { | |
1601 | .name = "power well 1", | |
1602 | .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS, | |
1603 | .ops = &skl_power_well_ops, | |
1604 | .data = SKL_DISP_PW_1, | |
1605 | }, | |
1606 | { | |
1607 | .name = "power well 2", | |
1608 | .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS, | |
1609 | .ops = &skl_power_well_ops, | |
1610 | .data = SKL_DISP_PW_2, | |
1611 | } | |
1612 | }; | |
1613 | ||
9c065a7d DV |
1614 | #define set_power_wells(power_domains, __power_wells) ({ \ |
1615 | (power_domains)->power_wells = (__power_wells); \ | |
1616 | (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ | |
1617 | }) | |
1618 | ||
e4e7684f DV |
1619 | /** |
1620 | * intel_power_domains_init - initializes the power domain structures | |
1621 | * @dev_priv: i915 device instance | |
1622 | * | |
1623 | * Initializes the power domain structures for @dev_priv depending upon the | |
1624 | * supported platform. | |
1625 | */ | |
9c065a7d DV |
1626 | int intel_power_domains_init(struct drm_i915_private *dev_priv) |
1627 | { | |
1628 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1629 | ||
1630 | mutex_init(&power_domains->lock); | |
1631 | ||
1632 | /* | |
1633 | * The enabling order will be from lower to higher indexed wells, | |
1634 | * the disabling order is reversed. | |
1635 | */ | |
1636 | if (IS_HASWELL(dev_priv->dev)) { | |
1637 | set_power_wells(power_domains, hsw_power_wells); | |
9c065a7d DV |
1638 | } else if (IS_BROADWELL(dev_priv->dev)) { |
1639 | set_power_wells(power_domains, bdw_power_wells); | |
94dd5138 S |
1640 | } else if (IS_SKYLAKE(dev_priv->dev)) { |
1641 | set_power_wells(power_domains, skl_power_wells); | |
0b4a2a36 S |
1642 | } else if (IS_BROXTON(dev_priv->dev)) { |
1643 | set_power_wells(power_domains, bxt_power_wells); | |
9c065a7d DV |
1644 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1645 | set_power_wells(power_domains, chv_power_wells); | |
1646 | } else if (IS_VALLEYVIEW(dev_priv->dev)) { | |
1647 | set_power_wells(power_domains, vlv_power_wells); | |
1648 | } else { | |
1649 | set_power_wells(power_domains, i9xx_always_on_power_well); | |
1650 | } | |
1651 | ||
1652 | return 0; | |
1653 | } | |
1654 | ||
41373cd5 DV |
1655 | static void intel_runtime_pm_disable(struct drm_i915_private *dev_priv) |
1656 | { | |
1657 | struct drm_device *dev = dev_priv->dev; | |
1658 | struct device *device = &dev->pdev->dev; | |
1659 | ||
1660 | if (!HAS_RUNTIME_PM(dev)) | |
1661 | return; | |
1662 | ||
1663 | if (!intel_enable_rc6(dev)) | |
1664 | return; | |
1665 | ||
1666 | /* Make sure we're not suspended first. */ | |
1667 | pm_runtime_get_sync(device); | |
1668 | pm_runtime_disable(device); | |
1669 | } | |
1670 | ||
e4e7684f DV |
1671 | /** |
1672 | * intel_power_domains_fini - finalizes the power domain structures | |
1673 | * @dev_priv: i915 device instance | |
1674 | * | |
1675 | * Finalizes the power domain structures for @dev_priv depending upon the | |
1676 | * supported platform. This function also disables runtime pm and ensures that | |
1677 | * the device stays powered up so that the driver can be reloaded. | |
1678 | */ | |
f458ebbc | 1679 | void intel_power_domains_fini(struct drm_i915_private *dev_priv) |
9c065a7d | 1680 | { |
41373cd5 DV |
1681 | intel_runtime_pm_disable(dev_priv); |
1682 | ||
f458ebbc DV |
1683 | /* The i915.ko module is still not prepared to be loaded when |
1684 | * the power well is not enabled, so just enable it in case | |
1685 | * we're going to unload/reload. */ | |
1686 | intel_display_set_init_power(dev_priv, true); | |
9c065a7d DV |
1687 | } |
1688 | ||
1689 | static void intel_power_domains_resume(struct drm_i915_private *dev_priv) | |
1690 | { | |
1691 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1692 | struct i915_power_well *power_well; | |
1693 | int i; | |
1694 | ||
1695 | mutex_lock(&power_domains->lock); | |
1696 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { | |
1697 | power_well->ops->sync_hw(dev_priv, power_well); | |
1698 | power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, | |
1699 | power_well); | |
1700 | } | |
1701 | mutex_unlock(&power_domains->lock); | |
1702 | } | |
1703 | ||
70722468 VS |
1704 | static void chv_phy_control_init(struct drm_i915_private *dev_priv) |
1705 | { | |
1706 | struct i915_power_well *cmn_bc = | |
1707 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); | |
1708 | struct i915_power_well *cmn_d = | |
1709 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D); | |
1710 | ||
1711 | /* | |
1712 | * DISPLAY_PHY_CONTROL can get corrupted if read. As a | |
1713 | * workaround never ever read DISPLAY_PHY_CONTROL, and | |
1714 | * instead maintain a shadow copy ourselves. Use the actual | |
e0fce78f VS |
1715 | * power well state and lane status to reconstruct the |
1716 | * expected initial value. | |
70722468 VS |
1717 | */ |
1718 | dev_priv->chv_phy_control = | |
bc284542 VS |
1719 | PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) | |
1720 | PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) | | |
e0fce78f VS |
1721 | PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) | |
1722 | PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) | | |
1723 | PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0); | |
1724 | ||
1725 | /* | |
1726 | * If all lanes are disabled we leave the override disabled | |
1727 | * with all power down bits cleared to match the state we | |
1728 | * would use after disabling the port. Otherwise enable the | |
1729 | * override and set the lane powerdown bits accding to the | |
1730 | * current lane status. | |
1731 | */ | |
1732 | if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) { | |
1733 | uint32_t status = I915_READ(DPLL(PIPE_A)); | |
1734 | unsigned int mask; | |
1735 | ||
1736 | mask = status & DPLL_PORTB_READY_MASK; | |
1737 | if (mask == 0xf) | |
1738 | mask = 0x0; | |
1739 | else | |
1740 | dev_priv->chv_phy_control |= | |
1741 | PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0); | |
1742 | ||
1743 | dev_priv->chv_phy_control |= | |
1744 | PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0); | |
1745 | ||
1746 | mask = (status & DPLL_PORTC_READY_MASK) >> 4; | |
1747 | if (mask == 0xf) | |
1748 | mask = 0x0; | |
1749 | else | |
1750 | dev_priv->chv_phy_control |= | |
1751 | PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1); | |
1752 | ||
1753 | dev_priv->chv_phy_control |= | |
1754 | PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1); | |
1755 | ||
70722468 | 1756 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0); |
e0fce78f VS |
1757 | } |
1758 | ||
1759 | if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) { | |
1760 | uint32_t status = I915_READ(DPIO_PHY_STATUS); | |
1761 | unsigned int mask; | |
1762 | ||
1763 | mask = status & DPLL_PORTD_READY_MASK; | |
1764 | ||
1765 | if (mask == 0xf) | |
1766 | mask = 0x0; | |
1767 | else | |
1768 | dev_priv->chv_phy_control |= | |
1769 | PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0); | |
1770 | ||
1771 | dev_priv->chv_phy_control |= | |
1772 | PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0); | |
1773 | ||
70722468 | 1774 | dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1); |
e0fce78f VS |
1775 | } |
1776 | ||
1777 | I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control); | |
1778 | ||
1779 | DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n", | |
1780 | dev_priv->chv_phy_control); | |
70722468 VS |
1781 | } |
1782 | ||
9c065a7d DV |
1783 | static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) |
1784 | { | |
1785 | struct i915_power_well *cmn = | |
1786 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); | |
1787 | struct i915_power_well *disp2d = | |
1788 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); | |
1789 | ||
9c065a7d | 1790 | /* If the display might be already active skip this */ |
5d93a6e5 VS |
1791 | if (cmn->ops->is_enabled(dev_priv, cmn) && |
1792 | disp2d->ops->is_enabled(dev_priv, disp2d) && | |
9c065a7d DV |
1793 | I915_READ(DPIO_CTL) & DPIO_CMNRST) |
1794 | return; | |
1795 | ||
1796 | DRM_DEBUG_KMS("toggling display PHY side reset\n"); | |
1797 | ||
1798 | /* cmnlane needs DPLL registers */ | |
1799 | disp2d->ops->enable(dev_priv, disp2d); | |
1800 | ||
1801 | /* | |
1802 | * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: | |
1803 | * Need to assert and de-assert PHY SB reset by gating the | |
1804 | * common lane power, then un-gating it. | |
1805 | * Simply ungating isn't enough to reset the PHY enough to get | |
1806 | * ports and lanes running. | |
1807 | */ | |
1808 | cmn->ops->disable(dev_priv, cmn); | |
1809 | } | |
1810 | ||
e4e7684f DV |
1811 | /** |
1812 | * intel_power_domains_init_hw - initialize hardware power domain state | |
1813 | * @dev_priv: i915 device instance | |
1814 | * | |
1815 | * This function initializes the hardware power domain state and enables all | |
1816 | * power domains using intel_display_set_init_power(). | |
1817 | */ | |
9c065a7d DV |
1818 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) |
1819 | { | |
1820 | struct drm_device *dev = dev_priv->dev; | |
1821 | struct i915_power_domains *power_domains = &dev_priv->power_domains; | |
1822 | ||
1823 | power_domains->initializing = true; | |
1824 | ||
70722468 | 1825 | if (IS_CHERRYVIEW(dev)) { |
770effb1 | 1826 | mutex_lock(&power_domains->lock); |
70722468 | 1827 | chv_phy_control_init(dev_priv); |
770effb1 | 1828 | mutex_unlock(&power_domains->lock); |
70722468 | 1829 | } else if (IS_VALLEYVIEW(dev)) { |
9c065a7d DV |
1830 | mutex_lock(&power_domains->lock); |
1831 | vlv_cmnlane_wa(dev_priv); | |
1832 | mutex_unlock(&power_domains->lock); | |
1833 | } | |
1834 | ||
1835 | /* For now, we need the power well to be always enabled. */ | |
1836 | intel_display_set_init_power(dev_priv, true); | |
1837 | intel_power_domains_resume(dev_priv); | |
1838 | power_domains->initializing = false; | |
1839 | } | |
1840 | ||
e4e7684f | 1841 | /** |
ca2b1403 | 1842 | * intel_aux_display_runtime_get - grab an auxiliary power domain reference |
e4e7684f DV |
1843 | * @dev_priv: i915 device instance |
1844 | * | |
1845 | * This function grabs a power domain reference for the auxiliary power domain | |
1846 | * (for access to the GMBUS and DP AUX blocks) and ensures that it and all its | |
1847 | * parents are powered up. Therefore users should only grab a reference to the | |
1848 | * innermost power domain they need. | |
1849 | * | |
1850 | * Any power domain reference obtained by this function must have a symmetric | |
1851 | * call to intel_aux_display_runtime_put() to release the reference again. | |
1852 | */ | |
9c065a7d DV |
1853 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) |
1854 | { | |
1855 | intel_runtime_pm_get(dev_priv); | |
1856 | } | |
1857 | ||
e4e7684f | 1858 | /** |
ca2b1403 | 1859 | * intel_aux_display_runtime_put - release an auxiliary power domain reference |
e4e7684f DV |
1860 | * @dev_priv: i915 device instance |
1861 | * | |
ca2b1403 | 1862 | * This function drops the auxiliary power domain reference obtained by |
e4e7684f DV |
1863 | * intel_aux_display_runtime_get() and might power down the corresponding |
1864 | * hardware block right away if this is the last reference. | |
1865 | */ | |
9c065a7d DV |
1866 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) |
1867 | { | |
1868 | intel_runtime_pm_put(dev_priv); | |
1869 | } | |
1870 | ||
e4e7684f DV |
1871 | /** |
1872 | * intel_runtime_pm_get - grab a runtime pm reference | |
1873 | * @dev_priv: i915 device instance | |
1874 | * | |
1875 | * This function grabs a device-level runtime pm reference (mostly used for GEM | |
1876 | * code to ensure the GTT or GT is on) and ensures that it is powered up. | |
1877 | * | |
1878 | * Any runtime pm reference obtained by this function must have a symmetric | |
1879 | * call to intel_runtime_pm_put() to release the reference again. | |
1880 | */ | |
9c065a7d DV |
1881 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv) |
1882 | { | |
1883 | struct drm_device *dev = dev_priv->dev; | |
1884 | struct device *device = &dev->pdev->dev; | |
1885 | ||
1886 | if (!HAS_RUNTIME_PM(dev)) | |
1887 | return; | |
1888 | ||
1889 | pm_runtime_get_sync(device); | |
1890 | WARN(dev_priv->pm.suspended, "Device still suspended.\n"); | |
1891 | } | |
1892 | ||
e4e7684f DV |
1893 | /** |
1894 | * intel_runtime_pm_get_noresume - grab a runtime pm reference | |
1895 | * @dev_priv: i915 device instance | |
1896 | * | |
1897 | * This function grabs a device-level runtime pm reference (mostly used for GEM | |
1898 | * code to ensure the GTT or GT is on). | |
1899 | * | |
1900 | * It will _not_ power up the device but instead only check that it's powered | |
1901 | * on. Therefore it is only valid to call this functions from contexts where | |
1902 | * the device is known to be powered up and where trying to power it up would | |
1903 | * result in hilarity and deadlocks. That pretty much means only the system | |
1904 | * suspend/resume code where this is used to grab runtime pm references for | |
1905 | * delayed setup down in work items. | |
1906 | * | |
1907 | * Any runtime pm reference obtained by this function must have a symmetric | |
1908 | * call to intel_runtime_pm_put() to release the reference again. | |
1909 | */ | |
9c065a7d DV |
1910 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) |
1911 | { | |
1912 | struct drm_device *dev = dev_priv->dev; | |
1913 | struct device *device = &dev->pdev->dev; | |
1914 | ||
1915 | if (!HAS_RUNTIME_PM(dev)) | |
1916 | return; | |
1917 | ||
1918 | WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n"); | |
1919 | pm_runtime_get_noresume(device); | |
1920 | } | |
1921 | ||
e4e7684f DV |
1922 | /** |
1923 | * intel_runtime_pm_put - release a runtime pm reference | |
1924 | * @dev_priv: i915 device instance | |
1925 | * | |
1926 | * This function drops the device-level runtime pm reference obtained by | |
1927 | * intel_runtime_pm_get() and might power down the corresponding | |
1928 | * hardware block right away if this is the last reference. | |
1929 | */ | |
9c065a7d DV |
1930 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv) |
1931 | { | |
1932 | struct drm_device *dev = dev_priv->dev; | |
1933 | struct device *device = &dev->pdev->dev; | |
1934 | ||
1935 | if (!HAS_RUNTIME_PM(dev)) | |
1936 | return; | |
1937 | ||
1938 | pm_runtime_mark_last_busy(device); | |
1939 | pm_runtime_put_autosuspend(device); | |
1940 | } | |
1941 | ||
e4e7684f DV |
1942 | /** |
1943 | * intel_runtime_pm_enable - enable runtime pm | |
1944 | * @dev_priv: i915 device instance | |
1945 | * | |
1946 | * This function enables runtime pm at the end of the driver load sequence. | |
1947 | * | |
1948 | * Note that this function does currently not enable runtime pm for the | |
1949 | * subordinate display power domains. That is only done on the first modeset | |
1950 | * using intel_display_set_init_power(). | |
1951 | */ | |
f458ebbc | 1952 | void intel_runtime_pm_enable(struct drm_i915_private *dev_priv) |
9c065a7d DV |
1953 | { |
1954 | struct drm_device *dev = dev_priv->dev; | |
1955 | struct device *device = &dev->pdev->dev; | |
1956 | ||
1957 | if (!HAS_RUNTIME_PM(dev)) | |
1958 | return; | |
1959 | ||
1960 | pm_runtime_set_active(device); | |
1961 | ||
1962 | /* | |
1963 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a | |
1964 | * requirement. | |
1965 | */ | |
1966 | if (!intel_enable_rc6(dev)) { | |
1967 | DRM_INFO("RC6 disabled, disabling runtime PM support\n"); | |
1968 | return; | |
1969 | } | |
1970 | ||
1971 | pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ | |
1972 | pm_runtime_mark_last_busy(device); | |
1973 | pm_runtime_use_autosuspend(device); | |
1974 | ||
1975 | pm_runtime_put_autosuspend(device); | |
1976 | } | |
1977 |