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drm/i915: Cache LVDS EDID
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945
JB		 30#include <linux/delay.h>
31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
2b8d33f7 34#include "drm_edid.h"
ea5b213a 35#include "intel_drv.h"
79e53945
JB		 36#include "i915_drm.h"
37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
46 SDVO_TV_MASK)
47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 50#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
14571b4c 51
79e53945 52
2e88e40b 53static const char *tv_format_names[] = {
ce6feabd
ZY		 54 "NTSC_M" , "NTSC_J" , "NTSC_443",
55 "PAL_B" , "PAL_D" , "PAL_G" ,
56 "PAL_H" , "PAL_I" , "PAL_M" ,
57 "PAL_N" , "PAL_NC" , "PAL_60" ,
58 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
59 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
60 "SECAM_60"
61};
62
63#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
64
ea5b213a
CW		 65struct intel_sdvo {
66 struct intel_encoder base;
67
f899fc64 68 struct i2c_adapter *i2c;
f9c10a9b 69 u8 slave_addr;
e2f0ba97
JB		 70
71 /* Register for the SDVO device: SDVOB or SDVOC */
c751ce4f 72 int sdvo_reg;
79e53945 73
e2f0ba97
JB		 74 /* Active outputs controlled by this SDVO output */
75 uint16_t controlled_output;
79e53945 76
e2f0ba97
JB		 77 /*
78 * Capabilities of the SDVO device returned by
79 * i830_sdvo_get_capabilities()
80 */
79e53945 81 struct intel_sdvo_caps caps;
e2f0ba97
JB		 82
83 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 84 int pixel_clock_min, pixel_clock_max;
85
fb7a46f3 86 /*
87 * For multiple function SDVO device,
88 * this is for current attached outputs.
89 */
90 uint16_t attached_output;
91
e2f0ba97
JB		 92 /**
93 * This is set if we're going to treat the device as TV-out.
94 *
95 * While we have these nice friendly flags for output types that ought
96 * to decide this for us, the S-Video output on our HDMI+S-Video card
97 * shows up as RGB1 (VGA).
98 */
99 bool is_tv;
100
ce6feabd 101 /* This is for current tv format name */
40039750 102 int tv_format_index;
ce6feabd 103
e2f0ba97
JB		 104 /**
105 * This is set if we treat the device as HDMI, instead of DVI.
106 */
107 bool is_hdmi;
12682a97 108
7086c87f 109 /**
6c9547ff
CW		 110 * This is set if we detect output of sdvo device as LVDS and
111 * have a valid fixed mode to use with the panel.
7086c87f
ML		 112 */
113 bool is_lvds;
e2f0ba97 114
12682a97 115 /**
116 * This is sdvo fixed pannel mode pointer
117 */
118 struct drm_display_mode *sdvo_lvds_fixed_mode;
119
e2f0ba97
JB		 120 /*
121 * supported encoding mode, used to determine whether HDMI is
122 * supported
123 */
124 struct intel_sdvo_encode encode;
125
c751ce4f 126 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 127 uint8_t ddc_bus;
128
6c9547ff
CW		 129 /* Input timings for adjusted_mode */
130 struct intel_sdvo_dtd input_dtd;
14571b4c
ZW		 131};
132
133struct intel_sdvo_connector {
615fb93f
CW		 134 struct intel_connector base;
135
14571b4c
ZW		 136 /* Mark the type of connector */
137 uint16_t output_flag;
138
139 /* This contains all current supported TV format */
40039750 140 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 141 int format_supported_num;
c5521706 142 struct drm_property *tv_format;
14571b4c 143
b9219c5e 144 /* add the property for the SDVO-TV */
c5521706
CW		 145 struct drm_property *left;
146 struct drm_property *right;
147 struct drm_property *top;
148 struct drm_property *bottom;
149 struct drm_property *hpos;
150 struct drm_property *vpos;
151 struct drm_property *contrast;
152 struct drm_property *saturation;
153 struct drm_property *hue;
154 struct drm_property *sharpness;
155 struct drm_property *flicker_filter;
156 struct drm_property *flicker_filter_adaptive;
157 struct drm_property *flicker_filter_2d;
158 struct drm_property *tv_chroma_filter;
159 struct drm_property *tv_luma_filter;
e044218a 160 struct drm_property *dot_crawl;
b9219c5e
ZY		 161
162 /* add the property for the SDVO-TV/LVDS */
c5521706 163 struct drm_property *brightness;
b9219c5e
ZY		 164
165 /* Add variable to record current setting for the above property */
166 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 167
b9219c5e
ZY		 168 /* this is to get the range of margin.*/
169 u32 max_hscan, max_vscan;
170 u32 max_hpos, cur_hpos;
171 u32 max_vpos, cur_vpos;
172 u32 cur_brightness, max_brightness;
173 u32 cur_contrast, max_contrast;
174 u32 cur_saturation, max_saturation;
175 u32 cur_hue, max_hue;
c5521706
CW		 176 u32 cur_sharpness, max_sharpness;
177 u32 cur_flicker_filter, max_flicker_filter;
178 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
179 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
180 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
181 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 182 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 183};
184
890f3359 185static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 186{
4ef69c7a 187 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 188}
189
df0e9248
CW		 190static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
191{
192 return container_of(intel_attached_encoder(connector),
193 struct intel_sdvo, base);
194}
195
615fb93f
CW		 196static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
197{
198 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
199}
200
fb7a46f3 201static bool
ea5b213a 202intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 203static bool
204intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
205 struct intel_sdvo_connector *intel_sdvo_connector,
206 int type);
207static bool
208intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
209 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 210
79e53945
JB		 211/**
212 * Writes the SDVOB or SDVOC with the given value, but always writes both
213 * SDVOB and SDVOC to work around apparent hardware issues (according to
214 * comments in the BIOS).
215 */
ea5b213a 216static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 217{
4ef69c7a 218 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 219 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 220 u32 bval = val, cval = val;
221 int i;
222
ea5b213a
CW		 223 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
224 I915_WRITE(intel_sdvo->sdvo_reg, val);
225 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 226 return;
227 }
228
ea5b213a 229 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 230 cval = I915_READ(SDVOC);
231 } else {
232 bval = I915_READ(SDVOB);
233 }
234 /*
235 * Write the registers twice for luck. Sometimes,
236 * writing them only once doesn't appear to 'stick'.
237 * The BIOS does this too. Yay, magic
238 */
239 for (i = 0; i < 2; i++)
240 {
241 I915_WRITE(SDVOB, bval);
242 I915_READ(SDVOB);
243 I915_WRITE(SDVOC, cval);
244 I915_READ(SDVOC);
245 }
246}
247
32aad86f 248static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 249{
32aad86f 250 u8 out_buf[2] = { addr, 0 };
79e53945 251 u8 buf[2];
79e53945
JB		 252 struct i2c_msg msgs[] = {
253 {
ea5b213a 254 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 255 .flags = 0,
256 .len = 1,
257 .buf = out_buf,
258 },
259 {
ea5b213a 260 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 261 .flags = I2C_M_RD,
262 .len = 1,
263 .buf = buf,
264 }
265 };
32aad86f 266 int ret;
79e53945 267
f899fc64 268 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945
JB		 269 {
270 *ch = buf[0];
271 return true;
272 }
273
8a4c47f3 274 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 275 return false;
276}
277
32aad86f 278static bool intel_sdvo_write_byte(struct intel_sdvo *intel_sdvo, int addr, u8 ch)
79e53945 279{
32aad86f 280 u8 out_buf[2] = { addr, ch };
79e53945
JB		 281 struct i2c_msg msgs[] = {
282 {
ea5b213a 283 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 284 .flags = 0,
285 .len = 2,
286 .buf = out_buf,
287 }
288 };
289
f899fc64 290 return i2c_transfer(intel_sdvo->i2c, msgs, 1) == 1;
79e53945
JB		 291}
292
293#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
294/** Mapping of command numbers to names, for debug output */
005568be 295static const struct _sdvo_cmd_name {
e2f0ba97 296 u8 cmd;
2e88e40b 297 const char *name;
79e53945
JB		 298} sdvo_cmd_names[] = {
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
e2f0ba97
JB		 334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
79e53945 338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
e2f0ba97
JB		 339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
c5521706 342
b9219c5e 343 /* Add the op code for SDVO enhancements */
c5521706
CW		 344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
b9219c5e
ZY		 350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
c5521706
CW		 368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
388
e2f0ba97
JB		 389 /* HDMI op code */
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 410};
411
461ed3ca 412#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
ea5b213a 413#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
79e53945 414
ea5b213a 415static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 416 const void *args, int args_len)
79e53945 417{
79e53945
JB		 418 int i;
419
8a4c47f3 420 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 421 SDVO_NAME(intel_sdvo), cmd);
79e53945 422 for (i = 0; i < args_len; i++)
342dc382 423 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 424 for (; i < 8; i++)
342dc382 425 DRM_LOG_KMS(" ");
04ad327f 426 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 427 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 428 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 429 break;
430 }
431 }
04ad327f 432 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 433 DRM_LOG_KMS("(%02X)", cmd);
434 DRM_LOG_KMS("\n");
79e53945 435}
79e53945 436
32aad86f
CW		 437static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
438 const void *args, int args_len)
79e53945
JB		 439{
440 int i;
441
ea5b213a 442 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 443
444 for (i = 0; i < args_len; i++) {
32aad86f
CW		 445 if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0 - i,
446 ((u8*)args)[i]))
447 return false;
79e53945
JB		 448 }
449
32aad86f 450 return intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_OPCODE, cmd);
79e53945
JB		 451}
452
79e53945
JB		 453static const char *cmd_status_names[] = {
454 "Power on",
455 "Success",
456 "Not supported",
457 "Invalid arg",
458 "Pending",
459 "Target not specified",
460 "Scaling not supported"
461};
462
b5c616a7
CW		 463static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
464 void *response, int response_len)
79e53945 465{
b5c616a7
CW		 466 u8 retry = 5;
467 u8 status;
33b52961 468 int i;
79e53945 469
b5c616a7
CW		 470 /*
471 * The documentation states that all commands will be
472 * processed within 15µs, and that we need only poll
473 * the status byte a maximum of 3 times in order for the
474 * command to be complete.
475 *
476 * Check 5 times in case the hardware failed to read the docs.
477 */
478 do {
479 if (!intel_sdvo_read_byte(intel_sdvo,
480 SDVO_I2C_CMD_STATUS,
481 &status))
482 return false;
483 } while (status == SDVO_CMD_STATUS_PENDING && --retry);
484
ea5b213a 485 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
79e53945 486 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 487 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 488 else
342dc382 489 DRM_LOG_KMS("(??? %d)", status);
79e53945 490
b5c616a7
CW		 491 if (status != SDVO_CMD_STATUS_SUCCESS)
492 goto log_fail;
79e53945 493
b5c616a7
CW		 494 /* Read the command response */
495 for (i = 0; i < response_len; i++) {
496 if (!intel_sdvo_read_byte(intel_sdvo,
497 SDVO_I2C_RETURN_0 + i,
498 &((u8 *)response)[i]))
499 goto log_fail;
500 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
501 }
79e53945 502
b5c616a7
CW		 503 for (; i < 8; i++)
504 DRM_LOG_KMS(" ");
505 DRM_LOG_KMS("\n");
79e53945 506
b5c616a7 507 return true;
79e53945 508
b5c616a7
CW		 509log_fail:
510 DRM_LOG_KMS("\n");
511 return false;
79e53945
JB		 512}
513
b358d0a6 514static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 515{
516 if (mode->clock >= 100000)
517 return 1;
518 else if (mode->clock >= 50000)
519 return 2;
520 else
521 return 4;
522}
523
524/**
6a304caf
ZY		 525 * Try to read the response after issuie the DDC switch command. But it
526 * is noted that we must do the action of reading response and issuing DDC
527 * switch command in one I2C transaction. Otherwise when we try to start
528 * another I2C transaction after issuing the DDC bus switch, it will be
529 * switched to the internal SDVO register.
79e53945 530 */
819f3fb7
CW		 531static int intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
532 u8 target)
79e53945 533{
6a304caf
ZY		 534 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
535 struct i2c_msg msgs[] = {
536 {
ea5b213a 537 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 538 .flags = 0,
539 .len = 2,
540 .buf = out_buf,
541 },
542 /* the following two are to read the response */
543 {
ea5b213a 544 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 545 .flags = 0,
546 .len = 1,
547 .buf = cmd_buf,
548 },
549 {
ea5b213a 550 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 551 .flags = I2C_M_RD,
552 .len = 1,
553 .buf = ret_value,
554 },
555 };
556
ea5b213a 557 intel_sdvo_debug_write(intel_sdvo, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
819f3fb7 558 &target, 1);
6a304caf 559 /* write the DDC switch command argument */
819f3fb7
CW		 560 if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0, target))
561 return -EIO;
6a304caf
ZY		 562
563 out_buf[0] = SDVO_I2C_OPCODE;
564 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
565 cmd_buf[0] = SDVO_I2C_CMD_STATUS;
566 cmd_buf[1] = 0;
567 ret_value[0] = 0;
568 ret_value[1] = 0;
569
f899fc64 570 ret = i2c_transfer(intel_sdvo->i2c, msgs, 3);
819f3fb7
CW		 571 if (ret < 0)
572 return ret;
6a304caf
ZY		 573 if (ret != 3) {
574 /* failure in I2C transfer */
575 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
819f3fb7 576 return -EIO;
6a304caf
ZY		 577 }
578 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
579 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
819f3fb7
CW		 580 ret_value[0]);
581 return -EIO;
6a304caf 582 }
819f3fb7
CW		 583
584 return 0;
79e53945
JB		 585}
586
32aad86f 587static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 588{
32aad86f
CW		 589 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
590 return false;
79e53945 591
32aad86f
CW		 592 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
593}
79e53945 594
32aad86f
CW		 595static bool
596intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
597{
598 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
599 return false;
79e53945 600
32aad86f
CW		 601 return intel_sdvo_read_response(intel_sdvo, value, len);
602}
79e53945 603
32aad86f
CW		 604static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
605{
606 struct intel_sdvo_set_target_input_args targets = {0};
607 return intel_sdvo_set_value(intel_sdvo,
608 SDVO_CMD_SET_TARGET_INPUT,
609 &targets, sizeof(targets));
79e53945
JB		 610}
611
612/**
613 * Return whether each input is trained.
614 *
615 * This function is making an assumption about the layout of the response,
616 * which should be checked against the docs.
617 */
ea5b213a 618static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 619{
620 struct intel_sdvo_get_trained_inputs_response response;
79e53945 621
32aad86f
CW		 622 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
623 &response, sizeof(response)))
79e53945
JB		 624 return false;
625
626 *input_1 = response.input0_trained;
627 *input_2 = response.input1_trained;
628 return true;
629}
630
ea5b213a 631static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 632 u16 outputs)
633{
32aad86f
CW		 634 return intel_sdvo_set_value(intel_sdvo,
635 SDVO_CMD_SET_ACTIVE_OUTPUTS,
636 &outputs, sizeof(outputs));
79e53945
JB		 637}
638
ea5b213a 639static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 640 int mode)
641{
32aad86f 642 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 643
644 switch (mode) {
645 case DRM_MODE_DPMS_ON:
646 state = SDVO_ENCODER_STATE_ON;
647 break;
648 case DRM_MODE_DPMS_STANDBY:
649 state = SDVO_ENCODER_STATE_STANDBY;
650 break;
651 case DRM_MODE_DPMS_SUSPEND:
652 state = SDVO_ENCODER_STATE_SUSPEND;
653 break;
654 case DRM_MODE_DPMS_OFF:
655 state = SDVO_ENCODER_STATE_OFF;
656 break;
657 }
658
32aad86f
CW		 659 return intel_sdvo_set_value(intel_sdvo,
660 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 661}
662
ea5b213a 663static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 664 int *clock_min,
665 int *clock_max)
666{
667 struct intel_sdvo_pixel_clock_range clocks;
79e53945 668
32aad86f
CW		 669 if (!intel_sdvo_get_value(intel_sdvo,
670 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
671 &clocks, sizeof(clocks)))
79e53945
JB		 672 return false;
673
674 /* Convert the values from units of 10 kHz to kHz. */
675 *clock_min = clocks.min * 10;
676 *clock_max = clocks.max * 10;
79e53945
JB		 677 return true;
678}
679
ea5b213a 680static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 681 u16 outputs)
682{
32aad86f
CW		 683 return intel_sdvo_set_value(intel_sdvo,
684 SDVO_CMD_SET_TARGET_OUTPUT,
685 &outputs, sizeof(outputs));
79e53945
JB		 686}
687
ea5b213a 688static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 689 struct intel_sdvo_dtd *dtd)
690{
32aad86f
CW		 691 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
692 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 693}
694
ea5b213a 695static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 696 struct intel_sdvo_dtd *dtd)
697{
ea5b213a 698 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 699 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
700}
701
ea5b213a 702static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 703 struct intel_sdvo_dtd *dtd)
704{
ea5b213a 705 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 706 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
707}
708
e2f0ba97 709static bool
ea5b213a 710intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 711 uint16_t clock,
712 uint16_t width,
713 uint16_t height)
714{
715 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 716
e642c6f1 717 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 718 args.clock = clock;
719 args.width = width;
720 args.height = height;
e642c6f1 721 args.interlace = 0;
12682a97 722
ea5b213a
CW		 723 if (intel_sdvo->is_lvds &&
724 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
725 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 726 args.scaled = 1;
727
32aad86f
CW		 728 return intel_sdvo_set_value(intel_sdvo,
729 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
730 &args, sizeof(args));
e2f0ba97
JB		 731}
732
ea5b213a 733static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 734 struct intel_sdvo_dtd *dtd)
735{
32aad86f
CW		 736 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
737 &dtd->part1, sizeof(dtd->part1)) &&
738 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
739 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 740}
79e53945 741
ea5b213a 742static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 743{
32aad86f 744 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 745}
746
e2f0ba97 747static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 748 const struct drm_display_mode *mode)
79e53945 749{
e2f0ba97
JB		 750 uint16_t width, height;
751 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
752 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 753
754 width = mode->crtc_hdisplay;
755 height = mode->crtc_vdisplay;
756
757 /* do some mode translations */
758 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
759 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
760
761 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
762 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
763
764 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
765 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
766
e2f0ba97
JB		 767 dtd->part1.clock = mode->clock / 10;
768 dtd->part1.h_active = width & 0xff;
769 dtd->part1.h_blank = h_blank_len & 0xff;
770 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 771 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 772 dtd->part1.v_active = height & 0xff;
773 dtd->part1.v_blank = v_blank_len & 0xff;
774 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 775 ((v_blank_len >> 8) & 0xf);
776
171a9e96 777 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 778 dtd->part2.h_sync_width = h_sync_len & 0xff;
779 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 780 (v_sync_len & 0xf);
e2f0ba97 781 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 782 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
783 ((v_sync_len & 0x30) >> 4);
784
e2f0ba97 785 dtd->part2.dtd_flags = 0x18;
79e53945 786 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 787 dtd->part2.dtd_flags |= 0x2;
79e53945 788 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 789 dtd->part2.dtd_flags |= 0x4;
790
791 dtd->part2.sdvo_flags = 0;
792 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
793 dtd->part2.reserved = 0;
794}
795
796static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 797 const struct intel_sdvo_dtd *dtd)
e2f0ba97 798{
e2f0ba97
JB		 799 mode->hdisplay = dtd->part1.h_active;
800 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
801 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 802 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 803 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
804 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
805 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
806 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
807
808 mode->vdisplay = dtd->part1.v_active;
809 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
810 mode->vsync_start = mode->vdisplay;
811 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 812 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 813 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
814 mode->vsync_end = mode->vsync_start +
815 (dtd->part2.v_sync_off_width & 0xf);
816 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
817 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
818 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
819
820 mode->clock = dtd->part1.clock * 10;
821
171a9e96 822 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 823 if (dtd->part2.dtd_flags & 0x2)
824 mode->flags |= DRM_MODE_FLAG_PHSYNC;
825 if (dtd->part2.dtd_flags & 0x4)
826 mode->flags |= DRM_MODE_FLAG_PVSYNC;
827}
828
ea5b213a 829static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 830 struct intel_sdvo_encode *encode)
831{
32aad86f
CW		 832 if (intel_sdvo_get_value(intel_sdvo,
833 SDVO_CMD_GET_SUPP_ENCODE,
834 encode, sizeof(*encode)))
835 return true;
e2f0ba97 836
32aad86f
CW		 837 /* non-support means DVI */
838 memset(encode, 0, sizeof(*encode));
839 return false;
e2f0ba97
JB		 840}
841
ea5b213a 842static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 843 uint8_t mode)
e2f0ba97 844{
32aad86f 845 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 846}
847
ea5b213a 848static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 849 uint8_t mode)
850{
32aad86f 851 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 852}
853
854#if 0
ea5b213a 855static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 856{
857 int i, j;
858 uint8_t set_buf_index[2];
859 uint8_t av_split;
860 uint8_t buf_size;
861 uint8_t buf[48];
862 uint8_t *pos;
863
32aad86f 864 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 865
866 for (i = 0; i <= av_split; i++) {
867 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 868 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 869 set_buf_index, 2);
c751ce4f
EA		 870 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
871 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 872
873 pos = buf;
874 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 875 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 876 NULL, 0);
c751ce4f 877 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 878 pos += 8;
879 }
880 }
881}
882#endif
883
32aad86f 884static bool intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo,
c751ce4f
EA		 885 int index,
886 uint8_t *data, int8_t size, uint8_t tx_rate)
e2f0ba97
JB		 887{
888 uint8_t set_buf_index[2];
889
890 set_buf_index[0] = index;
891 set_buf_index[1] = 0;
892
32aad86f
CW		 893 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX,
894 set_buf_index, 2))
895 return false;
e2f0ba97
JB		 896
897 for (; size > 0; size -= 8) {
32aad86f
CW		 898 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8))
899 return false;
900
e2f0ba97
JB		 901 data += 8;
902 }
903
32aad86f 904 return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
e2f0ba97
JB		 905}
906
907static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
908{
909 uint8_t csum = 0;
910 int i;
911
912 for (i = 0; i < size; i++)
913 csum += data[i];
914
915 return 0x100 - csum;
916}
917
918#define DIP_TYPE_AVI 0x82
919#define DIP_VERSION_AVI 0x2
920#define DIP_LEN_AVI 13
921
922struct dip_infoframe {
923 uint8_t type;
924 uint8_t version;
925 uint8_t len;
926 uint8_t checksum;
927 union {
928 struct {
929 /* Packet Byte #1 */
930 uint8_t S:2;
931 uint8_t B:2;
932 uint8_t A:1;
933 uint8_t Y:2;
934 uint8_t rsvd1:1;
935 /* Packet Byte #2 */
936 uint8_t R:4;
937 uint8_t M:2;
938 uint8_t C:2;
939 /* Packet Byte #3 */
940 uint8_t SC:2;
941 uint8_t Q:2;
942 uint8_t EC:3;
943 uint8_t ITC:1;
944 /* Packet Byte #4 */
945 uint8_t VIC:7;
946 uint8_t rsvd2:1;
947 /* Packet Byte #5 */
948 uint8_t PR:4;
949 uint8_t rsvd3:4;
950 /* Packet Byte #6~13 */
951 uint16_t top_bar_end;
952 uint16_t bottom_bar_start;
953 uint16_t left_bar_end;
954 uint16_t right_bar_start;
955 } avi;
956 struct {
957 /* Packet Byte #1 */
958 uint8_t channel_count:3;
959 uint8_t rsvd1:1;
960 uint8_t coding_type:4;
961 /* Packet Byte #2 */
962 uint8_t sample_size:2; /* SS0, SS1 */
963 uint8_t sample_frequency:3;
964 uint8_t rsvd2:3;
965 /* Packet Byte #3 */
966 uint8_t coding_type_private:5;
967 uint8_t rsvd3:3;
968 /* Packet Byte #4 */
969 uint8_t channel_allocation;
970 /* Packet Byte #5 */
971 uint8_t rsvd4:3;
972 uint8_t level_shift:4;
973 uint8_t downmix_inhibit:1;
974 } audio;
975 uint8_t payload[28];
976 } __attribute__ ((packed)) u;
977} __attribute__((packed));
978
32aad86f 979static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 980 struct drm_display_mode * mode)
981{
982 struct dip_infoframe avi_if = {
983 .type = DIP_TYPE_AVI,
984 .version = DIP_VERSION_AVI,
985 .len = DIP_LEN_AVI,
986 };
987
988 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
989 4 + avi_if.len);
32aad86f
CW		 990 return intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if,
991 4 + avi_if.len,
992 SDVO_HBUF_TX_VSYNC);
e2f0ba97
JB		 993}
994
32aad86f 995static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 996{
ce6feabd 997 struct intel_sdvo_tv_format format;
40039750 998 uint32_t format_map;
ce6feabd 999
40039750 1000 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1001 memset(&format, 0, sizeof(format));
32aad86f 1002 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1003
32aad86f
CW		 1004 BUILD_BUG_ON(sizeof(format) != 6);
1005 return intel_sdvo_set_value(intel_sdvo,
1006 SDVO_CMD_SET_TV_FORMAT,
1007 &format, sizeof(format));
7026d4ac
ZW		 1008}
1009
32aad86f
CW		 1010static bool
1011intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1012 struct drm_display_mode *mode)
e2f0ba97 1013{
32aad86f 1014 struct intel_sdvo_dtd output_dtd;
79e53945 1015
32aad86f
CW		 1016 if (!intel_sdvo_set_target_output(intel_sdvo,
1017 intel_sdvo->attached_output))
1018 return false;
e2f0ba97 1019
32aad86f
CW		 1020 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1021 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1022 return false;
e2f0ba97 1023
32aad86f
CW		 1024 return true;
1025}
1026
1027static bool
1028intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
1029 struct drm_display_mode *mode,
1030 struct drm_display_mode *adjusted_mode)
1031{
32aad86f
CW		 1032 /* Reset the input timing to the screen. Assume always input 0. */
1033 if (!intel_sdvo_set_target_input(intel_sdvo))
1034 return false;
e2f0ba97 1035
32aad86f
CW		 1036 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1037 mode->clock / 10,
1038 mode->hdisplay,
1039 mode->vdisplay))
1040 return false;
e2f0ba97 1041
32aad86f 1042 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
6c9547ff 1043 &intel_sdvo->input_dtd))
32aad86f 1044 return false;
e2f0ba97 1045
6c9547ff 1046 intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
79e53945 1047
32aad86f 1048 drm_mode_set_crtcinfo(adjusted_mode, 0);
32aad86f
CW		 1049 return true;
1050}
12682a97 1051
32aad86f
CW		 1052static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1053 struct drm_display_mode *mode,
1054 struct drm_display_mode *adjusted_mode)
1055{
890f3359 1056 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1057 int multiplier;
12682a97 1058
32aad86f
CW		 1059 /* We need to construct preferred input timings based on our
1060 * output timings. To do that, we have to set the output
1061 * timings, even though this isn't really the right place in
1062 * the sequence to do it. Oh well.
1063 */
1064 if (intel_sdvo->is_tv) {
1065 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1066 return false;
12682a97 1067
c74696b9
PR		 1068 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1069 mode,
1070 adjusted_mode);
ea5b213a 1071 } else if (intel_sdvo->is_lvds) {
32aad86f 1072 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1073 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1074 return false;
12682a97 1075
c74696b9
PR		 1076 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1077 mode,
1078 adjusted_mode);
e2f0ba97 1079 }
32aad86f
CW		 1080
1081 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1082 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1083 */
6c9547ff
CW		 1084 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
1085 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 1086
e2f0ba97
JB		 1087 return true;
1088}
1089
1090static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1091 struct drm_display_mode *mode,
1092 struct drm_display_mode *adjusted_mode)
1093{
1094 struct drm_device *dev = encoder->dev;
1095 struct drm_i915_private *dev_priv = dev->dev_private;
1096 struct drm_crtc *crtc = encoder->crtc;
1097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 1098 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1099 u32 sdvox;
e2f0ba97
JB		 1100 struct intel_sdvo_in_out_map in_out;
1101 struct intel_sdvo_dtd input_dtd;
6c9547ff
CW		 1102 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1103 int rate;
e2f0ba97
JB		 1104
1105 if (!mode)
1106 return;
1107
1108 /* First, set the input mapping for the first input to our controlled
1109 * output. This is only correct if we're a single-input device, in
1110 * which case the first input is the output from the appropriate SDVO
1111 * channel on the motherboard. In a two-input device, the first input
1112 * will be SDVOB and the second SDVOC.
1113 */
ea5b213a 1114 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1115 in_out.in1 = 0;
1116
c74696b9
PR		 1117 intel_sdvo_set_value(intel_sdvo,
1118 SDVO_CMD_SET_IN_OUT_MAP,
1119 &in_out, sizeof(in_out));
e2f0ba97 1120
6c9547ff
CW		 1121 /* Set the output timings to the screen */
1122 if (!intel_sdvo_set_target_output(intel_sdvo,
1123 intel_sdvo->attached_output))
1124 return;
e2f0ba97 1125
7026d4ac 1126 /* We have tried to get input timing in mode_fixup, and filled into
6c9547ff 1127 * adjusted_mode.
e2f0ba97 1128 */
6c9547ff
CW		 1129 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
1130 input_dtd = intel_sdvo->input_dtd;
1131 } else {
e2f0ba97 1132 /* Set the output timing to the screen */
32aad86f
CW		 1133 if (!intel_sdvo_set_target_output(intel_sdvo,
1134 intel_sdvo->attached_output))
1135 return;
1136
6c9547ff 1137 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c74696b9 1138 (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
e2f0ba97 1139 }
79e53945
JB		 1140
1141 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1142 if (!intel_sdvo_set_target_input(intel_sdvo))
1143 return;
79e53945 1144
6c9547ff
CW		 1145 if (intel_sdvo->is_hdmi &&
1146 !intel_sdvo_set_avi_infoframe(intel_sdvo, mode))
1147 return;
7026d4ac 1148
6c9547ff
CW		 1149 if (intel_sdvo->is_tv &&
1150 !intel_sdvo_set_tv_format(intel_sdvo))
1151 return;
e2f0ba97 1152
c74696b9 1153 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
79e53945 1154
6c9547ff
CW		 1155 switch (pixel_multiplier) {
1156 default:
32aad86f
CW		 1157 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1158 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1159 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1160 }
32aad86f
CW		 1161 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1162 return;
79e53945
JB		 1163
1164 /* Set the SDVO control regs. */
e2f0ba97 1165 if (IS_I965G(dev)) {
6c9547ff 1166 sdvox = SDVO_BORDER_ENABLE;
81a14b46
AJ		 1167 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1168 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
1169 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1170 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
e2f0ba97 1171 } else {
6c9547ff 1172 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1173 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1174 case SDVOB:
1175 sdvox &= SDVOB_PRESERVE_MASK;
1176 break;
1177 case SDVOC:
1178 sdvox &= SDVOC_PRESERVE_MASK;
1179 break;
1180 }
1181 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1182 }
79e53945
JB		 1183 if (intel_crtc->pipe == 1)
1184 sdvox |= SDVO_PIPE_B_SELECT;
6c9547ff
CW		 1185 if (intel_sdvo->is_hdmi)
1186 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1187
79e53945 1188 if (IS_I965G(dev)) {
e2f0ba97
JB		 1189 /* done in crtc_mode_set as the dpll_md reg must be written early */
1190 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1191 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1192 } else {
6c9547ff 1193 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1194 }
1195
6c9547ff 1196 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL)
12682a97 1197 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1198 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1199}
1200
1201static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1202{
1203 struct drm_device *dev = encoder->dev;
1204 struct drm_i915_private *dev_priv = dev->dev_private;
890f3359 1205 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
9d0498a2 1206 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1207 u32 temp;
1208
1209 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1210 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1211 if (0)
ea5b213a 1212 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1213
1214 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1215 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1216 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1217 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1218 }
1219 }
1220 } else {
1221 bool input1, input2;
1222 int i;
1223 u8 status;
1224
ea5b213a 1225 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1226 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1227 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1228 for (i = 0; i < 2; i++)
9d0498a2 1229 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1230
32aad86f 1231 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1232 /* Warn if the device reported failure to sync.
1233 * A lot of SDVO devices fail to notify of sync, but it's
1234 * a given it the status is a success, we succeeded.
1235 */
1236 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1237 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1238 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1239 }
1240
1241 if (0)
ea5b213a
CW		 1242 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1243 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1244 }
1245 return;
1246}
1247
79e53945
JB		 1248static int intel_sdvo_mode_valid(struct drm_connector *connector,
1249 struct drm_display_mode *mode)
1250{
df0e9248 1251 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1252
1253 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1254 return MODE_NO_DBLESCAN;
1255
ea5b213a 1256 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1257 return MODE_CLOCK_LOW;
1258
ea5b213a 1259 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1260 return MODE_CLOCK_HIGH;
1261
8545423a 1262 if (intel_sdvo->is_lvds) {
ea5b213a 1263 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1264 return MODE_PANEL;
1265
ea5b213a 1266 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1267 return MODE_PANEL;
1268 }
1269
79e53945
JB		 1270 return MODE_OK;
1271}
1272
ea5b213a 1273static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1274{
32aad86f 1275 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, caps, sizeof(*caps));
79e53945
JB		 1276}
1277
d2a82a6f
ZW		 1278/* No use! */
1279#if 0
79e53945
JB		 1280struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1281{
1282 struct drm_connector *connector = NULL;
ea5b213a
CW		 1283 struct intel_sdvo *iout = NULL;
1284 struct intel_sdvo *sdvo;
79e53945
JB		 1285
1286 /* find the sdvo connector */
1287 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
ea5b213a 1288 iout = to_intel_sdvo(connector);
79e53945
JB		 1289
1290 if (iout->type != INTEL_OUTPUT_SDVO)
1291 continue;
1292
1293 sdvo = iout->dev_priv;
1294
c751ce4f 1295 if (sdvo->sdvo_reg == SDVOB && sdvoB)
79e53945
JB		 1296 return connector;
1297
c751ce4f 1298 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
79e53945
JB		 1299 return connector;
1300
1301 }
1302
1303 return NULL;
1304}
1305
1306int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1307{
1308 u8 response[2];
1309 u8 status;
ea5b213a 1310 struct intel_sdvo *intel_sdvo;
8a4c47f3 1311 DRM_DEBUG_KMS("\n");
79e53945
JB		 1312
1313 if (!connector)
1314 return 0;
1315
ea5b213a 1316 intel_sdvo = to_intel_sdvo(connector);
79e53945 1317
32aad86f
CW		 1318 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1319 &response, 2) && response[0];
79e53945
JB		 1320}
1321
1322void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1323{
1324 u8 response[2];
1325 u8 status;
ea5b213a 1326 struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector);
79e53945 1327
ea5b213a
CW		 1328 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1329 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945
JB		 1330
1331 if (on) {
ea5b213a
CW		 1332 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1333 status = intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1334
ea5b213a 1335 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1336 } else {
1337 response[0] = 0;
1338 response[1] = 0;
ea5b213a 1339 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1340 }
1341
ea5b213a
CW		 1342 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1343 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1344}
d2a82a6f 1345#endif
79e53945 1346
fb7a46f3 1347static bool
ea5b213a 1348intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1349{
fb7a46f3 1350 int caps = 0;
1351
ea5b213a 1352 if (intel_sdvo->caps.output_flags &
fb7a46f3 1353 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1354 caps++;
ea5b213a 1355 if (intel_sdvo->caps.output_flags &
fb7a46f3 1356 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1357 caps++;
ea5b213a 1358 if (intel_sdvo->caps.output_flags &
19e1f888 1359 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
fb7a46f3 1360 caps++;
ea5b213a 1361 if (intel_sdvo->caps.output_flags &
fb7a46f3 1362 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1363 caps++;
ea5b213a 1364 if (intel_sdvo->caps.output_flags &
fb7a46f3 1365 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1366 caps++;
1367
ea5b213a 1368 if (intel_sdvo->caps.output_flags &
fb7a46f3 1369 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1370 caps++;
1371
ea5b213a 1372 if (intel_sdvo->caps.output_flags &
fb7a46f3 1373 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1374 caps++;
1375
1376 return (caps > 1);
1377}
1378
f899fc64
CW		 1379static struct edid *
1380intel_sdvo_get_edid(struct drm_connector *connector, int ddc)
1381{
1382 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1383 int ret;
1384
1385 ret = intel_sdvo_set_control_bus_switch(intel_sdvo, ddc);
1386 if (ret)
1387 return NULL;
1388
1389 return drm_get_edid(connector, intel_sdvo->i2c);
1390}
1391
57cdaf90
KP		 1392static struct drm_connector *
1393intel_find_analog_connector(struct drm_device *dev)
1394{
1395 struct drm_connector *connector;
df0e9248
CW		 1396 struct intel_sdvo *encoder;
1397
1398 list_for_each_entry(encoder,
1399 &dev->mode_config.encoder_list,
1400 base.base.head) {
1401 if (encoder->base.type == INTEL_OUTPUT_ANALOG) {
1402 list_for_each_entry(connector,
1403 &dev->mode_config.connector_list,
1404 head) {
1405 if (&encoder->base ==
1406 intel_attached_encoder(connector))
d2a82a6f
ZW		 1407 return connector;
1408 }
1409 }
57cdaf90 1410 }
df0e9248 1411
57cdaf90
KP		 1412 return NULL;
1413}
1414
1415static int
1416intel_analog_is_connected(struct drm_device *dev)
1417{
1418 struct drm_connector *analog_connector;
57cdaf90 1419
32aad86f 1420 analog_connector = intel_find_analog_connector(dev);
57cdaf90
KP		 1421 if (!analog_connector)
1422 return false;
1423
930a9e28 1424 if (analog_connector->funcs->detect(analog_connector, false) ==
57cdaf90
KP		 1425 connector_status_disconnected)
1426 return false;
1427
1428 return true;
1429}
1430
ff482d83
CW		 1431/* Mac mini hack -- use the same DDC as the analog connector */
1432static struct edid *
1433intel_sdvo_get_analog_edid(struct drm_connector *connector)
1434{
f899fc64 1435 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1436
f899fc64 1437 if (!intel_analog_is_connected(connector->dev))
ff482d83
CW		 1438 return NULL;
1439
f899fc64 1440 return drm_get_edid(connector, &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
ff482d83
CW		 1441}
1442
2b8d33f7 1443enum drm_connector_status
149c36a3 1444intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
9dff6af8 1445{
df0e9248 1446 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1447 enum drm_connector_status status;
1448 struct edid *edid;
9dff6af8 1449
f899fc64 1450 edid = intel_sdvo_get_edid(connector, intel_sdvo->ddc_bus);
57cdaf90 1451
ea5b213a 1452 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
f899fc64 1453 u8 ddc;
9d1a903d 1454
7c3f0a27
ZY		 1455 /*
1456 * Don't use the 1 as the argument of DDC bus switch to get
1457 * the EDID. It is used for SDVO SPD ROM.
1458 */
9d1a903d 1459 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
f899fc64
CW		 1460 edid = intel_sdvo_get_edid(connector, ddc);
1461 if (edid) {
1462 /*
1463 * If we found the EDID on the other bus,
1464 * assume that is the correct DDC bus.
1465 */
1466 intel_sdvo->ddc_bus = ddc;
7c3f0a27 1467 break;
f899fc64 1468 }
7c3f0a27 1469 }
7c3f0a27 1470 }
9d1a903d
CW		 1471
1472 /*
1473 * When there is no edid and no monitor is connected with VGA
1474 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1475 */
ff482d83
CW		 1476 if (edid == NULL)
1477 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1478
2f551c84 1479 status = connector_status_unknown;
9dff6af8 1480 if (edid != NULL) {
149c36a3 1481 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1482 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1483 status = connector_status_connected;
ea5b213a 1484 intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid);
9d1a903d 1485 }
149c36a3 1486 connector->display_info.raw_edid = NULL;
9d1a903d
CW		 1487 kfree(edid);
1488 }
149c36a3 1489
2b8d33f7 1490 return status;
9dff6af8
ML		 1491}
1492
7b334fcb 1493static enum drm_connector_status
930a9e28 1494intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1495{
fb7a46f3 1496 uint16_t response;
df0e9248 1497 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1498 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1499 enum drm_connector_status ret;
79e53945 1500
32aad86f
CW		 1501 if (!intel_sdvo_write_cmd(intel_sdvo,
1502 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
1503 return connector_status_unknown;
ea5b213a 1504 if (intel_sdvo->is_tv) {
d09c23de
ZY		 1505 /* add 30ms delay when the output type is SDVO-TV */
1506 mdelay(30);
1507 }
32aad86f
CW		 1508 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1509 return connector_status_unknown;
79e53945 1510
51c8b407 1511 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
e2f0ba97 1512
fb7a46f3 1513 if (response == 0)
79e53945 1514 return connector_status_disconnected;
fb7a46f3 1515
ea5b213a 1516 intel_sdvo->attached_output = response;
14571b4c 1517
615fb93f 1518 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1519 ret = connector_status_disconnected;
149c36a3
AJ		 1520 else if (response & SDVO_TMDS_MASK)
1521 ret = intel_sdvo_hdmi_sink_detect(connector);
14571b4c
ZW		 1522 else
1523 ret = connector_status_connected;
1524
1525 /* May update encoder flag for like clock for SDVO TV, etc.*/
1526 if (ret == connector_status_connected) {
ea5b213a
CW		 1527 intel_sdvo->is_tv = false;
1528 intel_sdvo->is_lvds = false;
1529 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1530
1531 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1532 intel_sdvo->is_tv = true;
1533 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1534 }
1535 if (response & SDVO_LVDS_MASK)
8545423a 1536 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1537 }
14571b4c
ZW		 1538
1539 return ret;
79e53945
JB		 1540}
1541
e2f0ba97 1542static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1543{
df0e9248 1544 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
ff482d83 1545 struct edid *edid;
79e53945
JB		 1546
1547 /* set the bus switch and get the modes */
f899fc64 1548 edid = intel_sdvo_get_edid(connector, intel_sdvo->ddc_bus);
79e53945 1549
57cdaf90
KP		 1550 /*
1551 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1552 * link between analog and digital outputs. So, if the regular SDVO
1553 * DDC fails, check to see if the analog output is disconnected, in
1554 * which case we'll look there for the digital DDC data.
e2f0ba97 1555 */
f899fc64
CW		 1556 if (edid == NULL)
1557 edid = intel_sdvo_get_analog_edid(connector);
1558
ff482d83
CW		 1559 if (edid != NULL) {
1560 drm_mode_connector_update_edid_property(connector, edid);
1561 drm_add_edid_modes(connector, edid);
1562 connector->display_info.raw_edid = NULL;
1563 kfree(edid);
e2f0ba97 1564 }
e2f0ba97
JB		 1565}
1566
1567/*
1568 * Set of SDVO TV modes.
1569 * Note! This is in reply order (see loop in get_tv_modes).
1570 * XXX: all 60Hz refresh?
1571 */
1572struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1573 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1574 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1575 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1576 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1577 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1578 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1579 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1580 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1581 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1582 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1583 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1585 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1586 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1587 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1588 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1589 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1590 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1591 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1592 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1593 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1594 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1595 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1596 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1597 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1598 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1599 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1600 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1601 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1602 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1603 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1604 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1605 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1606 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1607 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1609 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1610 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1611 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1612 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1613 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1614 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1615 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1616 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1617 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1618 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1619 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1620 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1621 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1622 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1623 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1624 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1625 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1626 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1627 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1628 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1629 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1630};
1631
1632static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1633{
df0e9248 1634 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1635 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1636 uint32_t reply = 0, format_map = 0;
1637 int i;
e2f0ba97
JB		 1638
1639 /* Read the list of supported input resolutions for the selected TV
1640 * format.
1641 */
40039750 1642 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1643 memcpy(&tv_res, &format_map,
32aad86f 1644 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1645
32aad86f
CW		 1646 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1647 return;
ce6feabd 1648
32aad86f
CW		 1649 BUILD_BUG_ON(sizeof(tv_res) != 3);
1650 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1651 &tv_res, sizeof(tv_res)))
1652 return;
1653 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1654 return;
1655
1656 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1657 if (reply & (1 << i)) {
1658 struct drm_display_mode *nmode;
1659 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1660 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1661 if (nmode)
1662 drm_mode_probed_add(connector, nmode);
1663 }
e2f0ba97
JB		 1664}
1665
7086c87f
ML		 1666static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1667{
df0e9248 1668 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1669 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1670 struct drm_display_mode *newmode;
7086c87f
ML		 1671
1672 /*
1673 * Attempt to get the mode list from DDC.
1674 * Assume that the preferred modes are
1675 * arranged in priority order.
1676 */
f899fc64 1677 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1678 if (list_empty(&connector->probed_modes) == false)
12682a97 1679 goto end;
7086c87f
ML		 1680
1681 /* Fetch modes from VBT */
1682 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1683 newmode = drm_mode_duplicate(connector->dev,
1684 dev_priv->sdvo_lvds_vbt_mode);
1685 if (newmode != NULL) {
1686 /* Guarantee the mode is preferred */
1687 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1688 DRM_MODE_TYPE_DRIVER);
1689 drm_mode_probed_add(connector, newmode);
1690 }
1691 }
12682a97 1692
1693end:
1694 list_for_each_entry(newmode, &connector->probed_modes, head) {
1695 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1696 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1697 drm_mode_duplicate(connector->dev, newmode);
6c9547ff
CW		 1698
1699 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode,
1700 0);
1701
8545423a 1702 intel_sdvo->is_lvds = true;
12682a97 1703 break;
1704 }
1705 }
1706
7086c87f
ML		 1707}
1708
e2f0ba97
JB		 1709static int intel_sdvo_get_modes(struct drm_connector *connector)
1710{
615fb93f 1711 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1712
615fb93f 1713 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1714 intel_sdvo_get_tv_modes(connector);
615fb93f 1715 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1716 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1717 else
1718 intel_sdvo_get_ddc_modes(connector);
1719
32aad86f 1720 return !list_empty(&connector->probed_modes);
79e53945
JB		 1721}
1722
fcc8d672
CW		 1723static void
1724intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1725{
615fb93f 1726 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1727 struct drm_device *dev = connector->dev;
1728
c5521706
CW		 1729 if (intel_sdvo_connector->left)
1730 drm_property_destroy(dev, intel_sdvo_connector->left);
1731 if (intel_sdvo_connector->right)
1732 drm_property_destroy(dev, intel_sdvo_connector->right);
1733 if (intel_sdvo_connector->top)
1734 drm_property_destroy(dev, intel_sdvo_connector->top);
1735 if (intel_sdvo_connector->bottom)
1736 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1737 if (intel_sdvo_connector->hpos)
1738 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1739 if (intel_sdvo_connector->vpos)
1740 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1741 if (intel_sdvo_connector->saturation)
1742 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1743 if (intel_sdvo_connector->contrast)
1744 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1745 if (intel_sdvo_connector->hue)
1746 drm_property_destroy(dev, intel_sdvo_connector->hue);
1747 if (intel_sdvo_connector->sharpness)
1748 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1749 if (intel_sdvo_connector->flicker_filter)
1750 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1751 if (intel_sdvo_connector->flicker_filter_2d)
1752 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1753 if (intel_sdvo_connector->flicker_filter_adaptive)
1754 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1755 if (intel_sdvo_connector->tv_luma_filter)
1756 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1757 if (intel_sdvo_connector->tv_chroma_filter)
1758 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1759 if (intel_sdvo_connector->dot_crawl)
1760 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1761 if (intel_sdvo_connector->brightness)
1762 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1763}
1764
79e53945
JB		 1765static void intel_sdvo_destroy(struct drm_connector *connector)
1766{
615fb93f 1767 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1768
c5521706 1769 if (intel_sdvo_connector->tv_format)
ce6feabd 1770 drm_property_destroy(connector->dev,
c5521706 1771 intel_sdvo_connector->tv_format);
b9219c5e 1772
d2a82a6f 1773 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1774 drm_sysfs_connector_remove(connector);
1775 drm_connector_cleanup(connector);
d2a82a6f 1776 kfree(connector);
79e53945
JB		 1777}
1778
ce6feabd
ZY		 1779static int
1780intel_sdvo_set_property(struct drm_connector *connector,
1781 struct drm_property *property,
1782 uint64_t val)
1783{
df0e9248 1784 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1785 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e 1786 uint16_t temp_value;
32aad86f
CW		 1787 uint8_t cmd;
1788 int ret;
ce6feabd
ZY		 1789
1790 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1791 if (ret)
1792 return ret;
ce6feabd 1793
c5521706
CW		 1794#define CHECK_PROPERTY(name, NAME) \
1795 if (intel_sdvo_connector->name == property) { \
1796 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1797 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1798 cmd = SDVO_CMD_SET_##NAME; \
1799 intel_sdvo_connector->cur_##name = temp_value; \
1800 goto set_value; \
1801 }
1802
1803 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1804 if (val >= TV_FORMAT_NUM)
1805 return -EINVAL;
1806
40039750 1807 if (intel_sdvo->tv_format_index ==
615fb93f 1808 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1809 return 0;
ce6feabd 1810
40039750 1811 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1812 goto done;
32aad86f 1813 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1814 temp_value = val;
c5521706 1815 if (intel_sdvo_connector->left == property) {
b9219c5e 1816 drm_connector_property_set_value(connector,
c5521706 1817 intel_sdvo_connector->right, val);
615fb93f 1818 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1819 return 0;
b9219c5e 1820
615fb93f
CW		 1821 intel_sdvo_connector->left_margin = temp_value;
1822 intel_sdvo_connector->right_margin = temp_value;
1823 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1824 intel_sdvo_connector->left_margin;
b9219c5e 1825 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1826 goto set_value;
1827 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1828 drm_connector_property_set_value(connector,
c5521706 1829 intel_sdvo_connector->left, val);
615fb93f 1830 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1831 return 0;
b9219c5e 1832
615fb93f
CW		 1833 intel_sdvo_connector->left_margin = temp_value;
1834 intel_sdvo_connector->right_margin = temp_value;
1835 temp_value = intel_sdvo_connector->max_hscan -
1836 intel_sdvo_connector->left_margin;
b9219c5e 1837 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1838 goto set_value;
1839 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1840 drm_connector_property_set_value(connector,
c5521706 1841 intel_sdvo_connector->bottom, val);
615fb93f 1842 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1843 return 0;
b9219c5e 1844
615fb93f
CW		 1845 intel_sdvo_connector->top_margin = temp_value;
1846 intel_sdvo_connector->bottom_margin = temp_value;
1847 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1848 intel_sdvo_connector->top_margin;
b9219c5e 1849 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1850 goto set_value;
1851 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1852 drm_connector_property_set_value(connector,
c5521706 1853 intel_sdvo_connector->top, val);
615fb93f 1854 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1855 return 0;
1856
615fb93f
CW		 1857 intel_sdvo_connector->top_margin = temp_value;
1858 intel_sdvo_connector->bottom_margin = temp_value;
1859 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1860 intel_sdvo_connector->top_margin;
b9219c5e 1861 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1862 goto set_value;
1863 }
1864 CHECK_PROPERTY(hpos, HPOS)
1865 CHECK_PROPERTY(vpos, VPOS)
1866 CHECK_PROPERTY(saturation, SATURATION)
1867 CHECK_PROPERTY(contrast, CONTRAST)
1868 CHECK_PROPERTY(hue, HUE)
1869 CHECK_PROPERTY(brightness, BRIGHTNESS)
1870 CHECK_PROPERTY(sharpness, SHARPNESS)
1871 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1872 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1873 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1874 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1875 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1876 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1877 }
b9219c5e 1878
c5521706 1879 return -EINVAL; /* unknown property */
b9219c5e 1880
c5521706
CW		 1881set_value:
1882 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1883 return -EIO;
b9219c5e 1884
b9219c5e 1885
c5521706 1886done:
df0e9248
CW		 1887 if (intel_sdvo->base.base.crtc) {
1888 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
ce6feabd 1889 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1890 crtc->y, crtc->fb);
1891 }
1892
32aad86f 1893 return 0;
c5521706 1894#undef CHECK_PROPERTY
ce6feabd
ZY		 1895}
1896
79e53945
JB		 1897static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1898 .dpms = intel_sdvo_dpms,
1899 .mode_fixup = intel_sdvo_mode_fixup,
1900 .prepare = intel_encoder_prepare,
1901 .mode_set = intel_sdvo_mode_set,
1902 .commit = intel_encoder_commit,
1903};
1904
1905static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1906 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1907 .detect = intel_sdvo_detect,
1908 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1909 .set_property = intel_sdvo_set_property,
79e53945
JB		 1910 .destroy = intel_sdvo_destroy,
1911};
1912
1913static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1914 .get_modes = intel_sdvo_get_modes,
1915 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1916 .best_encoder = intel_best_encoder,
79e53945
JB		 1917};
1918
b358d0a6 1919static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1920{
890f3359 1921 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 1922
ea5b213a 1923 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1924 drm_mode_destroy(encoder->dev,
ea5b213a 1925 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1926
ea5b213a 1927 intel_encoder_destroy(encoder);
79e53945
JB		 1928}
1929
1930static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1931 .destroy = intel_sdvo_enc_destroy,
1932};
1933
b66d8424
CW		 1934static void
1935intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1936{
1937 uint16_t mask = 0;
1938 unsigned int num_bits;
1939
1940 /* Make a mask of outputs less than or equal to our own priority in the
1941 * list.
1942 */
1943 switch (sdvo->controlled_output) {
1944 case SDVO_OUTPUT_LVDS1:
1945 mask |= SDVO_OUTPUT_LVDS1;
1946 case SDVO_OUTPUT_LVDS0:
1947 mask |= SDVO_OUTPUT_LVDS0;
1948 case SDVO_OUTPUT_TMDS1:
1949 mask |= SDVO_OUTPUT_TMDS1;
1950 case SDVO_OUTPUT_TMDS0:
1951 mask |= SDVO_OUTPUT_TMDS0;
1952 case SDVO_OUTPUT_RGB1:
1953 mask |= SDVO_OUTPUT_RGB1;
1954 case SDVO_OUTPUT_RGB0:
1955 mask |= SDVO_OUTPUT_RGB0;
1956 break;
1957 }
1958
1959 /* Count bits to find what number we are in the priority list. */
1960 mask &= sdvo->caps.output_flags;
1961 num_bits = hweight16(mask);
1962 /* If more than 3 outputs, default to DDC bus 3 for now. */
1963 if (num_bits > 3)
1964 num_bits = 3;
1965
1966 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1967 sdvo->ddc_bus = 1 << num_bits;
1968}
79e53945 1969
e2f0ba97
JB		 1970/**
1971 * Choose the appropriate DDC bus for control bus switch command for this
1972 * SDVO output based on the controlled output.
1973 *
1974 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1975 * outputs, then LVDS outputs.
1976 */
1977static void
b1083333 1978intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1979 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1980{
b1083333 1981 struct sdvo_device_mapping *mapping;
e2f0ba97 1982
b1083333
AJ		 1983 if (IS_SDVOB(reg))
1984 mapping = &(dev_priv->sdvo_mappings[0]);
1985 else
1986 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1987
b66d8424
CW		 1988 if (mapping->initialized)
1989 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1990 else
1991 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1992}
1993
1994static bool
ea5b213a 1995intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1996{
32aad86f
CW		 1997 return intel_sdvo_set_target_output(intel_sdvo,
1998 device == 0 ? SDVO_OUTPUT_TMDS0 : SDVO_OUTPUT_TMDS1) &&
1999 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
2000 &intel_sdvo->is_hdmi, 1);
e2f0ba97
JB		 2001}
2002
714605e4 2003static u8
c751ce4f 2004intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
714605e4 2005{
2006 struct drm_i915_private *dev_priv = dev->dev_private;
2007 struct sdvo_device_mapping *my_mapping, *other_mapping;
2008
461ed3ca 2009 if (IS_SDVOB(sdvo_reg)) {
714605e4 2010 my_mapping = &dev_priv->sdvo_mappings[0];
2011 other_mapping = &dev_priv->sdvo_mappings[1];
2012 } else {
2013 my_mapping = &dev_priv->sdvo_mappings[1];
2014 other_mapping = &dev_priv->sdvo_mappings[0];
2015 }
2016
2017 /* If the BIOS described our SDVO device, take advantage of it. */
2018 if (my_mapping->slave_addr)
2019 return my_mapping->slave_addr;
2020
2021 /* If the BIOS only described a different SDVO device, use the
2022 * address that it isn't using.
2023 */
2024 if (other_mapping->slave_addr) {
2025 if (other_mapping->slave_addr == 0x70)
2026 return 0x72;
2027 else
2028 return 0x70;
2029 }
2030
2031 /* No SDVO device info is found for another DVO port,
2032 * so use mapping assumption we had before BIOS parsing.
2033 */
461ed3ca 2034 if (IS_SDVOB(sdvo_reg))
714605e4 2035 return 0x70;
2036 else
2037 return 0x72;
2038}
2039
14571b4c 2040static void
df0e9248
CW		 2041intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2042 struct intel_sdvo *encoder)
14571b4c 2043{
df0e9248
CW		 2044 drm_connector_init(encoder->base.base.dev,
2045 &connector->base.base,
2046 &intel_sdvo_connector_funcs,
2047 connector->base.base.connector_type);
6070a4a9 2048
df0e9248
CW		 2049 drm_connector_helper_add(&connector->base.base,
2050 &intel_sdvo_connector_helper_funcs);
14571b4c 2051
df0e9248
CW		 2052 connector->base.base.interlace_allowed = 0;
2053 connector->base.base.doublescan_allowed = 0;
2054 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
14571b4c 2055
df0e9248
CW		 2056 intel_connector_attach_encoder(&connector->base, &encoder->base);
2057 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2058}
6070a4a9 2059
fb7a46f3 2060static bool
ea5b213a 2061intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2062{
4ef69c7a 2063 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c
ZW		 2064 struct drm_connector *connector;
2065 struct intel_connector *intel_connector;
615fb93f 2066 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2067
615fb93f
CW		 2068 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2069 if (!intel_sdvo_connector)
14571b4c
ZW		 2070 return false;
2071
14571b4c 2072 if (device == 0) {
ea5b213a 2073 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2074 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2075 } else if (device == 1) {
ea5b213a 2076 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2077 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2078 }
2079
615fb93f 2080 intel_connector = &intel_sdvo_connector->base;
14571b4c 2081 connector = &intel_connector->base;
eb1f8e4f 2082 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2083 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2084 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2085
ea5b213a
CW		 2086 if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode)
2087 && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device)
2088 && intel_sdvo->is_hdmi) {
14571b4c 2089 /* enable hdmi encoding mode if supported */
ea5b213a
CW		 2090 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
2091 intel_sdvo_set_colorimetry(intel_sdvo,
14571b4c
ZW		 2092 SDVO_COLORIMETRY_RGB256);
2093 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2094 }
ea5b213a
CW		 2095 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2096 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2097
df0e9248 2098 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c
ZW		 2099
2100 return true;
2101}
2102
2103static bool
ea5b213a 2104intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2105{
4ef69c7a
CW		 2106 struct drm_encoder *encoder = &intel_sdvo->base.base;
2107 struct drm_connector *connector;
2108 struct intel_connector *intel_connector;
2109 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2110
615fb93f
CW		 2111 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2112 if (!intel_sdvo_connector)
2113 return false;
14571b4c 2114
615fb93f 2115 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2116 connector = &intel_connector->base;
2117 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2118 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2119
4ef69c7a
CW		 2120 intel_sdvo->controlled_output |= type;
2121 intel_sdvo_connector->output_flag = type;
14571b4c 2122
4ef69c7a
CW		 2123 intel_sdvo->is_tv = true;
2124 intel_sdvo->base.needs_tv_clock = true;
2125 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2126
df0e9248 2127 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2128
4ef69c7a 2129 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2130 goto err;
14571b4c 2131
4ef69c7a 2132 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2133 goto err;
14571b4c 2134
4ef69c7a 2135 return true;
32aad86f
CW		 2136
2137err:
fcc8d672 2138 intel_sdvo_destroy_enhance_property(connector);
32aad86f
CW		 2139 kfree(intel_sdvo_connector);
2140 return false;
14571b4c
ZW		 2141}
2142
2143static bool
ea5b213a 2144intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2145{
4ef69c7a
CW		 2146 struct drm_encoder *encoder = &intel_sdvo->base.base;
2147 struct drm_connector *connector;
2148 struct intel_connector *intel_connector;
2149 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2150
615fb93f
CW		 2151 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2152 if (!intel_sdvo_connector)
2153 return false;
14571b4c 2154
615fb93f 2155 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2156 connector = &intel_connector->base;
eb1f8e4f 2157 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2158 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2159 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2160
2161 if (device == 0) {
2162 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2163 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2164 } else if (device == 1) {
2165 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2166 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2167 }
2168
2169 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
ea5b213a 2170 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2171
df0e9248
CW		 2172 intel_sdvo_connector_init(intel_sdvo_connector,
2173 intel_sdvo);
4ef69c7a 2174 return true;
14571b4c
ZW		 2175}
2176
2177static bool
ea5b213a 2178intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2179{
4ef69c7a
CW		 2180 struct drm_encoder *encoder = &intel_sdvo->base.base;
2181 struct drm_connector *connector;
2182 struct intel_connector *intel_connector;
2183 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2184
615fb93f
CW		 2185 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2186 if (!intel_sdvo_connector)
2187 return false;
14571b4c 2188
615fb93f
CW		 2189 intel_connector = &intel_sdvo_connector->base;
2190 connector = &intel_connector->base;
4ef69c7a
CW		 2191 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2192 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2193
2194 if (device == 0) {
2195 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2196 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2197 } else if (device == 1) {
2198 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2199 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2200 }
2201
2202 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
ea5b213a 2203 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2204
df0e9248 2205 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2206 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2207 goto err;
2208
2209 return true;
2210
2211err:
fcc8d672 2212 intel_sdvo_destroy_enhance_property(connector);
32aad86f
CW		 2213 kfree(intel_sdvo_connector);
2214 return false;
14571b4c
ZW		 2215}
2216
2217static bool
ea5b213a 2218intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2219{
ea5b213a
CW		 2220 intel_sdvo->is_tv = false;
2221 intel_sdvo->base.needs_tv_clock = false;
2222 intel_sdvo->is_lvds = false;
fb7a46f3 2223
14571b4c 2224 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2225
14571b4c 2226 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2227 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2228 return false;
2229
2230 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2231 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2232 return false;
2233
2234 /* TV has no XXX1 function block */
a1f4b7ff 2235 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2236 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2237 return false;
2238
2239 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2240 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2241 return false;
fb7a46f3 2242
14571b4c 2243 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2244 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2245 return false;
2246
2247 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2248 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2249 return false;
2250
2251 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2252 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2253 return false;
2254
2255 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2256 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2257 return false;
fb7a46f3 2258
14571b4c 2259 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2260 unsigned char bytes[2];
2261
ea5b213a
CW		 2262 intel_sdvo->controlled_output = 0;
2263 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2264 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2265 SDVO_NAME(intel_sdvo),
51c8b407 2266 bytes[0], bytes[1]);
14571b4c 2267 return false;
fb7a46f3 2268 }
ea5b213a 2269 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
fb7a46f3 2270
14571b4c 2271 return true;
fb7a46f3 2272}
2273
32aad86f
CW		 2274static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2275 struct intel_sdvo_connector *intel_sdvo_connector,
2276 int type)
ce6feabd 2277{
4ef69c7a 2278 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2279 struct intel_sdvo_tv_format format;
2280 uint32_t format_map, i;
ce6feabd 2281
32aad86f
CW		 2282 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2283 return false;
ce6feabd 2284
32aad86f
CW		 2285 if (!intel_sdvo_get_value(intel_sdvo,
2286 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2287 &format, sizeof(format)))
2288 return false;
ce6feabd 2289
32aad86f 2290 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2291
2292 if (format_map == 0)
32aad86f 2293 return false;
ce6feabd 2294
615fb93f 2295 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2296 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2297 if (format_map & (1 << i))
2298 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2299
2300
c5521706 2301 intel_sdvo_connector->tv_format =
32aad86f
CW		 2302 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2303 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2304 if (!intel_sdvo_connector->tv_format)
fcc8d672 2305 return false;
ce6feabd 2306
615fb93f 2307 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2308 drm_property_add_enum(
c5521706 2309 intel_sdvo_connector->tv_format, i,
40039750 2310 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2311
40039750 2312 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2313 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2314 intel_sdvo_connector->tv_format, 0);
32aad86f 2315 return true;
ce6feabd
ZY		 2316
2317}
2318
c5521706
CW		 2319#define ENHANCEMENT(name, NAME) do { \
2320 if (enhancements.name) { \
2321 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2322 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2323 return false; \
2324 intel_sdvo_connector->max_##name = data_value[0]; \
2325 intel_sdvo_connector->cur_##name = response; \
2326 intel_sdvo_connector->name = \
2327 drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
2328 if (!intel_sdvo_connector->name) return false; \
2329 intel_sdvo_connector->name->values[0] = 0; \
2330 intel_sdvo_connector->name->values[1] = data_value[0]; \
2331 drm_connector_attach_property(connector, \
2332 intel_sdvo_connector->name, \
2333 intel_sdvo_connector->cur_##name); \
2334 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2335 data_value[0], data_value[1], response); \
2336 } \
2337} while(0)
2338
2339static bool
2340intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2341 struct intel_sdvo_connector *intel_sdvo_connector,
2342 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2343{
4ef69c7a 2344 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2345 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2346 uint16_t response, data_value[2];
2347
c5521706
CW		 2348 /* when horizontal overscan is supported, Add the left/right property */
2349 if (enhancements.overscan_h) {
2350 if (!intel_sdvo_get_value(intel_sdvo,
2351 SDVO_CMD_GET_MAX_OVERSCAN_H,
2352 &data_value, 4))
2353 return false;
32aad86f 2354
c5521706
CW		 2355 if (!intel_sdvo_get_value(intel_sdvo,
2356 SDVO_CMD_GET_OVERSCAN_H,
2357 &response, 2))
2358 return false;
fcc8d672 2359
c5521706
CW		 2360 intel_sdvo_connector->max_hscan = data_value[0];
2361 intel_sdvo_connector->left_margin = data_value[0] - response;
2362 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2363 intel_sdvo_connector->left =
2364 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2365 "left_margin", 2);
2366 if (!intel_sdvo_connector->left)
2367 return false;
fcc8d672 2368
c5521706
CW		 2369 intel_sdvo_connector->left->values[0] = 0;
2370 intel_sdvo_connector->left->values[1] = data_value[0];
2371 drm_connector_attach_property(connector,
2372 intel_sdvo_connector->left,
2373 intel_sdvo_connector->left_margin);
fcc8d672 2374
c5521706
CW		 2375 intel_sdvo_connector->right =
2376 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2377 "right_margin", 2);
2378 if (!intel_sdvo_connector->right)
2379 return false;
32aad86f 2380
c5521706
CW		 2381 intel_sdvo_connector->right->values[0] = 0;
2382 intel_sdvo_connector->right->values[1] = data_value[0];
2383 drm_connector_attach_property(connector,
2384 intel_sdvo_connector->right,
2385 intel_sdvo_connector->right_margin);
2386 DRM_DEBUG_KMS("h_overscan: max %d, "
2387 "default %d, current %d\n",
2388 data_value[0], data_value[1], response);
2389 }
32aad86f 2390
c5521706
CW		 2391 if (enhancements.overscan_v) {
2392 if (!intel_sdvo_get_value(intel_sdvo,
2393 SDVO_CMD_GET_MAX_OVERSCAN_V,
2394 &data_value, 4))
2395 return false;
fcc8d672 2396
c5521706
CW		 2397 if (!intel_sdvo_get_value(intel_sdvo,
2398 SDVO_CMD_GET_OVERSCAN_V,
2399 &response, 2))
2400 return false;
32aad86f 2401
c5521706
CW		 2402 intel_sdvo_connector->max_vscan = data_value[0];
2403 intel_sdvo_connector->top_margin = data_value[0] - response;
2404 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2405 intel_sdvo_connector->top =
2406 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2407 "top_margin", 2);
2408 if (!intel_sdvo_connector->top)
2409 return false;
32aad86f 2410
c5521706
CW		 2411 intel_sdvo_connector->top->values[0] = 0;
2412 intel_sdvo_connector->top->values[1] = data_value[0];
2413 drm_connector_attach_property(connector,
2414 intel_sdvo_connector->top,
2415 intel_sdvo_connector->top_margin);
fcc8d672 2416
c5521706
CW		 2417 intel_sdvo_connector->bottom =
2418 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2419 "bottom_margin", 2);
2420 if (!intel_sdvo_connector->bottom)
2421 return false;
32aad86f 2422
c5521706
CW		 2423 intel_sdvo_connector->bottom->values[0] = 0;
2424 intel_sdvo_connector->bottom->values[1] = data_value[0];
2425 drm_connector_attach_property(connector,
2426 intel_sdvo_connector->bottom,
2427 intel_sdvo_connector->bottom_margin);
2428 DRM_DEBUG_KMS("v_overscan: max %d, "
2429 "default %d, current %d\n",
2430 data_value[0], data_value[1], response);
2431 }
32aad86f 2432
c5521706
CW		 2433 ENHANCEMENT(hpos, HPOS);
2434 ENHANCEMENT(vpos, VPOS);
2435 ENHANCEMENT(saturation, SATURATION);
2436 ENHANCEMENT(contrast, CONTRAST);
2437 ENHANCEMENT(hue, HUE);
2438 ENHANCEMENT(sharpness, SHARPNESS);
2439 ENHANCEMENT(brightness, BRIGHTNESS);
2440 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2441 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2442 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2443 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2444 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2445
e044218a
CW		 2446 if (enhancements.dot_crawl) {
2447 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2448 return false;
2449
2450 intel_sdvo_connector->max_dot_crawl = 1;
2451 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2452 intel_sdvo_connector->dot_crawl =
2453 drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2);
2454 if (!intel_sdvo_connector->dot_crawl)
2455 return false;
2456
2457 intel_sdvo_connector->dot_crawl->values[0] = 0;
2458 intel_sdvo_connector->dot_crawl->values[1] = 1;
2459 drm_connector_attach_property(connector,
2460 intel_sdvo_connector->dot_crawl,
2461 intel_sdvo_connector->cur_dot_crawl);
2462 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2463 }
2464
c5521706
CW		 2465 return true;
2466}
32aad86f 2467
c5521706
CW		 2468static bool
2469intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2470 struct intel_sdvo_connector *intel_sdvo_connector,
2471 struct intel_sdvo_enhancements_reply enhancements)
2472{
4ef69c7a 2473 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2474 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2475 uint16_t response, data_value[2];
32aad86f 2476
c5521706 2477 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2478
c5521706
CW		 2479 return true;
2480}
2481#undef ENHANCEMENT
32aad86f 2482
c5521706
CW		 2483static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2484 struct intel_sdvo_connector *intel_sdvo_connector)
2485{
2486 union {
2487 struct intel_sdvo_enhancements_reply reply;
2488 uint16_t response;
2489 } enhancements;
32aad86f 2490
c5521706
CW		 2491 if (!intel_sdvo_get_value(intel_sdvo,
2492 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2493 &enhancements, sizeof(enhancements)))
2494 return false;
fcc8d672 2495
c5521706
CW		 2496 if (enhancements.response == 0) {
2497 DRM_DEBUG_KMS("No enhancement is supported\n");
2498 return true;
b9219c5e 2499 }
32aad86f 2500
c5521706
CW		 2501 if (IS_TV(intel_sdvo_connector))
2502 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2503 else if(IS_LVDS(intel_sdvo_connector))
2504 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2505 else
2506 return true;
fcc8d672 2507
b9219c5e
ZY		 2508}
2509
c751ce4f 2510bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
79e53945 2511{
b01f2c3a 2512 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2513 struct intel_encoder *intel_encoder;
ea5b213a 2514 struct intel_sdvo *intel_sdvo;
79e53945 2515 int i;
79e53945 2516
ea5b213a
CW		 2517 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2518 if (!intel_sdvo)
7d57382e 2519 return false;
79e53945 2520
ea5b213a 2521 intel_sdvo->sdvo_reg = sdvo_reg;
308cd3a2 2522
ea5b213a 2523 intel_encoder = &intel_sdvo->base;
21d40d37 2524 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7
CW		 2525 /* encoder type will be decided later */
2526 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2527
f899fc64 2528 intel_sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
79e53945 2529
ea5b213a 2530 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
79e53945 2531
79e53945
JB		 2532 /* Read the regs to test if we can talk to the device */
2533 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2534 u8 byte;
2535
2536 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
8a4c47f3 2537 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
461ed3ca 2538 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
f899fc64 2539 goto err;
79e53945
JB		 2540 }
2541 }
2542
f899fc64 2543 if (IS_SDVOB(sdvo_reg))
b01f2c3a 2544 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
f899fc64 2545 else
b01f2c3a 2546 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
619ac3b7 2547
4ef69c7a 2548 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2549
af901ca1 2550 /* In default case sdvo lvds is false */
32aad86f 2551 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2552 goto err;
79e53945 2553
ea5b213a
CW		 2554 if (intel_sdvo_output_setup(intel_sdvo,
2555 intel_sdvo->caps.output_flags) != true) {
51c8b407 2556 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
461ed3ca 2557 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
f899fc64 2558 goto err;
79e53945
JB		 2559 }
2560
ea5b213a 2561 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2562
79e53945 2563 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2564 if (!intel_sdvo_set_target_input(intel_sdvo))
f899fc64 2565 goto err;
79e53945 2566
32aad86f
CW		 2567 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2568 &intel_sdvo->pixel_clock_min,
2569 &intel_sdvo->pixel_clock_max))
f899fc64 2570 goto err;
79e53945 2571
8a4c47f3 2572 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2573 "clock range %dMHz - %dMHz, "
2574 "input 1: %c, input 2: %c, "
2575 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2576 SDVO_NAME(intel_sdvo),
2577 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2578 intel_sdvo->caps.device_rev_id,
2579 intel_sdvo->pixel_clock_min / 1000,
2580 intel_sdvo->pixel_clock_max / 1000,
2581 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2582 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2583 /* check currently supported outputs */
ea5b213a 2584 intel_sdvo->caps.output_flags &
79e53945 2585 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2586 intel_sdvo->caps.output_flags &
79e53945 2587 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2588 return true;
79e53945 2589
f899fc64 2590err:
373a3cf7 2591 drm_encoder_cleanup(&intel_encoder->base);
ea5b213a 2592 kfree(intel_sdvo);
79e53945 2593
7d57382e 2594 return false;
79e53945 2595}
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