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drm/i915: Fix multifunction SDVO detection
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945
JB		 30#include <linux/delay.h>
31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
2b8d33f7 34#include "drm_edid.h"
ea5b213a 35#include "intel_drv.h"
79e53945
JB		 36#include "i915_drm.h"
37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 46 SDVO_TV_MASK)
14571b4c
ZW		 47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 50#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 51#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
14571b4c 52
79e53945 53
2e88e40b 54static const char *tv_format_names[] = {
ce6feabd
ZY		 55 "NTSC_M" , "NTSC_J" , "NTSC_443",
56 "PAL_B" , "PAL_D" , "PAL_G" ,
57 "PAL_H" , "PAL_I" , "PAL_M" ,
58 "PAL_N" , "PAL_NC" , "PAL_60" ,
59 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
60 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
61 "SECAM_60"
62};
63
64#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
65
ea5b213a
CW		 66struct intel_sdvo {
67 struct intel_encoder base;
68
f899fc64 69 struct i2c_adapter *i2c;
f9c10a9b 70 u8 slave_addr;
e2f0ba97 71
e957d772
CW		 72 struct i2c_adapter ddc;
73
e2f0ba97 74 /* Register for the SDVO device: SDVOB or SDVOC */
c751ce4f 75 int sdvo_reg;
79e53945 76
e2f0ba97
JB		 77 /* Active outputs controlled by this SDVO output */
78 uint16_t controlled_output;
79e53945 79
e2f0ba97
JB		 80 /*
81 * Capabilities of the SDVO device returned by
82 * i830_sdvo_get_capabilities()
83 */
79e53945 84 struct intel_sdvo_caps caps;
e2f0ba97
JB		 85
86 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 87 int pixel_clock_min, pixel_clock_max;
88
fb7a46f3 89 /*
90 * For multiple function SDVO device,
91 * this is for current attached outputs.
92 */
93 uint16_t attached_output;
94
cc68c81a
SF		 95 /*
96 * Hotplug activation bits for this device
97 */
98 uint8_t hotplug_active[2];
99
e953fd7b
CW		 100 /**
101 * This is used to select the color range of RBG outputs in HDMI mode.
102 * It is only valid when using TMDS encoding and 8 bit per color mode.
103 */
104 uint32_t color_range;
105
e2f0ba97
JB		 106 /**
107 * This is set if we're going to treat the device as TV-out.
108 *
109 * While we have these nice friendly flags for output types that ought
110 * to decide this for us, the S-Video output on our HDMI+S-Video card
111 * shows up as RGB1 (VGA).
112 */
113 bool is_tv;
114
ce6feabd 115 /* This is for current tv format name */
40039750 116 int tv_format_index;
ce6feabd 117
e2f0ba97
JB		 118 /**
119 * This is set if we treat the device as HDMI, instead of DVI.
120 */
121 bool is_hdmi;
da79de97
CW		 122 bool has_hdmi_monitor;
123 bool has_hdmi_audio;
12682a97 124
7086c87f 125 /**
6c9547ff
CW		 126 * This is set if we detect output of sdvo device as LVDS and
127 * have a valid fixed mode to use with the panel.
7086c87f
ML		 128 */
129 bool is_lvds;
e2f0ba97 130
12682a97 131 /**
132 * This is sdvo fixed pannel mode pointer
133 */
134 struct drm_display_mode *sdvo_lvds_fixed_mode;
135
c751ce4f 136 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 137 uint8_t ddc_bus;
138
6c9547ff
CW		 139 /* Input timings for adjusted_mode */
140 struct intel_sdvo_dtd input_dtd;
14571b4c
ZW		 141};
142
143struct intel_sdvo_connector {
615fb93f
CW		 144 struct intel_connector base;
145
14571b4c
ZW		 146 /* Mark the type of connector */
147 uint16_t output_flag;
148
7f36e7ed
CW		 149 int force_audio;
150
14571b4c 151 /* This contains all current supported TV format */
40039750 152 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 153 int format_supported_num;
c5521706 154 struct drm_property *tv_format;
14571b4c 155
b9219c5e 156 /* add the property for the SDVO-TV */
c5521706
CW		 157 struct drm_property *left;
158 struct drm_property *right;
159 struct drm_property *top;
160 struct drm_property *bottom;
161 struct drm_property *hpos;
162 struct drm_property *vpos;
163 struct drm_property *contrast;
164 struct drm_property *saturation;
165 struct drm_property *hue;
166 struct drm_property *sharpness;
167 struct drm_property *flicker_filter;
168 struct drm_property *flicker_filter_adaptive;
169 struct drm_property *flicker_filter_2d;
170 struct drm_property *tv_chroma_filter;
171 struct drm_property *tv_luma_filter;
e044218a 172 struct drm_property *dot_crawl;
b9219c5e
ZY		 173
174 /* add the property for the SDVO-TV/LVDS */
c5521706 175 struct drm_property *brightness;
b9219c5e
ZY		 176
177 /* Add variable to record current setting for the above property */
178 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 179
b9219c5e
ZY		 180 /* this is to get the range of margin.*/
181 u32 max_hscan, max_vscan;
182 u32 max_hpos, cur_hpos;
183 u32 max_vpos, cur_vpos;
184 u32 cur_brightness, max_brightness;
185 u32 cur_contrast, max_contrast;
186 u32 cur_saturation, max_saturation;
187 u32 cur_hue, max_hue;
c5521706
CW		 188 u32 cur_sharpness, max_sharpness;
189 u32 cur_flicker_filter, max_flicker_filter;
190 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
191 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
192 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
193 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 194 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 195};
196
890f3359 197static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 198{
4ef69c7a 199 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 200}
201
df0e9248
CW		 202static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
203{
204 return container_of(intel_attached_encoder(connector),
205 struct intel_sdvo, base);
206}
207
615fb93f
CW		 208static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
209{
210 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
211}
212
fb7a46f3 213static bool
ea5b213a 214intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 215static bool
216intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
217 struct intel_sdvo_connector *intel_sdvo_connector,
218 int type);
219static bool
220intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
221 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 222
79e53945
JB		 223/**
224 * Writes the SDVOB or SDVOC with the given value, but always writes both
225 * SDVOB and SDVOC to work around apparent hardware issues (according to
226 * comments in the BIOS).
227 */
ea5b213a 228static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 229{
4ef69c7a 230 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 231 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 232 u32 bval = val, cval = val;
233 int i;
234
ea5b213a
CW		 235 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
236 I915_WRITE(intel_sdvo->sdvo_reg, val);
237 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 238 return;
239 }
240
ea5b213a 241 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 242 cval = I915_READ(SDVOC);
243 } else {
244 bval = I915_READ(SDVOB);
245 }
246 /*
247 * Write the registers twice for luck. Sometimes,
248 * writing them only once doesn't appear to 'stick'.
249 * The BIOS does this too. Yay, magic
250 */
251 for (i = 0; i < 2; i++)
252 {
253 I915_WRITE(SDVOB, bval);
254 I915_READ(SDVOB);
255 I915_WRITE(SDVOC, cval);
256 I915_READ(SDVOC);
257 }
258}
259
32aad86f 260static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 261{
79e53945
JB		 262 struct i2c_msg msgs[] = {
263 {
e957d772 264 .addr = intel_sdvo->slave_addr,
79e53945
JB		 265 .flags = 0,
266 .len = 1,
e957d772 267 .buf = &addr,
79e53945
JB		 268 },
269 {
e957d772 270 .addr = intel_sdvo->slave_addr,
79e53945
JB		 271 .flags = I2C_M_RD,
272 .len = 1,
e957d772 273 .buf = ch,
79e53945
JB		 274 }
275 };
32aad86f 276 int ret;
79e53945 277
f899fc64 278 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 279 return true;
79e53945 280
8a4c47f3 281 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 282 return false;
283}
284
79e53945
JB		 285#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
286/** Mapping of command numbers to names, for debug output */
005568be 287static const struct _sdvo_cmd_name {
e2f0ba97 288 u8 cmd;
2e88e40b 289 const char *name;
79e53945 290} sdvo_cmd_names[] = {
0206e353
AJ		 291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
334
335 /* Add the op code for SDVO enhancements */
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
380
381 /* HDMI op code */
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 402};
403
461ed3ca 404#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
ea5b213a 405#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
79e53945 406
ea5b213a 407static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 408 const void *args, int args_len)
79e53945 409{
79e53945
JB		 410 int i;
411
8a4c47f3 412 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 413 SDVO_NAME(intel_sdvo), cmd);
79e53945 414 for (i = 0; i < args_len; i++)
342dc382 415 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 416 for (; i < 8; i++)
342dc382 417 DRM_LOG_KMS(" ");
04ad327f 418 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 419 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 420 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 421 break;
422 }
423 }
04ad327f 424 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 425 DRM_LOG_KMS("(%02X)", cmd);
426 DRM_LOG_KMS("\n");
79e53945 427}
79e53945 428
e957d772
CW		 429static const char *cmd_status_names[] = {
430 "Power on",
431 "Success",
432 "Not supported",
433 "Invalid arg",
434 "Pending",
435 "Target not specified",
436 "Scaling not supported"
437};
438
32aad86f
CW		 439static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
440 const void *args, int args_len)
79e53945 441{
e957d772
CW		 442 u8 buf[args_len*2 + 2], status;
443 struct i2c_msg msgs[args_len + 3];
444 int i, ret;
79e53945 445
ea5b213a 446 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 447
448 for (i = 0; i < args_len; i++) {
e957d772
CW		 449 msgs[i].addr = intel_sdvo->slave_addr;
450 msgs[i].flags = 0;
451 msgs[i].len = 2;
452 msgs[i].buf = buf + 2 *i;
453 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
454 buf[2*i + 1] = ((u8*)args)[i];
455 }
456 msgs[i].addr = intel_sdvo->slave_addr;
457 msgs[i].flags = 0;
458 msgs[i].len = 2;
459 msgs[i].buf = buf + 2*i;
460 buf[2*i + 0] = SDVO_I2C_OPCODE;
461 buf[2*i + 1] = cmd;
462
463 /* the following two are to read the response */
464 status = SDVO_I2C_CMD_STATUS;
465 msgs[i+1].addr = intel_sdvo->slave_addr;
466 msgs[i+1].flags = 0;
467 msgs[i+1].len = 1;
468 msgs[i+1].buf = &status;
469
470 msgs[i+2].addr = intel_sdvo->slave_addr;
471 msgs[i+2].flags = I2C_M_RD;
472 msgs[i+2].len = 1;
473 msgs[i+2].buf = &status;
474
475 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
476 if (ret < 0) {
477 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
478 return false;
479 }
480 if (ret != i+3) {
481 /* failure in I2C transfer */
482 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
483 return false;
484 }
485
e957d772 486 return true;
79e53945
JB		 487}
488
b5c616a7
CW		 489static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
490 void *response, int response_len)
79e53945 491{
b5c616a7
CW		 492 u8 retry = 5;
493 u8 status;
33b52961 494 int i;
79e53945 495
d121a5d2
CW		 496 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
497
b5c616a7
CW		 498 /*
499 * The documentation states that all commands will be
500 * processed within 15µs, and that we need only poll
501 * the status byte a maximum of 3 times in order for the
502 * command to be complete.
503 *
504 * Check 5 times in case the hardware failed to read the docs.
505 */
d121a5d2
CW		 506 if (!intel_sdvo_read_byte(intel_sdvo,
507 SDVO_I2C_CMD_STATUS,
508 &status))
509 goto log_fail;
510
511 while (status == SDVO_CMD_STATUS_PENDING && retry--) {
512 udelay(15);
b5c616a7
CW		 513 if (!intel_sdvo_read_byte(intel_sdvo,
514 SDVO_I2C_CMD_STATUS,
515 &status))
d121a5d2
CW		 516 goto log_fail;
517 }
b5c616a7 518
79e53945 519 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 520 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 521 else
342dc382 522 DRM_LOG_KMS("(??? %d)", status);
79e53945 523
b5c616a7
CW		 524 if (status != SDVO_CMD_STATUS_SUCCESS)
525 goto log_fail;
79e53945 526
b5c616a7
CW		 527 /* Read the command response */
528 for (i = 0; i < response_len; i++) {
529 if (!intel_sdvo_read_byte(intel_sdvo,
530 SDVO_I2C_RETURN_0 + i,
531 &((u8 *)response)[i]))
532 goto log_fail;
e957d772 533 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 534 }
b5c616a7 535 DRM_LOG_KMS("\n");
b5c616a7 536 return true;
79e53945 537
b5c616a7 538log_fail:
d121a5d2 539 DRM_LOG_KMS("... failed\n");
b5c616a7 540 return false;
79e53945
JB		 541}
542
b358d0a6 543static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 544{
545 if (mode->clock >= 100000)
546 return 1;
547 else if (mode->clock >= 50000)
548 return 2;
549 else
550 return 4;
551}
552
e957d772
CW		 553static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
554 u8 ddc_bus)
79e53945 555{
d121a5d2 556 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 557 return intel_sdvo_write_cmd(intel_sdvo,
558 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
559 &ddc_bus, 1);
79e53945
JB		 560}
561
32aad86f 562static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 563{
d121a5d2
CW		 564 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
565 return false;
566
567 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 568}
79e53945 569
32aad86f
CW		 570static bool
571intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
572{
573 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
574 return false;
79e53945 575
32aad86f
CW		 576 return intel_sdvo_read_response(intel_sdvo, value, len);
577}
79e53945 578
32aad86f
CW		 579static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
580{
581 struct intel_sdvo_set_target_input_args targets = {0};
582 return intel_sdvo_set_value(intel_sdvo,
583 SDVO_CMD_SET_TARGET_INPUT,
584 &targets, sizeof(targets));
79e53945
JB		 585}
586
587/**
588 * Return whether each input is trained.
589 *
590 * This function is making an assumption about the layout of the response,
591 * which should be checked against the docs.
592 */
ea5b213a 593static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 594{
595 struct intel_sdvo_get_trained_inputs_response response;
79e53945 596
1a3665c8 597 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 598 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
599 &response, sizeof(response)))
79e53945
JB		 600 return false;
601
602 *input_1 = response.input0_trained;
603 *input_2 = response.input1_trained;
604 return true;
605}
606
ea5b213a 607static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 608 u16 outputs)
609{
32aad86f
CW		 610 return intel_sdvo_set_value(intel_sdvo,
611 SDVO_CMD_SET_ACTIVE_OUTPUTS,
612 &outputs, sizeof(outputs));
79e53945
JB		 613}
614
ea5b213a 615static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 616 int mode)
617{
32aad86f 618 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 619
620 switch (mode) {
621 case DRM_MODE_DPMS_ON:
622 state = SDVO_ENCODER_STATE_ON;
623 break;
624 case DRM_MODE_DPMS_STANDBY:
625 state = SDVO_ENCODER_STATE_STANDBY;
626 break;
627 case DRM_MODE_DPMS_SUSPEND:
628 state = SDVO_ENCODER_STATE_SUSPEND;
629 break;
630 case DRM_MODE_DPMS_OFF:
631 state = SDVO_ENCODER_STATE_OFF;
632 break;
633 }
634
32aad86f
CW		 635 return intel_sdvo_set_value(intel_sdvo,
636 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 637}
638
ea5b213a 639static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 640 int *clock_min,
641 int *clock_max)
642{
643 struct intel_sdvo_pixel_clock_range clocks;
79e53945 644
1a3665c8 645 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 646 if (!intel_sdvo_get_value(intel_sdvo,
647 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
648 &clocks, sizeof(clocks)))
79e53945
JB		 649 return false;
650
651 /* Convert the values from units of 10 kHz to kHz. */
652 *clock_min = clocks.min * 10;
653 *clock_max = clocks.max * 10;
79e53945
JB		 654 return true;
655}
656
ea5b213a 657static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 658 u16 outputs)
659{
32aad86f
CW		 660 return intel_sdvo_set_value(intel_sdvo,
661 SDVO_CMD_SET_TARGET_OUTPUT,
662 &outputs, sizeof(outputs));
79e53945
JB		 663}
664
ea5b213a 665static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 666 struct intel_sdvo_dtd *dtd)
667{
32aad86f
CW		 668 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
669 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 670}
671
ea5b213a 672static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 673 struct intel_sdvo_dtd *dtd)
674{
ea5b213a 675 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 676 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
677}
678
ea5b213a 679static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 680 struct intel_sdvo_dtd *dtd)
681{
ea5b213a 682 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 683 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
684}
685
e2f0ba97 686static bool
ea5b213a 687intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 688 uint16_t clock,
689 uint16_t width,
690 uint16_t height)
691{
692 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 693
e642c6f1 694 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 695 args.clock = clock;
696 args.width = width;
697 args.height = height;
e642c6f1 698 args.interlace = 0;
12682a97 699
ea5b213a
CW		 700 if (intel_sdvo->is_lvds &&
701 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
702 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 703 args.scaled = 1;
704
32aad86f
CW		 705 return intel_sdvo_set_value(intel_sdvo,
706 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
707 &args, sizeof(args));
e2f0ba97
JB		 708}
709
ea5b213a 710static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 711 struct intel_sdvo_dtd *dtd)
712{
1a3665c8
CW		 713 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
714 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 715 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
716 &dtd->part1, sizeof(dtd->part1)) &&
717 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
718 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 719}
79e53945 720
ea5b213a 721static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 722{
32aad86f 723 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 724}
725
e2f0ba97 726static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 727 const struct drm_display_mode *mode)
79e53945 728{
e2f0ba97
JB		 729 uint16_t width, height;
730 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
731 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 732
733 width = mode->crtc_hdisplay;
734 height = mode->crtc_vdisplay;
735
736 /* do some mode translations */
737 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
738 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
739
740 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
741 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
742
743 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
744 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
745
e2f0ba97
JB		 746 dtd->part1.clock = mode->clock / 10;
747 dtd->part1.h_active = width & 0xff;
748 dtd->part1.h_blank = h_blank_len & 0xff;
749 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 750 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 751 dtd->part1.v_active = height & 0xff;
752 dtd->part1.v_blank = v_blank_len & 0xff;
753 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 754 ((v_blank_len >> 8) & 0xf);
755
171a9e96 756 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 757 dtd->part2.h_sync_width = h_sync_len & 0xff;
758 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 759 (v_sync_len & 0xf);
e2f0ba97 760 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 761 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
762 ((v_sync_len & 0x30) >> 4);
763
e2f0ba97 764 dtd->part2.dtd_flags = 0x18;
79e53945 765 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 766 dtd->part2.dtd_flags |= 0x2;
79e53945 767 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 768 dtd->part2.dtd_flags |= 0x4;
769
770 dtd->part2.sdvo_flags = 0;
771 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
772 dtd->part2.reserved = 0;
773}
774
775static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 776 const struct intel_sdvo_dtd *dtd)
e2f0ba97 777{
e2f0ba97
JB		 778 mode->hdisplay = dtd->part1.h_active;
779 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
780 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 781 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 782 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
783 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
784 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
785 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
786
787 mode->vdisplay = dtd->part1.v_active;
788 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
789 mode->vsync_start = mode->vdisplay;
790 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 791 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 792 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
793 mode->vsync_end = mode->vsync_start +
794 (dtd->part2.v_sync_off_width & 0xf);
795 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
796 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
797 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
798
799 mode->clock = dtd->part1.clock * 10;
800
171a9e96 801 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 802 if (dtd->part2.dtd_flags & 0x2)
803 mode->flags |= DRM_MODE_FLAG_PHSYNC;
804 if (dtd->part2.dtd_flags & 0x4)
805 mode->flags |= DRM_MODE_FLAG_PVSYNC;
806}
807
e27d8538 808static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 809{
e27d8538 810 struct intel_sdvo_encode encode;
e2f0ba97 811
1a3665c8 812 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 813 return intel_sdvo_get_value(intel_sdvo,
814 SDVO_CMD_GET_SUPP_ENCODE,
815 &encode, sizeof(encode));
e2f0ba97
JB		 816}
817
ea5b213a 818static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 819 uint8_t mode)
e2f0ba97 820{
32aad86f 821 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 822}
823
ea5b213a 824static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 825 uint8_t mode)
826{
32aad86f 827 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 828}
829
830#if 0
ea5b213a 831static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 832{
833 int i, j;
834 uint8_t set_buf_index[2];
835 uint8_t av_split;
836 uint8_t buf_size;
837 uint8_t buf[48];
838 uint8_t *pos;
839
32aad86f 840 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 841
842 for (i = 0; i <= av_split; i++) {
843 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 844 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 845 set_buf_index, 2);
c751ce4f
EA		 846 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
847 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 848
849 pos = buf;
850 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 851 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 852 NULL, 0);
c751ce4f 853 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 854 pos += 8;
855 }
856 }
857}
858#endif
859
3c17fe4b 860static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 861{
862 struct dip_infoframe avi_if = {
863 .type = DIP_TYPE_AVI,
3c17fe4b 864 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 865 .len = DIP_LEN_AVI,
866 };
3c17fe4b
DH		 867 uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
868 uint8_t set_buf_index[2] = { 1, 0 };
869 uint64_t *data = (uint64_t *)&avi_if;
870 unsigned i;
871
872 intel_dip_infoframe_csum(&avi_if);
873
d121a5d2
CW		 874 if (!intel_sdvo_set_value(intel_sdvo,
875 SDVO_CMD_SET_HBUF_INDEX,
3c17fe4b
DH		 876 set_buf_index, 2))
877 return false;
878
879 for (i = 0; i < sizeof(avi_if); i += 8) {
d121a5d2
CW		 880 if (!intel_sdvo_set_value(intel_sdvo,
881 SDVO_CMD_SET_HBUF_DATA,
3c17fe4b
DH		 882 data, 8))
883 return false;
884 data++;
885 }
e2f0ba97 886
d121a5d2
CW		 887 return intel_sdvo_set_value(intel_sdvo,
888 SDVO_CMD_SET_HBUF_TXRATE,
3c17fe4b 889 &tx_rate, 1);
e2f0ba97
JB		 890}
891
32aad86f 892static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 893{
ce6feabd 894 struct intel_sdvo_tv_format format;
40039750 895 uint32_t format_map;
ce6feabd 896
40039750 897 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 898 memset(&format, 0, sizeof(format));
32aad86f 899 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 900
32aad86f
CW		 901 BUILD_BUG_ON(sizeof(format) != 6);
902 return intel_sdvo_set_value(intel_sdvo,
903 SDVO_CMD_SET_TV_FORMAT,
904 &format, sizeof(format));
7026d4ac
ZW		 905}
906
32aad86f
CW		 907static bool
908intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
909 struct drm_display_mode *mode)
e2f0ba97 910{
32aad86f 911 struct intel_sdvo_dtd output_dtd;
79e53945 912
32aad86f
CW		 913 if (!intel_sdvo_set_target_output(intel_sdvo,
914 intel_sdvo->attached_output))
915 return false;
e2f0ba97 916
32aad86f
CW		 917 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
918 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
919 return false;
e2f0ba97 920
32aad86f
CW		 921 return true;
922}
923
924static bool
925intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
926 struct drm_display_mode *mode,
927 struct drm_display_mode *adjusted_mode)
928{
32aad86f
CW		 929 /* Reset the input timing to the screen. Assume always input 0. */
930 if (!intel_sdvo_set_target_input(intel_sdvo))
931 return false;
e2f0ba97 932
32aad86f
CW		 933 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
934 mode->clock / 10,
935 mode->hdisplay,
936 mode->vdisplay))
937 return false;
e2f0ba97 938
32aad86f 939 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
6c9547ff 940 &intel_sdvo->input_dtd))
32aad86f 941 return false;
e2f0ba97 942
6c9547ff 943 intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
79e53945 944
32aad86f 945 drm_mode_set_crtcinfo(adjusted_mode, 0);
32aad86f
CW		 946 return true;
947}
12682a97 948
32aad86f
CW		 949static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
950 struct drm_display_mode *mode,
951 struct drm_display_mode *adjusted_mode)
952{
890f3359 953 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 954 int multiplier;
12682a97 955
32aad86f
CW		 956 /* We need to construct preferred input timings based on our
957 * output timings. To do that, we have to set the output
958 * timings, even though this isn't really the right place in
959 * the sequence to do it. Oh well.
960 */
961 if (intel_sdvo->is_tv) {
962 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
963 return false;
12682a97 964
c74696b9
PR		 965 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
966 mode,
967 adjusted_mode);
ea5b213a 968 } else if (intel_sdvo->is_lvds) {
32aad86f 969 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 970 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 971 return false;
12682a97 972
c74696b9
PR		 973 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
974 mode,
975 adjusted_mode);
e2f0ba97 976 }
32aad86f
CW		 977
978 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 979 * SDVO device will factor out the multiplier during mode_set.
32aad86f 980 */
6c9547ff
CW		 981 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
982 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 983
e2f0ba97
JB		 984 return true;
985}
986
987static void intel_sdvo_mode_set(struct drm_encoder *encoder,
988 struct drm_display_mode *mode,
989 struct drm_display_mode *adjusted_mode)
990{
991 struct drm_device *dev = encoder->dev;
992 struct drm_i915_private *dev_priv = dev->dev_private;
993 struct drm_crtc *crtc = encoder->crtc;
994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 995 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 996 u32 sdvox;
e2f0ba97
JB		 997 struct intel_sdvo_in_out_map in_out;
998 struct intel_sdvo_dtd input_dtd;
6c9547ff
CW		 999 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1000 int rate;
e2f0ba97
JB		 1001
1002 if (!mode)
1003 return;
1004
1005 /* First, set the input mapping for the first input to our controlled
1006 * output. This is only correct if we're a single-input device, in
1007 * which case the first input is the output from the appropriate SDVO
1008 * channel on the motherboard. In a two-input device, the first input
1009 * will be SDVOB and the second SDVOC.
1010 */
ea5b213a 1011 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1012 in_out.in1 = 0;
1013
c74696b9
PR		 1014 intel_sdvo_set_value(intel_sdvo,
1015 SDVO_CMD_SET_IN_OUT_MAP,
1016 &in_out, sizeof(in_out));
e2f0ba97 1017
6c9547ff
CW		 1018 /* Set the output timings to the screen */
1019 if (!intel_sdvo_set_target_output(intel_sdvo,
1020 intel_sdvo->attached_output))
1021 return;
e2f0ba97 1022
7026d4ac 1023 /* We have tried to get input timing in mode_fixup, and filled into
6c9547ff 1024 * adjusted_mode.
e2f0ba97 1025 */
6c9547ff
CW		 1026 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
1027 input_dtd = intel_sdvo->input_dtd;
1028 } else {
e2f0ba97 1029 /* Set the output timing to the screen */
32aad86f
CW		 1030 if (!intel_sdvo_set_target_output(intel_sdvo,
1031 intel_sdvo->attached_output))
1032 return;
1033
6c9547ff 1034 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c74696b9 1035 (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
e2f0ba97 1036 }
79e53945
JB		 1037
1038 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1039 if (!intel_sdvo_set_target_input(intel_sdvo))
1040 return;
79e53945 1041
97aaf910
CW		 1042 if (intel_sdvo->has_hdmi_monitor) {
1043 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1044 intel_sdvo_set_colorimetry(intel_sdvo,
1045 SDVO_COLORIMETRY_RGB256);
1046 intel_sdvo_set_avi_infoframe(intel_sdvo);
1047 } else
1048 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1049
6c9547ff
CW		 1050 if (intel_sdvo->is_tv &&
1051 !intel_sdvo_set_tv_format(intel_sdvo))
1052 return;
e2f0ba97 1053
c74696b9 1054 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
79e53945 1055
6c9547ff
CW		 1056 switch (pixel_multiplier) {
1057 default:
32aad86f
CW		 1058 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1059 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1060 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1061 }
32aad86f
CW		 1062 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1063 return;
79e53945
JB		 1064
1065 /* Set the SDVO control regs. */
a6c45cf0 1066 if (INTEL_INFO(dev)->gen >= 4) {
6714afb1 1067 sdvox = 0;
e953fd7b
CW		 1068 if (intel_sdvo->is_hdmi)
1069 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1070 if (INTEL_INFO(dev)->gen < 5)
1071 sdvox |= SDVO_BORDER_ENABLE;
81a14b46
AJ		 1072 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1073 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
1074 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1075 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
e2f0ba97 1076 } else {
6c9547ff 1077 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1078 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1079 case SDVOB:
1080 sdvox &= SDVOB_PRESERVE_MASK;
1081 break;
1082 case SDVOC:
1083 sdvox &= SDVOC_PRESERVE_MASK;
1084 break;
1085 }
1086 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1087 }
79e53945
JB		 1088 if (intel_crtc->pipe == 1)
1089 sdvox |= SDVO_PIPE_B_SELECT;
da79de97 1090 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1091 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1092
a6c45cf0 1093 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1094 /* done in crtc_mode_set as the dpll_md reg must be written early */
1095 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1096 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1097 } else {
6c9547ff 1098 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1099 }
1100
6714afb1
CW		 1101 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1102 INTEL_INFO(dev)->gen < 5)
12682a97 1103 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1104 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1105}
1106
1107static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1108{
1109 struct drm_device *dev = encoder->dev;
1110 struct drm_i915_private *dev_priv = dev->dev_private;
890f3359 1111 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
9d0498a2 1112 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1113 u32 temp;
1114
1115 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1116 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1117 if (0)
ea5b213a 1118 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1119
1120 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1121 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1122 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1123 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1124 }
1125 }
1126 } else {
1127 bool input1, input2;
1128 int i;
1129 u8 status;
1130
ea5b213a 1131 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1132 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1133 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1134 for (i = 0; i < 2; i++)
9d0498a2 1135 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1136
32aad86f 1137 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1138 /* Warn if the device reported failure to sync.
1139 * A lot of SDVO devices fail to notify of sync, but it's
1140 * a given it the status is a success, we succeeded.
1141 */
1142 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1143 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1144 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1145 }
1146
1147 if (0)
ea5b213a
CW		 1148 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1149 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1150 }
1151 return;
1152}
1153
79e53945
JB		 1154static int intel_sdvo_mode_valid(struct drm_connector *connector,
1155 struct drm_display_mode *mode)
1156{
df0e9248 1157 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1158
1159 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1160 return MODE_NO_DBLESCAN;
1161
ea5b213a 1162 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1163 return MODE_CLOCK_LOW;
1164
ea5b213a 1165 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1166 return MODE_CLOCK_HIGH;
1167
8545423a 1168 if (intel_sdvo->is_lvds) {
ea5b213a 1169 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1170 return MODE_PANEL;
1171
ea5b213a 1172 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1173 return MODE_PANEL;
1174 }
1175
79e53945
JB		 1176 return MODE_OK;
1177}
1178
ea5b213a 1179static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1180{
1a3665c8 1181 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1182 if (!intel_sdvo_get_value(intel_sdvo,
1183 SDVO_CMD_GET_DEVICE_CAPS,
1184 caps, sizeof(*caps)))
1185 return false;
1186
1187 DRM_DEBUG_KMS("SDVO capabilities:\n"
1188 " vendor_id: %d\n"
1189 " device_id: %d\n"
1190 " device_rev_id: %d\n"
1191 " sdvo_version_major: %d\n"
1192 " sdvo_version_minor: %d\n"
1193 " sdvo_inputs_mask: %d\n"
1194 " smooth_scaling: %d\n"
1195 " sharp_scaling: %d\n"
1196 " up_scaling: %d\n"
1197 " down_scaling: %d\n"
1198 " stall_support: %d\n"
1199 " output_flags: %d\n",
1200 caps->vendor_id,
1201 caps->device_id,
1202 caps->device_rev_id,
1203 caps->sdvo_version_major,
1204 caps->sdvo_version_minor,
1205 caps->sdvo_inputs_mask,
1206 caps->smooth_scaling,
1207 caps->sharp_scaling,
1208 caps->up_scaling,
1209 caps->down_scaling,
1210 caps->stall_support,
1211 caps->output_flags);
1212
1213 return true;
79e53945
JB		 1214}
1215
cc68c81a 1216static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
79e53945
JB		 1217{
1218 u8 response[2];
79e53945 1219
32aad86f
CW		 1220 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1221 &response, 2) && response[0];
79e53945
JB		 1222}
1223
cc68c81a 1224static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1225{
cc68c81a 1226 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1227
cc68c81a 1228 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1229}
1230
fb7a46f3 1231static bool
ea5b213a 1232intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1233{
bc65212c 1234 /* Is there more than one type of output? */
2294488d 1235 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1236}
1237
f899fc64 1238static struct edid *
e957d772 1239intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1240{
e957d772
CW		 1241 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1242 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1243}
1244
ff482d83
CW		 1245/* Mac mini hack -- use the same DDC as the analog connector */
1246static struct edid *
1247intel_sdvo_get_analog_edid(struct drm_connector *connector)
1248{
f899fc64 1249 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1250
0c1dab89
CW		 1251 return drm_get_edid(connector,
1252 &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
ff482d83
CW		 1253}
1254
2b8d33f7 1255enum drm_connector_status
149c36a3 1256intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
9dff6af8 1257{
df0e9248 1258 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1259 enum drm_connector_status status;
1260 struct edid *edid;
9dff6af8 1261
e957d772 1262 edid = intel_sdvo_get_edid(connector);
57cdaf90 1263
ea5b213a 1264 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1265 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1266
7c3f0a27
ZY		 1267 /*
1268 * Don't use the 1 as the argument of DDC bus switch to get
1269 * the EDID. It is used for SDVO SPD ROM.
1270 */
9d1a903d 1271 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1272 intel_sdvo->ddc_bus = ddc;
1273 edid = intel_sdvo_get_edid(connector);
1274 if (edid)
7c3f0a27 1275 break;
7c3f0a27 1276 }
e957d772
CW		 1277 /*
1278 * If we found the EDID on the other bus,
1279 * assume that is the correct DDC bus.
1280 */
1281 if (edid == NULL)
1282 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1283 }
9d1a903d
CW		 1284
1285 /*
1286 * When there is no edid and no monitor is connected with VGA
1287 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1288 */
ff482d83
CW		 1289 if (edid == NULL)
1290 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1291
2f551c84 1292 status = connector_status_unknown;
9dff6af8 1293 if (edid != NULL) {
149c36a3 1294 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1295 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1296 status = connector_status_connected;
da79de97
CW		 1297 if (intel_sdvo->is_hdmi) {
1298 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1299 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1300 }
13946743
CW		 1301 } else
1302 status = connector_status_disconnected;
149c36a3 1303 connector->display_info.raw_edid = NULL;
9d1a903d
CW		 1304 kfree(edid);
1305 }
7f36e7ed
CW		 1306
1307 if (status == connector_status_connected) {
1308 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1309 if (intel_sdvo_connector->force_audio)
da79de97 1310 intel_sdvo->has_hdmi_audio = intel_sdvo_connector->force_audio > 0;
7f36e7ed
CW		 1311 }
1312
2b8d33f7 1313 return status;
9dff6af8
ML		 1314}
1315
7b334fcb 1316static enum drm_connector_status
930a9e28 1317intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1318{
fb7a46f3 1319 uint16_t response;
df0e9248 1320 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1321 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1322 enum drm_connector_status ret;
79e53945 1323
32aad86f 1324 if (!intel_sdvo_write_cmd(intel_sdvo,
e957d772 1325 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
32aad86f 1326 return connector_status_unknown;
ba84cd1f
CW		 1327
1328 /* add 30ms delay when the output type might be TV */
1329 if (intel_sdvo->caps.output_flags &
1330 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
d09c23de 1331 mdelay(30);
ba84cd1f 1332
32aad86f
CW		 1333 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1334 return connector_status_unknown;
79e53945 1335
e957d772
CW		 1336 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1337 response & 0xff, response >> 8,
1338 intel_sdvo_connector->output_flag);
e2f0ba97 1339
fb7a46f3 1340 if (response == 0)
79e53945 1341 return connector_status_disconnected;
fb7a46f3 1342
ea5b213a 1343 intel_sdvo->attached_output = response;
14571b4c 1344
97aaf910
CW		 1345 intel_sdvo->has_hdmi_monitor = false;
1346 intel_sdvo->has_hdmi_audio = false;
1347
615fb93f 1348 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1349 ret = connector_status_disconnected;
13946743 1350 else if (IS_TMDS(intel_sdvo_connector))
149c36a3 1351 ret = intel_sdvo_hdmi_sink_detect(connector);
13946743
CW		 1352 else {
1353 struct edid *edid;
1354
1355 /* if we have an edid check it matches the connection */
1356 edid = intel_sdvo_get_edid(connector);
1357 if (edid == NULL)
1358 edid = intel_sdvo_get_analog_edid(connector);
1359 if (edid != NULL) {
1360 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1361 ret = connector_status_disconnected;
1362 else
1363 ret = connector_status_connected;
1364 connector->display_info.raw_edid = NULL;
1365 kfree(edid);
1366 } else
1367 ret = connector_status_connected;
1368 }
14571b4c
ZW		 1369
1370 /* May update encoder flag for like clock for SDVO TV, etc.*/
1371 if (ret == connector_status_connected) {
ea5b213a
CW		 1372 intel_sdvo->is_tv = false;
1373 intel_sdvo->is_lvds = false;
1374 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1375
1376 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1377 intel_sdvo->is_tv = true;
1378 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1379 }
1380 if (response & SDVO_LVDS_MASK)
8545423a 1381 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1382 }
14571b4c
ZW		 1383
1384 return ret;
79e53945
JB		 1385}
1386
e2f0ba97 1387static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1388{
ff482d83 1389 struct edid *edid;
79e53945
JB		 1390
1391 /* set the bus switch and get the modes */
e957d772 1392 edid = intel_sdvo_get_edid(connector);
79e53945 1393
57cdaf90
KP		 1394 /*
1395 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1396 * link between analog and digital outputs. So, if the regular SDVO
1397 * DDC fails, check to see if the analog output is disconnected, in
1398 * which case we'll look there for the digital DDC data.
e2f0ba97 1399 */
f899fc64
CW		 1400 if (edid == NULL)
1401 edid = intel_sdvo_get_analog_edid(connector);
1402
ff482d83 1403 if (edid != NULL) {
13946743
CW		 1404 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1405 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1406 bool connector_is_digital = !!IS_TMDS(intel_sdvo_connector);
1407
1408 if (connector_is_digital == monitor_is_digital) {
0c1dab89
CW		 1409 drm_mode_connector_update_edid_property(connector, edid);
1410 drm_add_edid_modes(connector, edid);
1411 }
13946743 1412
ff482d83
CW		 1413 connector->display_info.raw_edid = NULL;
1414 kfree(edid);
e2f0ba97 1415 }
e2f0ba97
JB		 1416}
1417
1418/*
1419 * Set of SDVO TV modes.
1420 * Note! This is in reply order (see loop in get_tv_modes).
1421 * XXX: all 60Hz refresh?
1422 */
b1f559ec 1423static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1424 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1425 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1427 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1428 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1429 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1430 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1431 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1433 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1434 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1435 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1436 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1437 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1438 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1439 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1440 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1442 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1443 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1445 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1446 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1448 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1449 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1450 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1451 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1452 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1453 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1454 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1455 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1457 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1458 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1459 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1460 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1461 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1463 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1464 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1465 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1466 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1467 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1469 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1470 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1472 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1473 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1474 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1475 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1476 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1478 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1479 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1481};
1482
1483static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1484{
df0e9248 1485 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1486 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1487 uint32_t reply = 0, format_map = 0;
1488 int i;
e2f0ba97
JB		 1489
1490 /* Read the list of supported input resolutions for the selected TV
1491 * format.
1492 */
40039750 1493 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1494 memcpy(&tv_res, &format_map,
32aad86f 1495 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1496
32aad86f
CW		 1497 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1498 return;
ce6feabd 1499
32aad86f 1500 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1501 if (!intel_sdvo_write_cmd(intel_sdvo,
1502 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1503 &tv_res, sizeof(tv_res)))
1504 return;
1505 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1506 return;
1507
1508 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1509 if (reply & (1 << i)) {
1510 struct drm_display_mode *nmode;
1511 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1512 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1513 if (nmode)
1514 drm_mode_probed_add(connector, nmode);
1515 }
e2f0ba97
JB		 1516}
1517
7086c87f
ML		 1518static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1519{
df0e9248 1520 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1521 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1522 struct drm_display_mode *newmode;
7086c87f
ML		 1523
1524 /*
1525 * Attempt to get the mode list from DDC.
1526 * Assume that the preferred modes are
1527 * arranged in priority order.
1528 */
f899fc64 1529 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1530 if (list_empty(&connector->probed_modes) == false)
12682a97 1531 goto end;
7086c87f
ML		 1532
1533 /* Fetch modes from VBT */
1534 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1535 newmode = drm_mode_duplicate(connector->dev,
1536 dev_priv->sdvo_lvds_vbt_mode);
1537 if (newmode != NULL) {
1538 /* Guarantee the mode is preferred */
1539 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1540 DRM_MODE_TYPE_DRIVER);
1541 drm_mode_probed_add(connector, newmode);
1542 }
1543 }
12682a97 1544
1545end:
1546 list_for_each_entry(newmode, &connector->probed_modes, head) {
1547 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1548 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1549 drm_mode_duplicate(connector->dev, newmode);
6c9547ff
CW		 1550
1551 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode,
1552 0);
1553
8545423a 1554 intel_sdvo->is_lvds = true;
12682a97 1555 break;
1556 }
1557 }
1558
7086c87f
ML		 1559}
1560
e2f0ba97
JB		 1561static int intel_sdvo_get_modes(struct drm_connector *connector)
1562{
615fb93f 1563 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1564
615fb93f 1565 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1566 intel_sdvo_get_tv_modes(connector);
615fb93f 1567 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1568 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1569 else
1570 intel_sdvo_get_ddc_modes(connector);
1571
32aad86f 1572 return !list_empty(&connector->probed_modes);
79e53945
JB		 1573}
1574
fcc8d672
CW		 1575static void
1576intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1577{
615fb93f 1578 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1579 struct drm_device *dev = connector->dev;
1580
c5521706
CW		 1581 if (intel_sdvo_connector->left)
1582 drm_property_destroy(dev, intel_sdvo_connector->left);
1583 if (intel_sdvo_connector->right)
1584 drm_property_destroy(dev, intel_sdvo_connector->right);
1585 if (intel_sdvo_connector->top)
1586 drm_property_destroy(dev, intel_sdvo_connector->top);
1587 if (intel_sdvo_connector->bottom)
1588 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1589 if (intel_sdvo_connector->hpos)
1590 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1591 if (intel_sdvo_connector->vpos)
1592 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1593 if (intel_sdvo_connector->saturation)
1594 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1595 if (intel_sdvo_connector->contrast)
1596 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1597 if (intel_sdvo_connector->hue)
1598 drm_property_destroy(dev, intel_sdvo_connector->hue);
1599 if (intel_sdvo_connector->sharpness)
1600 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1601 if (intel_sdvo_connector->flicker_filter)
1602 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1603 if (intel_sdvo_connector->flicker_filter_2d)
1604 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1605 if (intel_sdvo_connector->flicker_filter_adaptive)
1606 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1607 if (intel_sdvo_connector->tv_luma_filter)
1608 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1609 if (intel_sdvo_connector->tv_chroma_filter)
1610 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1611 if (intel_sdvo_connector->dot_crawl)
1612 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1613 if (intel_sdvo_connector->brightness)
1614 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1615}
1616
79e53945
JB		 1617static void intel_sdvo_destroy(struct drm_connector *connector)
1618{
615fb93f 1619 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1620
c5521706 1621 if (intel_sdvo_connector->tv_format)
ce6feabd 1622 drm_property_destroy(connector->dev,
c5521706 1623 intel_sdvo_connector->tv_format);
b9219c5e 1624
d2a82a6f 1625 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1626 drm_sysfs_connector_remove(connector);
1627 drm_connector_cleanup(connector);
d2a82a6f 1628 kfree(connector);
79e53945
JB		 1629}
1630
1aad7ac0
CW		 1631static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1632{
1633 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1634 struct edid *edid;
1635 bool has_audio = false;
1636
1637 if (!intel_sdvo->is_hdmi)
1638 return false;
1639
1640 edid = intel_sdvo_get_edid(connector);
1641 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1642 has_audio = drm_detect_monitor_audio(edid);
1643
1644 return has_audio;
1645}
1646
ce6feabd
ZY		 1647static int
1648intel_sdvo_set_property(struct drm_connector *connector,
1649 struct drm_property *property,
1650 uint64_t val)
1651{
df0e9248 1652 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1653 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1654 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1655 uint16_t temp_value;
32aad86f
CW		 1656 uint8_t cmd;
1657 int ret;
ce6feabd
ZY		 1658
1659 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1660 if (ret)
1661 return ret;
ce6feabd 1662
3f43c48d 1663 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1664 int i = val;
1665 bool has_audio;
1666
1667 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1668 return 0;
1669
1aad7ac0 1670 intel_sdvo_connector->force_audio = i;
7f36e7ed 1671
1aad7ac0
CW		 1672 if (i == 0)
1673 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1674 else
1675 has_audio = i > 0;
7f36e7ed 1676
1aad7ac0 1677 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1678 return 0;
7f36e7ed 1679
1aad7ac0 1680 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 1681 goto done;
1682 }
1683
e953fd7b
CW		 1684 if (property == dev_priv->broadcast_rgb_property) {
1685 if (val == !!intel_sdvo->color_range)
7f36e7ed
CW		 1686 return 0;
1687
e953fd7b 1688 intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
7f36e7ed
CW		 1689 goto done;
1690 }
1691
c5521706
CW		 1692#define CHECK_PROPERTY(name, NAME) \
1693 if (intel_sdvo_connector->name == property) { \
1694 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1695 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1696 cmd = SDVO_CMD_SET_##NAME; \
1697 intel_sdvo_connector->cur_##name = temp_value; \
1698 goto set_value; \
1699 }
1700
1701 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1702 if (val >= TV_FORMAT_NUM)
1703 return -EINVAL;
1704
40039750 1705 if (intel_sdvo->tv_format_index ==
615fb93f 1706 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1707 return 0;
ce6feabd 1708
40039750 1709 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1710 goto done;
32aad86f 1711 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1712 temp_value = val;
c5521706 1713 if (intel_sdvo_connector->left == property) {
b9219c5e 1714 drm_connector_property_set_value(connector,
c5521706 1715 intel_sdvo_connector->right, val);
615fb93f 1716 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1717 return 0;
b9219c5e 1718
615fb93f
CW		 1719 intel_sdvo_connector->left_margin = temp_value;
1720 intel_sdvo_connector->right_margin = temp_value;
1721 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1722 intel_sdvo_connector->left_margin;
b9219c5e 1723 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1724 goto set_value;
1725 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1726 drm_connector_property_set_value(connector,
c5521706 1727 intel_sdvo_connector->left, val);
615fb93f 1728 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1729 return 0;
b9219c5e 1730
615fb93f
CW		 1731 intel_sdvo_connector->left_margin = temp_value;
1732 intel_sdvo_connector->right_margin = temp_value;
1733 temp_value = intel_sdvo_connector->max_hscan -
1734 intel_sdvo_connector->left_margin;
b9219c5e 1735 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1736 goto set_value;
1737 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1738 drm_connector_property_set_value(connector,
c5521706 1739 intel_sdvo_connector->bottom, val);
615fb93f 1740 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1741 return 0;
b9219c5e 1742
615fb93f
CW		 1743 intel_sdvo_connector->top_margin = temp_value;
1744 intel_sdvo_connector->bottom_margin = temp_value;
1745 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1746 intel_sdvo_connector->top_margin;
b9219c5e 1747 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1748 goto set_value;
1749 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1750 drm_connector_property_set_value(connector,
c5521706 1751 intel_sdvo_connector->top, val);
615fb93f 1752 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1753 return 0;
1754
615fb93f
CW		 1755 intel_sdvo_connector->top_margin = temp_value;
1756 intel_sdvo_connector->bottom_margin = temp_value;
1757 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1758 intel_sdvo_connector->top_margin;
b9219c5e 1759 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1760 goto set_value;
1761 }
1762 CHECK_PROPERTY(hpos, HPOS)
1763 CHECK_PROPERTY(vpos, VPOS)
1764 CHECK_PROPERTY(saturation, SATURATION)
1765 CHECK_PROPERTY(contrast, CONTRAST)
1766 CHECK_PROPERTY(hue, HUE)
1767 CHECK_PROPERTY(brightness, BRIGHTNESS)
1768 CHECK_PROPERTY(sharpness, SHARPNESS)
1769 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1770 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1771 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1772 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1773 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1774 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1775 }
b9219c5e 1776
c5521706 1777 return -EINVAL; /* unknown property */
b9219c5e 1778
c5521706
CW		 1779set_value:
1780 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1781 return -EIO;
b9219c5e 1782
b9219c5e 1783
c5521706 1784done:
df0e9248
CW		 1785 if (intel_sdvo->base.base.crtc) {
1786 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
ce6feabd 1787 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1788 crtc->y, crtc->fb);
1789 }
1790
32aad86f 1791 return 0;
c5521706 1792#undef CHECK_PROPERTY
ce6feabd
ZY		 1793}
1794
79e53945
JB		 1795static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1796 .dpms = intel_sdvo_dpms,
1797 .mode_fixup = intel_sdvo_mode_fixup,
1798 .prepare = intel_encoder_prepare,
1799 .mode_set = intel_sdvo_mode_set,
1800 .commit = intel_encoder_commit,
1801};
1802
1803static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1804 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1805 .detect = intel_sdvo_detect,
1806 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1807 .set_property = intel_sdvo_set_property,
79e53945
JB		 1808 .destroy = intel_sdvo_destroy,
1809};
1810
1811static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1812 .get_modes = intel_sdvo_get_modes,
1813 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1814 .best_encoder = intel_best_encoder,
79e53945
JB		 1815};
1816
b358d0a6 1817static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1818{
890f3359 1819 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 1820
ea5b213a 1821 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1822 drm_mode_destroy(encoder->dev,
ea5b213a 1823 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1824
e957d772 1825 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 1826 intel_encoder_destroy(encoder);
79e53945
JB		 1827}
1828
1829static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1830 .destroy = intel_sdvo_enc_destroy,
1831};
1832
b66d8424
CW		 1833static void
1834intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1835{
1836 uint16_t mask = 0;
1837 unsigned int num_bits;
1838
1839 /* Make a mask of outputs less than or equal to our own priority in the
1840 * list.
1841 */
1842 switch (sdvo->controlled_output) {
1843 case SDVO_OUTPUT_LVDS1:
1844 mask |= SDVO_OUTPUT_LVDS1;
1845 case SDVO_OUTPUT_LVDS0:
1846 mask |= SDVO_OUTPUT_LVDS0;
1847 case SDVO_OUTPUT_TMDS1:
1848 mask |= SDVO_OUTPUT_TMDS1;
1849 case SDVO_OUTPUT_TMDS0:
1850 mask |= SDVO_OUTPUT_TMDS0;
1851 case SDVO_OUTPUT_RGB1:
1852 mask |= SDVO_OUTPUT_RGB1;
1853 case SDVO_OUTPUT_RGB0:
1854 mask |= SDVO_OUTPUT_RGB0;
1855 break;
1856 }
1857
1858 /* Count bits to find what number we are in the priority list. */
1859 mask &= sdvo->caps.output_flags;
1860 num_bits = hweight16(mask);
1861 /* If more than 3 outputs, default to DDC bus 3 for now. */
1862 if (num_bits > 3)
1863 num_bits = 3;
1864
1865 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1866 sdvo->ddc_bus = 1 << num_bits;
1867}
79e53945 1868
e2f0ba97
JB		 1869/**
1870 * Choose the appropriate DDC bus for control bus switch command for this
1871 * SDVO output based on the controlled output.
1872 *
1873 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1874 * outputs, then LVDS outputs.
1875 */
1876static void
b1083333 1877intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1878 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1879{
b1083333 1880 struct sdvo_device_mapping *mapping;
e2f0ba97 1881
b1083333
AJ		 1882 if (IS_SDVOB(reg))
1883 mapping = &(dev_priv->sdvo_mappings[0]);
1884 else
1885 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1886
b66d8424
CW		 1887 if (mapping->initialized)
1888 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1889 else
1890 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1891}
1892
e957d772
CW		 1893static void
1894intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
1895 struct intel_sdvo *sdvo, u32 reg)
1896{
1897 struct sdvo_device_mapping *mapping;
46eb3036 1898 u8 pin;
e957d772
CW		 1899
1900 if (IS_SDVOB(reg))
1901 mapping = &dev_priv->sdvo_mappings[0];
1902 else
1903 mapping = &dev_priv->sdvo_mappings[1];
1904
1905 pin = GMBUS_PORT_DPB;
46eb3036 1906 if (mapping->initialized)
e957d772 1907 pin = mapping->i2c_pin;
e957d772 1908
63abf3ed
CW		 1909 if (pin < GMBUS_NUM_PORTS) {
1910 sdvo->i2c = &dev_priv->gmbus[pin].adapter;
46eb3036 1911 intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ >> 8);
63abf3ed 1912 intel_gmbus_force_bit(sdvo->i2c, true);
46eb3036 1913 } else {
63abf3ed 1914 sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
46eb3036 1915 }
e957d772
CW		 1916}
1917
e2f0ba97 1918static bool
e27d8538 1919intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1920{
97aaf910 1921 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 1922}
1923
714605e4 1924static u8
c751ce4f 1925intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
714605e4 1926{
1927 struct drm_i915_private *dev_priv = dev->dev_private;
1928 struct sdvo_device_mapping *my_mapping, *other_mapping;
1929
461ed3ca 1930 if (IS_SDVOB(sdvo_reg)) {
714605e4 1931 my_mapping = &dev_priv->sdvo_mappings[0];
1932 other_mapping = &dev_priv->sdvo_mappings[1];
1933 } else {
1934 my_mapping = &dev_priv->sdvo_mappings[1];
1935 other_mapping = &dev_priv->sdvo_mappings[0];
1936 }
1937
1938 /* If the BIOS described our SDVO device, take advantage of it. */
1939 if (my_mapping->slave_addr)
1940 return my_mapping->slave_addr;
1941
1942 /* If the BIOS only described a different SDVO device, use the
1943 * address that it isn't using.
1944 */
1945 if (other_mapping->slave_addr) {
1946 if (other_mapping->slave_addr == 0x70)
1947 return 0x72;
1948 else
1949 return 0x70;
1950 }
1951
1952 /* No SDVO device info is found for another DVO port,
1953 * so use mapping assumption we had before BIOS parsing.
1954 */
461ed3ca 1955 if (IS_SDVOB(sdvo_reg))
714605e4 1956 return 0x70;
1957 else
1958 return 0x72;
1959}
1960
14571b4c 1961static void
df0e9248
CW		 1962intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
1963 struct intel_sdvo *encoder)
14571b4c 1964{
df0e9248
CW		 1965 drm_connector_init(encoder->base.base.dev,
1966 &connector->base.base,
1967 &intel_sdvo_connector_funcs,
1968 connector->base.base.connector_type);
6070a4a9 1969
df0e9248
CW		 1970 drm_connector_helper_add(&connector->base.base,
1971 &intel_sdvo_connector_helper_funcs);
14571b4c 1972
df0e9248
CW		 1973 connector->base.base.interlace_allowed = 0;
1974 connector->base.base.doublescan_allowed = 0;
1975 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
14571b4c 1976
df0e9248
CW		 1977 intel_connector_attach_encoder(&connector->base, &encoder->base);
1978 drm_sysfs_connector_add(&connector->base.base);
14571b4c 1979}
6070a4a9 1980
7f36e7ed
CW		 1981static void
1982intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
1983{
1984 struct drm_device *dev = connector->base.base.dev;
1985
3f43c48d 1986 intel_attach_force_audio_property(&connector->base.base);
e953fd7b
CW		 1987 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
1988 intel_attach_broadcast_rgb_property(&connector->base.base);
7f36e7ed
CW		 1989}
1990
fb7a46f3 1991static bool
ea5b213a 1992intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 1993{
4ef69c7a 1994 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 1995 struct drm_connector *connector;
cc68c81a 1996 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 1997 struct intel_connector *intel_connector;
615fb93f 1998 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 1999
615fb93f
CW		 2000 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2001 if (!intel_sdvo_connector)
14571b4c
ZW		 2002 return false;
2003
14571b4c 2004 if (device == 0) {
ea5b213a 2005 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2006 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2007 } else if (device == 1) {
ea5b213a 2008 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2009 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2010 }
2011
615fb93f 2012 intel_connector = &intel_sdvo_connector->base;
14571b4c 2013 connector = &intel_connector->base;
cc68c81a
SF		 2014 if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
2015 connector->polled = DRM_CONNECTOR_POLL_HPD;
2016 intel_sdvo->hotplug_active[0] |= 1 << device;
2017 /* Some SDVO devices have one-shot hotplug interrupts.
2018 * Ensure that they get re-enabled when an interrupt happens.
2019 */
2020 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2021 intel_sdvo_enable_hotplug(intel_encoder);
2022 }
2023 else
2024 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2025 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2026 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2027
e27d8538 2028 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2029 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2030 intel_sdvo->is_hdmi = true;
14571b4c 2031 }
ea5b213a
CW		 2032 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2033 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2034
df0e9248 2035 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221
CW		 2036 if (intel_sdvo->is_hdmi)
2037 intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
14571b4c
ZW		 2038
2039 return true;
2040}
2041
2042static bool
ea5b213a 2043intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2044{
4ef69c7a
CW		 2045 struct drm_encoder *encoder = &intel_sdvo->base.base;
2046 struct drm_connector *connector;
2047 struct intel_connector *intel_connector;
2048 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2049
615fb93f
CW		 2050 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2051 if (!intel_sdvo_connector)
2052 return false;
14571b4c 2053
615fb93f 2054 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2055 connector = &intel_connector->base;
2056 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2057 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2058
4ef69c7a
CW		 2059 intel_sdvo->controlled_output |= type;
2060 intel_sdvo_connector->output_flag = type;
14571b4c 2061
4ef69c7a
CW		 2062 intel_sdvo->is_tv = true;
2063 intel_sdvo->base.needs_tv_clock = true;
2064 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2065
df0e9248 2066 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2067
4ef69c7a 2068 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2069 goto err;
14571b4c 2070
4ef69c7a 2071 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2072 goto err;
14571b4c 2073
4ef69c7a 2074 return true;
32aad86f
CW		 2075
2076err:
123d5c01 2077 intel_sdvo_destroy(connector);
32aad86f 2078 return false;
14571b4c
ZW		 2079}
2080
2081static bool
ea5b213a 2082intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2083{
4ef69c7a
CW		 2084 struct drm_encoder *encoder = &intel_sdvo->base.base;
2085 struct drm_connector *connector;
2086 struct intel_connector *intel_connector;
2087 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2088
615fb93f
CW		 2089 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2090 if (!intel_sdvo_connector)
2091 return false;
14571b4c 2092
615fb93f 2093 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2094 connector = &intel_connector->base;
eb1f8e4f 2095 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2096 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2097 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2098
2099 if (device == 0) {
2100 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2101 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2102 } else if (device == 1) {
2103 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2104 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2105 }
2106
2107 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
ea5b213a 2108 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2109
df0e9248
CW		 2110 intel_sdvo_connector_init(intel_sdvo_connector,
2111 intel_sdvo);
4ef69c7a 2112 return true;
14571b4c
ZW		 2113}
2114
2115static bool
ea5b213a 2116intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2117{
4ef69c7a
CW		 2118 struct drm_encoder *encoder = &intel_sdvo->base.base;
2119 struct drm_connector *connector;
2120 struct intel_connector *intel_connector;
2121 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2122
615fb93f
CW		 2123 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2124 if (!intel_sdvo_connector)
2125 return false;
14571b4c 2126
615fb93f
CW		 2127 intel_connector = &intel_sdvo_connector->base;
2128 connector = &intel_connector->base;
4ef69c7a
CW		 2129 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2130 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2131
2132 if (device == 0) {
2133 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2134 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2135 } else if (device == 1) {
2136 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2137 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2138 }
2139
2140 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
ea5b213a 2141 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2142
df0e9248 2143 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2144 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2145 goto err;
2146
2147 return true;
2148
2149err:
123d5c01 2150 intel_sdvo_destroy(connector);
32aad86f 2151 return false;
14571b4c
ZW		 2152}
2153
2154static bool
ea5b213a 2155intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2156{
ea5b213a
CW		 2157 intel_sdvo->is_tv = false;
2158 intel_sdvo->base.needs_tv_clock = false;
2159 intel_sdvo->is_lvds = false;
fb7a46f3 2160
14571b4c 2161 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2162
14571b4c 2163 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2164 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2165 return false;
2166
2167 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2168 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2169 return false;
2170
2171 /* TV has no XXX1 function block */
a1f4b7ff 2172 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2173 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2174 return false;
2175
2176 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2177 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2178 return false;
fb7a46f3 2179
14571b4c 2180 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2181 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2182 return false;
2183
2184 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2185 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2186 return false;
2187
2188 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2189 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2190 return false;
2191
2192 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2193 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2194 return false;
fb7a46f3 2195
14571b4c 2196 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2197 unsigned char bytes[2];
2198
ea5b213a
CW		 2199 intel_sdvo->controlled_output = 0;
2200 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2201 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2202 SDVO_NAME(intel_sdvo),
51c8b407 2203 bytes[0], bytes[1]);
14571b4c 2204 return false;
fb7a46f3 2205 }
ea5b213a 2206 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
fb7a46f3 2207
14571b4c 2208 return true;
fb7a46f3 2209}
2210
32aad86f
CW		 2211static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2212 struct intel_sdvo_connector *intel_sdvo_connector,
2213 int type)
ce6feabd 2214{
4ef69c7a 2215 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2216 struct intel_sdvo_tv_format format;
2217 uint32_t format_map, i;
ce6feabd 2218
32aad86f
CW		 2219 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2220 return false;
ce6feabd 2221
1a3665c8 2222 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2223 if (!intel_sdvo_get_value(intel_sdvo,
2224 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2225 &format, sizeof(format)))
2226 return false;
ce6feabd 2227
32aad86f 2228 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2229
2230 if (format_map == 0)
32aad86f 2231 return false;
ce6feabd 2232
615fb93f 2233 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2234 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2235 if (format_map & (1 << i))
2236 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2237
2238
c5521706 2239 intel_sdvo_connector->tv_format =
32aad86f
CW		 2240 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2241 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2242 if (!intel_sdvo_connector->tv_format)
fcc8d672 2243 return false;
ce6feabd 2244
615fb93f 2245 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2246 drm_property_add_enum(
c5521706 2247 intel_sdvo_connector->tv_format, i,
40039750 2248 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2249
40039750 2250 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2251 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2252 intel_sdvo_connector->tv_format, 0);
32aad86f 2253 return true;
ce6feabd
ZY		 2254
2255}
2256
c5521706
CW		 2257#define ENHANCEMENT(name, NAME) do { \
2258 if (enhancements.name) { \
2259 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2260 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2261 return false; \
2262 intel_sdvo_connector->max_##name = data_value[0]; \
2263 intel_sdvo_connector->cur_##name = response; \
2264 intel_sdvo_connector->name = \
2265 drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
2266 if (!intel_sdvo_connector->name) return false; \
2267 intel_sdvo_connector->name->values[0] = 0; \
2268 intel_sdvo_connector->name->values[1] = data_value[0]; \
2269 drm_connector_attach_property(connector, \
2270 intel_sdvo_connector->name, \
2271 intel_sdvo_connector->cur_##name); \
2272 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2273 data_value[0], data_value[1], response); \
2274 } \
0206e353 2275} while (0)
c5521706
CW		 2276
2277static bool
2278intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2279 struct intel_sdvo_connector *intel_sdvo_connector,
2280 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2281{
4ef69c7a 2282 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2283 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2284 uint16_t response, data_value[2];
2285
c5521706
CW		 2286 /* when horizontal overscan is supported, Add the left/right property */
2287 if (enhancements.overscan_h) {
2288 if (!intel_sdvo_get_value(intel_sdvo,
2289 SDVO_CMD_GET_MAX_OVERSCAN_H,
2290 &data_value, 4))
2291 return false;
32aad86f 2292
c5521706
CW		 2293 if (!intel_sdvo_get_value(intel_sdvo,
2294 SDVO_CMD_GET_OVERSCAN_H,
2295 &response, 2))
2296 return false;
fcc8d672 2297
c5521706
CW		 2298 intel_sdvo_connector->max_hscan = data_value[0];
2299 intel_sdvo_connector->left_margin = data_value[0] - response;
2300 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2301 intel_sdvo_connector->left =
2302 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2303 "left_margin", 2);
2304 if (!intel_sdvo_connector->left)
2305 return false;
fcc8d672 2306
c5521706
CW		 2307 intel_sdvo_connector->left->values[0] = 0;
2308 intel_sdvo_connector->left->values[1] = data_value[0];
2309 drm_connector_attach_property(connector,
2310 intel_sdvo_connector->left,
2311 intel_sdvo_connector->left_margin);
fcc8d672 2312
c5521706
CW		 2313 intel_sdvo_connector->right =
2314 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2315 "right_margin", 2);
2316 if (!intel_sdvo_connector->right)
2317 return false;
32aad86f 2318
c5521706
CW		 2319 intel_sdvo_connector->right->values[0] = 0;
2320 intel_sdvo_connector->right->values[1] = data_value[0];
2321 drm_connector_attach_property(connector,
2322 intel_sdvo_connector->right,
2323 intel_sdvo_connector->right_margin);
2324 DRM_DEBUG_KMS("h_overscan: max %d, "
2325 "default %d, current %d\n",
2326 data_value[0], data_value[1], response);
2327 }
32aad86f 2328
c5521706
CW		 2329 if (enhancements.overscan_v) {
2330 if (!intel_sdvo_get_value(intel_sdvo,
2331 SDVO_CMD_GET_MAX_OVERSCAN_V,
2332 &data_value, 4))
2333 return false;
fcc8d672 2334
c5521706
CW		 2335 if (!intel_sdvo_get_value(intel_sdvo,
2336 SDVO_CMD_GET_OVERSCAN_V,
2337 &response, 2))
2338 return false;
32aad86f 2339
c5521706
CW		 2340 intel_sdvo_connector->max_vscan = data_value[0];
2341 intel_sdvo_connector->top_margin = data_value[0] - response;
2342 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2343 intel_sdvo_connector->top =
2344 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2345 "top_margin", 2);
2346 if (!intel_sdvo_connector->top)
2347 return false;
32aad86f 2348
c5521706
CW		 2349 intel_sdvo_connector->top->values[0] = 0;
2350 intel_sdvo_connector->top->values[1] = data_value[0];
2351 drm_connector_attach_property(connector,
2352 intel_sdvo_connector->top,
2353 intel_sdvo_connector->top_margin);
fcc8d672 2354
c5521706
CW		 2355 intel_sdvo_connector->bottom =
2356 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2357 "bottom_margin", 2);
2358 if (!intel_sdvo_connector->bottom)
2359 return false;
32aad86f 2360
c5521706
CW		 2361 intel_sdvo_connector->bottom->values[0] = 0;
2362 intel_sdvo_connector->bottom->values[1] = data_value[0];
2363 drm_connector_attach_property(connector,
2364 intel_sdvo_connector->bottom,
2365 intel_sdvo_connector->bottom_margin);
2366 DRM_DEBUG_KMS("v_overscan: max %d, "
2367 "default %d, current %d\n",
2368 data_value[0], data_value[1], response);
2369 }
32aad86f 2370
c5521706
CW		 2371 ENHANCEMENT(hpos, HPOS);
2372 ENHANCEMENT(vpos, VPOS);
2373 ENHANCEMENT(saturation, SATURATION);
2374 ENHANCEMENT(contrast, CONTRAST);
2375 ENHANCEMENT(hue, HUE);
2376 ENHANCEMENT(sharpness, SHARPNESS);
2377 ENHANCEMENT(brightness, BRIGHTNESS);
2378 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2379 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2380 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2381 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2382 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2383
e044218a
CW		 2384 if (enhancements.dot_crawl) {
2385 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2386 return false;
2387
2388 intel_sdvo_connector->max_dot_crawl = 1;
2389 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2390 intel_sdvo_connector->dot_crawl =
2391 drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2);
2392 if (!intel_sdvo_connector->dot_crawl)
2393 return false;
2394
2395 intel_sdvo_connector->dot_crawl->values[0] = 0;
2396 intel_sdvo_connector->dot_crawl->values[1] = 1;
2397 drm_connector_attach_property(connector,
2398 intel_sdvo_connector->dot_crawl,
2399 intel_sdvo_connector->cur_dot_crawl);
2400 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2401 }
2402
c5521706
CW		 2403 return true;
2404}
32aad86f 2405
c5521706
CW		 2406static bool
2407intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2408 struct intel_sdvo_connector *intel_sdvo_connector,
2409 struct intel_sdvo_enhancements_reply enhancements)
2410{
4ef69c7a 2411 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2412 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2413 uint16_t response, data_value[2];
32aad86f 2414
c5521706 2415 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2416
c5521706
CW		 2417 return true;
2418}
2419#undef ENHANCEMENT
32aad86f 2420
c5521706
CW		 2421static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2422 struct intel_sdvo_connector *intel_sdvo_connector)
2423{
2424 union {
2425 struct intel_sdvo_enhancements_reply reply;
2426 uint16_t response;
2427 } enhancements;
32aad86f 2428
1a3665c8
CW		 2429 BUILD_BUG_ON(sizeof(enhancements) != 2);
2430
cf9a2f3a
CW		 2431 enhancements.response = 0;
2432 intel_sdvo_get_value(intel_sdvo,
2433 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2434 &enhancements, sizeof(enhancements));
c5521706
CW		 2435 if (enhancements.response == 0) {
2436 DRM_DEBUG_KMS("No enhancement is supported\n");
2437 return true;
b9219c5e 2438 }
32aad86f 2439
c5521706
CW		 2440 if (IS_TV(intel_sdvo_connector))
2441 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2442 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2443 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2444 else
2445 return true;
e957d772
CW		 2446}
2447
2448static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2449 struct i2c_msg *msgs,
2450 int num)
2451{
2452 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2453
e957d772
CW		 2454 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2455 return -EIO;
2456
2457 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2458}
2459
2460static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2461{
2462 struct intel_sdvo *sdvo = adapter->algo_data;
2463 return sdvo->i2c->algo->functionality(sdvo->i2c);
2464}
2465
2466static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2467 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2468 .functionality = intel_sdvo_ddc_proxy_func
2469};
2470
2471static bool
2472intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2473 struct drm_device *dev)
2474{
2475 sdvo->ddc.owner = THIS_MODULE;
2476 sdvo->ddc.class = I2C_CLASS_DDC;
2477 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2478 sdvo->ddc.dev.parent = &dev->pdev->dev;
2479 sdvo->ddc.algo_data = sdvo;
2480 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2481
2482 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2483}
2484
c751ce4f 2485bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
79e53945 2486{
b01f2c3a 2487 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2488 struct intel_encoder *intel_encoder;
ea5b213a 2489 struct intel_sdvo *intel_sdvo;
79e53945 2490 int i;
79e53945 2491
ea5b213a
CW		 2492 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2493 if (!intel_sdvo)
7d57382e 2494 return false;
79e53945 2495
56184e3d
CW		 2496 intel_sdvo->sdvo_reg = sdvo_reg;
2497 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
2498 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
e957d772
CW		 2499 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
2500 kfree(intel_sdvo);
2501 return false;
2502 }
2503
56184e3d 2504 /* encoder type will be decided later */
ea5b213a 2505 intel_encoder = &intel_sdvo->base;
21d40d37 2506 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2507 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2508
79e53945
JB		 2509 /* Read the regs to test if we can talk to the device */
2510 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2511 u8 byte;
2512
2513 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
8a4c47f3 2514 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
461ed3ca 2515 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
f899fc64 2516 goto err;
79e53945
JB		 2517 }
2518 }
2519
f899fc64 2520 if (IS_SDVOB(sdvo_reg))
b01f2c3a 2521 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
f899fc64 2522 else
b01f2c3a 2523 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
619ac3b7 2524
4ef69c7a 2525 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2526
af901ca1 2527 /* In default case sdvo lvds is false */
32aad86f 2528 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2529 goto err;
79e53945 2530
cc68c81a
SF		 2531 /* Set up hotplug command - note paranoia about contents of reply.
2532 * We assume that the hardware is in a sane state, and only touch
2533 * the bits we think we understand.
2534 */
2535 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
2536 &intel_sdvo->hotplug_active, 2);
2537 intel_sdvo->hotplug_active[0] &= ~0x3;
2538
ea5b213a
CW		 2539 if (intel_sdvo_output_setup(intel_sdvo,
2540 intel_sdvo->caps.output_flags) != true) {
51c8b407 2541 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
461ed3ca 2542 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
f899fc64 2543 goto err;
79e53945
JB		 2544 }
2545
ea5b213a 2546 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2547
79e53945 2548 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2549 if (!intel_sdvo_set_target_input(intel_sdvo))
f899fc64 2550 goto err;
79e53945 2551
32aad86f
CW		 2552 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2553 &intel_sdvo->pixel_clock_min,
2554 &intel_sdvo->pixel_clock_max))
f899fc64 2555 goto err;
79e53945 2556
8a4c47f3 2557 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2558 "clock range %dMHz - %dMHz, "
2559 "input 1: %c, input 2: %c, "
2560 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2561 SDVO_NAME(intel_sdvo),
2562 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2563 intel_sdvo->caps.device_rev_id,
2564 intel_sdvo->pixel_clock_min / 1000,
2565 intel_sdvo->pixel_clock_max / 1000,
2566 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2567 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2568 /* check currently supported outputs */
ea5b213a 2569 intel_sdvo->caps.output_flags &
79e53945 2570 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2571 intel_sdvo->caps.output_flags &
79e53945 2572 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2573 return true;
79e53945 2574
f899fc64 2575err:
373a3cf7 2576 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2577 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2578 kfree(intel_sdvo);
79e53945 2579
7d57382e 2580 return false;
79e53945 2581}
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