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[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
79e53945
JB		 32#include "drmP.h"
33#include "drm.h"
34#include "drm_crtc.h"
2b8d33f7 35#include "drm_edid.h"
ea5b213a 36#include "intel_drv.h"
79e53945
JB		 37#include "i915_drm.h"
38#include "i915_drv.h"
39#include "intel_sdvo_regs.h"
40
14571b4c
ZW		 41#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
44#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
45
46#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 47 SDVO_TV_MASK)
14571b4c
ZW		 48
49#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 50#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 51#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 52#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 53#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 54
79e53945 55
2e88e40b 56static const char *tv_format_names[] = {
ce6feabd
ZY		 57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64};
65
66#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
67
ea5b213a
CW		 68struct intel_sdvo {
69 struct intel_encoder base;
70
f899fc64 71 struct i2c_adapter *i2c;
f9c10a9b 72 u8 slave_addr;
e2f0ba97 73
e957d772
CW		 74 struct i2c_adapter ddc;
75
e2f0ba97 76 /* Register for the SDVO device: SDVOB or SDVOC */
c751ce4f 77 int sdvo_reg;
79e53945 78
e2f0ba97
JB		 79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
79e53945 81
e2f0ba97
JB		 82 /*
83 * Capabilities of the SDVO device returned by
84 * i830_sdvo_get_capabilities()
85 */
79e53945 86 struct intel_sdvo_caps caps;
e2f0ba97
JB		 87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 89 int pixel_clock_min, pixel_clock_max;
90
fb7a46f3 91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
cc68c81a
SF		 97 /*
98 * Hotplug activation bits for this device
99 */
100 uint8_t hotplug_active[2];
101
e953fd7b
CW		 102 /**
103 * This is used to select the color range of RBG outputs in HDMI mode.
104 * It is only valid when using TMDS encoding and 8 bit per color mode.
105 */
106 uint32_t color_range;
107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
ce6feabd 117 /* This is for current tv format name */
40039750 118 int tv_format_index;
ce6feabd 119
e2f0ba97
JB		 120 /**
121 * This is set if we treat the device as HDMI, instead of DVI.
122 */
123 bool is_hdmi;
da79de97
CW		 124 bool has_hdmi_monitor;
125 bool has_hdmi_audio;
12682a97 126
7086c87f 127 /**
6c9547ff
CW		 128 * This is set if we detect output of sdvo device as LVDS and
129 * have a valid fixed mode to use with the panel.
7086c87f
ML		 130 */
131 bool is_lvds;
e2f0ba97 132
12682a97 133 /**
134 * This is sdvo fixed pannel mode pointer
135 */
136 struct drm_display_mode *sdvo_lvds_fixed_mode;
137
c751ce4f 138 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 139 uint8_t ddc_bus;
140
6c9547ff
CW		 141 /* Input timings for adjusted_mode */
142 struct intel_sdvo_dtd input_dtd;
14571b4c
ZW		 143};
144
145struct intel_sdvo_connector {
615fb93f
CW		 146 struct intel_connector base;
147
14571b4c
ZW		 148 /* Mark the type of connector */
149 uint16_t output_flag;
150
7f36e7ed
CW		 151 int force_audio;
152
14571b4c 153 /* This contains all current supported TV format */
40039750 154 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 155 int format_supported_num;
c5521706 156 struct drm_property *tv_format;
14571b4c 157
b9219c5e 158 /* add the property for the SDVO-TV */
c5521706
CW		 159 struct drm_property *left;
160 struct drm_property *right;
161 struct drm_property *top;
162 struct drm_property *bottom;
163 struct drm_property *hpos;
164 struct drm_property *vpos;
165 struct drm_property *contrast;
166 struct drm_property *saturation;
167 struct drm_property *hue;
168 struct drm_property *sharpness;
169 struct drm_property *flicker_filter;
170 struct drm_property *flicker_filter_adaptive;
171 struct drm_property *flicker_filter_2d;
172 struct drm_property *tv_chroma_filter;
173 struct drm_property *tv_luma_filter;
e044218a 174 struct drm_property *dot_crawl;
b9219c5e
ZY		 175
176 /* add the property for the SDVO-TV/LVDS */
c5521706 177 struct drm_property *brightness;
b9219c5e
ZY		 178
179 /* Add variable to record current setting for the above property */
180 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 181
b9219c5e
ZY		 182 /* this is to get the range of margin.*/
183 u32 max_hscan, max_vscan;
184 u32 max_hpos, cur_hpos;
185 u32 max_vpos, cur_vpos;
186 u32 cur_brightness, max_brightness;
187 u32 cur_contrast, max_contrast;
188 u32 cur_saturation, max_saturation;
189 u32 cur_hue, max_hue;
c5521706
CW		 190 u32 cur_sharpness, max_sharpness;
191 u32 cur_flicker_filter, max_flicker_filter;
192 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
193 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
194 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
195 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 196 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 197};
198
890f3359 199static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 200{
4ef69c7a 201 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 202}
203
df0e9248
CW		 204static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
205{
206 return container_of(intel_attached_encoder(connector),
207 struct intel_sdvo, base);
208}
209
615fb93f
CW		 210static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
211{
212 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
213}
214
fb7a46f3 215static bool
ea5b213a 216intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 217static bool
218intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
219 struct intel_sdvo_connector *intel_sdvo_connector,
220 int type);
221static bool
222intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
223 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 224
79e53945
JB		 225/**
226 * Writes the SDVOB or SDVOC with the given value, but always writes both
227 * SDVOB and SDVOC to work around apparent hardware issues (according to
228 * comments in the BIOS).
229 */
ea5b213a 230static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 231{
4ef69c7a 232 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 233 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 234 u32 bval = val, cval = val;
235 int i;
236
ea5b213a
CW		 237 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
238 I915_WRITE(intel_sdvo->sdvo_reg, val);
239 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 240 return;
241 }
242
ea5b213a 243 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 244 cval = I915_READ(SDVOC);
245 } else {
246 bval = I915_READ(SDVOB);
247 }
248 /*
249 * Write the registers twice for luck. Sometimes,
250 * writing them only once doesn't appear to 'stick'.
251 * The BIOS does this too. Yay, magic
252 */
253 for (i = 0; i < 2; i++)
254 {
255 I915_WRITE(SDVOB, bval);
256 I915_READ(SDVOB);
257 I915_WRITE(SDVOC, cval);
258 I915_READ(SDVOC);
259 }
260}
261
32aad86f 262static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 263{
79e53945
JB		 264 struct i2c_msg msgs[] = {
265 {
e957d772 266 .addr = intel_sdvo->slave_addr,
79e53945
JB		 267 .flags = 0,
268 .len = 1,
e957d772 269 .buf = &addr,
79e53945
JB		 270 },
271 {
e957d772 272 .addr = intel_sdvo->slave_addr,
79e53945
JB		 273 .flags = I2C_M_RD,
274 .len = 1,
e957d772 275 .buf = ch,
79e53945
JB		 276 }
277 };
32aad86f 278 int ret;
79e53945 279
f899fc64 280 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 281 return true;
79e53945 282
8a4c47f3 283 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 284 return false;
285}
286
79e53945
JB		 287#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
288/** Mapping of command numbers to names, for debug output */
005568be 289static const struct _sdvo_cmd_name {
e2f0ba97 290 u8 cmd;
2e88e40b 291 const char *name;
79e53945 292} sdvo_cmd_names[] = {
0206e353
AJ		 293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
336
337 /* Add the op code for SDVO enhancements */
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
382
383 /* HDMI op code */
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 404};
405
461ed3ca 406#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
ea5b213a 407#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
79e53945 408
ea5b213a 409static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 410 const void *args, int args_len)
79e53945 411{
79e53945
JB		 412 int i;
413
8a4c47f3 414 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 415 SDVO_NAME(intel_sdvo), cmd);
79e53945 416 for (i = 0; i < args_len; i++)
342dc382 417 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 418 for (; i < 8; i++)
342dc382 419 DRM_LOG_KMS(" ");
04ad327f 420 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 421 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 422 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 423 break;
424 }
425 }
04ad327f 426 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 427 DRM_LOG_KMS("(%02X)", cmd);
428 DRM_LOG_KMS("\n");
79e53945 429}
79e53945 430
e957d772
CW		 431static const char *cmd_status_names[] = {
432 "Power on",
433 "Success",
434 "Not supported",
435 "Invalid arg",
436 "Pending",
437 "Target not specified",
438 "Scaling not supported"
439};
440
32aad86f
CW		 441static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
442 const void *args, int args_len)
79e53945 443{
e957d772
CW		 444 u8 buf[args_len*2 + 2], status;
445 struct i2c_msg msgs[args_len + 3];
446 int i, ret;
79e53945 447
ea5b213a 448 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 449
450 for (i = 0; i < args_len; i++) {
e957d772
CW		 451 msgs[i].addr = intel_sdvo->slave_addr;
452 msgs[i].flags = 0;
453 msgs[i].len = 2;
454 msgs[i].buf = buf + 2 *i;
455 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
456 buf[2*i + 1] = ((u8*)args)[i];
457 }
458 msgs[i].addr = intel_sdvo->slave_addr;
459 msgs[i].flags = 0;
460 msgs[i].len = 2;
461 msgs[i].buf = buf + 2*i;
462 buf[2*i + 0] = SDVO_I2C_OPCODE;
463 buf[2*i + 1] = cmd;
464
465 /* the following two are to read the response */
466 status = SDVO_I2C_CMD_STATUS;
467 msgs[i+1].addr = intel_sdvo->slave_addr;
468 msgs[i+1].flags = 0;
469 msgs[i+1].len = 1;
470 msgs[i+1].buf = &status;
471
472 msgs[i+2].addr = intel_sdvo->slave_addr;
473 msgs[i+2].flags = I2C_M_RD;
474 msgs[i+2].len = 1;
475 msgs[i+2].buf = &status;
476
477 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
478 if (ret < 0) {
479 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
480 return false;
481 }
482 if (ret != i+3) {
483 /* failure in I2C transfer */
484 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
485 return false;
486 }
487
e957d772 488 return true;
79e53945
JB		 489}
490
b5c616a7
CW		 491static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
492 void *response, int response_len)
79e53945 493{
b5c616a7
CW		 494 u8 retry = 5;
495 u8 status;
33b52961 496 int i;
79e53945 497
d121a5d2
CW		 498 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
499
b5c616a7
CW		 500 /*
501 * The documentation states that all commands will be
502 * processed within 15µs, and that we need only poll
503 * the status byte a maximum of 3 times in order for the
504 * command to be complete.
505 *
506 * Check 5 times in case the hardware failed to read the docs.
507 */
d121a5d2
CW		 508 if (!intel_sdvo_read_byte(intel_sdvo,
509 SDVO_I2C_CMD_STATUS,
510 &status))
511 goto log_fail;
512
513 while (status == SDVO_CMD_STATUS_PENDING && retry--) {
514 udelay(15);
b5c616a7
CW		 515 if (!intel_sdvo_read_byte(intel_sdvo,
516 SDVO_I2C_CMD_STATUS,
517 &status))
d121a5d2
CW		 518 goto log_fail;
519 }
b5c616a7 520
79e53945 521 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 522 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 523 else
342dc382 524 DRM_LOG_KMS("(??? %d)", status);
79e53945 525
b5c616a7
CW		 526 if (status != SDVO_CMD_STATUS_SUCCESS)
527 goto log_fail;
79e53945 528
b5c616a7
CW		 529 /* Read the command response */
530 for (i = 0; i < response_len; i++) {
531 if (!intel_sdvo_read_byte(intel_sdvo,
532 SDVO_I2C_RETURN_0 + i,
533 &((u8 *)response)[i]))
534 goto log_fail;
e957d772 535 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 536 }
b5c616a7 537 DRM_LOG_KMS("\n");
b5c616a7 538 return true;
79e53945 539
b5c616a7 540log_fail:
d121a5d2 541 DRM_LOG_KMS("... failed\n");
b5c616a7 542 return false;
79e53945
JB		 543}
544
b358d0a6 545static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 546{
547 if (mode->clock >= 100000)
548 return 1;
549 else if (mode->clock >= 50000)
550 return 2;
551 else
552 return 4;
553}
554
e957d772
CW		 555static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
556 u8 ddc_bus)
79e53945 557{
d121a5d2 558 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 559 return intel_sdvo_write_cmd(intel_sdvo,
560 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
561 &ddc_bus, 1);
79e53945
JB		 562}
563
32aad86f 564static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 565{
d121a5d2
CW		 566 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
567 return false;
568
569 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 570}
79e53945 571
32aad86f
CW		 572static bool
573intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
574{
575 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
576 return false;
79e53945 577
32aad86f
CW		 578 return intel_sdvo_read_response(intel_sdvo, value, len);
579}
79e53945 580
32aad86f
CW		 581static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
582{
583 struct intel_sdvo_set_target_input_args targets = {0};
584 return intel_sdvo_set_value(intel_sdvo,
585 SDVO_CMD_SET_TARGET_INPUT,
586 &targets, sizeof(targets));
79e53945
JB		 587}
588
589/**
590 * Return whether each input is trained.
591 *
592 * This function is making an assumption about the layout of the response,
593 * which should be checked against the docs.
594 */
ea5b213a 595static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 596{
597 struct intel_sdvo_get_trained_inputs_response response;
79e53945 598
1a3665c8 599 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 600 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
601 &response, sizeof(response)))
79e53945
JB		 602 return false;
603
604 *input_1 = response.input0_trained;
605 *input_2 = response.input1_trained;
606 return true;
607}
608
ea5b213a 609static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 610 u16 outputs)
611{
32aad86f
CW		 612 return intel_sdvo_set_value(intel_sdvo,
613 SDVO_CMD_SET_ACTIVE_OUTPUTS,
614 &outputs, sizeof(outputs));
79e53945
JB		 615}
616
ea5b213a 617static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 618 int mode)
619{
32aad86f 620 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 621
622 switch (mode) {
623 case DRM_MODE_DPMS_ON:
624 state = SDVO_ENCODER_STATE_ON;
625 break;
626 case DRM_MODE_DPMS_STANDBY:
627 state = SDVO_ENCODER_STATE_STANDBY;
628 break;
629 case DRM_MODE_DPMS_SUSPEND:
630 state = SDVO_ENCODER_STATE_SUSPEND;
631 break;
632 case DRM_MODE_DPMS_OFF:
633 state = SDVO_ENCODER_STATE_OFF;
634 break;
635 }
636
32aad86f
CW		 637 return intel_sdvo_set_value(intel_sdvo,
638 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 639}
640
ea5b213a 641static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 642 int *clock_min,
643 int *clock_max)
644{
645 struct intel_sdvo_pixel_clock_range clocks;
79e53945 646
1a3665c8 647 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 648 if (!intel_sdvo_get_value(intel_sdvo,
649 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
650 &clocks, sizeof(clocks)))
79e53945
JB		 651 return false;
652
653 /* Convert the values from units of 10 kHz to kHz. */
654 *clock_min = clocks.min * 10;
655 *clock_max = clocks.max * 10;
79e53945
JB		 656 return true;
657}
658
ea5b213a 659static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 660 u16 outputs)
661{
32aad86f
CW		 662 return intel_sdvo_set_value(intel_sdvo,
663 SDVO_CMD_SET_TARGET_OUTPUT,
664 &outputs, sizeof(outputs));
79e53945
JB		 665}
666
ea5b213a 667static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 668 struct intel_sdvo_dtd *dtd)
669{
32aad86f
CW		 670 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
671 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 672}
673
ea5b213a 674static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 675 struct intel_sdvo_dtd *dtd)
676{
ea5b213a 677 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 678 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
679}
680
ea5b213a 681static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 682 struct intel_sdvo_dtd *dtd)
683{
ea5b213a 684 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 685 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
686}
687
e2f0ba97 688static bool
ea5b213a 689intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 690 uint16_t clock,
691 uint16_t width,
692 uint16_t height)
693{
694 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 695
e642c6f1 696 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 697 args.clock = clock;
698 args.width = width;
699 args.height = height;
e642c6f1 700 args.interlace = 0;
12682a97 701
ea5b213a
CW		 702 if (intel_sdvo->is_lvds &&
703 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
704 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 705 args.scaled = 1;
706
32aad86f
CW		 707 return intel_sdvo_set_value(intel_sdvo,
708 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
709 &args, sizeof(args));
e2f0ba97
JB		 710}
711
ea5b213a 712static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 713 struct intel_sdvo_dtd *dtd)
714{
1a3665c8
CW		 715 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
716 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 717 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
718 &dtd->part1, sizeof(dtd->part1)) &&
719 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
720 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 721}
79e53945 722
ea5b213a 723static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 724{
32aad86f 725 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 726}
727
e2f0ba97 728static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 729 const struct drm_display_mode *mode)
79e53945 730{
e2f0ba97
JB		 731 uint16_t width, height;
732 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
733 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 734
735 width = mode->crtc_hdisplay;
736 height = mode->crtc_vdisplay;
737
738 /* do some mode translations */
739 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
740 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
741
742 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
743 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
744
745 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
746 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
747
e2f0ba97
JB		 748 dtd->part1.clock = mode->clock / 10;
749 dtd->part1.h_active = width & 0xff;
750 dtd->part1.h_blank = h_blank_len & 0xff;
751 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 752 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 753 dtd->part1.v_active = height & 0xff;
754 dtd->part1.v_blank = v_blank_len & 0xff;
755 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 756 ((v_blank_len >> 8) & 0xf);
757
171a9e96 758 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 759 dtd->part2.h_sync_width = h_sync_len & 0xff;
760 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 761 (v_sync_len & 0xf);
e2f0ba97 762 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 763 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
764 ((v_sync_len & 0x30) >> 4);
765
e2f0ba97 766 dtd->part2.dtd_flags = 0x18;
79e53945 767 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 768 dtd->part2.dtd_flags |= 0x2;
79e53945 769 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 770 dtd->part2.dtd_flags |= 0x4;
771
772 dtd->part2.sdvo_flags = 0;
773 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
774 dtd->part2.reserved = 0;
775}
776
777static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 778 const struct intel_sdvo_dtd *dtd)
e2f0ba97 779{
e2f0ba97
JB		 780 mode->hdisplay = dtd->part1.h_active;
781 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
782 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 783 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 784 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
785 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
786 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
787 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
788
789 mode->vdisplay = dtd->part1.v_active;
790 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
791 mode->vsync_start = mode->vdisplay;
792 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 793 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 794 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
795 mode->vsync_end = mode->vsync_start +
796 (dtd->part2.v_sync_off_width & 0xf);
797 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
798 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
799 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
800
801 mode->clock = dtd->part1.clock * 10;
802
171a9e96 803 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 804 if (dtd->part2.dtd_flags & 0x2)
805 mode->flags |= DRM_MODE_FLAG_PHSYNC;
806 if (dtd->part2.dtd_flags & 0x4)
807 mode->flags |= DRM_MODE_FLAG_PVSYNC;
808}
809
e27d8538 810static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 811{
e27d8538 812 struct intel_sdvo_encode encode;
e2f0ba97 813
1a3665c8 814 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 815 return intel_sdvo_get_value(intel_sdvo,
816 SDVO_CMD_GET_SUPP_ENCODE,
817 &encode, sizeof(encode));
e2f0ba97
JB		 818}
819
ea5b213a 820static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 821 uint8_t mode)
e2f0ba97 822{
32aad86f 823 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 824}
825
ea5b213a 826static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 827 uint8_t mode)
828{
32aad86f 829 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 830}
831
832#if 0
ea5b213a 833static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 834{
835 int i, j;
836 uint8_t set_buf_index[2];
837 uint8_t av_split;
838 uint8_t buf_size;
839 uint8_t buf[48];
840 uint8_t *pos;
841
32aad86f 842 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 843
844 for (i = 0; i <= av_split; i++) {
845 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 846 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 847 set_buf_index, 2);
c751ce4f
EA		 848 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
849 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 850
851 pos = buf;
852 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 853 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 854 NULL, 0);
c751ce4f 855 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 856 pos += 8;
857 }
858 }
859}
860#endif
861
3c17fe4b 862static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 863{
864 struct dip_infoframe avi_if = {
865 .type = DIP_TYPE_AVI,
3c17fe4b 866 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 867 .len = DIP_LEN_AVI,
868 };
3c17fe4b
DH		 869 uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
870 uint8_t set_buf_index[2] = { 1, 0 };
871 uint64_t *data = (uint64_t *)&avi_if;
872 unsigned i;
873
874 intel_dip_infoframe_csum(&avi_if);
875
d121a5d2
CW		 876 if (!intel_sdvo_set_value(intel_sdvo,
877 SDVO_CMD_SET_HBUF_INDEX,
3c17fe4b
DH		 878 set_buf_index, 2))
879 return false;
880
881 for (i = 0; i < sizeof(avi_if); i += 8) {
d121a5d2
CW		 882 if (!intel_sdvo_set_value(intel_sdvo,
883 SDVO_CMD_SET_HBUF_DATA,
3c17fe4b
DH		 884 data, 8))
885 return false;
886 data++;
887 }
e2f0ba97 888
d121a5d2
CW		 889 return intel_sdvo_set_value(intel_sdvo,
890 SDVO_CMD_SET_HBUF_TXRATE,
3c17fe4b 891 &tx_rate, 1);
e2f0ba97
JB		 892}
893
32aad86f 894static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 895{
ce6feabd 896 struct intel_sdvo_tv_format format;
40039750 897 uint32_t format_map;
ce6feabd 898
40039750 899 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 900 memset(&format, 0, sizeof(format));
32aad86f 901 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 902
32aad86f
CW		 903 BUILD_BUG_ON(sizeof(format) != 6);
904 return intel_sdvo_set_value(intel_sdvo,
905 SDVO_CMD_SET_TV_FORMAT,
906 &format, sizeof(format));
7026d4ac
ZW		 907}
908
32aad86f
CW		 909static bool
910intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
911 struct drm_display_mode *mode)
e2f0ba97 912{
32aad86f 913 struct intel_sdvo_dtd output_dtd;
79e53945 914
32aad86f
CW		 915 if (!intel_sdvo_set_target_output(intel_sdvo,
916 intel_sdvo->attached_output))
917 return false;
e2f0ba97 918
32aad86f
CW		 919 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
920 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
921 return false;
e2f0ba97 922
32aad86f
CW		 923 return true;
924}
925
926static bool
927intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
928 struct drm_display_mode *mode,
929 struct drm_display_mode *adjusted_mode)
930{
32aad86f
CW		 931 /* Reset the input timing to the screen. Assume always input 0. */
932 if (!intel_sdvo_set_target_input(intel_sdvo))
933 return false;
e2f0ba97 934
32aad86f
CW		 935 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
936 mode->clock / 10,
937 mode->hdisplay,
938 mode->vdisplay))
939 return false;
e2f0ba97 940
32aad86f 941 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
6c9547ff 942 &intel_sdvo->input_dtd))
32aad86f 943 return false;
e2f0ba97 944
6c9547ff 945 intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
79e53945 946
32aad86f
CW		 947 return true;
948}
12682a97 949
32aad86f
CW		 950static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
951 struct drm_display_mode *mode,
952 struct drm_display_mode *adjusted_mode)
953{
890f3359 954 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 955 int multiplier;
12682a97 956
32aad86f
CW		 957 /* We need to construct preferred input timings based on our
958 * output timings. To do that, we have to set the output
959 * timings, even though this isn't really the right place in
960 * the sequence to do it. Oh well.
961 */
962 if (intel_sdvo->is_tv) {
963 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
964 return false;
12682a97 965
c74696b9
PR		 966 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
967 mode,
968 adjusted_mode);
ea5b213a 969 } else if (intel_sdvo->is_lvds) {
32aad86f 970 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 971 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 972 return false;
12682a97 973
c74696b9
PR		 974 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
975 mode,
976 adjusted_mode);
e2f0ba97 977 }
32aad86f
CW		 978
979 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 980 * SDVO device will factor out the multiplier during mode_set.
32aad86f 981 */
6c9547ff
CW		 982 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
983 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 984
e2f0ba97
JB		 985 return true;
986}
987
988static void intel_sdvo_mode_set(struct drm_encoder *encoder,
989 struct drm_display_mode *mode,
990 struct drm_display_mode *adjusted_mode)
991{
992 struct drm_device *dev = encoder->dev;
993 struct drm_i915_private *dev_priv = dev->dev_private;
994 struct drm_crtc *crtc = encoder->crtc;
995 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 996 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 997 u32 sdvox;
e2f0ba97
JB		 998 struct intel_sdvo_in_out_map in_out;
999 struct intel_sdvo_dtd input_dtd;
6c9547ff
CW		 1000 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1001 int rate;
e2f0ba97
JB		 1002
1003 if (!mode)
1004 return;
1005
1006 /* First, set the input mapping for the first input to our controlled
1007 * output. This is only correct if we're a single-input device, in
1008 * which case the first input is the output from the appropriate SDVO
1009 * channel on the motherboard. In a two-input device, the first input
1010 * will be SDVOB and the second SDVOC.
1011 */
ea5b213a 1012 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1013 in_out.in1 = 0;
1014
c74696b9
PR		 1015 intel_sdvo_set_value(intel_sdvo,
1016 SDVO_CMD_SET_IN_OUT_MAP,
1017 &in_out, sizeof(in_out));
e2f0ba97 1018
6c9547ff
CW		 1019 /* Set the output timings to the screen */
1020 if (!intel_sdvo_set_target_output(intel_sdvo,
1021 intel_sdvo->attached_output))
1022 return;
e2f0ba97 1023
7026d4ac 1024 /* We have tried to get input timing in mode_fixup, and filled into
6c9547ff 1025 * adjusted_mode.
e2f0ba97 1026 */
6c9547ff
CW		 1027 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
1028 input_dtd = intel_sdvo->input_dtd;
1029 } else {
e2f0ba97 1030 /* Set the output timing to the screen */
32aad86f
CW		 1031 if (!intel_sdvo_set_target_output(intel_sdvo,
1032 intel_sdvo->attached_output))
1033 return;
1034
6c9547ff 1035 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c74696b9 1036 (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
e2f0ba97 1037 }
79e53945
JB		 1038
1039 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1040 if (!intel_sdvo_set_target_input(intel_sdvo))
1041 return;
79e53945 1042
97aaf910
CW		 1043 if (intel_sdvo->has_hdmi_monitor) {
1044 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1045 intel_sdvo_set_colorimetry(intel_sdvo,
1046 SDVO_COLORIMETRY_RGB256);
1047 intel_sdvo_set_avi_infoframe(intel_sdvo);
1048 } else
1049 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1050
6c9547ff
CW		 1051 if (intel_sdvo->is_tv &&
1052 !intel_sdvo_set_tv_format(intel_sdvo))
1053 return;
e2f0ba97 1054
c74696b9 1055 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
79e53945 1056
6c9547ff
CW		 1057 switch (pixel_multiplier) {
1058 default:
32aad86f
CW		 1059 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1060 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1061 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1062 }
32aad86f
CW		 1063 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1064 return;
79e53945
JB		 1065
1066 /* Set the SDVO control regs. */
a6c45cf0 1067 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1068 /* The real mode polarity is set by the SDVO commands, using
1069 * struct intel_sdvo_dtd. */
1070 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
e953fd7b
CW		 1071 if (intel_sdvo->is_hdmi)
1072 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1073 if (INTEL_INFO(dev)->gen < 5)
1074 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1075 } else {
6c9547ff 1076 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1077 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1078 case SDVOB:
1079 sdvox &= SDVOB_PRESERVE_MASK;
1080 break;
1081 case SDVOC:
1082 sdvox &= SDVOC_PRESERVE_MASK;
1083 break;
1084 }
1085 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1086 }
3573c410
PZ		 1087
1088 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1089 sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
1090 else
1091 sdvox |= TRANSCODER(intel_crtc->pipe);
1092
da79de97 1093 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1094 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1095
a6c45cf0 1096 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1097 /* done in crtc_mode_set as the dpll_md reg must be written early */
1098 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1099 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1100 } else {
6c9547ff 1101 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1102 }
1103
6714afb1
CW		 1104 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1105 INTEL_INFO(dev)->gen < 5)
12682a97 1106 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1107 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1108}
1109
1110static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1111{
1112 struct drm_device *dev = encoder->dev;
1113 struct drm_i915_private *dev_priv = dev->dev_private;
890f3359 1114 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
9d0498a2 1115 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1116 u32 temp;
1117
1118 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1119 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1120 if (0)
ea5b213a 1121 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1122
1123 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1124 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1125 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1126 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1127 }
1128 }
1129 } else {
1130 bool input1, input2;
1131 int i;
1132 u8 status;
1133
ea5b213a 1134 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1135 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1136 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1137 for (i = 0; i < 2; i++)
9d0498a2 1138 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1139
32aad86f 1140 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1141 /* Warn if the device reported failure to sync.
1142 * A lot of SDVO devices fail to notify of sync, but it's
1143 * a given it the status is a success, we succeeded.
1144 */
1145 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1146 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1147 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1148 }
1149
1150 if (0)
ea5b213a
CW		 1151 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1152 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1153 }
1154 return;
1155}
1156
79e53945
JB		 1157static int intel_sdvo_mode_valid(struct drm_connector *connector,
1158 struct drm_display_mode *mode)
1159{
df0e9248 1160 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1161
1162 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1163 return MODE_NO_DBLESCAN;
1164
ea5b213a 1165 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1166 return MODE_CLOCK_LOW;
1167
ea5b213a 1168 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1169 return MODE_CLOCK_HIGH;
1170
8545423a 1171 if (intel_sdvo->is_lvds) {
ea5b213a 1172 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1173 return MODE_PANEL;
1174
ea5b213a 1175 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1176 return MODE_PANEL;
1177 }
1178
79e53945
JB		 1179 return MODE_OK;
1180}
1181
ea5b213a 1182static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1183{
1a3665c8 1184 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1185 if (!intel_sdvo_get_value(intel_sdvo,
1186 SDVO_CMD_GET_DEVICE_CAPS,
1187 caps, sizeof(*caps)))
1188 return false;
1189
1190 DRM_DEBUG_KMS("SDVO capabilities:\n"
1191 " vendor_id: %d\n"
1192 " device_id: %d\n"
1193 " device_rev_id: %d\n"
1194 " sdvo_version_major: %d\n"
1195 " sdvo_version_minor: %d\n"
1196 " sdvo_inputs_mask: %d\n"
1197 " smooth_scaling: %d\n"
1198 " sharp_scaling: %d\n"
1199 " up_scaling: %d\n"
1200 " down_scaling: %d\n"
1201 " stall_support: %d\n"
1202 " output_flags: %d\n",
1203 caps->vendor_id,
1204 caps->device_id,
1205 caps->device_rev_id,
1206 caps->sdvo_version_major,
1207 caps->sdvo_version_minor,
1208 caps->sdvo_inputs_mask,
1209 caps->smooth_scaling,
1210 caps->sharp_scaling,
1211 caps->up_scaling,
1212 caps->down_scaling,
1213 caps->stall_support,
1214 caps->output_flags);
1215
1216 return true;
79e53945
JB		 1217}
1218
cc68c81a 1219static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
79e53945
JB		 1220{
1221 u8 response[2];
79e53945 1222
32aad86f
CW		 1223 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1224 &response, 2) && response[0];
79e53945
JB		 1225}
1226
cc68c81a 1227static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1228{
cc68c81a 1229 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1230
cc68c81a 1231 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1232}
1233
fb7a46f3 1234static bool
ea5b213a 1235intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1236{
bc65212c 1237 /* Is there more than one type of output? */
2294488d 1238 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1239}
1240
f899fc64 1241static struct edid *
e957d772 1242intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1243{
e957d772
CW		 1244 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1245 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1246}
1247
ff482d83
CW		 1248/* Mac mini hack -- use the same DDC as the analog connector */
1249static struct edid *
1250intel_sdvo_get_analog_edid(struct drm_connector *connector)
1251{
f899fc64 1252 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1253
0c1dab89
CW		 1254 return drm_get_edid(connector,
1255 &dev_priv->gmbus[dev_priv->crt_ddc_pin].adapter);
ff482d83
CW		 1256}
1257
2b8d33f7 1258enum drm_connector_status
8bf38485 1259intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1260{
df0e9248 1261 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1262 enum drm_connector_status status;
1263 struct edid *edid;
9dff6af8 1264
e957d772 1265 edid = intel_sdvo_get_edid(connector);
57cdaf90 1266
ea5b213a 1267 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1268 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1269
7c3f0a27
ZY		 1270 /*
1271 * Don't use the 1 as the argument of DDC bus switch to get
1272 * the EDID. It is used for SDVO SPD ROM.
1273 */
9d1a903d 1274 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1275 intel_sdvo->ddc_bus = ddc;
1276 edid = intel_sdvo_get_edid(connector);
1277 if (edid)
7c3f0a27 1278 break;
7c3f0a27 1279 }
e957d772
CW		 1280 /*
1281 * If we found the EDID on the other bus,
1282 * assume that is the correct DDC bus.
1283 */
1284 if (edid == NULL)
1285 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1286 }
9d1a903d
CW		 1287
1288 /*
1289 * When there is no edid and no monitor is connected with VGA
1290 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1291 */
ff482d83
CW		 1292 if (edid == NULL)
1293 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1294
2f551c84 1295 status = connector_status_unknown;
9dff6af8 1296 if (edid != NULL) {
149c36a3 1297 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1298 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1299 status = connector_status_connected;
da79de97
CW		 1300 if (intel_sdvo->is_hdmi) {
1301 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1302 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1303 }
13946743
CW		 1304 } else
1305 status = connector_status_disconnected;
149c36a3 1306 connector->display_info.raw_edid = NULL;
9d1a903d
CW		 1307 kfree(edid);
1308 }
7f36e7ed
CW		 1309
1310 if (status == connector_status_connected) {
1311 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
1312 if (intel_sdvo_connector->force_audio)
da79de97 1313 intel_sdvo->has_hdmi_audio = intel_sdvo_connector->force_audio > 0;
7f36e7ed
CW		 1314 }
1315
2b8d33f7 1316 return status;
9dff6af8
ML		 1317}
1318
52220085
CW		 1319static bool
1320intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1321 struct edid *edid)
1322{
1323 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1324 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1325
1326 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1327 connector_is_digital, monitor_is_digital);
1328 return connector_is_digital == monitor_is_digital;
1329}
1330
7b334fcb 1331static enum drm_connector_status
930a9e28 1332intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1333{
fb7a46f3 1334 uint16_t response;
df0e9248 1335 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1336 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1337 enum drm_connector_status ret;
79e53945 1338
32aad86f 1339 if (!intel_sdvo_write_cmd(intel_sdvo,
e957d772 1340 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
32aad86f 1341 return connector_status_unknown;
ba84cd1f
CW		 1342
1343 /* add 30ms delay when the output type might be TV */
1344 if (intel_sdvo->caps.output_flags &
1345 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_CVBS0))
d09c23de 1346 mdelay(30);
ba84cd1f 1347
32aad86f
CW		 1348 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1349 return connector_status_unknown;
79e53945 1350
e957d772
CW		 1351 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1352 response & 0xff, response >> 8,
1353 intel_sdvo_connector->output_flag);
e2f0ba97 1354
fb7a46f3 1355 if (response == 0)
79e53945 1356 return connector_status_disconnected;
fb7a46f3 1357
ea5b213a 1358 intel_sdvo->attached_output = response;
14571b4c 1359
97aaf910
CW		 1360 intel_sdvo->has_hdmi_monitor = false;
1361 intel_sdvo->has_hdmi_audio = false;
1362
615fb93f 1363 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1364 ret = connector_status_disconnected;
13946743 1365 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1366 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1367 else {
1368 struct edid *edid;
1369
1370 /* if we have an edid check it matches the connection */
1371 edid = intel_sdvo_get_edid(connector);
1372 if (edid == NULL)
1373 edid = intel_sdvo_get_analog_edid(connector);
1374 if (edid != NULL) {
52220085
CW		 1375 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1376 edid))
13946743 1377 ret = connector_status_connected;
52220085
CW		 1378 else
1379 ret = connector_status_disconnected;
1380
13946743
CW		 1381 connector->display_info.raw_edid = NULL;
1382 kfree(edid);
1383 } else
1384 ret = connector_status_connected;
1385 }
14571b4c
ZW		 1386
1387 /* May update encoder flag for like clock for SDVO TV, etc.*/
1388 if (ret == connector_status_connected) {
ea5b213a
CW		 1389 intel_sdvo->is_tv = false;
1390 intel_sdvo->is_lvds = false;
1391 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1392
1393 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1394 intel_sdvo->is_tv = true;
1395 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1396 }
1397 if (response & SDVO_LVDS_MASK)
8545423a 1398 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1399 }
14571b4c
ZW		 1400
1401 return ret;
79e53945
JB		 1402}
1403
e2f0ba97 1404static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1405{
ff482d83 1406 struct edid *edid;
79e53945
JB		 1407
1408 /* set the bus switch and get the modes */
e957d772 1409 edid = intel_sdvo_get_edid(connector);
79e53945 1410
57cdaf90
KP		 1411 /*
1412 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1413 * link between analog and digital outputs. So, if the regular SDVO
1414 * DDC fails, check to see if the analog output is disconnected, in
1415 * which case we'll look there for the digital DDC data.
e2f0ba97 1416 */
f899fc64
CW		 1417 if (edid == NULL)
1418 edid = intel_sdvo_get_analog_edid(connector);
1419
ff482d83 1420 if (edid != NULL) {
52220085
CW		 1421 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1422 edid)) {
0c1dab89
CW		 1423 drm_mode_connector_update_edid_property(connector, edid);
1424 drm_add_edid_modes(connector, edid);
1425 }
13946743 1426
ff482d83
CW		 1427 connector->display_info.raw_edid = NULL;
1428 kfree(edid);
e2f0ba97 1429 }
e2f0ba97
JB		 1430}
1431
1432/*
1433 * Set of SDVO TV modes.
1434 * Note! This is in reply order (see loop in get_tv_modes).
1435 * XXX: all 60Hz refresh?
1436 */
b1f559ec 1437static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1438 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1439 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1440 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1441 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1442 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1443 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1444 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1445 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1447 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1448 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1449 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1450 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1451 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1453 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1454 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1455 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1456 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1457 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1458 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1459 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1460 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1462 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1463 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1465 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1466 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1468 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1469 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1470 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1471 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1472 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1473 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1474 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1475 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1477 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1478 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1479 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1480 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1481 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1483 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1484 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1485 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1486 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1487 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1489 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1490 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1492 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1493 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1494 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1495};
1496
1497static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1498{
df0e9248 1499 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1500 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1501 uint32_t reply = 0, format_map = 0;
1502 int i;
e2f0ba97
JB		 1503
1504 /* Read the list of supported input resolutions for the selected TV
1505 * format.
1506 */
40039750 1507 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1508 memcpy(&tv_res, &format_map,
32aad86f 1509 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1510
32aad86f
CW		 1511 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1512 return;
ce6feabd 1513
32aad86f 1514 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1515 if (!intel_sdvo_write_cmd(intel_sdvo,
1516 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1517 &tv_res, sizeof(tv_res)))
1518 return;
1519 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1520 return;
1521
1522 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1523 if (reply & (1 << i)) {
1524 struct drm_display_mode *nmode;
1525 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1526 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1527 if (nmode)
1528 drm_mode_probed_add(connector, nmode);
1529 }
e2f0ba97
JB		 1530}
1531
7086c87f
ML		 1532static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1533{
df0e9248 1534 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1535 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1536 struct drm_display_mode *newmode;
7086c87f
ML		 1537
1538 /*
1539 * Attempt to get the mode list from DDC.
1540 * Assume that the preferred modes are
1541 * arranged in priority order.
1542 */
f899fc64 1543 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1544 if (list_empty(&connector->probed_modes) == false)
12682a97 1545 goto end;
7086c87f
ML		 1546
1547 /* Fetch modes from VBT */
1548 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1549 newmode = drm_mode_duplicate(connector->dev,
1550 dev_priv->sdvo_lvds_vbt_mode);
1551 if (newmode != NULL) {
1552 /* Guarantee the mode is preferred */
1553 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1554 DRM_MODE_TYPE_DRIVER);
1555 drm_mode_probed_add(connector, newmode);
1556 }
1557 }
12682a97 1558
1559end:
1560 list_for_each_entry(newmode, &connector->probed_modes, head) {
1561 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1562 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1563 drm_mode_duplicate(connector->dev, newmode);
6c9547ff
CW		 1564
1565 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode,
1566 0);
1567
8545423a 1568 intel_sdvo->is_lvds = true;
12682a97 1569 break;
1570 }
1571 }
1572
7086c87f
ML		 1573}
1574
e2f0ba97
JB		 1575static int intel_sdvo_get_modes(struct drm_connector *connector)
1576{
615fb93f 1577 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1578
615fb93f 1579 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1580 intel_sdvo_get_tv_modes(connector);
615fb93f 1581 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1582 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1583 else
1584 intel_sdvo_get_ddc_modes(connector);
1585
32aad86f 1586 return !list_empty(&connector->probed_modes);
79e53945
JB		 1587}
1588
fcc8d672
CW		 1589static void
1590intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1591{
615fb93f 1592 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1593 struct drm_device *dev = connector->dev;
1594
c5521706
CW		 1595 if (intel_sdvo_connector->left)
1596 drm_property_destroy(dev, intel_sdvo_connector->left);
1597 if (intel_sdvo_connector->right)
1598 drm_property_destroy(dev, intel_sdvo_connector->right);
1599 if (intel_sdvo_connector->top)
1600 drm_property_destroy(dev, intel_sdvo_connector->top);
1601 if (intel_sdvo_connector->bottom)
1602 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1603 if (intel_sdvo_connector->hpos)
1604 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1605 if (intel_sdvo_connector->vpos)
1606 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1607 if (intel_sdvo_connector->saturation)
1608 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1609 if (intel_sdvo_connector->contrast)
1610 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1611 if (intel_sdvo_connector->hue)
1612 drm_property_destroy(dev, intel_sdvo_connector->hue);
1613 if (intel_sdvo_connector->sharpness)
1614 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1615 if (intel_sdvo_connector->flicker_filter)
1616 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1617 if (intel_sdvo_connector->flicker_filter_2d)
1618 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1619 if (intel_sdvo_connector->flicker_filter_adaptive)
1620 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1621 if (intel_sdvo_connector->tv_luma_filter)
1622 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1623 if (intel_sdvo_connector->tv_chroma_filter)
1624 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1625 if (intel_sdvo_connector->dot_crawl)
1626 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1627 if (intel_sdvo_connector->brightness)
1628 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1629}
1630
79e53945
JB		 1631static void intel_sdvo_destroy(struct drm_connector *connector)
1632{
615fb93f 1633 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1634
c5521706 1635 if (intel_sdvo_connector->tv_format)
ce6feabd 1636 drm_property_destroy(connector->dev,
c5521706 1637 intel_sdvo_connector->tv_format);
b9219c5e 1638
d2a82a6f 1639 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1640 drm_sysfs_connector_remove(connector);
1641 drm_connector_cleanup(connector);
d2a82a6f 1642 kfree(connector);
79e53945
JB		 1643}
1644
1aad7ac0
CW		 1645static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1646{
1647 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1648 struct edid *edid;
1649 bool has_audio = false;
1650
1651 if (!intel_sdvo->is_hdmi)
1652 return false;
1653
1654 edid = intel_sdvo_get_edid(connector);
1655 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1656 has_audio = drm_detect_monitor_audio(edid);
1657
1658 return has_audio;
1659}
1660
ce6feabd
ZY		 1661static int
1662intel_sdvo_set_property(struct drm_connector *connector,
1663 struct drm_property *property,
1664 uint64_t val)
1665{
df0e9248 1666 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1667 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1668 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1669 uint16_t temp_value;
32aad86f
CW		 1670 uint8_t cmd;
1671 int ret;
ce6feabd
ZY		 1672
1673 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1674 if (ret)
1675 return ret;
ce6feabd 1676
3f43c48d 1677 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1678 int i = val;
1679 bool has_audio;
1680
1681 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1682 return 0;
1683
1aad7ac0 1684 intel_sdvo_connector->force_audio = i;
7f36e7ed 1685
1aad7ac0
CW		 1686 if (i == 0)
1687 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1688 else
1689 has_audio = i > 0;
7f36e7ed 1690
1aad7ac0 1691 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1692 return 0;
7f36e7ed 1693
1aad7ac0 1694 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 1695 goto done;
1696 }
1697
e953fd7b
CW		 1698 if (property == dev_priv->broadcast_rgb_property) {
1699 if (val == !!intel_sdvo->color_range)
7f36e7ed
CW		 1700 return 0;
1701
e953fd7b 1702 intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
7f36e7ed
CW		 1703 goto done;
1704 }
1705
c5521706
CW		 1706#define CHECK_PROPERTY(name, NAME) \
1707 if (intel_sdvo_connector->name == property) { \
1708 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1709 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1710 cmd = SDVO_CMD_SET_##NAME; \
1711 intel_sdvo_connector->cur_##name = temp_value; \
1712 goto set_value; \
1713 }
1714
1715 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1716 if (val >= TV_FORMAT_NUM)
1717 return -EINVAL;
1718
40039750 1719 if (intel_sdvo->tv_format_index ==
615fb93f 1720 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1721 return 0;
ce6feabd 1722
40039750 1723 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1724 goto done;
32aad86f 1725 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1726 temp_value = val;
c5521706 1727 if (intel_sdvo_connector->left == property) {
b9219c5e 1728 drm_connector_property_set_value(connector,
c5521706 1729 intel_sdvo_connector->right, val);
615fb93f 1730 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1731 return 0;
b9219c5e 1732
615fb93f
CW		 1733 intel_sdvo_connector->left_margin = temp_value;
1734 intel_sdvo_connector->right_margin = temp_value;
1735 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1736 intel_sdvo_connector->left_margin;
b9219c5e 1737 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1738 goto set_value;
1739 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1740 drm_connector_property_set_value(connector,
c5521706 1741 intel_sdvo_connector->left, val);
615fb93f 1742 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1743 return 0;
b9219c5e 1744
615fb93f
CW		 1745 intel_sdvo_connector->left_margin = temp_value;
1746 intel_sdvo_connector->right_margin = temp_value;
1747 temp_value = intel_sdvo_connector->max_hscan -
1748 intel_sdvo_connector->left_margin;
b9219c5e 1749 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1750 goto set_value;
1751 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1752 drm_connector_property_set_value(connector,
c5521706 1753 intel_sdvo_connector->bottom, val);
615fb93f 1754 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1755 return 0;
b9219c5e 1756
615fb93f
CW		 1757 intel_sdvo_connector->top_margin = temp_value;
1758 intel_sdvo_connector->bottom_margin = temp_value;
1759 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1760 intel_sdvo_connector->top_margin;
b9219c5e 1761 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1762 goto set_value;
1763 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1764 drm_connector_property_set_value(connector,
c5521706 1765 intel_sdvo_connector->top, val);
615fb93f 1766 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1767 return 0;
1768
615fb93f
CW		 1769 intel_sdvo_connector->top_margin = temp_value;
1770 intel_sdvo_connector->bottom_margin = temp_value;
1771 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1772 intel_sdvo_connector->top_margin;
b9219c5e 1773 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1774 goto set_value;
1775 }
1776 CHECK_PROPERTY(hpos, HPOS)
1777 CHECK_PROPERTY(vpos, VPOS)
1778 CHECK_PROPERTY(saturation, SATURATION)
1779 CHECK_PROPERTY(contrast, CONTRAST)
1780 CHECK_PROPERTY(hue, HUE)
1781 CHECK_PROPERTY(brightness, BRIGHTNESS)
1782 CHECK_PROPERTY(sharpness, SHARPNESS)
1783 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1784 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1785 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1786 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1787 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1788 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1789 }
b9219c5e 1790
c5521706 1791 return -EINVAL; /* unknown property */
b9219c5e 1792
c5521706
CW		 1793set_value:
1794 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1795 return -EIO;
b9219c5e 1796
b9219c5e 1797
c5521706 1798done:
df0e9248
CW		 1799 if (intel_sdvo->base.base.crtc) {
1800 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
ce6feabd 1801 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1802 crtc->y, crtc->fb);
1803 }
1804
32aad86f 1805 return 0;
c5521706 1806#undef CHECK_PROPERTY
ce6feabd
ZY		 1807}
1808
79e53945
JB		 1809static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1810 .dpms = intel_sdvo_dpms,
1811 .mode_fixup = intel_sdvo_mode_fixup,
1812 .prepare = intel_encoder_prepare,
1813 .mode_set = intel_sdvo_mode_set,
1814 .commit = intel_encoder_commit,
1815};
1816
1817static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1818 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1819 .detect = intel_sdvo_detect,
1820 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1821 .set_property = intel_sdvo_set_property,
79e53945
JB		 1822 .destroy = intel_sdvo_destroy,
1823};
1824
1825static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1826 .get_modes = intel_sdvo_get_modes,
1827 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1828 .best_encoder = intel_best_encoder,
79e53945
JB		 1829};
1830
b358d0a6 1831static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1832{
890f3359 1833 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 1834
ea5b213a 1835 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1836 drm_mode_destroy(encoder->dev,
ea5b213a 1837 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1838
e957d772 1839 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 1840 intel_encoder_destroy(encoder);
79e53945
JB		 1841}
1842
1843static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1844 .destroy = intel_sdvo_enc_destroy,
1845};
1846
b66d8424
CW		 1847static void
1848intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1849{
1850 uint16_t mask = 0;
1851 unsigned int num_bits;
1852
1853 /* Make a mask of outputs less than or equal to our own priority in the
1854 * list.
1855 */
1856 switch (sdvo->controlled_output) {
1857 case SDVO_OUTPUT_LVDS1:
1858 mask |= SDVO_OUTPUT_LVDS1;
1859 case SDVO_OUTPUT_LVDS0:
1860 mask |= SDVO_OUTPUT_LVDS0;
1861 case SDVO_OUTPUT_TMDS1:
1862 mask |= SDVO_OUTPUT_TMDS1;
1863 case SDVO_OUTPUT_TMDS0:
1864 mask |= SDVO_OUTPUT_TMDS0;
1865 case SDVO_OUTPUT_RGB1:
1866 mask |= SDVO_OUTPUT_RGB1;
1867 case SDVO_OUTPUT_RGB0:
1868 mask |= SDVO_OUTPUT_RGB0;
1869 break;
1870 }
1871
1872 /* Count bits to find what number we are in the priority list. */
1873 mask &= sdvo->caps.output_flags;
1874 num_bits = hweight16(mask);
1875 /* If more than 3 outputs, default to DDC bus 3 for now. */
1876 if (num_bits > 3)
1877 num_bits = 3;
1878
1879 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1880 sdvo->ddc_bus = 1 << num_bits;
1881}
79e53945 1882
e2f0ba97
JB		 1883/**
1884 * Choose the appropriate DDC bus for control bus switch command for this
1885 * SDVO output based on the controlled output.
1886 *
1887 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1888 * outputs, then LVDS outputs.
1889 */
1890static void
b1083333 1891intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1892 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1893{
b1083333 1894 struct sdvo_device_mapping *mapping;
e2f0ba97 1895
b1083333
AJ		 1896 if (IS_SDVOB(reg))
1897 mapping = &(dev_priv->sdvo_mappings[0]);
1898 else
1899 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1900
b66d8424
CW		 1901 if (mapping->initialized)
1902 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1903 else
1904 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1905}
1906
e957d772
CW		 1907static void
1908intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
1909 struct intel_sdvo *sdvo, u32 reg)
1910{
1911 struct sdvo_device_mapping *mapping;
46eb3036 1912 u8 pin;
e957d772
CW		 1913
1914 if (IS_SDVOB(reg))
1915 mapping = &dev_priv->sdvo_mappings[0];
1916 else
1917 mapping = &dev_priv->sdvo_mappings[1];
1918
1919 pin = GMBUS_PORT_DPB;
46eb3036 1920 if (mapping->initialized)
e957d772 1921 pin = mapping->i2c_pin;
e957d772 1922
63abf3ed
CW		 1923 if (pin < GMBUS_NUM_PORTS) {
1924 sdvo->i2c = &dev_priv->gmbus[pin].adapter;
d5090b96 1925 intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ);
63abf3ed 1926 intel_gmbus_force_bit(sdvo->i2c, true);
46eb3036 1927 } else {
63abf3ed 1928 sdvo->i2c = &dev_priv->gmbus[GMBUS_PORT_DPB].adapter;
46eb3036 1929 }
e957d772
CW		 1930}
1931
e2f0ba97 1932static bool
e27d8538 1933intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1934{
97aaf910 1935 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 1936}
1937
714605e4 1938static u8
c751ce4f 1939intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
714605e4 1940{
1941 struct drm_i915_private *dev_priv = dev->dev_private;
1942 struct sdvo_device_mapping *my_mapping, *other_mapping;
1943
461ed3ca 1944 if (IS_SDVOB(sdvo_reg)) {
714605e4 1945 my_mapping = &dev_priv->sdvo_mappings[0];
1946 other_mapping = &dev_priv->sdvo_mappings[1];
1947 } else {
1948 my_mapping = &dev_priv->sdvo_mappings[1];
1949 other_mapping = &dev_priv->sdvo_mappings[0];
1950 }
1951
1952 /* If the BIOS described our SDVO device, take advantage of it. */
1953 if (my_mapping->slave_addr)
1954 return my_mapping->slave_addr;
1955
1956 /* If the BIOS only described a different SDVO device, use the
1957 * address that it isn't using.
1958 */
1959 if (other_mapping->slave_addr) {
1960 if (other_mapping->slave_addr == 0x70)
1961 return 0x72;
1962 else
1963 return 0x70;
1964 }
1965
1966 /* No SDVO device info is found for another DVO port,
1967 * so use mapping assumption we had before BIOS parsing.
1968 */
461ed3ca 1969 if (IS_SDVOB(sdvo_reg))
714605e4 1970 return 0x70;
1971 else
1972 return 0x72;
1973}
1974
14571b4c 1975static void
df0e9248
CW		 1976intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
1977 struct intel_sdvo *encoder)
14571b4c 1978{
df0e9248
CW		 1979 drm_connector_init(encoder->base.base.dev,
1980 &connector->base.base,
1981 &intel_sdvo_connector_funcs,
1982 connector->base.base.connector_type);
6070a4a9 1983
df0e9248
CW		 1984 drm_connector_helper_add(&connector->base.base,
1985 &intel_sdvo_connector_helper_funcs);
14571b4c 1986
8f4839e2 1987 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 1988 connector->base.base.doublescan_allowed = 0;
1989 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
14571b4c 1990
df0e9248
CW		 1991 intel_connector_attach_encoder(&connector->base, &encoder->base);
1992 drm_sysfs_connector_add(&connector->base.base);
14571b4c 1993}
6070a4a9 1994
7f36e7ed
CW		 1995static void
1996intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
1997{
1998 struct drm_device *dev = connector->base.base.dev;
1999
3f43c48d 2000 intel_attach_force_audio_property(&connector->base.base);
e953fd7b
CW		 2001 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
2002 intel_attach_broadcast_rgb_property(&connector->base.base);
7f36e7ed
CW		 2003}
2004
fb7a46f3 2005static bool
ea5b213a 2006intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2007{
4ef69c7a 2008 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2009 struct drm_connector *connector;
cc68c81a 2010 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2011 struct intel_connector *intel_connector;
615fb93f 2012 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2013
615fb93f
CW		 2014 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2015 if (!intel_sdvo_connector)
14571b4c
ZW		 2016 return false;
2017
14571b4c 2018 if (device == 0) {
ea5b213a 2019 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2020 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2021 } else if (device == 1) {
ea5b213a 2022 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2023 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2024 }
2025
615fb93f 2026 intel_connector = &intel_sdvo_connector->base;
14571b4c 2027 connector = &intel_connector->base;
cc68c81a
SF		 2028 if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
2029 connector->polled = DRM_CONNECTOR_POLL_HPD;
2030 intel_sdvo->hotplug_active[0] |= 1 << device;
2031 /* Some SDVO devices have one-shot hotplug interrupts.
2032 * Ensure that they get re-enabled when an interrupt happens.
2033 */
2034 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2035 intel_sdvo_enable_hotplug(intel_encoder);
2036 }
2037 else
2038 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2039 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2040 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2041
e27d8538 2042 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2043 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2044 intel_sdvo->is_hdmi = true;
14571b4c 2045 }
ea5b213a
CW		 2046 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2047 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2048
df0e9248 2049 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221
CW		 2050 if (intel_sdvo->is_hdmi)
2051 intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
14571b4c
ZW		 2052
2053 return true;
2054}
2055
2056static bool
ea5b213a 2057intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2058{
4ef69c7a
CW		 2059 struct drm_encoder *encoder = &intel_sdvo->base.base;
2060 struct drm_connector *connector;
2061 struct intel_connector *intel_connector;
2062 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2063
615fb93f
CW		 2064 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2065 if (!intel_sdvo_connector)
2066 return false;
14571b4c 2067
615fb93f 2068 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2069 connector = &intel_connector->base;
2070 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2071 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2072
4ef69c7a
CW		 2073 intel_sdvo->controlled_output |= type;
2074 intel_sdvo_connector->output_flag = type;
14571b4c 2075
4ef69c7a
CW		 2076 intel_sdvo->is_tv = true;
2077 intel_sdvo->base.needs_tv_clock = true;
2078 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2079
df0e9248 2080 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2081
4ef69c7a 2082 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2083 goto err;
14571b4c 2084
4ef69c7a 2085 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2086 goto err;
14571b4c 2087
4ef69c7a 2088 return true;
32aad86f
CW		 2089
2090err:
123d5c01 2091 intel_sdvo_destroy(connector);
32aad86f 2092 return false;
14571b4c
ZW		 2093}
2094
2095static bool
ea5b213a 2096intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2097{
4ef69c7a
CW		 2098 struct drm_encoder *encoder = &intel_sdvo->base.base;
2099 struct drm_connector *connector;
2100 struct intel_connector *intel_connector;
2101 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2102
615fb93f
CW		 2103 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2104 if (!intel_sdvo_connector)
2105 return false;
14571b4c 2106
615fb93f 2107 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2108 connector = &intel_connector->base;
eb1f8e4f 2109 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2110 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2111 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2112
2113 if (device == 0) {
2114 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2115 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2116 } else if (device == 1) {
2117 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2118 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2119 }
2120
2121 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
ea5b213a 2122 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2123
df0e9248
CW		 2124 intel_sdvo_connector_init(intel_sdvo_connector,
2125 intel_sdvo);
4ef69c7a 2126 return true;
14571b4c
ZW		 2127}
2128
2129static bool
ea5b213a 2130intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2131{
4ef69c7a
CW		 2132 struct drm_encoder *encoder = &intel_sdvo->base.base;
2133 struct drm_connector *connector;
2134 struct intel_connector *intel_connector;
2135 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2136
615fb93f
CW		 2137 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2138 if (!intel_sdvo_connector)
2139 return false;
14571b4c 2140
615fb93f
CW		 2141 intel_connector = &intel_sdvo_connector->base;
2142 connector = &intel_connector->base;
4ef69c7a
CW		 2143 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2144 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2145
2146 if (device == 0) {
2147 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2148 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2149 } else if (device == 1) {
2150 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2151 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2152 }
2153
2154 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
ea5b213a 2155 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2156
df0e9248 2157 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2158 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2159 goto err;
2160
2161 return true;
2162
2163err:
123d5c01 2164 intel_sdvo_destroy(connector);
32aad86f 2165 return false;
14571b4c
ZW		 2166}
2167
2168static bool
ea5b213a 2169intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2170{
ea5b213a
CW		 2171 intel_sdvo->is_tv = false;
2172 intel_sdvo->base.needs_tv_clock = false;
2173 intel_sdvo->is_lvds = false;
fb7a46f3 2174
14571b4c 2175 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2176
14571b4c 2177 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2178 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2179 return false;
2180
2181 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2182 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2183 return false;
2184
2185 /* TV has no XXX1 function block */
a1f4b7ff 2186 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2187 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2188 return false;
2189
2190 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2191 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2192 return false;
fb7a46f3 2193
14571b4c 2194 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2195 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2196 return false;
2197
2198 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2199 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2200 return false;
2201
2202 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2203 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2204 return false;
2205
2206 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2207 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2208 return false;
fb7a46f3 2209
14571b4c 2210 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2211 unsigned char bytes[2];
2212
ea5b213a
CW		 2213 intel_sdvo->controlled_output = 0;
2214 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2215 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2216 SDVO_NAME(intel_sdvo),
51c8b407 2217 bytes[0], bytes[1]);
14571b4c 2218 return false;
fb7a46f3 2219 }
27f8227b 2220 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2221
14571b4c 2222 return true;
fb7a46f3 2223}
2224
32aad86f
CW		 2225static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2226 struct intel_sdvo_connector *intel_sdvo_connector,
2227 int type)
ce6feabd 2228{
4ef69c7a 2229 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2230 struct intel_sdvo_tv_format format;
2231 uint32_t format_map, i;
ce6feabd 2232
32aad86f
CW		 2233 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2234 return false;
ce6feabd 2235
1a3665c8 2236 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2237 if (!intel_sdvo_get_value(intel_sdvo,
2238 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2239 &format, sizeof(format)))
2240 return false;
ce6feabd 2241
32aad86f 2242 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2243
2244 if (format_map == 0)
32aad86f 2245 return false;
ce6feabd 2246
615fb93f 2247 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2248 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2249 if (format_map & (1 << i))
2250 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2251
2252
c5521706 2253 intel_sdvo_connector->tv_format =
32aad86f
CW		 2254 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2255 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2256 if (!intel_sdvo_connector->tv_format)
fcc8d672 2257 return false;
ce6feabd 2258
615fb93f 2259 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2260 drm_property_add_enum(
c5521706 2261 intel_sdvo_connector->tv_format, i,
40039750 2262 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2263
40039750 2264 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2265 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2266 intel_sdvo_connector->tv_format, 0);
32aad86f 2267 return true;
ce6feabd
ZY		 2268
2269}
2270
c5521706
CW		 2271#define ENHANCEMENT(name, NAME) do { \
2272 if (enhancements.name) { \
2273 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2274 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2275 return false; \
2276 intel_sdvo_connector->max_##name = data_value[0]; \
2277 intel_sdvo_connector->cur_##name = response; \
2278 intel_sdvo_connector->name = \
d9bc3c02 2279 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2280 if (!intel_sdvo_connector->name) return false; \
c5521706
CW		 2281 drm_connector_attach_property(connector, \
2282 intel_sdvo_connector->name, \
2283 intel_sdvo_connector->cur_##name); \
2284 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2285 data_value[0], data_value[1], response); \
2286 } \
0206e353 2287} while (0)
c5521706
CW		 2288
2289static bool
2290intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2291 struct intel_sdvo_connector *intel_sdvo_connector,
2292 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2293{
4ef69c7a 2294 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2295 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2296 uint16_t response, data_value[2];
2297
c5521706
CW		 2298 /* when horizontal overscan is supported, Add the left/right property */
2299 if (enhancements.overscan_h) {
2300 if (!intel_sdvo_get_value(intel_sdvo,
2301 SDVO_CMD_GET_MAX_OVERSCAN_H,
2302 &data_value, 4))
2303 return false;
32aad86f 2304
c5521706
CW		 2305 if (!intel_sdvo_get_value(intel_sdvo,
2306 SDVO_CMD_GET_OVERSCAN_H,
2307 &response, 2))
2308 return false;
fcc8d672 2309
c5521706
CW		 2310 intel_sdvo_connector->max_hscan = data_value[0];
2311 intel_sdvo_connector->left_margin = data_value[0] - response;
2312 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2313 intel_sdvo_connector->left =
d9bc3c02 2314 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2315 if (!intel_sdvo_connector->left)
2316 return false;
fcc8d672 2317
c5521706
CW		 2318 drm_connector_attach_property(connector,
2319 intel_sdvo_connector->left,
2320 intel_sdvo_connector->left_margin);
fcc8d672 2321
c5521706 2322 intel_sdvo_connector->right =
d9bc3c02 2323 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2324 if (!intel_sdvo_connector->right)
2325 return false;
32aad86f 2326
c5521706
CW		 2327 drm_connector_attach_property(connector,
2328 intel_sdvo_connector->right,
2329 intel_sdvo_connector->right_margin);
2330 DRM_DEBUG_KMS("h_overscan: max %d, "
2331 "default %d, current %d\n",
2332 data_value[0], data_value[1], response);
2333 }
32aad86f 2334
c5521706
CW		 2335 if (enhancements.overscan_v) {
2336 if (!intel_sdvo_get_value(intel_sdvo,
2337 SDVO_CMD_GET_MAX_OVERSCAN_V,
2338 &data_value, 4))
2339 return false;
fcc8d672 2340
c5521706
CW		 2341 if (!intel_sdvo_get_value(intel_sdvo,
2342 SDVO_CMD_GET_OVERSCAN_V,
2343 &response, 2))
2344 return false;
32aad86f 2345
c5521706
CW		 2346 intel_sdvo_connector->max_vscan = data_value[0];
2347 intel_sdvo_connector->top_margin = data_value[0] - response;
2348 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2349 intel_sdvo_connector->top =
d9bc3c02
SH		 2350 drm_property_create_range(dev, 0,
2351 "top_margin", 0, data_value[0]);
c5521706
CW		 2352 if (!intel_sdvo_connector->top)
2353 return false;
32aad86f 2354
c5521706
CW		 2355 drm_connector_attach_property(connector,
2356 intel_sdvo_connector->top,
2357 intel_sdvo_connector->top_margin);
fcc8d672 2358
c5521706 2359 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2360 drm_property_create_range(dev, 0,
2361 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2362 if (!intel_sdvo_connector->bottom)
2363 return false;
32aad86f 2364
c5521706
CW		 2365 drm_connector_attach_property(connector,
2366 intel_sdvo_connector->bottom,
2367 intel_sdvo_connector->bottom_margin);
2368 DRM_DEBUG_KMS("v_overscan: max %d, "
2369 "default %d, current %d\n",
2370 data_value[0], data_value[1], response);
2371 }
32aad86f 2372
c5521706
CW		 2373 ENHANCEMENT(hpos, HPOS);
2374 ENHANCEMENT(vpos, VPOS);
2375 ENHANCEMENT(saturation, SATURATION);
2376 ENHANCEMENT(contrast, CONTRAST);
2377 ENHANCEMENT(hue, HUE);
2378 ENHANCEMENT(sharpness, SHARPNESS);
2379 ENHANCEMENT(brightness, BRIGHTNESS);
2380 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2381 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2382 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2383 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2384 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2385
e044218a
CW		 2386 if (enhancements.dot_crawl) {
2387 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2388 return false;
2389
2390 intel_sdvo_connector->max_dot_crawl = 1;
2391 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2392 intel_sdvo_connector->dot_crawl =
d9bc3c02 2393 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2394 if (!intel_sdvo_connector->dot_crawl)
2395 return false;
2396
e044218a
CW		 2397 drm_connector_attach_property(connector,
2398 intel_sdvo_connector->dot_crawl,
2399 intel_sdvo_connector->cur_dot_crawl);
2400 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2401 }
2402
c5521706
CW		 2403 return true;
2404}
32aad86f 2405
c5521706
CW		 2406static bool
2407intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2408 struct intel_sdvo_connector *intel_sdvo_connector,
2409 struct intel_sdvo_enhancements_reply enhancements)
2410{
4ef69c7a 2411 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2412 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2413 uint16_t response, data_value[2];
32aad86f 2414
c5521706 2415 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2416
c5521706
CW		 2417 return true;
2418}
2419#undef ENHANCEMENT
32aad86f 2420
c5521706
CW		 2421static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2422 struct intel_sdvo_connector *intel_sdvo_connector)
2423{
2424 union {
2425 struct intel_sdvo_enhancements_reply reply;
2426 uint16_t response;
2427 } enhancements;
32aad86f 2428
1a3665c8
CW		 2429 BUILD_BUG_ON(sizeof(enhancements) != 2);
2430
cf9a2f3a
CW		 2431 enhancements.response = 0;
2432 intel_sdvo_get_value(intel_sdvo,
2433 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2434 &enhancements, sizeof(enhancements));
c5521706
CW		 2435 if (enhancements.response == 0) {
2436 DRM_DEBUG_KMS("No enhancement is supported\n");
2437 return true;
b9219c5e 2438 }
32aad86f 2439
c5521706
CW		 2440 if (IS_TV(intel_sdvo_connector))
2441 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2442 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2443 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2444 else
2445 return true;
e957d772
CW		 2446}
2447
2448static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2449 struct i2c_msg *msgs,
2450 int num)
2451{
2452 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2453
e957d772
CW		 2454 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2455 return -EIO;
2456
2457 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2458}
2459
2460static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2461{
2462 struct intel_sdvo *sdvo = adapter->algo_data;
2463 return sdvo->i2c->algo->functionality(sdvo->i2c);
2464}
2465
2466static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2467 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2468 .functionality = intel_sdvo_ddc_proxy_func
2469};
2470
2471static bool
2472intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2473 struct drm_device *dev)
2474{
2475 sdvo->ddc.owner = THIS_MODULE;
2476 sdvo->ddc.class = I2C_CLASS_DDC;
2477 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2478 sdvo->ddc.dev.parent = &dev->pdev->dev;
2479 sdvo->ddc.algo_data = sdvo;
2480 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2481
2482 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2483}
2484
c751ce4f 2485bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
79e53945 2486{
b01f2c3a 2487 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2488 struct intel_encoder *intel_encoder;
ea5b213a 2489 struct intel_sdvo *intel_sdvo;
79e53945 2490 int i;
79e53945 2491
ea5b213a
CW		 2492 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2493 if (!intel_sdvo)
7d57382e 2494 return false;
79e53945 2495
56184e3d
CW		 2496 intel_sdvo->sdvo_reg = sdvo_reg;
2497 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
2498 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
e957d772
CW		 2499 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
2500 kfree(intel_sdvo);
2501 return false;
2502 }
2503
56184e3d 2504 /* encoder type will be decided later */
ea5b213a 2505 intel_encoder = &intel_sdvo->base;
21d40d37 2506 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2507 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2508
79e53945
JB		 2509 /* Read the regs to test if we can talk to the device */
2510 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2511 u8 byte;
2512
2513 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
8a4c47f3 2514 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
461ed3ca 2515 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
f899fc64 2516 goto err;
79e53945
JB		 2517 }
2518 }
2519
f899fc64 2520 if (IS_SDVOB(sdvo_reg))
b01f2c3a 2521 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
f899fc64 2522 else
b01f2c3a 2523 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
619ac3b7 2524
4ef69c7a 2525 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2526
af901ca1 2527 /* In default case sdvo lvds is false */
32aad86f 2528 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2529 goto err;
79e53945 2530
cc68c81a
SF		 2531 /* Set up hotplug command - note paranoia about contents of reply.
2532 * We assume that the hardware is in a sane state, and only touch
2533 * the bits we think we understand.
2534 */
2535 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
2536 &intel_sdvo->hotplug_active, 2);
2537 intel_sdvo->hotplug_active[0] &= ~0x3;
2538
ea5b213a
CW		 2539 if (intel_sdvo_output_setup(intel_sdvo,
2540 intel_sdvo->caps.output_flags) != true) {
51c8b407 2541 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
461ed3ca 2542 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
f899fc64 2543 goto err;
79e53945
JB		 2544 }
2545
ea5b213a 2546 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2547
79e53945 2548 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2549 if (!intel_sdvo_set_target_input(intel_sdvo))
f899fc64 2550 goto err;
79e53945 2551
32aad86f
CW		 2552 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2553 &intel_sdvo->pixel_clock_min,
2554 &intel_sdvo->pixel_clock_max))
f899fc64 2555 goto err;
79e53945 2556
8a4c47f3 2557 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2558 "clock range %dMHz - %dMHz, "
2559 "input 1: %c, input 2: %c, "
2560 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2561 SDVO_NAME(intel_sdvo),
2562 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2563 intel_sdvo->caps.device_rev_id,
2564 intel_sdvo->pixel_clock_min / 1000,
2565 intel_sdvo->pixel_clock_max / 1000,
2566 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2567 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2568 /* check currently supported outputs */
ea5b213a 2569 intel_sdvo->caps.output_flags &
79e53945 2570 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2571 intel_sdvo->caps.output_flags &
79e53945 2572 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2573 return true;
79e53945 2574
f899fc64 2575err:
373a3cf7 2576 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2577 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2578 kfree(intel_sdvo);
79e53945 2579
7d57382e 2580 return false;
79e53945 2581}
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