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drm/i915: Apply the IBX transcoder A w/a for HDMI to SDVO as well
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
ea5b213a 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
79e53945
JB		 37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 46 SDVO_TV_MASK)
14571b4c
ZW		 47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 50#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 51#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 52#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 53
79e53945 54
2e88e40b 55static const char *tv_format_names[] = {
ce6feabd
ZY		 56 "NTSC_M" , "NTSC_J" , "NTSC_443",
57 "PAL_B" , "PAL_D" , "PAL_G" ,
58 "PAL_H" , "PAL_I" , "PAL_M" ,
59 "PAL_N" , "PAL_NC" , "PAL_60" ,
60 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
61 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
62 "SECAM_60"
63};
64
65#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
66
ea5b213a
CW		 67struct intel_sdvo {
68 struct intel_encoder base;
69
f899fc64 70 struct i2c_adapter *i2c;
f9c10a9b 71 u8 slave_addr;
e2f0ba97 72
e957d772
CW		 73 struct i2c_adapter ddc;
74
e2f0ba97 75 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 76 uint32_t sdvo_reg;
79e53945 77
e2f0ba97
JB		 78 /* Active outputs controlled by this SDVO output */
79 uint16_t controlled_output;
79e53945 80
e2f0ba97
JB		 81 /*
82 * Capabilities of the SDVO device returned by
83 * i830_sdvo_get_capabilities()
84 */
79e53945 85 struct intel_sdvo_caps caps;
e2f0ba97
JB		 86
87 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 88 int pixel_clock_min, pixel_clock_max;
89
fb7a46f3 90 /*
91 * For multiple function SDVO device,
92 * this is for current attached outputs.
93 */
94 uint16_t attached_output;
95
cc68c81a
SF		 96 /*
97 * Hotplug activation bits for this device
98 */
5fa7ac9c 99 uint16_t hotplug_active;
cc68c81a 100
e953fd7b
CW		 101 /**
102 * This is used to select the color range of RBG outputs in HDMI mode.
103 * It is only valid when using TMDS encoding and 8 bit per color mode.
104 */
105 uint32_t color_range;
106
e2f0ba97
JB		 107 /**
108 * This is set if we're going to treat the device as TV-out.
109 *
110 * While we have these nice friendly flags for output types that ought
111 * to decide this for us, the S-Video output on our HDMI+S-Video card
112 * shows up as RGB1 (VGA).
113 */
114 bool is_tv;
115
eef4eacb
DV		 116 /* On different gens SDVOB is at different places. */
117 bool is_sdvob;
118
ce6feabd 119 /* This is for current tv format name */
40039750 120 int tv_format_index;
ce6feabd 121
e2f0ba97
JB		 122 /**
123 * This is set if we treat the device as HDMI, instead of DVI.
124 */
125 bool is_hdmi;
da79de97
CW		 126 bool has_hdmi_monitor;
127 bool has_hdmi_audio;
12682a97 128
7086c87f 129 /**
6c9547ff
CW		 130 * This is set if we detect output of sdvo device as LVDS and
131 * have a valid fixed mode to use with the panel.
7086c87f
ML		 132 */
133 bool is_lvds;
e2f0ba97 134
12682a97 135 /**
136 * This is sdvo fixed pannel mode pointer
137 */
138 struct drm_display_mode *sdvo_lvds_fixed_mode;
139
c751ce4f 140 /* DDC bus used by this SDVO encoder */
e2f0ba97 141 uint8_t ddc_bus;
e751823d
EE		 142
143 /*
144 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
145 */
146 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 147};
148
149struct intel_sdvo_connector {
615fb93f
CW		 150 struct intel_connector base;
151
14571b4c
ZW		 152 /* Mark the type of connector */
153 uint16_t output_flag;
154
c3e5f67b 155 enum hdmi_force_audio force_audio;
7f36e7ed 156
14571b4c 157 /* This contains all current supported TV format */
40039750 158 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 159 int format_supported_num;
c5521706 160 struct drm_property *tv_format;
14571b4c 161
b9219c5e 162 /* add the property for the SDVO-TV */
c5521706
CW		 163 struct drm_property *left;
164 struct drm_property *right;
165 struct drm_property *top;
166 struct drm_property *bottom;
167 struct drm_property *hpos;
168 struct drm_property *vpos;
169 struct drm_property *contrast;
170 struct drm_property *saturation;
171 struct drm_property *hue;
172 struct drm_property *sharpness;
173 struct drm_property *flicker_filter;
174 struct drm_property *flicker_filter_adaptive;
175 struct drm_property *flicker_filter_2d;
176 struct drm_property *tv_chroma_filter;
177 struct drm_property *tv_luma_filter;
e044218a 178 struct drm_property *dot_crawl;
b9219c5e
ZY		 179
180 /* add the property for the SDVO-TV/LVDS */
c5521706 181 struct drm_property *brightness;
b9219c5e
ZY		 182
183 /* Add variable to record current setting for the above property */
184 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 185
b9219c5e
ZY		 186 /* this is to get the range of margin.*/
187 u32 max_hscan, max_vscan;
188 u32 max_hpos, cur_hpos;
189 u32 max_vpos, cur_vpos;
190 u32 cur_brightness, max_brightness;
191 u32 cur_contrast, max_contrast;
192 u32 cur_saturation, max_saturation;
193 u32 cur_hue, max_hue;
c5521706
CW		 194 u32 cur_sharpness, max_sharpness;
195 u32 cur_flicker_filter, max_flicker_filter;
196 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
197 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
198 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
199 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 200 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 201};
202
890f3359 203static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 204{
4ef69c7a 205 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 206}
207
df0e9248
CW		 208static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
209{
210 return container_of(intel_attached_encoder(connector),
211 struct intel_sdvo, base);
212}
213
615fb93f
CW		 214static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
215{
216 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
217}
218
fb7a46f3 219static bool
ea5b213a 220intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 221static bool
222intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
223 struct intel_sdvo_connector *intel_sdvo_connector,
224 int type);
225static bool
226intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
227 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 228
79e53945
JB		 229/**
230 * Writes the SDVOB or SDVOC with the given value, but always writes both
231 * SDVOB and SDVOC to work around apparent hardware issues (according to
232 * comments in the BIOS).
233 */
ea5b213a 234static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 235{
4ef69c7a 236 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 237 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 238 u32 bval = val, cval = val;
239 int i;
240
ea5b213a
CW		 241 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
242 I915_WRITE(intel_sdvo->sdvo_reg, val);
243 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 244 return;
245 }
246
ea5b213a 247 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 248 cval = I915_READ(SDVOC);
249 } else {
250 bval = I915_READ(SDVOB);
251 }
252 /*
253 * Write the registers twice for luck. Sometimes,
254 * writing them only once doesn't appear to 'stick'.
255 * The BIOS does this too. Yay, magic
256 */
257 for (i = 0; i < 2; i++)
258 {
259 I915_WRITE(SDVOB, bval);
260 I915_READ(SDVOB);
261 I915_WRITE(SDVOC, cval);
262 I915_READ(SDVOC);
263 }
264}
265
32aad86f 266static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 267{
79e53945
JB		 268 struct i2c_msg msgs[] = {
269 {
e957d772 270 .addr = intel_sdvo->slave_addr,
79e53945
JB		 271 .flags = 0,
272 .len = 1,
e957d772 273 .buf = &addr,
79e53945
JB		 274 },
275 {
e957d772 276 .addr = intel_sdvo->slave_addr,
79e53945
JB		 277 .flags = I2C_M_RD,
278 .len = 1,
e957d772 279 .buf = ch,
79e53945
JB		 280 }
281 };
32aad86f 282 int ret;
79e53945 283
f899fc64 284 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 285 return true;
79e53945 286
8a4c47f3 287 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 288 return false;
289}
290
79e53945
JB		 291#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
292/** Mapping of command numbers to names, for debug output */
005568be 293static const struct _sdvo_cmd_name {
e2f0ba97 294 u8 cmd;
2e88e40b 295 const char *name;
79e53945 296} sdvo_cmd_names[] = {
0206e353
AJ		 297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
340
341 /* Add the op code for SDVO enhancements */
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
386
387 /* HDMI op code */
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 408};
409
eef4eacb 410#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 411
ea5b213a 412static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 413 const void *args, int args_len)
79e53945 414{
79e53945
JB		 415 int i;
416
8a4c47f3 417 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 418 SDVO_NAME(intel_sdvo), cmd);
79e53945 419 for (i = 0; i < args_len; i++)
342dc382 420 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 421 for (; i < 8; i++)
342dc382 422 DRM_LOG_KMS(" ");
04ad327f 423 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 424 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 425 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 426 break;
427 }
428 }
04ad327f 429 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 430 DRM_LOG_KMS("(%02X)", cmd);
431 DRM_LOG_KMS("\n");
79e53945 432}
79e53945 433
e957d772
CW		 434static const char *cmd_status_names[] = {
435 "Power on",
436 "Success",
437 "Not supported",
438 "Invalid arg",
439 "Pending",
440 "Target not specified",
441 "Scaling not supported"
442};
443
32aad86f
CW		 444static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
445 const void *args, int args_len)
79e53945 446{
3bf3f452
BW		 447 u8 *buf, status;
448 struct i2c_msg *msgs;
449 int i, ret = true;
450
0274df3e 451 /* Would be simpler to allocate both in one go ? */
3bf3f452
BW		 452 buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
453 if (!buf)
454 return false;
455
456 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e
AC		 457 if (!msgs) {
458 kfree(buf);
3bf3f452 459 return false;
0274df3e 460 }
79e53945 461
ea5b213a 462 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 463
464 for (i = 0; i < args_len; i++) {
e957d772
CW		 465 msgs[i].addr = intel_sdvo->slave_addr;
466 msgs[i].flags = 0;
467 msgs[i].len = 2;
468 msgs[i].buf = buf + 2 *i;
469 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
470 buf[2*i + 1] = ((u8*)args)[i];
471 }
472 msgs[i].addr = intel_sdvo->slave_addr;
473 msgs[i].flags = 0;
474 msgs[i].len = 2;
475 msgs[i].buf = buf + 2*i;
476 buf[2*i + 0] = SDVO_I2C_OPCODE;
477 buf[2*i + 1] = cmd;
478
479 /* the following two are to read the response */
480 status = SDVO_I2C_CMD_STATUS;
481 msgs[i+1].addr = intel_sdvo->slave_addr;
482 msgs[i+1].flags = 0;
483 msgs[i+1].len = 1;
484 msgs[i+1].buf = &status;
485
486 msgs[i+2].addr = intel_sdvo->slave_addr;
487 msgs[i+2].flags = I2C_M_RD;
488 msgs[i+2].len = 1;
489 msgs[i+2].buf = &status;
490
491 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
492 if (ret < 0) {
493 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 494 ret = false;
495 goto out;
e957d772
CW		 496 }
497 if (ret != i+3) {
498 /* failure in I2C transfer */
499 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 500 ret = false;
e957d772
CW		 501 }
502
3bf3f452
BW		 503out:
504 kfree(msgs);
505 kfree(buf);
506 return ret;
79e53945
JB		 507}
508
b5c616a7
CW		 509static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
510 void *response, int response_len)
79e53945 511{
b5c616a7
CW		 512 u8 retry = 5;
513 u8 status;
33b52961 514 int i;
79e53945 515
d121a5d2
CW		 516 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
517
b5c616a7
CW		 518 /*
519 * The documentation states that all commands will be
520 * processed within 15µs, and that we need only poll
521 * the status byte a maximum of 3 times in order for the
522 * command to be complete.
523 *
524 * Check 5 times in case the hardware failed to read the docs.
525 */
d121a5d2
CW		 526 if (!intel_sdvo_read_byte(intel_sdvo,
527 SDVO_I2C_CMD_STATUS,
528 &status))
529 goto log_fail;
530
531 while (status == SDVO_CMD_STATUS_PENDING && retry--) {
532 udelay(15);
b5c616a7
CW		 533 if (!intel_sdvo_read_byte(intel_sdvo,
534 SDVO_I2C_CMD_STATUS,
535 &status))
d121a5d2
CW		 536 goto log_fail;
537 }
b5c616a7 538
79e53945 539 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 540 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 541 else
342dc382 542 DRM_LOG_KMS("(??? %d)", status);
79e53945 543
b5c616a7
CW		 544 if (status != SDVO_CMD_STATUS_SUCCESS)
545 goto log_fail;
79e53945 546
b5c616a7
CW		 547 /* Read the command response */
548 for (i = 0; i < response_len; i++) {
549 if (!intel_sdvo_read_byte(intel_sdvo,
550 SDVO_I2C_RETURN_0 + i,
551 &((u8 *)response)[i]))
552 goto log_fail;
e957d772 553 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 554 }
b5c616a7 555 DRM_LOG_KMS("\n");
b5c616a7 556 return true;
79e53945 557
b5c616a7 558log_fail:
d121a5d2 559 DRM_LOG_KMS("... failed\n");
b5c616a7 560 return false;
79e53945
JB		 561}
562
b358d0a6 563static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 564{
565 if (mode->clock >= 100000)
566 return 1;
567 else if (mode->clock >= 50000)
568 return 2;
569 else
570 return 4;
571}
572
e957d772
CW		 573static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
574 u8 ddc_bus)
79e53945 575{
d121a5d2 576 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 577 return intel_sdvo_write_cmd(intel_sdvo,
578 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
579 &ddc_bus, 1);
79e53945
JB		 580}
581
32aad86f 582static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 583{
d121a5d2
CW		 584 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
585 return false;
586
587 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 588}
79e53945 589
32aad86f
CW		 590static bool
591intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
592{
593 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
594 return false;
79e53945 595
32aad86f
CW		 596 return intel_sdvo_read_response(intel_sdvo, value, len);
597}
79e53945 598
32aad86f
CW		 599static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
600{
601 struct intel_sdvo_set_target_input_args targets = {0};
602 return intel_sdvo_set_value(intel_sdvo,
603 SDVO_CMD_SET_TARGET_INPUT,
604 &targets, sizeof(targets));
79e53945
JB		 605}
606
607/**
608 * Return whether each input is trained.
609 *
610 * This function is making an assumption about the layout of the response,
611 * which should be checked against the docs.
612 */
ea5b213a 613static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 614{
615 struct intel_sdvo_get_trained_inputs_response response;
79e53945 616
1a3665c8 617 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 618 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
619 &response, sizeof(response)))
79e53945
JB		 620 return false;
621
622 *input_1 = response.input0_trained;
623 *input_2 = response.input1_trained;
624 return true;
625}
626
ea5b213a 627static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 628 u16 outputs)
629{
32aad86f
CW		 630 return intel_sdvo_set_value(intel_sdvo,
631 SDVO_CMD_SET_ACTIVE_OUTPUTS,
632 &outputs, sizeof(outputs));
79e53945
JB		 633}
634
4ac41f47
DV		 635static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
636 u16 *outputs)
637{
638 return intel_sdvo_get_value(intel_sdvo,
639 SDVO_CMD_GET_ACTIVE_OUTPUTS,
640 outputs, sizeof(*outputs));
641}
642
ea5b213a 643static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 644 int mode)
645{
32aad86f 646 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 647
648 switch (mode) {
649 case DRM_MODE_DPMS_ON:
650 state = SDVO_ENCODER_STATE_ON;
651 break;
652 case DRM_MODE_DPMS_STANDBY:
653 state = SDVO_ENCODER_STATE_STANDBY;
654 break;
655 case DRM_MODE_DPMS_SUSPEND:
656 state = SDVO_ENCODER_STATE_SUSPEND;
657 break;
658 case DRM_MODE_DPMS_OFF:
659 state = SDVO_ENCODER_STATE_OFF;
660 break;
661 }
662
32aad86f
CW		 663 return intel_sdvo_set_value(intel_sdvo,
664 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 665}
666
ea5b213a 667static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 668 int *clock_min,
669 int *clock_max)
670{
671 struct intel_sdvo_pixel_clock_range clocks;
79e53945 672
1a3665c8 673 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 674 if (!intel_sdvo_get_value(intel_sdvo,
675 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
676 &clocks, sizeof(clocks)))
79e53945
JB		 677 return false;
678
679 /* Convert the values from units of 10 kHz to kHz. */
680 *clock_min = clocks.min * 10;
681 *clock_max = clocks.max * 10;
79e53945
JB		 682 return true;
683}
684
ea5b213a 685static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 686 u16 outputs)
687{
32aad86f
CW		 688 return intel_sdvo_set_value(intel_sdvo,
689 SDVO_CMD_SET_TARGET_OUTPUT,
690 &outputs, sizeof(outputs));
79e53945
JB		 691}
692
ea5b213a 693static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 694 struct intel_sdvo_dtd *dtd)
695{
32aad86f
CW		 696 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
697 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 698}
699
ea5b213a 700static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 701 struct intel_sdvo_dtd *dtd)
702{
ea5b213a 703 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 704 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
705}
706
ea5b213a 707static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 708 struct intel_sdvo_dtd *dtd)
709{
ea5b213a 710 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 711 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
712}
713
e2f0ba97 714static bool
ea5b213a 715intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 716 uint16_t clock,
717 uint16_t width,
718 uint16_t height)
719{
720 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 721
e642c6f1 722 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 723 args.clock = clock;
724 args.width = width;
725 args.height = height;
e642c6f1 726 args.interlace = 0;
12682a97 727
ea5b213a
CW		 728 if (intel_sdvo->is_lvds &&
729 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
730 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 731 args.scaled = 1;
732
32aad86f
CW		 733 return intel_sdvo_set_value(intel_sdvo,
734 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
735 &args, sizeof(args));
e2f0ba97
JB		 736}
737
ea5b213a 738static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 739 struct intel_sdvo_dtd *dtd)
740{
1a3665c8
CW		 741 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
742 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 743 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
744 &dtd->part1, sizeof(dtd->part1)) &&
745 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
746 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 747}
79e53945 748
ea5b213a 749static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 750{
32aad86f 751 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 752}
753
e2f0ba97 754static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 755 const struct drm_display_mode *mode)
79e53945 756{
e2f0ba97
JB		 757 uint16_t width, height;
758 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
759 uint16_t h_sync_offset, v_sync_offset;
6651819b 760 int mode_clock;
79e53945 761
c6ebd4c0
DV		 762 width = mode->hdisplay;
763 height = mode->vdisplay;
79e53945
JB		 764
765 /* do some mode translations */
c6ebd4c0
DV		 766 h_blank_len = mode->htotal - mode->hdisplay;
767 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 768
c6ebd4c0
DV		 769 v_blank_len = mode->vtotal - mode->vdisplay;
770 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 771
c6ebd4c0
DV		 772 h_sync_offset = mode->hsync_start - mode->hdisplay;
773 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 774
6651819b
DV		 775 mode_clock = mode->clock;
776 mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
777 mode_clock /= 10;
778 dtd->part1.clock = mode_clock;
779
e2f0ba97
JB		 780 dtd->part1.h_active = width & 0xff;
781 dtd->part1.h_blank = h_blank_len & 0xff;
782 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 783 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 784 dtd->part1.v_active = height & 0xff;
785 dtd->part1.v_blank = v_blank_len & 0xff;
786 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 787 ((v_blank_len >> 8) & 0xf);
788
171a9e96 789 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 790 dtd->part2.h_sync_width = h_sync_len & 0xff;
791 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 792 (v_sync_len & 0xf);
e2f0ba97 793 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 794 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
795 ((v_sync_len & 0x30) >> 4);
796
e2f0ba97 797 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 798 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
799 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 800 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 801 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 802 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 803 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97
JB		 804
805 dtd->part2.sdvo_flags = 0;
806 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
807 dtd->part2.reserved = 0;
808}
809
810static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 811 const struct intel_sdvo_dtd *dtd)
e2f0ba97 812{
e2f0ba97
JB		 813 mode->hdisplay = dtd->part1.h_active;
814 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
815 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 816 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 817 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
818 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
819 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
820 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
821
822 mode->vdisplay = dtd->part1.v_active;
823 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
824 mode->vsync_start = mode->vdisplay;
825 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 826 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 827 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
828 mode->vsync_end = mode->vsync_start +
829 (dtd->part2.v_sync_off_width & 0xf);
830 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
831 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
832 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
833
834 mode->clock = dtd->part1.clock * 10;
835
171a9e96 836 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
59d92bfa
DV		 837 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
838 mode->flags |= DRM_MODE_FLAG_INTERLACE;
839 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
e2f0ba97 840 mode->flags |= DRM_MODE_FLAG_PHSYNC;
59d92bfa 841 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
e2f0ba97
JB		 842 mode->flags |= DRM_MODE_FLAG_PVSYNC;
843}
844
e27d8538 845static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 846{
e27d8538 847 struct intel_sdvo_encode encode;
e2f0ba97 848
1a3665c8 849 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 850 return intel_sdvo_get_value(intel_sdvo,
851 SDVO_CMD_GET_SUPP_ENCODE,
852 &encode, sizeof(encode));
e2f0ba97
JB		 853}
854
ea5b213a 855static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 856 uint8_t mode)
e2f0ba97 857{
32aad86f 858 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 859}
860
ea5b213a 861static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 862 uint8_t mode)
863{
32aad86f 864 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 865}
866
867#if 0
ea5b213a 868static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 869{
870 int i, j;
871 uint8_t set_buf_index[2];
872 uint8_t av_split;
873 uint8_t buf_size;
874 uint8_t buf[48];
875 uint8_t *pos;
876
32aad86f 877 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 878
879 for (i = 0; i <= av_split; i++) {
880 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 881 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 882 set_buf_index, 2);
c751ce4f
EA		 883 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
884 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 885
886 pos = buf;
887 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 888 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 889 NULL, 0);
c751ce4f 890 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 891 pos += 8;
892 }
893 }
894}
895#endif
896
b6e0e543
DV		 897static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
898 unsigned if_index, uint8_t tx_rate,
899 uint8_t *data, unsigned length)
900{
901 uint8_t set_buf_index[2] = { if_index, 0 };
902 uint8_t hbuf_size, tmp[8];
903 int i;
904
905 if (!intel_sdvo_set_value(intel_sdvo,
906 SDVO_CMD_SET_HBUF_INDEX,
907 set_buf_index, 2))
908 return false;
909
910 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
911 &hbuf_size, 1))
912 return false;
913
914 /* Buffer size is 0 based, hooray! */
915 hbuf_size++;
916
917 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
918 if_index, length, hbuf_size);
919
920 for (i = 0; i < hbuf_size; i += 8) {
921 memset(tmp, 0, 8);
922 if (i < length)
923 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
924
925 if (!intel_sdvo_set_value(intel_sdvo,
926 SDVO_CMD_SET_HBUF_DATA,
927 tmp, 8))
928 return false;
929 }
930
931 return intel_sdvo_set_value(intel_sdvo,
932 SDVO_CMD_SET_HBUF_TXRATE,
933 &tx_rate, 1);
934}
935
3c17fe4b 936static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 937{
938 struct dip_infoframe avi_if = {
939 .type = DIP_TYPE_AVI,
3c17fe4b 940 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 941 .len = DIP_LEN_AVI,
942 };
81014b9d 943 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
3c17fe4b
DH		 944
945 intel_dip_infoframe_csum(&avi_if);
946
81014b9d
DV		 947 /* sdvo spec says that the ecc is handled by the hw, and it looks like
948 * we must not send the ecc field, either. */
949 memcpy(sdvo_data, &avi_if, 3);
950 sdvo_data[3] = avi_if.checksum;
951 memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
952
b6e0e543
DV		 953 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
954 SDVO_HBUF_TX_VSYNC,
955 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 956}
957
32aad86f 958static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 959{
ce6feabd 960 struct intel_sdvo_tv_format format;
40039750 961 uint32_t format_map;
ce6feabd 962
40039750 963 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 964 memset(&format, 0, sizeof(format));
32aad86f 965 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 966
32aad86f
CW		 967 BUILD_BUG_ON(sizeof(format) != 6);
968 return intel_sdvo_set_value(intel_sdvo,
969 SDVO_CMD_SET_TV_FORMAT,
970 &format, sizeof(format));
7026d4ac
ZW		 971}
972
32aad86f
CW		 973static bool
974intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 975 const struct drm_display_mode *mode)
e2f0ba97 976{
32aad86f 977 struct intel_sdvo_dtd output_dtd;
79e53945 978
32aad86f
CW		 979 if (!intel_sdvo_set_target_output(intel_sdvo,
980 intel_sdvo->attached_output))
981 return false;
e2f0ba97 982
32aad86f
CW		 983 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
984 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
985 return false;
e2f0ba97 986
32aad86f
CW		 987 return true;
988}
989
c9a29698
DV		 990/* Asks the sdvo controller for the preferred input mode given the output mode.
991 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 992static bool
c9a29698 993intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 994 const struct drm_display_mode *mode,
c9a29698 995 struct drm_display_mode *adjusted_mode)
32aad86f 996{
c9a29698
DV		 997 struct intel_sdvo_dtd input_dtd;
998
32aad86f
CW		 999 /* Reset the input timing to the screen. Assume always input 0. */
1000 if (!intel_sdvo_set_target_input(intel_sdvo))
1001 return false;
e2f0ba97 1002
32aad86f
CW		 1003 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1004 mode->clock / 10,
1005 mode->hdisplay,
1006 mode->vdisplay))
1007 return false;
e2f0ba97 1008
32aad86f 1009 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1010 &input_dtd))
32aad86f 1011 return false;
e2f0ba97 1012
c9a29698 1013 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1014 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1015
32aad86f
CW		 1016 return true;
1017}
12682a97 1018
32aad86f 1019static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
e811f5ae 1020 const struct drm_display_mode *mode,
32aad86f
CW		 1021 struct drm_display_mode *adjusted_mode)
1022{
890f3359 1023 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1024 int multiplier;
12682a97 1025
32aad86f
CW		 1026 /* We need to construct preferred input timings based on our
1027 * output timings. To do that, we have to set the output
1028 * timings, even though this isn't really the right place in
1029 * the sequence to do it. Oh well.
1030 */
1031 if (intel_sdvo->is_tv) {
1032 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1033 return false;
12682a97 1034
c9a29698
DV		 1035 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1036 mode,
1037 adjusted_mode);
ea5b213a 1038 } else if (intel_sdvo->is_lvds) {
32aad86f 1039 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1040 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1041 return false;
12682a97 1042
c9a29698
DV		 1043 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1044 mode,
1045 adjusted_mode);
e2f0ba97 1046 }
32aad86f
CW		 1047
1048 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1049 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1050 */
6c9547ff
CW		 1051 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
1052 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 1053
e2f0ba97
JB		 1054 return true;
1055}
1056
1057static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1058 struct drm_display_mode *mode,
1059 struct drm_display_mode *adjusted_mode)
1060{
1061 struct drm_device *dev = encoder->dev;
1062 struct drm_i915_private *dev_priv = dev->dev_private;
1063 struct drm_crtc *crtc = encoder->crtc;
1064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 1065 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1066 u32 sdvox;
e2f0ba97 1067 struct intel_sdvo_in_out_map in_out;
6651819b 1068 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff
CW		 1069 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1070 int rate;
e2f0ba97
JB		 1071
1072 if (!mode)
1073 return;
1074
1075 /* First, set the input mapping for the first input to our controlled
1076 * output. This is only correct if we're a single-input device, in
1077 * which case the first input is the output from the appropriate SDVO
1078 * channel on the motherboard. In a two-input device, the first input
1079 * will be SDVOB and the second SDVOC.
1080 */
ea5b213a 1081 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1082 in_out.in1 = 0;
1083
c74696b9
PR		 1084 intel_sdvo_set_value(intel_sdvo,
1085 SDVO_CMD_SET_IN_OUT_MAP,
1086 &in_out, sizeof(in_out));
e2f0ba97 1087
6c9547ff
CW		 1088 /* Set the output timings to the screen */
1089 if (!intel_sdvo_set_target_output(intel_sdvo,
1090 intel_sdvo->attached_output))
1091 return;
e2f0ba97 1092
6651819b
DV		 1093 /* lvds has a special fixed output timing. */
1094 if (intel_sdvo->is_lvds)
1095 intel_sdvo_get_dtd_from_mode(&output_dtd,
1096 intel_sdvo->sdvo_lvds_fixed_mode);
1097 else
1098 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1099 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1100 DRM_INFO("Setting output timings on %s failed\n",
1101 SDVO_NAME(intel_sdvo));
79e53945
JB		 1102
1103 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1104 if (!intel_sdvo_set_target_input(intel_sdvo))
1105 return;
79e53945 1106
97aaf910
CW		 1107 if (intel_sdvo->has_hdmi_monitor) {
1108 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1109 intel_sdvo_set_colorimetry(intel_sdvo,
1110 SDVO_COLORIMETRY_RGB256);
1111 intel_sdvo_set_avi_infoframe(intel_sdvo);
1112 } else
1113 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1114
6c9547ff
CW		 1115 if (intel_sdvo->is_tv &&
1116 !intel_sdvo_set_tv_format(intel_sdvo))
1117 return;
e2f0ba97 1118
6651819b
DV		 1119 /* We have tried to get input timing in mode_fixup, and filled into
1120 * adjusted_mode.
1121 */
1122 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
e751823d
EE		 1123 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1124 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1125 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1126 DRM_INFO("Setting input timings on %s failed\n",
1127 SDVO_NAME(intel_sdvo));
79e53945 1128
6c9547ff
CW		 1129 switch (pixel_multiplier) {
1130 default:
32aad86f
CW		 1131 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1132 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1133 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1134 }
32aad86f
CW		 1135 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1136 return;
79e53945
JB		 1137
1138 /* Set the SDVO control regs. */
a6c45cf0 1139 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1140 /* The real mode polarity is set by the SDVO commands, using
1141 * struct intel_sdvo_dtd. */
1142 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
e953fd7b
CW		 1143 if (intel_sdvo->is_hdmi)
1144 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1145 if (INTEL_INFO(dev)->gen < 5)
1146 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1147 } else {
6c9547ff 1148 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1149 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1150 case SDVOB:
1151 sdvox &= SDVOB_PRESERVE_MASK;
1152 break;
1153 case SDVOC:
1154 sdvox &= SDVOC_PRESERVE_MASK;
1155 break;
1156 }
1157 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1158 }
3573c410
PZ		 1159
1160 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1161 sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
1162 else
1163 sdvox |= TRANSCODER(intel_crtc->pipe);
1164
da79de97 1165 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1166 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1167
a6c45cf0 1168 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1169 /* done in crtc_mode_set as the dpll_md reg must be written early */
1170 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1171 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1172 } else {
6c9547ff 1173 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1174 }
1175
6714afb1
CW		 1176 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1177 INTEL_INFO(dev)->gen < 5)
12682a97 1178 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1179 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1180}
1181
4ac41f47 1182static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1183{
4ac41f47
DV		 1184 struct intel_sdvo_connector *intel_sdvo_connector =
1185 to_intel_sdvo_connector(&connector->base);
1186 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
1187 u16 active_outputs;
1188
1189 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1190
1191 if (active_outputs & intel_sdvo_connector->output_flag)
1192 return true;
1193 else
1194 return false;
1195}
1196
1197static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1198 enum pipe *pipe)
1199{
1200 struct drm_device *dev = encoder->base.dev;
79e53945 1201 struct drm_i915_private *dev_priv = dev->dev_private;
4ac41f47
DV		 1202 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1203 u32 tmp;
1204
1205 tmp = I915_READ(intel_sdvo->sdvo_reg);
1206
1207 if (!(tmp & SDVO_ENABLE))
1208 return false;
1209
1210 if (HAS_PCH_CPT(dev))
1211 *pipe = PORT_TO_PIPE_CPT(tmp);
1212 else
1213 *pipe = PORT_TO_PIPE(tmp);
1214
1215 return true;
1216}
1217
ce22c320
DV		 1218static void intel_disable_sdvo(struct intel_encoder *encoder)
1219{
1220 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1221 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1222 u32 temp;
1223
1224 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1225 if (0)
1226 intel_sdvo_set_encoder_power_state(intel_sdvo,
1227 DRM_MODE_DPMS_OFF);
1228
1229 temp = I915_READ(intel_sdvo->sdvo_reg);
1230 if ((temp & SDVO_ENABLE) != 0) {
776ca7cf
CW		 1231 /* HW workaround for IBX, we need to move the port to
1232 * transcoder A before disabling it. */
1233 if (HAS_PCH_IBX(encoder->base.dev)) {
1234 struct drm_crtc *crtc = encoder->base.crtc;
1235 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1236
1237 if (temp & SDVO_PIPE_B_SELECT) {
1238 temp &= ~SDVO_PIPE_B_SELECT;
1239 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1240 POSTING_READ(intel_sdvo->sdvo_reg);
1241
1242 /* Again we need to write this twice. */
1243 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1244 POSTING_READ(intel_sdvo->sdvo_reg);
1245
1246 /* Transcoder selection bits only update
1247 * effectively on vblank. */
1248 if (crtc)
1249 intel_wait_for_vblank(encoder->base.dev, pipe);
1250 else
1251 msleep(50);
1252 }
1253 }
1254
ce22c320
DV		 1255 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1256 }
1257}
1258
1259static void intel_enable_sdvo(struct intel_encoder *encoder)
1260{
1261 struct drm_device *dev = encoder->base.dev;
1262 struct drm_i915_private *dev_priv = dev->dev_private;
1263 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1264 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 1265 u32 temp;
ce22c320
DV		 1266 bool input1, input2;
1267 int i;
1268 u8 status;
1269
1270 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf
CW		 1271 if ((temp & SDVO_ENABLE) == 0) {
1272 /* HW workaround for IBX, we need to move the port
1273 * to transcoder A before disabling it. */
1274 if (HAS_PCH_IBX(dev)) {
1275 struct drm_crtc *crtc = encoder->base.crtc;
1276 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1277
1278 /* Restore the transcoder select bit. */
1279 if (pipe == PIPE_B)
1280 temp |= SDVO_PIPE_B_SELECT;
1281 }
1282
ce22c320 1283 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
776ca7cf 1284 }
ce22c320
DV		 1285 for (i = 0; i < 2; i++)
1286 intel_wait_for_vblank(dev, intel_crtc->pipe);
1287
1288 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1289 /* Warn if the device reported failure to sync.
1290 * A lot of SDVO devices fail to notify of sync, but it's
1291 * a given it the status is a success, we succeeded.
1292 */
1293 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1294 DRM_DEBUG_KMS("First %s output reported failure to "
1295 "sync\n", SDVO_NAME(intel_sdvo));
1296 }
1297
1298 if (0)
1299 intel_sdvo_set_encoder_power_state(intel_sdvo,
1300 DRM_MODE_DPMS_ON);
1301 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1302}
1303
b2cabb0e 1304static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
79e53945 1305{
b2cabb0e
DV		 1306 struct drm_crtc *crtc;
1307 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1308
1309 /* dvo supports only 2 dpms states. */
1310 if (mode != DRM_MODE_DPMS_ON)
1311 mode = DRM_MODE_DPMS_OFF;
1312
1313 if (mode == connector->dpms)
1314 return;
1315
1316 connector->dpms = mode;
1317
1318 /* Only need to change hw state when actually enabled */
1319 crtc = intel_sdvo->base.base.crtc;
1320 if (!crtc) {
1321 intel_sdvo->base.connectors_active = false;
1322 return;
1323 }
79e53945
JB		 1324
1325 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1326 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1327 if (0)
ea5b213a 1328 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945 1329
b2cabb0e
DV		 1330 intel_sdvo->base.connectors_active = false;
1331
1332 intel_crtc_update_dpms(crtc);
79e53945 1333 } else {
b2cabb0e
DV		 1334 intel_sdvo->base.connectors_active = true;
1335
1336 intel_crtc_update_dpms(crtc);
79e53945
JB		 1337
1338 if (0)
ea5b213a
CW		 1339 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1340 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945 1341 }
0a91ca29 1342
b980514c 1343 intel_modeset_check_state(connector->dev);
79e53945
JB		 1344}
1345
79e53945
JB		 1346static int intel_sdvo_mode_valid(struct drm_connector *connector,
1347 struct drm_display_mode *mode)
1348{
df0e9248 1349 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1350
1351 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1352 return MODE_NO_DBLESCAN;
1353
ea5b213a 1354 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1355 return MODE_CLOCK_LOW;
1356
ea5b213a 1357 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1358 return MODE_CLOCK_HIGH;
1359
8545423a 1360 if (intel_sdvo->is_lvds) {
ea5b213a 1361 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1362 return MODE_PANEL;
1363
ea5b213a 1364 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1365 return MODE_PANEL;
1366 }
1367
79e53945
JB		 1368 return MODE_OK;
1369}
1370
ea5b213a 1371static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1372{
1a3665c8 1373 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1374 if (!intel_sdvo_get_value(intel_sdvo,
1375 SDVO_CMD_GET_DEVICE_CAPS,
1376 caps, sizeof(*caps)))
1377 return false;
1378
1379 DRM_DEBUG_KMS("SDVO capabilities:\n"
1380 " vendor_id: %d\n"
1381 " device_id: %d\n"
1382 " device_rev_id: %d\n"
1383 " sdvo_version_major: %d\n"
1384 " sdvo_version_minor: %d\n"
1385 " sdvo_inputs_mask: %d\n"
1386 " smooth_scaling: %d\n"
1387 " sharp_scaling: %d\n"
1388 " up_scaling: %d\n"
1389 " down_scaling: %d\n"
1390 " stall_support: %d\n"
1391 " output_flags: %d\n",
1392 caps->vendor_id,
1393 caps->device_id,
1394 caps->device_rev_id,
1395 caps->sdvo_version_major,
1396 caps->sdvo_version_minor,
1397 caps->sdvo_inputs_mask,
1398 caps->smooth_scaling,
1399 caps->sharp_scaling,
1400 caps->up_scaling,
1401 caps->down_scaling,
1402 caps->stall_support,
1403 caps->output_flags);
1404
1405 return true;
79e53945
JB		 1406}
1407
5fa7ac9c 1408static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1409{
768b107e 1410 struct drm_device *dev = intel_sdvo->base.base.dev;
5fa7ac9c 1411 uint16_t hotplug;
79e53945 1412
768b107e
DV		 1413 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1414 * on the line. */
1415 if (IS_I945G(dev) || IS_I945GM(dev))
5fa7ac9c 1416 return 0;
768b107e 1417
5fa7ac9c
JN		 1418 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1419 &hotplug, sizeof(hotplug)))
1420 return 0;
768b107e 1421
5fa7ac9c 1422 return hotplug;
79e53945
JB		 1423}
1424
cc68c81a 1425static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1426{
cc68c81a 1427 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1428
5fa7ac9c
JN		 1429 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1430 &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1431}
1432
fb7a46f3 1433static bool
ea5b213a 1434intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1435{
bc65212c 1436 /* Is there more than one type of output? */
2294488d 1437 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1438}
1439
f899fc64 1440static struct edid *
e957d772 1441intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1442{
e957d772
CW		 1443 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1444 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1445}
1446
ff482d83
CW		 1447/* Mac mini hack -- use the same DDC as the analog connector */
1448static struct edid *
1449intel_sdvo_get_analog_edid(struct drm_connector *connector)
1450{
f899fc64 1451 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1452
0c1dab89 1453 return drm_get_edid(connector,
3bd7d909
DK		 1454 intel_gmbus_get_adapter(dev_priv,
1455 dev_priv->crt_ddc_pin));
ff482d83
CW		 1456}
1457
c43b5634 1458static enum drm_connector_status
8bf38485 1459intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1460{
df0e9248 1461 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1462 enum drm_connector_status status;
1463 struct edid *edid;
9dff6af8 1464
e957d772 1465 edid = intel_sdvo_get_edid(connector);
57cdaf90 1466
ea5b213a 1467 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1468 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1469
7c3f0a27
ZY		 1470 /*
1471 * Don't use the 1 as the argument of DDC bus switch to get
1472 * the EDID. It is used for SDVO SPD ROM.
1473 */
9d1a903d 1474 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1475 intel_sdvo->ddc_bus = ddc;
1476 edid = intel_sdvo_get_edid(connector);
1477 if (edid)
7c3f0a27 1478 break;
7c3f0a27 1479 }
e957d772
CW		 1480 /*
1481 * If we found the EDID on the other bus,
1482 * assume that is the correct DDC bus.
1483 */
1484 if (edid == NULL)
1485 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1486 }
9d1a903d
CW		 1487
1488 /*
1489 * When there is no edid and no monitor is connected with VGA
1490 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1491 */
ff482d83
CW		 1492 if (edid == NULL)
1493 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1494
2f551c84 1495 status = connector_status_unknown;
9dff6af8 1496 if (edid != NULL) {
149c36a3 1497 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1498 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1499 status = connector_status_connected;
da79de97
CW		 1500 if (intel_sdvo->is_hdmi) {
1501 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1502 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1503 }
13946743
CW		 1504 } else
1505 status = connector_status_disconnected;
9d1a903d
CW		 1506 kfree(edid);
1507 }
7f36e7ed
CW		 1508
1509 if (status == connector_status_connected) {
1510 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1511 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1512 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1513 }
1514
2b8d33f7 1515 return status;
9dff6af8
ML		 1516}
1517
52220085
CW		 1518static bool
1519intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1520 struct edid *edid)
1521{
1522 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1523 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1524
1525 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1526 connector_is_digital, monitor_is_digital);
1527 return connector_is_digital == monitor_is_digital;
1528}
1529
7b334fcb 1530static enum drm_connector_status
930a9e28 1531intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1532{
fb7a46f3 1533 uint16_t response;
df0e9248 1534 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1535 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1536 enum drm_connector_status ret;
79e53945 1537
32aad86f 1538 if (!intel_sdvo_write_cmd(intel_sdvo,
e957d772 1539 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
32aad86f 1540 return connector_status_unknown;
ba84cd1f
CW		 1541
1542 /* add 30ms delay when the output type might be TV */
a0b1c7a5 1543 if (intel_sdvo->caps.output_flags & SDVO_TV_MASK)
6c982376 1544 msleep(30);
ba84cd1f 1545
32aad86f
CW		 1546 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1547 return connector_status_unknown;
79e53945 1548
e957d772
CW		 1549 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1550 response & 0xff, response >> 8,
1551 intel_sdvo_connector->output_flag);
e2f0ba97 1552
fb7a46f3 1553 if (response == 0)
79e53945 1554 return connector_status_disconnected;
fb7a46f3 1555
ea5b213a 1556 intel_sdvo->attached_output = response;
14571b4c 1557
97aaf910
CW		 1558 intel_sdvo->has_hdmi_monitor = false;
1559 intel_sdvo->has_hdmi_audio = false;
1560
615fb93f 1561 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1562 ret = connector_status_disconnected;
13946743 1563 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1564 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1565 else {
1566 struct edid *edid;
1567
1568 /* if we have an edid check it matches the connection */
1569 edid = intel_sdvo_get_edid(connector);
1570 if (edid == NULL)
1571 edid = intel_sdvo_get_analog_edid(connector);
1572 if (edid != NULL) {
52220085
CW		 1573 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1574 edid))
13946743 1575 ret = connector_status_connected;
52220085
CW		 1576 else
1577 ret = connector_status_disconnected;
1578
13946743
CW		 1579 kfree(edid);
1580 } else
1581 ret = connector_status_connected;
1582 }
14571b4c
ZW		 1583
1584 /* May update encoder flag for like clock for SDVO TV, etc.*/
1585 if (ret == connector_status_connected) {
ea5b213a
CW		 1586 intel_sdvo->is_tv = false;
1587 intel_sdvo->is_lvds = false;
1588 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1589
1590 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1591 intel_sdvo->is_tv = true;
1592 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1593 }
1594 if (response & SDVO_LVDS_MASK)
8545423a 1595 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1596 }
14571b4c
ZW		 1597
1598 return ret;
79e53945
JB		 1599}
1600
e2f0ba97 1601static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1602{
ff482d83 1603 struct edid *edid;
79e53945
JB		 1604
1605 /* set the bus switch and get the modes */
e957d772 1606 edid = intel_sdvo_get_edid(connector);
79e53945 1607
57cdaf90
KP		 1608 /*
1609 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1610 * link between analog and digital outputs. So, if the regular SDVO
1611 * DDC fails, check to see if the analog output is disconnected, in
1612 * which case we'll look there for the digital DDC data.
e2f0ba97 1613 */
f899fc64
CW		 1614 if (edid == NULL)
1615 edid = intel_sdvo_get_analog_edid(connector);
1616
ff482d83 1617 if (edid != NULL) {
52220085
CW		 1618 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1619 edid)) {
0c1dab89
CW		 1620 drm_mode_connector_update_edid_property(connector, edid);
1621 drm_add_edid_modes(connector, edid);
1622 }
13946743 1623
ff482d83 1624 kfree(edid);
e2f0ba97 1625 }
e2f0ba97
JB		 1626}
1627
1628/*
1629 * Set of SDVO TV modes.
1630 * Note! This is in reply order (see loop in get_tv_modes).
1631 * XXX: all 60Hz refresh?
1632 */
b1f559ec 1633static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1634 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1635 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1636 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1637 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1638 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1639 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1640 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1641 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1642 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1643 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1644 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1645 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1646 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1647 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1648 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1649 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1650 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1651 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1652 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1653 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1654 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1655 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1656 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1657 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1658 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1659 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1660 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1661 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1662 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1663 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1664 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1665 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1666 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1667 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1668 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1669 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1670 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1671 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1672 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1673 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1674 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1675 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1676 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1677 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1678 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1679 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1680 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1681 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1682 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1683 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1684 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1685 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1686 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1687 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1688 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1689 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1690 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1691};
1692
1693static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1694{
df0e9248 1695 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1696 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1697 uint32_t reply = 0, format_map = 0;
1698 int i;
e2f0ba97
JB		 1699
1700 /* Read the list of supported input resolutions for the selected TV
1701 * format.
1702 */
40039750 1703 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1704 memcpy(&tv_res, &format_map,
32aad86f 1705 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1706
32aad86f
CW		 1707 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1708 return;
ce6feabd 1709
32aad86f 1710 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1711 if (!intel_sdvo_write_cmd(intel_sdvo,
1712 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1713 &tv_res, sizeof(tv_res)))
1714 return;
1715 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1716 return;
1717
1718 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1719 if (reply & (1 << i)) {
1720 struct drm_display_mode *nmode;
1721 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1722 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1723 if (nmode)
1724 drm_mode_probed_add(connector, nmode);
1725 }
e2f0ba97
JB		 1726}
1727
7086c87f
ML		 1728static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1729{
df0e9248 1730 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1731 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1732 struct drm_display_mode *newmode;
7086c87f
ML		 1733
1734 /*
1735 * Attempt to get the mode list from DDC.
1736 * Assume that the preferred modes are
1737 * arranged in priority order.
1738 */
f899fc64 1739 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1740 if (list_empty(&connector->probed_modes) == false)
12682a97 1741 goto end;
7086c87f
ML		 1742
1743 /* Fetch modes from VBT */
1744 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1745 newmode = drm_mode_duplicate(connector->dev,
1746 dev_priv->sdvo_lvds_vbt_mode);
1747 if (newmode != NULL) {
1748 /* Guarantee the mode is preferred */
1749 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1750 DRM_MODE_TYPE_DRIVER);
1751 drm_mode_probed_add(connector, newmode);
1752 }
1753 }
12682a97 1754
1755end:
1756 list_for_each_entry(newmode, &connector->probed_modes, head) {
1757 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1758 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1759 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1760
8545423a 1761 intel_sdvo->is_lvds = true;
12682a97 1762 break;
1763 }
1764 }
1765
7086c87f
ML		 1766}
1767
e2f0ba97
JB		 1768static int intel_sdvo_get_modes(struct drm_connector *connector)
1769{
615fb93f 1770 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1771
615fb93f 1772 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1773 intel_sdvo_get_tv_modes(connector);
615fb93f 1774 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1775 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1776 else
1777 intel_sdvo_get_ddc_modes(connector);
1778
32aad86f 1779 return !list_empty(&connector->probed_modes);
79e53945
JB		 1780}
1781
fcc8d672
CW		 1782static void
1783intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1784{
615fb93f 1785 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1786 struct drm_device *dev = connector->dev;
1787
c5521706
CW		 1788 if (intel_sdvo_connector->left)
1789 drm_property_destroy(dev, intel_sdvo_connector->left);
1790 if (intel_sdvo_connector->right)
1791 drm_property_destroy(dev, intel_sdvo_connector->right);
1792 if (intel_sdvo_connector->top)
1793 drm_property_destroy(dev, intel_sdvo_connector->top);
1794 if (intel_sdvo_connector->bottom)
1795 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1796 if (intel_sdvo_connector->hpos)
1797 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1798 if (intel_sdvo_connector->vpos)
1799 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1800 if (intel_sdvo_connector->saturation)
1801 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1802 if (intel_sdvo_connector->contrast)
1803 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1804 if (intel_sdvo_connector->hue)
1805 drm_property_destroy(dev, intel_sdvo_connector->hue);
1806 if (intel_sdvo_connector->sharpness)
1807 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1808 if (intel_sdvo_connector->flicker_filter)
1809 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1810 if (intel_sdvo_connector->flicker_filter_2d)
1811 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1812 if (intel_sdvo_connector->flicker_filter_adaptive)
1813 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1814 if (intel_sdvo_connector->tv_luma_filter)
1815 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1816 if (intel_sdvo_connector->tv_chroma_filter)
1817 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1818 if (intel_sdvo_connector->dot_crawl)
1819 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1820 if (intel_sdvo_connector->brightness)
1821 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1822}
1823
79e53945
JB		 1824static void intel_sdvo_destroy(struct drm_connector *connector)
1825{
615fb93f 1826 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1827
c5521706 1828 if (intel_sdvo_connector->tv_format)
ce6feabd 1829 drm_property_destroy(connector->dev,
c5521706 1830 intel_sdvo_connector->tv_format);
b9219c5e 1831
d2a82a6f 1832 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1833 drm_sysfs_connector_remove(connector);
1834 drm_connector_cleanup(connector);
d2a82a6f 1835 kfree(connector);
79e53945
JB		 1836}
1837
1aad7ac0
CW		 1838static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1839{
1840 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1841 struct edid *edid;
1842 bool has_audio = false;
1843
1844 if (!intel_sdvo->is_hdmi)
1845 return false;
1846
1847 edid = intel_sdvo_get_edid(connector);
1848 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1849 has_audio = drm_detect_monitor_audio(edid);
38ab8a20 1850 kfree(edid);
1aad7ac0
CW		 1851
1852 return has_audio;
1853}
1854
ce6feabd
ZY		 1855static int
1856intel_sdvo_set_property(struct drm_connector *connector,
1857 struct drm_property *property,
1858 uint64_t val)
1859{
df0e9248 1860 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1861 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1862 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1863 uint16_t temp_value;
32aad86f
CW		 1864 uint8_t cmd;
1865 int ret;
ce6feabd
ZY		 1866
1867 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1868 if (ret)
1869 return ret;
ce6feabd 1870
3f43c48d 1871 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1872 int i = val;
1873 bool has_audio;
1874
1875 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1876 return 0;
1877
1aad7ac0 1878 intel_sdvo_connector->force_audio = i;
7f36e7ed 1879
c3e5f67b 1880 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 1881 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1882 else
c3e5f67b 1883 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 1884
1aad7ac0 1885 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1886 return 0;
7f36e7ed 1887
1aad7ac0 1888 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 1889 goto done;
1890 }
1891
e953fd7b
CW		 1892 if (property == dev_priv->broadcast_rgb_property) {
1893 if (val == !!intel_sdvo->color_range)
7f36e7ed
CW		 1894 return 0;
1895
e953fd7b 1896 intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
7f36e7ed
CW		 1897 goto done;
1898 }
1899
c5521706
CW		 1900#define CHECK_PROPERTY(name, NAME) \
1901 if (intel_sdvo_connector->name == property) { \
1902 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1903 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1904 cmd = SDVO_CMD_SET_##NAME; \
1905 intel_sdvo_connector->cur_##name = temp_value; \
1906 goto set_value; \
1907 }
1908
1909 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1910 if (val >= TV_FORMAT_NUM)
1911 return -EINVAL;
1912
40039750 1913 if (intel_sdvo->tv_format_index ==
615fb93f 1914 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1915 return 0;
ce6feabd 1916
40039750 1917 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1918 goto done;
32aad86f 1919 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1920 temp_value = val;
c5521706 1921 if (intel_sdvo_connector->left == property) {
b9219c5e 1922 drm_connector_property_set_value(connector,
c5521706 1923 intel_sdvo_connector->right, val);
615fb93f 1924 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1925 return 0;
b9219c5e 1926
615fb93f
CW		 1927 intel_sdvo_connector->left_margin = temp_value;
1928 intel_sdvo_connector->right_margin = temp_value;
1929 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1930 intel_sdvo_connector->left_margin;
b9219c5e 1931 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1932 goto set_value;
1933 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1934 drm_connector_property_set_value(connector,
c5521706 1935 intel_sdvo_connector->left, val);
615fb93f 1936 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1937 return 0;
b9219c5e 1938
615fb93f
CW		 1939 intel_sdvo_connector->left_margin = temp_value;
1940 intel_sdvo_connector->right_margin = temp_value;
1941 temp_value = intel_sdvo_connector->max_hscan -
1942 intel_sdvo_connector->left_margin;
b9219c5e 1943 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1944 goto set_value;
1945 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1946 drm_connector_property_set_value(connector,
c5521706 1947 intel_sdvo_connector->bottom, val);
615fb93f 1948 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1949 return 0;
b9219c5e 1950
615fb93f
CW		 1951 intel_sdvo_connector->top_margin = temp_value;
1952 intel_sdvo_connector->bottom_margin = temp_value;
1953 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1954 intel_sdvo_connector->top_margin;
b9219c5e 1955 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1956 goto set_value;
1957 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1958 drm_connector_property_set_value(connector,
c5521706 1959 intel_sdvo_connector->top, val);
615fb93f 1960 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1961 return 0;
1962
615fb93f
CW		 1963 intel_sdvo_connector->top_margin = temp_value;
1964 intel_sdvo_connector->bottom_margin = temp_value;
1965 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1966 intel_sdvo_connector->top_margin;
b9219c5e 1967 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1968 goto set_value;
1969 }
1970 CHECK_PROPERTY(hpos, HPOS)
1971 CHECK_PROPERTY(vpos, VPOS)
1972 CHECK_PROPERTY(saturation, SATURATION)
1973 CHECK_PROPERTY(contrast, CONTRAST)
1974 CHECK_PROPERTY(hue, HUE)
1975 CHECK_PROPERTY(brightness, BRIGHTNESS)
1976 CHECK_PROPERTY(sharpness, SHARPNESS)
1977 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1978 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1979 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1980 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1981 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1982 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1983 }
b9219c5e 1984
c5521706 1985 return -EINVAL; /* unknown property */
b9219c5e 1986
c5521706
CW		 1987set_value:
1988 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1989 return -EIO;
b9219c5e 1990
b9219c5e 1991
c5521706 1992done:
df0e9248
CW		 1993 if (intel_sdvo->base.base.crtc) {
1994 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
a6778b3c
DV		 1995 intel_set_mode(crtc, &crtc->mode,
1996 crtc->x, crtc->y, crtc->fb);
c5521706
CW		 1997 }
1998
32aad86f 1999 return 0;
c5521706 2000#undef CHECK_PROPERTY
ce6feabd
ZY		 2001}
2002
79e53945 2003static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
79e53945 2004 .mode_fixup = intel_sdvo_mode_fixup,
79e53945 2005 .mode_set = intel_sdvo_mode_set,
1f703855 2006 .disable = intel_encoder_noop,
79e53945
JB		 2007};
2008
2009static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
b2cabb0e 2010 .dpms = intel_sdvo_dpms,
79e53945
JB		 2011 .detect = intel_sdvo_detect,
2012 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 2013 .set_property = intel_sdvo_set_property,
79e53945
JB		 2014 .destroy = intel_sdvo_destroy,
2015};
2016
2017static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2018 .get_modes = intel_sdvo_get_modes,
2019 .mode_valid = intel_sdvo_mode_valid,
df0e9248 2020 .best_encoder = intel_best_encoder,
79e53945
JB		 2021};
2022
b358d0a6 2023static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2024{
890f3359 2025 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 2026
ea5b213a 2027 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2028 drm_mode_destroy(encoder->dev,
ea5b213a 2029 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2030
e957d772 2031 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2032 intel_encoder_destroy(encoder);
79e53945
JB		 2033}
2034
2035static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2036 .destroy = intel_sdvo_enc_destroy,
2037};
2038
b66d8424
CW		 2039static void
2040intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2041{
2042 uint16_t mask = 0;
2043 unsigned int num_bits;
2044
2045 /* Make a mask of outputs less than or equal to our own priority in the
2046 * list.
2047 */
2048 switch (sdvo->controlled_output) {
2049 case SDVO_OUTPUT_LVDS1:
2050 mask |= SDVO_OUTPUT_LVDS1;
2051 case SDVO_OUTPUT_LVDS0:
2052 mask |= SDVO_OUTPUT_LVDS0;
2053 case SDVO_OUTPUT_TMDS1:
2054 mask |= SDVO_OUTPUT_TMDS1;
2055 case SDVO_OUTPUT_TMDS0:
2056 mask |= SDVO_OUTPUT_TMDS0;
2057 case SDVO_OUTPUT_RGB1:
2058 mask |= SDVO_OUTPUT_RGB1;
2059 case SDVO_OUTPUT_RGB0:
2060 mask |= SDVO_OUTPUT_RGB0;
2061 break;
2062 }
2063
2064 /* Count bits to find what number we are in the priority list. */
2065 mask &= sdvo->caps.output_flags;
2066 num_bits = hweight16(mask);
2067 /* If more than 3 outputs, default to DDC bus 3 for now. */
2068 if (num_bits > 3)
2069 num_bits = 3;
2070
2071 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2072 sdvo->ddc_bus = 1 << num_bits;
2073}
79e53945 2074
e2f0ba97
JB		 2075/**
2076 * Choose the appropriate DDC bus for control bus switch command for this
2077 * SDVO output based on the controlled output.
2078 *
2079 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2080 * outputs, then LVDS outputs.
2081 */
2082static void
b1083333 2083intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 2084 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 2085{
b1083333 2086 struct sdvo_device_mapping *mapping;
e2f0ba97 2087
eef4eacb 2088 if (sdvo->is_sdvob)
b1083333
AJ		 2089 mapping = &(dev_priv->sdvo_mappings[0]);
2090 else
2091 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 2092
b66d8424
CW		 2093 if (mapping->initialized)
2094 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2095 else
2096 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2097}
2098
e957d772
CW		 2099static void
2100intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2101 struct intel_sdvo *sdvo, u32 reg)
2102{
2103 struct sdvo_device_mapping *mapping;
46eb3036 2104 u8 pin;
e957d772 2105
eef4eacb 2106 if (sdvo->is_sdvob)
e957d772
CW		 2107 mapping = &dev_priv->sdvo_mappings[0];
2108 else
2109 mapping = &dev_priv->sdvo_mappings[1];
2110
6cb1612a 2111 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
e957d772 2112 pin = mapping->i2c_pin;
6cb1612a
JN		 2113 else
2114 pin = GMBUS_PORT_DPB;
e957d772 2115
6cb1612a
JN		 2116 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2117
2118 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2119 * our code totally fails once we start using gmbus. Hence fall back to
2120 * bit banging for now. */
2121 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2122}
2123
fbfcc4f3
JN		 2124/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2125static void
2126intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2127{
2128 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2129}
2130
e2f0ba97 2131static bool
e27d8538 2132intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2133{
97aaf910 2134 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2135}
2136
714605e4 2137static u8
eef4eacb 2138intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 2139{
2140 struct drm_i915_private *dev_priv = dev->dev_private;
2141 struct sdvo_device_mapping *my_mapping, *other_mapping;
2142
eef4eacb 2143 if (sdvo->is_sdvob) {
714605e4 2144 my_mapping = &dev_priv->sdvo_mappings[0];
2145 other_mapping = &dev_priv->sdvo_mappings[1];
2146 } else {
2147 my_mapping = &dev_priv->sdvo_mappings[1];
2148 other_mapping = &dev_priv->sdvo_mappings[0];
2149 }
2150
2151 /* If the BIOS described our SDVO device, take advantage of it. */
2152 if (my_mapping->slave_addr)
2153 return my_mapping->slave_addr;
2154
2155 /* If the BIOS only described a different SDVO device, use the
2156 * address that it isn't using.
2157 */
2158 if (other_mapping->slave_addr) {
2159 if (other_mapping->slave_addr == 0x70)
2160 return 0x72;
2161 else
2162 return 0x70;
2163 }
2164
2165 /* No SDVO device info is found for another DVO port,
2166 * so use mapping assumption we had before BIOS parsing.
2167 */
eef4eacb 2168 if (sdvo->is_sdvob)
714605e4 2169 return 0x70;
2170 else
2171 return 0x72;
2172}
2173
14571b4c 2174static void
df0e9248
CW		 2175intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2176 struct intel_sdvo *encoder)
14571b4c 2177{
df0e9248
CW		 2178 drm_connector_init(encoder->base.base.dev,
2179 &connector->base.base,
2180 &intel_sdvo_connector_funcs,
2181 connector->base.base.connector_type);
6070a4a9 2182
df0e9248
CW		 2183 drm_connector_helper_add(&connector->base.base,
2184 &intel_sdvo_connector_helper_funcs);
14571b4c 2185
8f4839e2 2186 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2187 connector->base.base.doublescan_allowed = 0;
2188 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2189 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2190
df0e9248
CW		 2191 intel_connector_attach_encoder(&connector->base, &encoder->base);
2192 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2193}
6070a4a9 2194
7f36e7ed
CW		 2195static void
2196intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
2197{
2198 struct drm_device *dev = connector->base.base.dev;
2199
3f43c48d 2200 intel_attach_force_audio_property(&connector->base.base);
e953fd7b
CW		 2201 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
2202 intel_attach_broadcast_rgb_property(&connector->base.base);
7f36e7ed
CW		 2203}
2204
fb7a46f3 2205static bool
ea5b213a 2206intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2207{
4ef69c7a 2208 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2209 struct drm_connector *connector;
cc68c81a 2210 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2211 struct intel_connector *intel_connector;
615fb93f 2212 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2213
615fb93f
CW		 2214 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2215 if (!intel_sdvo_connector)
14571b4c
ZW		 2216 return false;
2217
14571b4c 2218 if (device == 0) {
ea5b213a 2219 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2220 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2221 } else if (device == 1) {
ea5b213a 2222 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2223 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2224 }
2225
615fb93f 2226 intel_connector = &intel_sdvo_connector->base;
14571b4c 2227 connector = &intel_connector->base;
5fa7ac9c
JN		 2228 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2229 intel_sdvo_connector->output_flag) {
cc68c81a 2230 connector->polled = DRM_CONNECTOR_POLL_HPD;
5fa7ac9c 2231 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
cc68c81a
SF		 2232 /* Some SDVO devices have one-shot hotplug interrupts.
2233 * Ensure that they get re-enabled when an interrupt happens.
2234 */
2235 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2236 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2237 } else {
cc68c81a 2238 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2239 }
14571b4c
ZW		 2240 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2241 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2242
e27d8538 2243 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2244 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2245 intel_sdvo->is_hdmi = true;
14571b4c 2246 }
66a9278e 2247 intel_sdvo->base.cloneable = true;
14571b4c 2248
df0e9248 2249 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221
CW		 2250 if (intel_sdvo->is_hdmi)
2251 intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
14571b4c
ZW		 2252
2253 return true;
2254}
2255
2256static bool
ea5b213a 2257intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2258{
4ef69c7a
CW		 2259 struct drm_encoder *encoder = &intel_sdvo->base.base;
2260 struct drm_connector *connector;
2261 struct intel_connector *intel_connector;
2262 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2263
615fb93f
CW		 2264 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2265 if (!intel_sdvo_connector)
2266 return false;
14571b4c 2267
615fb93f 2268 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2269 connector = &intel_connector->base;
2270 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2271 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2272
4ef69c7a
CW		 2273 intel_sdvo->controlled_output |= type;
2274 intel_sdvo_connector->output_flag = type;
14571b4c 2275
4ef69c7a
CW		 2276 intel_sdvo->is_tv = true;
2277 intel_sdvo->base.needs_tv_clock = true;
66a9278e 2278 intel_sdvo->base.cloneable = false;
14571b4c 2279
df0e9248 2280 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2281
4ef69c7a 2282 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2283 goto err;
14571b4c 2284
4ef69c7a 2285 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2286 goto err;
14571b4c 2287
4ef69c7a 2288 return true;
32aad86f
CW		 2289
2290err:
123d5c01 2291 intel_sdvo_destroy(connector);
32aad86f 2292 return false;
14571b4c
ZW		 2293}
2294
2295static bool
ea5b213a 2296intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2297{
4ef69c7a
CW		 2298 struct drm_encoder *encoder = &intel_sdvo->base.base;
2299 struct drm_connector *connector;
2300 struct intel_connector *intel_connector;
2301 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2302
615fb93f
CW		 2303 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2304 if (!intel_sdvo_connector)
2305 return false;
14571b4c 2306
615fb93f 2307 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2308 connector = &intel_connector->base;
eb1f8e4f 2309 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2310 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2311 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2312
2313 if (device == 0) {
2314 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2315 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2316 } else if (device == 1) {
2317 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2318 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2319 }
2320
66a9278e 2321 intel_sdvo->base.cloneable = true;
14571b4c 2322
df0e9248
CW		 2323 intel_sdvo_connector_init(intel_sdvo_connector,
2324 intel_sdvo);
4ef69c7a 2325 return true;
14571b4c
ZW		 2326}
2327
2328static bool
ea5b213a 2329intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2330{
4ef69c7a
CW		 2331 struct drm_encoder *encoder = &intel_sdvo->base.base;
2332 struct drm_connector *connector;
2333 struct intel_connector *intel_connector;
2334 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2335
615fb93f
CW		 2336 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2337 if (!intel_sdvo_connector)
2338 return false;
14571b4c 2339
615fb93f
CW		 2340 intel_connector = &intel_sdvo_connector->base;
2341 connector = &intel_connector->base;
4ef69c7a
CW		 2342 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2343 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2344
2345 if (device == 0) {
2346 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2347 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2348 } else if (device == 1) {
2349 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2350 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2351 }
2352
e3b86d69
EE		 2353 /* SDVO LVDS is not cloneable because the input mode gets adjusted by the encoder */
2354 intel_sdvo->base.cloneable = false;
14571b4c 2355
df0e9248 2356 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2357 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2358 goto err;
2359
2360 return true;
2361
2362err:
123d5c01 2363 intel_sdvo_destroy(connector);
32aad86f 2364 return false;
14571b4c
ZW		 2365}
2366
2367static bool
ea5b213a 2368intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2369{
ea5b213a
CW		 2370 intel_sdvo->is_tv = false;
2371 intel_sdvo->base.needs_tv_clock = false;
2372 intel_sdvo->is_lvds = false;
fb7a46f3 2373
14571b4c 2374 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2375
14571b4c 2376 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2377 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2378 return false;
2379
2380 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2381 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2382 return false;
2383
2384 /* TV has no XXX1 function block */
a1f4b7ff 2385 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2386 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2387 return false;
2388
2389 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2390 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2391 return false;
fb7a46f3 2392
a0b1c7a5
CW		 2393 if (flags & SDVO_OUTPUT_YPRPB0)
2394 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2395 return false;
2396
14571b4c 2397 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2398 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2399 return false;
2400
2401 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2402 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2403 return false;
2404
2405 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2406 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2407 return false;
2408
2409 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2410 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2411 return false;
fb7a46f3 2412
14571b4c 2413 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2414 unsigned char bytes[2];
2415
ea5b213a
CW		 2416 intel_sdvo->controlled_output = 0;
2417 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2418 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2419 SDVO_NAME(intel_sdvo),
51c8b407 2420 bytes[0], bytes[1]);
14571b4c 2421 return false;
fb7a46f3 2422 }
27f8227b 2423 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2424
14571b4c 2425 return true;
fb7a46f3 2426}
2427
32aad86f
CW		 2428static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2429 struct intel_sdvo_connector *intel_sdvo_connector,
2430 int type)
ce6feabd 2431{
4ef69c7a 2432 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2433 struct intel_sdvo_tv_format format;
2434 uint32_t format_map, i;
ce6feabd 2435
32aad86f
CW		 2436 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2437 return false;
ce6feabd 2438
1a3665c8 2439 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2440 if (!intel_sdvo_get_value(intel_sdvo,
2441 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2442 &format, sizeof(format)))
2443 return false;
ce6feabd 2444
32aad86f 2445 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2446
2447 if (format_map == 0)
32aad86f 2448 return false;
ce6feabd 2449
615fb93f 2450 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2451 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2452 if (format_map & (1 << i))
2453 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2454
2455
c5521706 2456 intel_sdvo_connector->tv_format =
32aad86f
CW		 2457 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2458 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2459 if (!intel_sdvo_connector->tv_format)
fcc8d672 2460 return false;
ce6feabd 2461
615fb93f 2462 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2463 drm_property_add_enum(
c5521706 2464 intel_sdvo_connector->tv_format, i,
40039750 2465 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2466
40039750 2467 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2468 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2469 intel_sdvo_connector->tv_format, 0);
32aad86f 2470 return true;
ce6feabd
ZY		 2471
2472}
2473
c5521706
CW		 2474#define ENHANCEMENT(name, NAME) do { \
2475 if (enhancements.name) { \
2476 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2477 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2478 return false; \
2479 intel_sdvo_connector->max_##name = data_value[0]; \
2480 intel_sdvo_connector->cur_##name = response; \
2481 intel_sdvo_connector->name = \
d9bc3c02 2482 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2483 if (!intel_sdvo_connector->name) return false; \
c5521706
CW		 2484 drm_connector_attach_property(connector, \
2485 intel_sdvo_connector->name, \
2486 intel_sdvo_connector->cur_##name); \
2487 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2488 data_value[0], data_value[1], response); \
2489 } \
0206e353 2490} while (0)
c5521706
CW		 2491
2492static bool
2493intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2494 struct intel_sdvo_connector *intel_sdvo_connector,
2495 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2496{
4ef69c7a 2497 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2498 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2499 uint16_t response, data_value[2];
2500
c5521706
CW		 2501 /* when horizontal overscan is supported, Add the left/right property */
2502 if (enhancements.overscan_h) {
2503 if (!intel_sdvo_get_value(intel_sdvo,
2504 SDVO_CMD_GET_MAX_OVERSCAN_H,
2505 &data_value, 4))
2506 return false;
32aad86f 2507
c5521706
CW		 2508 if (!intel_sdvo_get_value(intel_sdvo,
2509 SDVO_CMD_GET_OVERSCAN_H,
2510 &response, 2))
2511 return false;
fcc8d672 2512
c5521706
CW		 2513 intel_sdvo_connector->max_hscan = data_value[0];
2514 intel_sdvo_connector->left_margin = data_value[0] - response;
2515 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2516 intel_sdvo_connector->left =
d9bc3c02 2517 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2518 if (!intel_sdvo_connector->left)
2519 return false;
fcc8d672 2520
c5521706
CW		 2521 drm_connector_attach_property(connector,
2522 intel_sdvo_connector->left,
2523 intel_sdvo_connector->left_margin);
fcc8d672 2524
c5521706 2525 intel_sdvo_connector->right =
d9bc3c02 2526 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2527 if (!intel_sdvo_connector->right)
2528 return false;
32aad86f 2529
c5521706
CW		 2530 drm_connector_attach_property(connector,
2531 intel_sdvo_connector->right,
2532 intel_sdvo_connector->right_margin);
2533 DRM_DEBUG_KMS("h_overscan: max %d, "
2534 "default %d, current %d\n",
2535 data_value[0], data_value[1], response);
2536 }
32aad86f 2537
c5521706
CW		 2538 if (enhancements.overscan_v) {
2539 if (!intel_sdvo_get_value(intel_sdvo,
2540 SDVO_CMD_GET_MAX_OVERSCAN_V,
2541 &data_value, 4))
2542 return false;
fcc8d672 2543
c5521706
CW		 2544 if (!intel_sdvo_get_value(intel_sdvo,
2545 SDVO_CMD_GET_OVERSCAN_V,
2546 &response, 2))
2547 return false;
32aad86f 2548
c5521706
CW		 2549 intel_sdvo_connector->max_vscan = data_value[0];
2550 intel_sdvo_connector->top_margin = data_value[0] - response;
2551 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2552 intel_sdvo_connector->top =
d9bc3c02
SH		 2553 drm_property_create_range(dev, 0,
2554 "top_margin", 0, data_value[0]);
c5521706
CW		 2555 if (!intel_sdvo_connector->top)
2556 return false;
32aad86f 2557
c5521706
CW		 2558 drm_connector_attach_property(connector,
2559 intel_sdvo_connector->top,
2560 intel_sdvo_connector->top_margin);
fcc8d672 2561
c5521706 2562 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2563 drm_property_create_range(dev, 0,
2564 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2565 if (!intel_sdvo_connector->bottom)
2566 return false;
32aad86f 2567
c5521706
CW		 2568 drm_connector_attach_property(connector,
2569 intel_sdvo_connector->bottom,
2570 intel_sdvo_connector->bottom_margin);
2571 DRM_DEBUG_KMS("v_overscan: max %d, "
2572 "default %d, current %d\n",
2573 data_value[0], data_value[1], response);
2574 }
32aad86f 2575
c5521706
CW		 2576 ENHANCEMENT(hpos, HPOS);
2577 ENHANCEMENT(vpos, VPOS);
2578 ENHANCEMENT(saturation, SATURATION);
2579 ENHANCEMENT(contrast, CONTRAST);
2580 ENHANCEMENT(hue, HUE);
2581 ENHANCEMENT(sharpness, SHARPNESS);
2582 ENHANCEMENT(brightness, BRIGHTNESS);
2583 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2584 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2585 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2586 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2587 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2588
e044218a
CW		 2589 if (enhancements.dot_crawl) {
2590 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2591 return false;
2592
2593 intel_sdvo_connector->max_dot_crawl = 1;
2594 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2595 intel_sdvo_connector->dot_crawl =
d9bc3c02 2596 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2597 if (!intel_sdvo_connector->dot_crawl)
2598 return false;
2599
e044218a
CW		 2600 drm_connector_attach_property(connector,
2601 intel_sdvo_connector->dot_crawl,
2602 intel_sdvo_connector->cur_dot_crawl);
2603 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2604 }
2605
c5521706
CW		 2606 return true;
2607}
32aad86f 2608
c5521706
CW		 2609static bool
2610intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2611 struct intel_sdvo_connector *intel_sdvo_connector,
2612 struct intel_sdvo_enhancements_reply enhancements)
2613{
4ef69c7a 2614 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2615 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2616 uint16_t response, data_value[2];
32aad86f 2617
c5521706 2618 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2619
c5521706
CW		 2620 return true;
2621}
2622#undef ENHANCEMENT
32aad86f 2623
c5521706
CW		 2624static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2625 struct intel_sdvo_connector *intel_sdvo_connector)
2626{
2627 union {
2628 struct intel_sdvo_enhancements_reply reply;
2629 uint16_t response;
2630 } enhancements;
32aad86f 2631
1a3665c8
CW		 2632 BUILD_BUG_ON(sizeof(enhancements) != 2);
2633
cf9a2f3a
CW		 2634 enhancements.response = 0;
2635 intel_sdvo_get_value(intel_sdvo,
2636 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2637 &enhancements, sizeof(enhancements));
c5521706
CW		 2638 if (enhancements.response == 0) {
2639 DRM_DEBUG_KMS("No enhancement is supported\n");
2640 return true;
b9219c5e 2641 }
32aad86f 2642
c5521706
CW		 2643 if (IS_TV(intel_sdvo_connector))
2644 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2645 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2646 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2647 else
2648 return true;
e957d772
CW		 2649}
2650
2651static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2652 struct i2c_msg *msgs,
2653 int num)
2654{
2655 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2656
e957d772
CW		 2657 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2658 return -EIO;
2659
2660 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2661}
2662
2663static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2664{
2665 struct intel_sdvo *sdvo = adapter->algo_data;
2666 return sdvo->i2c->algo->functionality(sdvo->i2c);
2667}
2668
2669static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2670 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2671 .functionality = intel_sdvo_ddc_proxy_func
2672};
2673
2674static bool
2675intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2676 struct drm_device *dev)
2677{
2678 sdvo->ddc.owner = THIS_MODULE;
2679 sdvo->ddc.class = I2C_CLASS_DDC;
2680 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2681 sdvo->ddc.dev.parent = &dev->pdev->dev;
2682 sdvo->ddc.algo_data = sdvo;
2683 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2684
2685 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2686}
2687
eef4eacb 2688bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2689{
b01f2c3a 2690 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2691 struct intel_encoder *intel_encoder;
ea5b213a 2692 struct intel_sdvo *intel_sdvo;
084b612e 2693 u32 hotplug_mask;
79e53945 2694 int i;
79e53945 2695
ea5b213a
CW		 2696 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2697 if (!intel_sdvo)
7d57382e 2698 return false;
79e53945 2699
56184e3d 2700 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2701 intel_sdvo->is_sdvob = is_sdvob;
2702 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2703 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
fbfcc4f3
JN		 2704 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
2705 goto err_i2c_bus;
e957d772 2706
56184e3d 2707 /* encoder type will be decided later */
ea5b213a 2708 intel_encoder = &intel_sdvo->base;
21d40d37 2709 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2710 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2711
79e53945
JB		 2712 /* Read the regs to test if we can talk to the device */
2713 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2714 u8 byte;
2715
2716 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2717 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2718 SDVO_NAME(intel_sdvo));
f899fc64 2719 goto err;
79e53945
JB		 2720 }
2721 }
2722
084b612e
CW		 2723 hotplug_mask = 0;
2724 if (IS_G4X(dev)) {
2725 hotplug_mask = intel_sdvo->is_sdvob ?
2726 SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X;
2727 } else if (IS_GEN4(dev)) {
2728 hotplug_mask = intel_sdvo->is_sdvob ?
2729 SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965;
2730 } else {
2731 hotplug_mask = intel_sdvo->is_sdvob ?
2732 SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
2733 }
619ac3b7 2734
4ef69c7a 2735 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2736
ce22c320
DV		 2737 intel_encoder->disable = intel_disable_sdvo;
2738 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 2739 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
ce22c320 2740
af901ca1 2741 /* In default case sdvo lvds is false */
32aad86f 2742 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2743 goto err;
79e53945 2744
ea5b213a
CW		 2745 if (intel_sdvo_output_setup(intel_sdvo,
2746 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 2747 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2748 SDVO_NAME(intel_sdvo));
f899fc64 2749 goto err;
79e53945
JB		 2750 }
2751
fcbc50da
JN		 2752 /* Only enable the hotplug irq if we need it, to work around noisy
2753 * hotplug lines.
2754 */
5fa7ac9c 2755 if (intel_sdvo->hotplug_active)
fcbc50da
JN		 2756 dev_priv->hotplug_supported_mask |= hotplug_mask;
2757
ea5b213a 2758 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2759
79e53945 2760 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2761 if (!intel_sdvo_set_target_input(intel_sdvo))
f899fc64 2762 goto err;
79e53945 2763
32aad86f
CW		 2764 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2765 &intel_sdvo->pixel_clock_min,
2766 &intel_sdvo->pixel_clock_max))
f899fc64 2767 goto err;
79e53945 2768
8a4c47f3 2769 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2770 "clock range %dMHz - %dMHz, "
2771 "input 1: %c, input 2: %c, "
2772 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2773 SDVO_NAME(intel_sdvo),
2774 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2775 intel_sdvo->caps.device_rev_id,
2776 intel_sdvo->pixel_clock_min / 1000,
2777 intel_sdvo->pixel_clock_max / 1000,
2778 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2779 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2780 /* check currently supported outputs */
ea5b213a 2781 intel_sdvo->caps.output_flags &
79e53945 2782 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2783 intel_sdvo->caps.output_flags &
79e53945 2784 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2785 return true;
79e53945 2786
f899fc64 2787err:
373a3cf7 2788 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2789 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 2790err_i2c_bus:
2791 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 2792 kfree(intel_sdvo);
79e53945 2793
7d57382e 2794 return false;
79e53945 2795}
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