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[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
ea5b213a 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
79e53945
JB		 37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 46 SDVO_TV_MASK)
14571b4c
ZW		 47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 50#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 51#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 52#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 53
79e53945 54
2e88e40b 55static const char *tv_format_names[] = {
ce6feabd
ZY		 56 "NTSC_M" , "NTSC_J" , "NTSC_443",
57 "PAL_B" , "PAL_D" , "PAL_G" ,
58 "PAL_H" , "PAL_I" , "PAL_M" ,
59 "PAL_N" , "PAL_NC" , "PAL_60" ,
60 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
61 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
62 "SECAM_60"
63};
64
65#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
66
ea5b213a
CW		 67struct intel_sdvo {
68 struct intel_encoder base;
69
f899fc64 70 struct i2c_adapter *i2c;
f9c10a9b 71 u8 slave_addr;
e2f0ba97 72
e957d772
CW		 73 struct i2c_adapter ddc;
74
e2f0ba97 75 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 76 uint32_t sdvo_reg;
79e53945 77
e2f0ba97
JB		 78 /* Active outputs controlled by this SDVO output */
79 uint16_t controlled_output;
79e53945 80
e2f0ba97
JB		 81 /*
82 * Capabilities of the SDVO device returned by
19d415a2 83 * intel_sdvo_get_capabilities()
e2f0ba97 84 */
79e53945 85 struct intel_sdvo_caps caps;
e2f0ba97
JB		 86
87 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 88 int pixel_clock_min, pixel_clock_max;
89
fb7a46f3 90 /*
91 * For multiple function SDVO device,
92 * this is for current attached outputs.
93 */
94 uint16_t attached_output;
95
cc68c81a
SF		 96 /*
97 * Hotplug activation bits for this device
98 */
5fa7ac9c 99 uint16_t hotplug_active;
cc68c81a 100
e953fd7b
CW		 101 /**
102 * This is used to select the color range of RBG outputs in HDMI mode.
103 * It is only valid when using TMDS encoding and 8 bit per color mode.
104 */
105 uint32_t color_range;
55bc60db 106 bool color_range_auto;
e953fd7b 107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
eef4eacb
DV		 117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
ce6feabd 120 /* This is for current tv format name */
40039750 121 int tv_format_index;
ce6feabd 122
e2f0ba97
JB		 123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
da79de97
CW		 127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
abedc077 129 bool rgb_quant_range_selectable;
12682a97 130
7086c87f 131 /**
6c9547ff
CW		 132 * This is set if we detect output of sdvo device as LVDS and
133 * have a valid fixed mode to use with the panel.
7086c87f
ML		 134 */
135 bool is_lvds;
e2f0ba97 136
12682a97 137 /**
138 * This is sdvo fixed pannel mode pointer
139 */
140 struct drm_display_mode *sdvo_lvds_fixed_mode;
141
c751ce4f 142 /* DDC bus used by this SDVO encoder */
e2f0ba97 143 uint8_t ddc_bus;
e751823d
EE		 144
145 /*
146 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
147 */
148 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 149};
150
151struct intel_sdvo_connector {
615fb93f
CW		 152 struct intel_connector base;
153
14571b4c
ZW		 154 /* Mark the type of connector */
155 uint16_t output_flag;
156
c3e5f67b 157 enum hdmi_force_audio force_audio;
7f36e7ed 158
14571b4c 159 /* This contains all current supported TV format */
40039750 160 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 161 int format_supported_num;
c5521706 162 struct drm_property *tv_format;
14571b4c 163
b9219c5e 164 /* add the property for the SDVO-TV */
c5521706
CW		 165 struct drm_property *left;
166 struct drm_property *right;
167 struct drm_property *top;
168 struct drm_property *bottom;
169 struct drm_property *hpos;
170 struct drm_property *vpos;
171 struct drm_property *contrast;
172 struct drm_property *saturation;
173 struct drm_property *hue;
174 struct drm_property *sharpness;
175 struct drm_property *flicker_filter;
176 struct drm_property *flicker_filter_adaptive;
177 struct drm_property *flicker_filter_2d;
178 struct drm_property *tv_chroma_filter;
179 struct drm_property *tv_luma_filter;
e044218a 180 struct drm_property *dot_crawl;
b9219c5e
ZY		 181
182 /* add the property for the SDVO-TV/LVDS */
c5521706 183 struct drm_property *brightness;
b9219c5e
ZY		 184
185 /* Add variable to record current setting for the above property */
186 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 187
b9219c5e
ZY		 188 /* this is to get the range of margin.*/
189 u32 max_hscan, max_vscan;
190 u32 max_hpos, cur_hpos;
191 u32 max_vpos, cur_vpos;
192 u32 cur_brightness, max_brightness;
193 u32 cur_contrast, max_contrast;
194 u32 cur_saturation, max_saturation;
195 u32 cur_hue, max_hue;
c5521706
CW		 196 u32 cur_sharpness, max_sharpness;
197 u32 cur_flicker_filter, max_flicker_filter;
198 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
199 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
200 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
201 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 202 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 203};
204
8aca63aa 205static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
ea5b213a 206{
8aca63aa 207 return container_of(encoder, struct intel_sdvo, base);
ea5b213a
CW		 208}
209
df0e9248
CW		 210static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
211{
8aca63aa 212 return to_sdvo(intel_attached_encoder(connector));
df0e9248
CW		 213}
214
615fb93f
CW		 215static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
216{
217 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
218}
219
fb7a46f3 220static bool
ea5b213a 221intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 222static bool
223intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
224 struct intel_sdvo_connector *intel_sdvo_connector,
225 int type);
226static bool
227intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
228 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 229
79e53945
JB		 230/**
231 * Writes the SDVOB or SDVOC with the given value, but always writes both
232 * SDVOB and SDVOC to work around apparent hardware issues (according to
233 * comments in the BIOS).
234 */
ea5b213a 235static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 236{
4ef69c7a 237 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 238 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 239 u32 bval = val, cval = val;
240 int i;
241
ea5b213a
CW		 242 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
243 I915_WRITE(intel_sdvo->sdvo_reg, val);
244 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 245 return;
246 }
247
e2debe91
PZ		 248 if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
249 cval = I915_READ(GEN3_SDVOC);
250 else
251 bval = I915_READ(GEN3_SDVOB);
252
79e53945
JB		 253 /*
254 * Write the registers twice for luck. Sometimes,
255 * writing them only once doesn't appear to 'stick'.
256 * The BIOS does this too. Yay, magic
257 */
258 for (i = 0; i < 2; i++)
259 {
e2debe91
PZ		 260 I915_WRITE(GEN3_SDVOB, bval);
261 I915_READ(GEN3_SDVOB);
262 I915_WRITE(GEN3_SDVOC, cval);
263 I915_READ(GEN3_SDVOC);
79e53945
JB		 264 }
265}
266
32aad86f 267static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 268{
79e53945
JB		 269 struct i2c_msg msgs[] = {
270 {
e957d772 271 .addr = intel_sdvo->slave_addr,
79e53945
JB		 272 .flags = 0,
273 .len = 1,
e957d772 274 .buf = &addr,
79e53945
JB		 275 },
276 {
e957d772 277 .addr = intel_sdvo->slave_addr,
79e53945
JB		 278 .flags = I2C_M_RD,
279 .len = 1,
e957d772 280 .buf = ch,
79e53945
JB		 281 }
282 };
32aad86f 283 int ret;
79e53945 284
f899fc64 285 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 286 return true;
79e53945 287
8a4c47f3 288 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 289 return false;
290}
291
79e53945
JB		 292#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
293/** Mapping of command numbers to names, for debug output */
005568be 294static const struct _sdvo_cmd_name {
e2f0ba97 295 u8 cmd;
2e88e40b 296 const char *name;
79e53945 297} sdvo_cmd_names[] = {
0206e353
AJ		 298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
341
342 /* Add the op code for SDVO enhancements */
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
387
388 /* HDMI op code */
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 409};
410
eef4eacb 411#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 412
ea5b213a 413static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 414 const void *args, int args_len)
79e53945 415{
79e53945
JB		 416 int i;
417
8a4c47f3 418 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 419 SDVO_NAME(intel_sdvo), cmd);
79e53945 420 for (i = 0; i < args_len; i++)
342dc382 421 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 422 for (; i < 8; i++)
342dc382 423 DRM_LOG_KMS(" ");
04ad327f 424 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 425 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 426 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 427 break;
428 }
429 }
04ad327f 430 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 431 DRM_LOG_KMS("(%02X)", cmd);
432 DRM_LOG_KMS("\n");
79e53945 433}
79e53945 434
e957d772
CW		 435static const char *cmd_status_names[] = {
436 "Power on",
437 "Success",
438 "Not supported",
439 "Invalid arg",
440 "Pending",
441 "Target not specified",
442 "Scaling not supported"
443};
444
32aad86f
CW		 445static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
446 const void *args, int args_len)
79e53945 447{
3bf3f452
BW		 448 u8 *buf, status;
449 struct i2c_msg *msgs;
450 int i, ret = true;
451
0274df3e 452 /* Would be simpler to allocate both in one go ? */
5c67eeb6 453 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3bf3f452
BW		 454 if (!buf)
455 return false;
456
457 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e
AC		 458 if (!msgs) {
459 kfree(buf);
3bf3f452 460 return false;
0274df3e 461 }
79e53945 462
ea5b213a 463 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 464
465 for (i = 0; i < args_len; i++) {
e957d772
CW		 466 msgs[i].addr = intel_sdvo->slave_addr;
467 msgs[i].flags = 0;
468 msgs[i].len = 2;
469 msgs[i].buf = buf + 2 *i;
470 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
471 buf[2*i + 1] = ((u8*)args)[i];
472 }
473 msgs[i].addr = intel_sdvo->slave_addr;
474 msgs[i].flags = 0;
475 msgs[i].len = 2;
476 msgs[i].buf = buf + 2*i;
477 buf[2*i + 0] = SDVO_I2C_OPCODE;
478 buf[2*i + 1] = cmd;
479
480 /* the following two are to read the response */
481 status = SDVO_I2C_CMD_STATUS;
482 msgs[i+1].addr = intel_sdvo->slave_addr;
483 msgs[i+1].flags = 0;
484 msgs[i+1].len = 1;
485 msgs[i+1].buf = &status;
486
487 msgs[i+2].addr = intel_sdvo->slave_addr;
488 msgs[i+2].flags = I2C_M_RD;
489 msgs[i+2].len = 1;
490 msgs[i+2].buf = &status;
491
492 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
493 if (ret < 0) {
494 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 495 ret = false;
496 goto out;
e957d772
CW		 497 }
498 if (ret != i+3) {
499 /* failure in I2C transfer */
500 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 501 ret = false;
e957d772
CW		 502 }
503
3bf3f452
BW		 504out:
505 kfree(msgs);
506 kfree(buf);
507 return ret;
79e53945
JB		 508}
509
b5c616a7
CW		 510static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
511 void *response, int response_len)
79e53945 512{
fc37381c 513 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 514 u8 status;
33b52961 515 int i;
79e53945 516
d121a5d2
CW		 517 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
518
b5c616a7
CW		 519 /*
520 * The documentation states that all commands will be
521 * processed within 15µs, and that we need only poll
522 * the status byte a maximum of 3 times in order for the
523 * command to be complete.
524 *
525 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 526 *
527 * Also beware that the first response by many devices is to
528 * reply PENDING and stall for time. TVs are notorious for
529 * requiring longer than specified to complete their replies.
530 * Originally (in the DDX long ago), the delay was only ever 15ms
531 * with an additional delay of 30ms applied for TVs added later after
532 * many experiments. To accommodate both sets of delays, we do a
533 * sequence of slow checks if the device is falling behind and fails
534 * to reply within 5*15µs.
b5c616a7 535 */
d121a5d2
CW		 536 if (!intel_sdvo_read_byte(intel_sdvo,
537 SDVO_I2C_CMD_STATUS,
538 &status))
539 goto log_fail;
540
fc37381c
CW		 541 while (status == SDVO_CMD_STATUS_PENDING && --retry) {
542 if (retry < 10)
543 msleep(15);
544 else
545 udelay(15);
546
b5c616a7
CW		 547 if (!intel_sdvo_read_byte(intel_sdvo,
548 SDVO_I2C_CMD_STATUS,
549 &status))
d121a5d2
CW		 550 goto log_fail;
551 }
b5c616a7 552
79e53945 553 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 554 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 555 else
342dc382 556 DRM_LOG_KMS("(??? %d)", status);
79e53945 557
b5c616a7
CW		 558 if (status != SDVO_CMD_STATUS_SUCCESS)
559 goto log_fail;
79e53945 560
b5c616a7
CW		 561 /* Read the command response */
562 for (i = 0; i < response_len; i++) {
563 if (!intel_sdvo_read_byte(intel_sdvo,
564 SDVO_I2C_RETURN_0 + i,
565 &((u8 *)response)[i]))
566 goto log_fail;
e957d772 567 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 568 }
b5c616a7 569 DRM_LOG_KMS("\n");
b5c616a7 570 return true;
79e53945 571
b5c616a7 572log_fail:
d121a5d2 573 DRM_LOG_KMS("... failed\n");
b5c616a7 574 return false;
79e53945
JB		 575}
576
b358d0a6 577static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 578{
579 if (mode->clock >= 100000)
580 return 1;
581 else if (mode->clock >= 50000)
582 return 2;
583 else
584 return 4;
585}
586
e957d772
CW		 587static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
588 u8 ddc_bus)
79e53945 589{
d121a5d2 590 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 591 return intel_sdvo_write_cmd(intel_sdvo,
592 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
593 &ddc_bus, 1);
79e53945
JB		 594}
595
32aad86f 596static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 597{
d121a5d2
CW		 598 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
599 return false;
600
601 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 602}
79e53945 603
32aad86f
CW		 604static bool
605intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
606{
607 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
608 return false;
79e53945 609
32aad86f
CW		 610 return intel_sdvo_read_response(intel_sdvo, value, len);
611}
79e53945 612
32aad86f
CW		 613static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
614{
615 struct intel_sdvo_set_target_input_args targets = {0};
616 return intel_sdvo_set_value(intel_sdvo,
617 SDVO_CMD_SET_TARGET_INPUT,
618 &targets, sizeof(targets));
79e53945
JB		 619}
620
621/**
622 * Return whether each input is trained.
623 *
624 * This function is making an assumption about the layout of the response,
625 * which should be checked against the docs.
626 */
ea5b213a 627static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 628{
629 struct intel_sdvo_get_trained_inputs_response response;
79e53945 630
1a3665c8 631 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 632 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
633 &response, sizeof(response)))
79e53945
JB		 634 return false;
635
636 *input_1 = response.input0_trained;
637 *input_2 = response.input1_trained;
638 return true;
639}
640
ea5b213a 641static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 642 u16 outputs)
643{
32aad86f
CW		 644 return intel_sdvo_set_value(intel_sdvo,
645 SDVO_CMD_SET_ACTIVE_OUTPUTS,
646 &outputs, sizeof(outputs));
79e53945
JB		 647}
648
4ac41f47
DV		 649static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
650 u16 *outputs)
651{
652 return intel_sdvo_get_value(intel_sdvo,
653 SDVO_CMD_GET_ACTIVE_OUTPUTS,
654 outputs, sizeof(*outputs));
655}
656
ea5b213a 657static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 658 int mode)
659{
32aad86f 660 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 661
662 switch (mode) {
663 case DRM_MODE_DPMS_ON:
664 state = SDVO_ENCODER_STATE_ON;
665 break;
666 case DRM_MODE_DPMS_STANDBY:
667 state = SDVO_ENCODER_STATE_STANDBY;
668 break;
669 case DRM_MODE_DPMS_SUSPEND:
670 state = SDVO_ENCODER_STATE_SUSPEND;
671 break;
672 case DRM_MODE_DPMS_OFF:
673 state = SDVO_ENCODER_STATE_OFF;
674 break;
675 }
676
32aad86f
CW		 677 return intel_sdvo_set_value(intel_sdvo,
678 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 679}
680
ea5b213a 681static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 682 int *clock_min,
683 int *clock_max)
684{
685 struct intel_sdvo_pixel_clock_range clocks;
79e53945 686
1a3665c8 687 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 688 if (!intel_sdvo_get_value(intel_sdvo,
689 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
690 &clocks, sizeof(clocks)))
79e53945
JB		 691 return false;
692
693 /* Convert the values from units of 10 kHz to kHz. */
694 *clock_min = clocks.min * 10;
695 *clock_max = clocks.max * 10;
79e53945
JB		 696 return true;
697}
698
ea5b213a 699static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 700 u16 outputs)
701{
32aad86f
CW		 702 return intel_sdvo_set_value(intel_sdvo,
703 SDVO_CMD_SET_TARGET_OUTPUT,
704 &outputs, sizeof(outputs));
79e53945
JB		 705}
706
ea5b213a 707static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 708 struct intel_sdvo_dtd *dtd)
709{
32aad86f
CW		 710 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
711 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 712}
713
045ac3b5
JB		 714static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
715 struct intel_sdvo_dtd *dtd)
716{
717 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
718 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
719}
720
ea5b213a 721static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 722 struct intel_sdvo_dtd *dtd)
723{
ea5b213a 724 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 725 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
726}
727
ea5b213a 728static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 729 struct intel_sdvo_dtd *dtd)
730{
ea5b213a 731 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 732 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
733}
734
045ac3b5
JB		 735static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
736 struct intel_sdvo_dtd *dtd)
737{
738 return intel_sdvo_get_timing(intel_sdvo,
739 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
740}
741
e2f0ba97 742static bool
ea5b213a 743intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 744 uint16_t clock,
745 uint16_t width,
746 uint16_t height)
747{
748 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 749
e642c6f1 750 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 751 args.clock = clock;
752 args.width = width;
753 args.height = height;
e642c6f1 754 args.interlace = 0;
12682a97 755
ea5b213a
CW		 756 if (intel_sdvo->is_lvds &&
757 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
758 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 759 args.scaled = 1;
760
32aad86f
CW		 761 return intel_sdvo_set_value(intel_sdvo,
762 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
763 &args, sizeof(args));
e2f0ba97
JB		 764}
765
ea5b213a 766static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 767 struct intel_sdvo_dtd *dtd)
768{
1a3665c8
CW		 769 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
770 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 771 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
772 &dtd->part1, sizeof(dtd->part1)) &&
773 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
774 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 775}
79e53945 776
ea5b213a 777static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 778{
32aad86f 779 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 780}
781
e2f0ba97 782static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 783 const struct drm_display_mode *mode)
79e53945 784{
e2f0ba97
JB		 785 uint16_t width, height;
786 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
787 uint16_t h_sync_offset, v_sync_offset;
6651819b 788 int mode_clock;
79e53945 789
c6ebd4c0
DV		 790 width = mode->hdisplay;
791 height = mode->vdisplay;
79e53945
JB		 792
793 /* do some mode translations */
c6ebd4c0
DV		 794 h_blank_len = mode->htotal - mode->hdisplay;
795 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 796
c6ebd4c0
DV		 797 v_blank_len = mode->vtotal - mode->vdisplay;
798 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 799
c6ebd4c0
DV		 800 h_sync_offset = mode->hsync_start - mode->hdisplay;
801 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 802
6651819b 803 mode_clock = mode->clock;
6651819b
DV		 804 mode_clock /= 10;
805 dtd->part1.clock = mode_clock;
806
e2f0ba97
JB		 807 dtd->part1.h_active = width & 0xff;
808 dtd->part1.h_blank = h_blank_len & 0xff;
809 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 810 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 811 dtd->part1.v_active = height & 0xff;
812 dtd->part1.v_blank = v_blank_len & 0xff;
813 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 814 ((v_blank_len >> 8) & 0xf);
815
171a9e96 816 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 817 dtd->part2.h_sync_width = h_sync_len & 0xff;
818 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 819 (v_sync_len & 0xf);
e2f0ba97 820 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 821 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
822 ((v_sync_len & 0x30) >> 4);
823
e2f0ba97 824 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 825 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
826 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 827 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 828 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 829 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 830 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97
JB		 831
832 dtd->part2.sdvo_flags = 0;
833 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
834 dtd->part2.reserved = 0;
835}
836
837static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 838 const struct intel_sdvo_dtd *dtd)
e2f0ba97 839{
e2f0ba97
JB		 840 mode->hdisplay = dtd->part1.h_active;
841 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
842 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 843 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 844 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
845 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
846 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
847 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
848
849 mode->vdisplay = dtd->part1.v_active;
850 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
851 mode->vsync_start = mode->vdisplay;
852 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 853 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 854 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
855 mode->vsync_end = mode->vsync_start +
856 (dtd->part2.v_sync_off_width & 0xf);
857 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
858 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
859 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
860
861 mode->clock = dtd->part1.clock * 10;
862
171a9e96 863 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
59d92bfa
DV		 864 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
865 mode->flags |= DRM_MODE_FLAG_INTERLACE;
866 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
e2f0ba97 867 mode->flags |= DRM_MODE_FLAG_PHSYNC;
59d92bfa 868 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
e2f0ba97
JB		 869 mode->flags |= DRM_MODE_FLAG_PVSYNC;
870}
871
e27d8538 872static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 873{
e27d8538 874 struct intel_sdvo_encode encode;
e2f0ba97 875
1a3665c8 876 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 877 return intel_sdvo_get_value(intel_sdvo,
878 SDVO_CMD_GET_SUPP_ENCODE,
879 &encode, sizeof(encode));
e2f0ba97
JB		 880}
881
ea5b213a 882static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 883 uint8_t mode)
e2f0ba97 884{
32aad86f 885 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 886}
887
ea5b213a 888static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 889 uint8_t mode)
890{
32aad86f 891 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 892}
893
894#if 0
ea5b213a 895static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 896{
897 int i, j;
898 uint8_t set_buf_index[2];
899 uint8_t av_split;
900 uint8_t buf_size;
901 uint8_t buf[48];
902 uint8_t *pos;
903
32aad86f 904 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 905
906 for (i = 0; i <= av_split; i++) {
907 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 908 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 909 set_buf_index, 2);
c751ce4f
EA		 910 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
911 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 912
913 pos = buf;
914 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 915 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 916 NULL, 0);
c751ce4f 917 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 918 pos += 8;
919 }
920 }
921}
922#endif
923
b6e0e543
DV		 924static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
925 unsigned if_index, uint8_t tx_rate,
926 uint8_t *data, unsigned length)
927{
928 uint8_t set_buf_index[2] = { if_index, 0 };
929 uint8_t hbuf_size, tmp[8];
930 int i;
931
932 if (!intel_sdvo_set_value(intel_sdvo,
933 SDVO_CMD_SET_HBUF_INDEX,
934 set_buf_index, 2))
935 return false;
936
937 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
938 &hbuf_size, 1))
939 return false;
940
941 /* Buffer size is 0 based, hooray! */
942 hbuf_size++;
943
944 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
945 if_index, length, hbuf_size);
946
947 for (i = 0; i < hbuf_size; i += 8) {
948 memset(tmp, 0, 8);
949 if (i < length)
950 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
951
952 if (!intel_sdvo_set_value(intel_sdvo,
953 SDVO_CMD_SET_HBUF_DATA,
954 tmp, 8))
955 return false;
956 }
957
958 return intel_sdvo_set_value(intel_sdvo,
959 SDVO_CMD_SET_HBUF_TXRATE,
960 &tx_rate, 1);
961}
962
abedc077
VS		 963static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
964 const struct drm_display_mode *adjusted_mode)
e2f0ba97 965{
15dcd350
DL		 966 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
967 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
969 union hdmi_infoframe frame;
970 int ret;
971 ssize_t len;
972
973 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
974 adjusted_mode);
975 if (ret < 0) {
976 DRM_ERROR("couldn't fill AVI infoframe\n");
977 return false;
978 }
3c17fe4b 979
abedc077 980 if (intel_sdvo->rgb_quant_range_selectable) {
50f3b016 981 if (intel_crtc->config.limited_color_range)
15dcd350
DL		 982 frame.avi.quantization_range =
983 HDMI_QUANTIZATION_RANGE_LIMITED;
abedc077 984 else
15dcd350
DL		 985 frame.avi.quantization_range =
986 HDMI_QUANTIZATION_RANGE_FULL;
abedc077
VS		 987 }
988
15dcd350
DL		 989 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
990 if (len < 0)
991 return false;
81014b9d 992
b6e0e543
DV		 993 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
994 SDVO_HBUF_TX_VSYNC,
995 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 996}
997
32aad86f 998static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 999{
ce6feabd 1000 struct intel_sdvo_tv_format format;
40039750 1001 uint32_t format_map;
ce6feabd 1002
40039750 1003 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1004 memset(&format, 0, sizeof(format));
32aad86f 1005 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1006
32aad86f
CW		 1007 BUILD_BUG_ON(sizeof(format) != 6);
1008 return intel_sdvo_set_value(intel_sdvo,
1009 SDVO_CMD_SET_TV_FORMAT,
1010 &format, sizeof(format));
7026d4ac
ZW		 1011}
1012
32aad86f
CW		 1013static bool
1014intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1015 const struct drm_display_mode *mode)
e2f0ba97 1016{
32aad86f 1017 struct intel_sdvo_dtd output_dtd;
79e53945 1018
32aad86f
CW		 1019 if (!intel_sdvo_set_target_output(intel_sdvo,
1020 intel_sdvo->attached_output))
1021 return false;
e2f0ba97 1022
32aad86f
CW		 1023 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1024 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1025 return false;
e2f0ba97 1026
32aad86f
CW		 1027 return true;
1028}
1029
c9a29698
DV		 1030/* Asks the sdvo controller for the preferred input mode given the output mode.
1031 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 1032static bool
c9a29698 1033intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1034 const struct drm_display_mode *mode,
c9a29698 1035 struct drm_display_mode *adjusted_mode)
32aad86f 1036{
c9a29698
DV		 1037 struct intel_sdvo_dtd input_dtd;
1038
32aad86f
CW		 1039 /* Reset the input timing to the screen. Assume always input 0. */
1040 if (!intel_sdvo_set_target_input(intel_sdvo))
1041 return false;
e2f0ba97 1042
32aad86f
CW		 1043 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1044 mode->clock / 10,
1045 mode->hdisplay,
1046 mode->vdisplay))
1047 return false;
e2f0ba97 1048
32aad86f 1049 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1050 &input_dtd))
32aad86f 1051 return false;
e2f0ba97 1052
c9a29698 1053 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1054 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1055
32aad86f
CW		 1056 return true;
1057}
12682a97 1058
70484559
DV		 1059static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
1060{
1061 unsigned dotclock = pipe_config->adjusted_mode.clock;
1062 struct dpll *clock = &pipe_config->dpll;
1063
1064 /* SDVO TV has fixed PLL values depend on its clock range,
1065 this mirrors vbios setting. */
1066 if (dotclock >= 100000 && dotclock < 140500) {
1067 clock->p1 = 2;
1068 clock->p2 = 10;
1069 clock->n = 3;
1070 clock->m1 = 16;
1071 clock->m2 = 8;
1072 } else if (dotclock >= 140500 && dotclock <= 200000) {
1073 clock->p1 = 1;
1074 clock->p2 = 10;
1075 clock->n = 6;
1076 clock->m1 = 12;
1077 clock->m2 = 8;
1078 } else {
1079 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1080 }
1081
1082 pipe_config->clock_set = true;
1083}
1084
6cc5f341
DV		 1085static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1086 struct intel_crtc_config *pipe_config)
32aad86f 1087{
8aca63aa 1088 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
6cc5f341
DV		 1089 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1090 struct drm_display_mode *mode = &pipe_config->requested_mode;
12682a97 1091
5d2d38dd
DV		 1092 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1093 pipe_config->pipe_bpp = 8*3;
1094
5bfe2ac0
DV		 1095 if (HAS_PCH_SPLIT(encoder->base.dev))
1096 pipe_config->has_pch_encoder = true;
1097
32aad86f
CW		 1098 /* We need to construct preferred input timings based on our
1099 * output timings. To do that, we have to set the output
1100 * timings, even though this isn't really the right place in
1101 * the sequence to do it. Oh well.
1102 */
1103 if (intel_sdvo->is_tv) {
1104 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1105 return false;
12682a97 1106
c9a29698
DV		 1107 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1108 mode,
1109 adjusted_mode);
09ede541 1110 pipe_config->sdvo_tv_clock = true;
ea5b213a 1111 } else if (intel_sdvo->is_lvds) {
32aad86f 1112 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1113 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1114 return false;
12682a97 1115
c9a29698
DV		 1116 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1117 mode,
1118 adjusted_mode);
e2f0ba97 1119 }
32aad86f
CW		 1120
1121 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1122 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1123 */
6cc5f341
DV		 1124 pipe_config->pixel_multiplier =
1125 intel_sdvo_get_pixel_multiplier(adjusted_mode);
1126 adjusted_mode->clock *= pipe_config->pixel_multiplier;
32aad86f 1127
55bc60db
VS		 1128 if (intel_sdvo->color_range_auto) {
1129 /* See CEA-861-E - 5.1 Default Encoding Parameters */
4f3a8bc7
PZ		 1130 /* FIXME: This bit is only valid when using TMDS encoding and 8
1131 * bit per color mode. */
55bc60db 1132 if (intel_sdvo->has_hdmi_monitor &&
18316c8c 1133 drm_match_cea_mode(adjusted_mode) > 1)
4f3a8bc7 1134 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 1135 else
1136 intel_sdvo->color_range = 0;
1137 }
1138
3685a8f3 1139 if (intel_sdvo->color_range)
50f3b016 1140 pipe_config->limited_color_range = true;
3685a8f3 1141
70484559
DV		 1142 /* Clock computation needs to happen after pixel multiplier. */
1143 if (intel_sdvo->is_tv)
1144 i9xx_adjust_sdvo_tv_clock(pipe_config);
1145
e2f0ba97
JB		 1146 return true;
1147}
1148
6cc5f341 1149static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
e2f0ba97 1150{
6cc5f341 1151 struct drm_device *dev = intel_encoder->base.dev;
e2f0ba97 1152 struct drm_i915_private *dev_priv = dev->dev_private;
6cc5f341 1153 struct drm_crtc *crtc = intel_encoder->base.crtc;
e2f0ba97 1154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 1155 struct drm_display_mode *adjusted_mode =
1156 &intel_crtc->config.adjusted_mode;
1157 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
8aca63aa 1158 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
6c9547ff 1159 u32 sdvox;
e2f0ba97 1160 struct intel_sdvo_in_out_map in_out;
6651819b 1161 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff 1162 int rate;
e2f0ba97
JB		 1163
1164 if (!mode)
1165 return;
1166
1167 /* First, set the input mapping for the first input to our controlled
1168 * output. This is only correct if we're a single-input device, in
1169 * which case the first input is the output from the appropriate SDVO
1170 * channel on the motherboard. In a two-input device, the first input
1171 * will be SDVOB and the second SDVOC.
1172 */
ea5b213a 1173 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1174 in_out.in1 = 0;
1175
c74696b9
PR		 1176 intel_sdvo_set_value(intel_sdvo,
1177 SDVO_CMD_SET_IN_OUT_MAP,
1178 &in_out, sizeof(in_out));
e2f0ba97 1179
6c9547ff
CW		 1180 /* Set the output timings to the screen */
1181 if (!intel_sdvo_set_target_output(intel_sdvo,
1182 intel_sdvo->attached_output))
1183 return;
e2f0ba97 1184
6651819b
DV		 1185 /* lvds has a special fixed output timing. */
1186 if (intel_sdvo->is_lvds)
1187 intel_sdvo_get_dtd_from_mode(&output_dtd,
1188 intel_sdvo->sdvo_lvds_fixed_mode);
1189 else
1190 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1191 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1192 DRM_INFO("Setting output timings on %s failed\n",
1193 SDVO_NAME(intel_sdvo));
79e53945
JB		 1194
1195 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1196 if (!intel_sdvo_set_target_input(intel_sdvo))
1197 return;
79e53945 1198
97aaf910
CW		 1199 if (intel_sdvo->has_hdmi_monitor) {
1200 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1201 intel_sdvo_set_colorimetry(intel_sdvo,
1202 SDVO_COLORIMETRY_RGB256);
abedc077 1203 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
97aaf910
CW		 1204 } else
1205 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1206
6c9547ff
CW		 1207 if (intel_sdvo->is_tv &&
1208 !intel_sdvo_set_tv_format(intel_sdvo))
1209 return;
e2f0ba97 1210
6651819b
DV		 1211 /* We have tried to get input timing in mode_fixup, and filled into
1212 * adjusted_mode.
1213 */
1214 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
e751823d
EE		 1215 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1216 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1217 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1218 DRM_INFO("Setting input timings on %s failed\n",
1219 SDVO_NAME(intel_sdvo));
79e53945 1220
6cc5f341 1221 switch (intel_crtc->config.pixel_multiplier) {
6c9547ff 1222 default:
ef1b460d 1223 WARN(1, "unknown pixel mutlipler specified\n");
32aad86f
CW		 1224 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1225 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1226 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1227 }
32aad86f
CW		 1228 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1229 return;
79e53945
JB		 1230
1231 /* Set the SDVO control regs. */
a6c45cf0 1232 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1233 /* The real mode polarity is set by the SDVO commands, using
1234 * struct intel_sdvo_dtd. */
1235 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
3685a8f3 1236 if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
e953fd7b 1237 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1238 if (INTEL_INFO(dev)->gen < 5)
1239 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1240 } else {
6c9547ff 1241 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1242 switch (intel_sdvo->sdvo_reg) {
e2debe91 1243 case GEN3_SDVOB:
e2f0ba97
JB		 1244 sdvox &= SDVOB_PRESERVE_MASK;
1245 break;
e2debe91 1246 case GEN3_SDVOC:
e2f0ba97
JB		 1247 sdvox &= SDVOC_PRESERVE_MASK;
1248 break;
1249 }
1250 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1251 }
3573c410
PZ		 1252
1253 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
dc0fa718 1254 sdvox |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe);
3573c410 1255 else
dc0fa718 1256 sdvox |= SDVO_PIPE_SEL(intel_crtc->pipe);
3573c410 1257
da79de97 1258 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1259 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1260
a6c45cf0 1261 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1262 /* done in crtc_mode_set as the dpll_md reg must be written early */
1263 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1264 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1265 } else {
6cc5f341
DV		 1266 sdvox |= (intel_crtc->config.pixel_multiplier - 1)
1267 << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1268 }
1269
6714afb1
CW		 1270 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1271 INTEL_INFO(dev)->gen < 5)
12682a97 1272 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1273 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1274}
1275
4ac41f47 1276static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1277{
4ac41f47
DV		 1278 struct intel_sdvo_connector *intel_sdvo_connector =
1279 to_intel_sdvo_connector(&connector->base);
1280 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
2f28c50b 1281 u16 active_outputs = 0;
4ac41f47
DV		 1282
1283 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1284
1285 if (active_outputs & intel_sdvo_connector->output_flag)
1286 return true;
1287 else
1288 return false;
1289}
1290
1291static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1292 enum pipe *pipe)
1293{
1294 struct drm_device *dev = encoder->base.dev;
79e53945 1295 struct drm_i915_private *dev_priv = dev->dev_private;
8aca63aa 1296 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2f28c50b 1297 u16 active_outputs = 0;
4ac41f47
DV		 1298 u32 tmp;
1299
1300 tmp = I915_READ(intel_sdvo->sdvo_reg);
7a7d1fb7 1301 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
4ac41f47 1302
7a7d1fb7 1303 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
4ac41f47
DV		 1304 return false;
1305
1306 if (HAS_PCH_CPT(dev))
1307 *pipe = PORT_TO_PIPE_CPT(tmp);
1308 else
1309 *pipe = PORT_TO_PIPE(tmp);
1310
1311 return true;
1312}
1313
045ac3b5
JB		 1314static void intel_sdvo_get_config(struct intel_encoder *encoder,
1315 struct intel_crtc_config *pipe_config)
1316{
6c49f241
DV		 1317 struct drm_device *dev = encoder->base.dev;
1318 struct drm_i915_private *dev_priv = dev->dev_private;
8aca63aa 1319 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
045ac3b5 1320 struct intel_sdvo_dtd dtd;
6c49f241
DV		 1321 int encoder_pixel_multiplier = 0;
1322 u32 flags = 0, sdvox;
1323 u8 val;
045ac3b5
JB		 1324 bool ret;
1325
1326 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1327 if (!ret) {
bb760063
DV		 1328 /* Some sdvo encoders are not spec compliant and don't
1329 * implement the mandatory get_timings function. */
045ac3b5 1330 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
bb760063
DV		 1331 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1332 } else {
1333 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1334 flags |= DRM_MODE_FLAG_PHSYNC;
1335 else
1336 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1337
bb760063
DV		 1338 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1339 flags |= DRM_MODE_FLAG_PVSYNC;
1340 else
1341 flags |= DRM_MODE_FLAG_NVSYNC;
045ac3b5
JB		 1342 }
1343
045ac3b5 1344 pipe_config->adjusted_mode.flags |= flags;
045ac3b5 1345
fdafa9e2
DV		 1346 /*
1347 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1348 * the sdvo port register, on all other platforms it is part of the dpll
1349 * state. Since the general pipe state readout happens before the
1350 * encoder->get_config we so already have a valid pixel multplier on all
1351 * other platfroms.
1352 */
6c49f241
DV		 1353 if (IS_I915G(dev) || IS_I915GM(dev)) {
1354 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1355 pipe_config->pixel_multiplier =
1356 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1357 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1358 }
045ac3b5 1359
6c49f241 1360 /* Cross check the port pixel multiplier with the sdvo encoder state. */
53b91408
DL		 1361 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1362 &val, 1)) {
1363 switch (val) {
1364 case SDVO_CLOCK_RATE_MULT_1X:
1365 encoder_pixel_multiplier = 1;
1366 break;
1367 case SDVO_CLOCK_RATE_MULT_2X:
1368 encoder_pixel_multiplier = 2;
1369 break;
1370 case SDVO_CLOCK_RATE_MULT_4X:
1371 encoder_pixel_multiplier = 4;
1372 break;
1373 }
6c49f241 1374 }
fdafa9e2 1375
6c49f241
DV		 1376 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1377 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1378 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
045ac3b5
JB		 1379}
1380
ce22c320
DV		 1381static void intel_disable_sdvo(struct intel_encoder *encoder)
1382{
1383 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
8aca63aa 1384 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
ce22c320
DV		 1385 u32 temp;
1386
1387 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1388 if (0)
1389 intel_sdvo_set_encoder_power_state(intel_sdvo,
1390 DRM_MODE_DPMS_OFF);
1391
1392 temp = I915_READ(intel_sdvo->sdvo_reg);
1393 if ((temp & SDVO_ENABLE) != 0) {
776ca7cf
CW		 1394 /* HW workaround for IBX, we need to move the port to
1395 * transcoder A before disabling it. */
1396 if (HAS_PCH_IBX(encoder->base.dev)) {
1397 struct drm_crtc *crtc = encoder->base.crtc;
1398 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1399
1400 if (temp & SDVO_PIPE_B_SELECT) {
1401 temp &= ~SDVO_PIPE_B_SELECT;
1402 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1403 POSTING_READ(intel_sdvo->sdvo_reg);
1404
1405 /* Again we need to write this twice. */
1406 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1407 POSTING_READ(intel_sdvo->sdvo_reg);
1408
1409 /* Transcoder selection bits only update
1410 * effectively on vblank. */
1411 if (crtc)
1412 intel_wait_for_vblank(encoder->base.dev, pipe);
1413 else
1414 msleep(50);
1415 }
1416 }
1417
ce22c320
DV		 1418 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1419 }
1420}
1421
1422static void intel_enable_sdvo(struct intel_encoder *encoder)
1423{
1424 struct drm_device *dev = encoder->base.dev;
1425 struct drm_i915_private *dev_priv = dev->dev_private;
8aca63aa 1426 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
ce22c320 1427 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 1428 u32 temp;
ce22c320
DV		 1429 bool input1, input2;
1430 int i;
1431 u8 status;
1432
1433 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf
CW		 1434 if ((temp & SDVO_ENABLE) == 0) {
1435 /* HW workaround for IBX, we need to move the port
dc0fa718
PZ		 1436 * to transcoder A before disabling it, so restore it here. */
1437 if (HAS_PCH_IBX(dev))
1438 temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
776ca7cf 1439
ce22c320 1440 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
776ca7cf 1441 }
ce22c320
DV		 1442 for (i = 0; i < 2; i++)
1443 intel_wait_for_vblank(dev, intel_crtc->pipe);
1444
1445 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1446 /* Warn if the device reported failure to sync.
1447 * A lot of SDVO devices fail to notify of sync, but it's
1448 * a given it the status is a success, we succeeded.
1449 */
1450 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1451 DRM_DEBUG_KMS("First %s output reported failure to "
1452 "sync\n", SDVO_NAME(intel_sdvo));
1453 }
1454
1455 if (0)
1456 intel_sdvo_set_encoder_power_state(intel_sdvo,
1457 DRM_MODE_DPMS_ON);
1458 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1459}
1460
6b1c087b 1461/* Special dpms function to support cloning between dvo/sdvo/crt. */
b2cabb0e 1462static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
79e53945 1463{
b2cabb0e
DV		 1464 struct drm_crtc *crtc;
1465 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1466
1467 /* dvo supports only 2 dpms states. */
1468 if (mode != DRM_MODE_DPMS_ON)
1469 mode = DRM_MODE_DPMS_OFF;
1470
1471 if (mode == connector->dpms)
1472 return;
1473
1474 connector->dpms = mode;
1475
1476 /* Only need to change hw state when actually enabled */
1477 crtc = intel_sdvo->base.base.crtc;
1478 if (!crtc) {
1479 intel_sdvo->base.connectors_active = false;
1480 return;
1481 }
79e53945 1482
6b1c087b
JN		 1483 /* We set active outputs manually below in case pipe dpms doesn't change
1484 * due to cloning. */
79e53945 1485 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1486 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1487 if (0)
ea5b213a 1488 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945 1489
b2cabb0e
DV		 1490 intel_sdvo->base.connectors_active = false;
1491
1492 intel_crtc_update_dpms(crtc);
79e53945 1493 } else {
b2cabb0e
DV		 1494 intel_sdvo->base.connectors_active = true;
1495
1496 intel_crtc_update_dpms(crtc);
79e53945
JB		 1497
1498 if (0)
ea5b213a
CW		 1499 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1500 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945 1501 }
0a91ca29 1502
b980514c 1503 intel_modeset_check_state(connector->dev);
79e53945
JB		 1504}
1505
79e53945
JB		 1506static int intel_sdvo_mode_valid(struct drm_connector *connector,
1507 struct drm_display_mode *mode)
1508{
df0e9248 1509 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1510
1511 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1512 return MODE_NO_DBLESCAN;
1513
ea5b213a 1514 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1515 return MODE_CLOCK_LOW;
1516
ea5b213a 1517 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1518 return MODE_CLOCK_HIGH;
1519
8545423a 1520 if (intel_sdvo->is_lvds) {
ea5b213a 1521 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1522 return MODE_PANEL;
1523
ea5b213a 1524 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1525 return MODE_PANEL;
1526 }
1527
79e53945
JB		 1528 return MODE_OK;
1529}
1530
ea5b213a 1531static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1532{
1a3665c8 1533 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1534 if (!intel_sdvo_get_value(intel_sdvo,
1535 SDVO_CMD_GET_DEVICE_CAPS,
1536 caps, sizeof(*caps)))
1537 return false;
1538
1539 DRM_DEBUG_KMS("SDVO capabilities:\n"
1540 " vendor_id: %d\n"
1541 " device_id: %d\n"
1542 " device_rev_id: %d\n"
1543 " sdvo_version_major: %d\n"
1544 " sdvo_version_minor: %d\n"
1545 " sdvo_inputs_mask: %d\n"
1546 " smooth_scaling: %d\n"
1547 " sharp_scaling: %d\n"
1548 " up_scaling: %d\n"
1549 " down_scaling: %d\n"
1550 " stall_support: %d\n"
1551 " output_flags: %d\n",
1552 caps->vendor_id,
1553 caps->device_id,
1554 caps->device_rev_id,
1555 caps->sdvo_version_major,
1556 caps->sdvo_version_minor,
1557 caps->sdvo_inputs_mask,
1558 caps->smooth_scaling,
1559 caps->sharp_scaling,
1560 caps->up_scaling,
1561 caps->down_scaling,
1562 caps->stall_support,
1563 caps->output_flags);
1564
1565 return true;
79e53945
JB		 1566}
1567
5fa7ac9c 1568static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1569{
768b107e 1570 struct drm_device *dev = intel_sdvo->base.base.dev;
5fa7ac9c 1571 uint16_t hotplug;
79e53945 1572
768b107e
DV		 1573 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1574 * on the line. */
1575 if (IS_I945G(dev) || IS_I945GM(dev))
5fa7ac9c 1576 return 0;
768b107e 1577
5fa7ac9c
JN		 1578 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1579 &hotplug, sizeof(hotplug)))
1580 return 0;
768b107e 1581
5fa7ac9c 1582 return hotplug;
79e53945
JB		 1583}
1584
cc68c81a 1585static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1586{
8aca63aa 1587 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
79e53945 1588
5fa7ac9c
JN		 1589 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1590 &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1591}
1592
fb7a46f3 1593static bool
ea5b213a 1594intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1595{
bc65212c 1596 /* Is there more than one type of output? */
2294488d 1597 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1598}
1599
f899fc64 1600static struct edid *
e957d772 1601intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1602{
e957d772
CW		 1603 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1604 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1605}
1606
ff482d83
CW		 1607/* Mac mini hack -- use the same DDC as the analog connector */
1608static struct edid *
1609intel_sdvo_get_analog_edid(struct drm_connector *connector)
1610{
f899fc64 1611 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1612
0c1dab89 1613 return drm_get_edid(connector,
3bd7d909 1614 intel_gmbus_get_adapter(dev_priv,
41aa3448 1615 dev_priv->vbt.crt_ddc_pin));
ff482d83
CW		 1616}
1617
c43b5634 1618static enum drm_connector_status
8bf38485 1619intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1620{
df0e9248 1621 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1622 enum drm_connector_status status;
1623 struct edid *edid;
9dff6af8 1624
e957d772 1625 edid = intel_sdvo_get_edid(connector);
57cdaf90 1626
ea5b213a 1627 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1628 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1629
7c3f0a27
ZY		 1630 /*
1631 * Don't use the 1 as the argument of DDC bus switch to get
1632 * the EDID. It is used for SDVO SPD ROM.
1633 */
9d1a903d 1634 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1635 intel_sdvo->ddc_bus = ddc;
1636 edid = intel_sdvo_get_edid(connector);
1637 if (edid)
7c3f0a27 1638 break;
7c3f0a27 1639 }
e957d772
CW		 1640 /*
1641 * If we found the EDID on the other bus,
1642 * assume that is the correct DDC bus.
1643 */
1644 if (edid == NULL)
1645 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1646 }
9d1a903d
CW		 1647
1648 /*
1649 * When there is no edid and no monitor is connected with VGA
1650 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1651 */
ff482d83
CW		 1652 if (edid == NULL)
1653 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1654
2f551c84 1655 status = connector_status_unknown;
9dff6af8 1656 if (edid != NULL) {
149c36a3 1657 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1658 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1659 status = connector_status_connected;
da79de97
CW		 1660 if (intel_sdvo->is_hdmi) {
1661 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1662 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
abedc077
VS		 1663 intel_sdvo->rgb_quant_range_selectable =
1664 drm_rgb_quant_range_selectable(edid);
da79de97 1665 }
13946743
CW		 1666 } else
1667 status = connector_status_disconnected;
9d1a903d
CW		 1668 kfree(edid);
1669 }
7f36e7ed
CW		 1670
1671 if (status == connector_status_connected) {
1672 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1673 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1674 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1675 }
1676
2b8d33f7 1677 return status;
9dff6af8
ML		 1678}
1679
52220085
CW		 1680static bool
1681intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1682 struct edid *edid)
1683{
1684 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1685 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1686
1687 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1688 connector_is_digital, monitor_is_digital);
1689 return connector_is_digital == monitor_is_digital;
1690}
1691
7b334fcb 1692static enum drm_connector_status
930a9e28 1693intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1694{
fb7a46f3 1695 uint16_t response;
df0e9248 1696 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1697 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1698 enum drm_connector_status ret;
79e53945 1699
164c8598
CW		 1700 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1701 connector->base.id, drm_get_connector_name(connector));
1702
fc37381c
CW		 1703 if (!intel_sdvo_get_value(intel_sdvo,
1704 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1705 &response, 2))
32aad86f 1706 return connector_status_unknown;
79e53945 1707
e957d772
CW		 1708 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1709 response & 0xff, response >> 8,
1710 intel_sdvo_connector->output_flag);
e2f0ba97 1711
fb7a46f3 1712 if (response == 0)
79e53945 1713 return connector_status_disconnected;
fb7a46f3 1714
ea5b213a 1715 intel_sdvo->attached_output = response;
14571b4c 1716
97aaf910
CW		 1717 intel_sdvo->has_hdmi_monitor = false;
1718 intel_sdvo->has_hdmi_audio = false;
abedc077 1719 intel_sdvo->rgb_quant_range_selectable = false;
97aaf910 1720
615fb93f 1721 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1722 ret = connector_status_disconnected;
13946743 1723 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1724 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1725 else {
1726 struct edid *edid;
1727
1728 /* if we have an edid check it matches the connection */
1729 edid = intel_sdvo_get_edid(connector);
1730 if (edid == NULL)
1731 edid = intel_sdvo_get_analog_edid(connector);
1732 if (edid != NULL) {
52220085
CW		 1733 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1734 edid))
13946743 1735 ret = connector_status_connected;
52220085
CW		 1736 else
1737 ret = connector_status_disconnected;
1738
13946743
CW		 1739 kfree(edid);
1740 } else
1741 ret = connector_status_connected;
1742 }
14571b4c
ZW		 1743
1744 /* May update encoder flag for like clock for SDVO TV, etc.*/
1745 if (ret == connector_status_connected) {
ea5b213a
CW		 1746 intel_sdvo->is_tv = false;
1747 intel_sdvo->is_lvds = false;
14571b4c 1748
09ede541 1749 if (response & SDVO_TV_MASK)
ea5b213a 1750 intel_sdvo->is_tv = true;
14571b4c 1751 if (response & SDVO_LVDS_MASK)
8545423a 1752 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1753 }
14571b4c
ZW		 1754
1755 return ret;
79e53945
JB		 1756}
1757
e2f0ba97 1758static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1759{
ff482d83 1760 struct edid *edid;
79e53945
JB		 1761
1762 /* set the bus switch and get the modes */
e957d772 1763 edid = intel_sdvo_get_edid(connector);
79e53945 1764
57cdaf90
KP		 1765 /*
1766 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1767 * link between analog and digital outputs. So, if the regular SDVO
1768 * DDC fails, check to see if the analog output is disconnected, in
1769 * which case we'll look there for the digital DDC data.
e2f0ba97 1770 */
f899fc64
CW		 1771 if (edid == NULL)
1772 edid = intel_sdvo_get_analog_edid(connector);
1773
ff482d83 1774 if (edid != NULL) {
52220085
CW		 1775 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1776 edid)) {
0c1dab89
CW		 1777 drm_mode_connector_update_edid_property(connector, edid);
1778 drm_add_edid_modes(connector, edid);
1779 }
13946743 1780
ff482d83 1781 kfree(edid);
e2f0ba97 1782 }
e2f0ba97
JB		 1783}
1784
1785/*
1786 * Set of SDVO TV modes.
1787 * Note! This is in reply order (see loop in get_tv_modes).
1788 * XXX: all 60Hz refresh?
1789 */
b1f559ec 1790static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1791 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1792 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1793 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1794 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1795 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1796 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1797 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1798 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1799 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1800 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1801 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1802 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1803 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1804 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1805 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1806 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1807 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1808 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1809 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1810 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1811 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1812 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1813 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1814 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1815 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1816 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1817 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1818 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1819 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1820 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1821 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1822 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1823 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1824 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1825 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1827 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1828 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1829 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1830 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1831 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1832 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1833 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1834 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1836 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1837 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1838 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1839 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1840 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1841 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1842 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1843 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1844 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1845 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1846 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1847 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1848};
1849
1850static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1851{
df0e9248 1852 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1853 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1854 uint32_t reply = 0, format_map = 0;
1855 int i;
e2f0ba97
JB		 1856
1857 /* Read the list of supported input resolutions for the selected TV
1858 * format.
1859 */
40039750 1860 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1861 memcpy(&tv_res, &format_map,
32aad86f 1862 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1863
32aad86f
CW		 1864 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1865 return;
ce6feabd 1866
32aad86f 1867 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1868 if (!intel_sdvo_write_cmd(intel_sdvo,
1869 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1870 &tv_res, sizeof(tv_res)))
1871 return;
1872 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1873 return;
1874
1875 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1876 if (reply & (1 << i)) {
1877 struct drm_display_mode *nmode;
1878 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1879 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1880 if (nmode)
1881 drm_mode_probed_add(connector, nmode);
1882 }
e2f0ba97
JB		 1883}
1884
7086c87f
ML		 1885static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1886{
df0e9248 1887 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1888 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1889 struct drm_display_mode *newmode;
7086c87f
ML		 1890
1891 /*
c3456fb3 1892 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
4300a0f8 1893 * SDVO->LVDS transcoders can't cope with the EDID mode.
7086c87f 1894 */
41aa3448 1895 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
7086c87f 1896 newmode = drm_mode_duplicate(connector->dev,
41aa3448 1897 dev_priv->vbt.sdvo_lvds_vbt_mode);
7086c87f
ML		 1898 if (newmode != NULL) {
1899 /* Guarantee the mode is preferred */
1900 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1901 DRM_MODE_TYPE_DRIVER);
1902 drm_mode_probed_add(connector, newmode);
1903 }
1904 }
12682a97 1905
4300a0f8
DA		 1906 /*
1907 * Attempt to get the mode list from DDC.
1908 * Assume that the preferred modes are
1909 * arranged in priority order.
1910 */
1911 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
1912
12682a97 1913 list_for_each_entry(newmode, &connector->probed_modes, head) {
1914 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1915 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1916 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1917
8545423a 1918 intel_sdvo->is_lvds = true;
12682a97 1919 break;
1920 }
1921 }
1922
7086c87f
ML		 1923}
1924
e2f0ba97
JB		 1925static int intel_sdvo_get_modes(struct drm_connector *connector)
1926{
615fb93f 1927 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1928
615fb93f 1929 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1930 intel_sdvo_get_tv_modes(connector);
615fb93f 1931 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1932 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1933 else
1934 intel_sdvo_get_ddc_modes(connector);
1935
32aad86f 1936 return !list_empty(&connector->probed_modes);
79e53945
JB		 1937}
1938
fcc8d672
CW		 1939static void
1940intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1941{
615fb93f 1942 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1943 struct drm_device *dev = connector->dev;
1944
c5521706
CW		 1945 if (intel_sdvo_connector->left)
1946 drm_property_destroy(dev, intel_sdvo_connector->left);
1947 if (intel_sdvo_connector->right)
1948 drm_property_destroy(dev, intel_sdvo_connector->right);
1949 if (intel_sdvo_connector->top)
1950 drm_property_destroy(dev, intel_sdvo_connector->top);
1951 if (intel_sdvo_connector->bottom)
1952 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1953 if (intel_sdvo_connector->hpos)
1954 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1955 if (intel_sdvo_connector->vpos)
1956 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1957 if (intel_sdvo_connector->saturation)
1958 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1959 if (intel_sdvo_connector->contrast)
1960 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1961 if (intel_sdvo_connector->hue)
1962 drm_property_destroy(dev, intel_sdvo_connector->hue);
1963 if (intel_sdvo_connector->sharpness)
1964 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1965 if (intel_sdvo_connector->flicker_filter)
1966 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1967 if (intel_sdvo_connector->flicker_filter_2d)
1968 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1969 if (intel_sdvo_connector->flicker_filter_adaptive)
1970 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1971 if (intel_sdvo_connector->tv_luma_filter)
1972 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1973 if (intel_sdvo_connector->tv_chroma_filter)
1974 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1975 if (intel_sdvo_connector->dot_crawl)
1976 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1977 if (intel_sdvo_connector->brightness)
1978 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1979}
1980
79e53945
JB		 1981static void intel_sdvo_destroy(struct drm_connector *connector)
1982{
615fb93f 1983 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1984
c5521706 1985 if (intel_sdvo_connector->tv_format)
ce6feabd 1986 drm_property_destroy(connector->dev,
c5521706 1987 intel_sdvo_connector->tv_format);
b9219c5e 1988
d2a82a6f 1989 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1990 drm_sysfs_connector_remove(connector);
1991 drm_connector_cleanup(connector);
4b745b1e 1992 kfree(intel_sdvo_connector);
79e53945
JB		 1993}
1994
1aad7ac0
CW		 1995static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1996{
1997 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1998 struct edid *edid;
1999 bool has_audio = false;
2000
2001 if (!intel_sdvo->is_hdmi)
2002 return false;
2003
2004 edid = intel_sdvo_get_edid(connector);
2005 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
2006 has_audio = drm_detect_monitor_audio(edid);
38ab8a20 2007 kfree(edid);
1aad7ac0
CW		 2008
2009 return has_audio;
2010}
2011
ce6feabd
ZY		 2012static int
2013intel_sdvo_set_property(struct drm_connector *connector,
2014 struct drm_property *property,
2015 uint64_t val)
2016{
df0e9248 2017 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 2018 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 2019 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 2020 uint16_t temp_value;
32aad86f
CW		 2021 uint8_t cmd;
2022 int ret;
ce6feabd 2023
662595df 2024 ret = drm_object_property_set_value(&connector->base, property, val);
32aad86f
CW		 2025 if (ret)
2026 return ret;
ce6feabd 2027
3f43c48d 2028 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2029 int i = val;
2030 bool has_audio;
2031
2032 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 2033 return 0;
2034
1aad7ac0 2035 intel_sdvo_connector->force_audio = i;
7f36e7ed 2036
c3e5f67b 2037 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2038 has_audio = intel_sdvo_detect_hdmi_audio(connector);
2039 else
c3e5f67b 2040 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 2041
1aad7ac0 2042 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 2043 return 0;
7f36e7ed 2044
1aad7ac0 2045 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 2046 goto done;
2047 }
2048
e953fd7b 2049 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 2050 bool old_auto = intel_sdvo->color_range_auto;
2051 uint32_t old_range = intel_sdvo->color_range;
2052
55bc60db
VS		 2053 switch (val) {
2054 case INTEL_BROADCAST_RGB_AUTO:
2055 intel_sdvo->color_range_auto = true;
2056 break;
2057 case INTEL_BROADCAST_RGB_FULL:
2058 intel_sdvo->color_range_auto = false;
2059 intel_sdvo->color_range = 0;
2060 break;
2061 case INTEL_BROADCAST_RGB_LIMITED:
2062 intel_sdvo->color_range_auto = false;
4f3a8bc7
PZ		 2063 /* FIXME: this bit is only valid when using TMDS
2064 * encoding and 8 bit per color mode. */
2065 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 2066 break;
2067 default:
2068 return -EINVAL;
2069 }
ae4edb80
DV		 2070
2071 if (old_auto == intel_sdvo->color_range_auto &&
2072 old_range == intel_sdvo->color_range)
2073 return 0;
2074
7f36e7ed
CW		 2075 goto done;
2076 }
2077
c5521706
CW		 2078#define CHECK_PROPERTY(name, NAME) \
2079 if (intel_sdvo_connector->name == property) { \
2080 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
2081 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
2082 cmd = SDVO_CMD_SET_##NAME; \
2083 intel_sdvo_connector->cur_##name = temp_value; \
2084 goto set_value; \
2085 }
2086
2087 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 2088 if (val >= TV_FORMAT_NUM)
2089 return -EINVAL;
2090
40039750 2091 if (intel_sdvo->tv_format_index ==
615fb93f 2092 intel_sdvo_connector->tv_format_supported[val])
32aad86f 2093 return 0;
ce6feabd 2094
40039750 2095 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 2096 goto done;
32aad86f 2097 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 2098 temp_value = val;
c5521706 2099 if (intel_sdvo_connector->left == property) {
662595df 2100 drm_object_property_set_value(&connector->base,
c5521706 2101 intel_sdvo_connector->right, val);
615fb93f 2102 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 2103 return 0;
b9219c5e 2104
615fb93f
CW		 2105 intel_sdvo_connector->left_margin = temp_value;
2106 intel_sdvo_connector->right_margin = temp_value;
2107 temp_value = intel_sdvo_connector->max_hscan -
c5521706 2108 intel_sdvo_connector->left_margin;
b9219c5e 2109 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2110 goto set_value;
2111 } else if (intel_sdvo_connector->right == property) {
662595df 2112 drm_object_property_set_value(&connector->base,
c5521706 2113 intel_sdvo_connector->left, val);
615fb93f 2114 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 2115 return 0;
b9219c5e 2116
615fb93f
CW		 2117 intel_sdvo_connector->left_margin = temp_value;
2118 intel_sdvo_connector->right_margin = temp_value;
2119 temp_value = intel_sdvo_connector->max_hscan -
2120 intel_sdvo_connector->left_margin;
b9219c5e 2121 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2122 goto set_value;
2123 } else if (intel_sdvo_connector->top == property) {
662595df 2124 drm_object_property_set_value(&connector->base,
c5521706 2125 intel_sdvo_connector->bottom, val);
615fb93f 2126 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 2127 return 0;
b9219c5e 2128
615fb93f
CW		 2129 intel_sdvo_connector->top_margin = temp_value;
2130 intel_sdvo_connector->bottom_margin = temp_value;
2131 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2132 intel_sdvo_connector->top_margin;
b9219c5e 2133 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2134 goto set_value;
2135 } else if (intel_sdvo_connector->bottom == property) {
662595df 2136 drm_object_property_set_value(&connector->base,
c5521706 2137 intel_sdvo_connector->top, val);
615fb93f 2138 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 2139 return 0;
2140
615fb93f
CW		 2141 intel_sdvo_connector->top_margin = temp_value;
2142 intel_sdvo_connector->bottom_margin = temp_value;
2143 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2144 intel_sdvo_connector->top_margin;
b9219c5e 2145 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2146 goto set_value;
2147 }
2148 CHECK_PROPERTY(hpos, HPOS)
2149 CHECK_PROPERTY(vpos, VPOS)
2150 CHECK_PROPERTY(saturation, SATURATION)
2151 CHECK_PROPERTY(contrast, CONTRAST)
2152 CHECK_PROPERTY(hue, HUE)
2153 CHECK_PROPERTY(brightness, BRIGHTNESS)
2154 CHECK_PROPERTY(sharpness, SHARPNESS)
2155 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
2156 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
2157 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
2158 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
2159 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 2160 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 2161 }
b9219c5e 2162
c5521706 2163 return -EINVAL; /* unknown property */
b9219c5e 2164
c5521706
CW		 2165set_value:
2166 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
2167 return -EIO;
b9219c5e 2168
b9219c5e 2169
c5521706 2170done:
c0c36b94
CW		 2171 if (intel_sdvo->base.base.crtc)
2172 intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
c5521706 2173
32aad86f 2174 return 0;
c5521706 2175#undef CHECK_PROPERTY
ce6feabd
ZY		 2176}
2177
79e53945 2178static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
b2cabb0e 2179 .dpms = intel_sdvo_dpms,
79e53945
JB		 2180 .detect = intel_sdvo_detect,
2181 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 2182 .set_property = intel_sdvo_set_property,
79e53945
JB		 2183 .destroy = intel_sdvo_destroy,
2184};
2185
2186static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2187 .get_modes = intel_sdvo_get_modes,
2188 .mode_valid = intel_sdvo_mode_valid,
df0e9248 2189 .best_encoder = intel_best_encoder,
79e53945
JB		 2190};
2191
b358d0a6 2192static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2193{
8aca63aa 2194 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
d2a82a6f 2195
ea5b213a 2196 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2197 drm_mode_destroy(encoder->dev,
ea5b213a 2198 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2199
e957d772 2200 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2201 intel_encoder_destroy(encoder);
79e53945
JB		 2202}
2203
2204static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2205 .destroy = intel_sdvo_enc_destroy,
2206};
2207
b66d8424
CW		 2208static void
2209intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2210{
2211 uint16_t mask = 0;
2212 unsigned int num_bits;
2213
2214 /* Make a mask of outputs less than or equal to our own priority in the
2215 * list.
2216 */
2217 switch (sdvo->controlled_output) {
2218 case SDVO_OUTPUT_LVDS1:
2219 mask |= SDVO_OUTPUT_LVDS1;
2220 case SDVO_OUTPUT_LVDS0:
2221 mask |= SDVO_OUTPUT_LVDS0;
2222 case SDVO_OUTPUT_TMDS1:
2223 mask |= SDVO_OUTPUT_TMDS1;
2224 case SDVO_OUTPUT_TMDS0:
2225 mask |= SDVO_OUTPUT_TMDS0;
2226 case SDVO_OUTPUT_RGB1:
2227 mask |= SDVO_OUTPUT_RGB1;
2228 case SDVO_OUTPUT_RGB0:
2229 mask |= SDVO_OUTPUT_RGB0;
2230 break;
2231 }
2232
2233 /* Count bits to find what number we are in the priority list. */
2234 mask &= sdvo->caps.output_flags;
2235 num_bits = hweight16(mask);
2236 /* If more than 3 outputs, default to DDC bus 3 for now. */
2237 if (num_bits > 3)
2238 num_bits = 3;
2239
2240 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2241 sdvo->ddc_bus = 1 << num_bits;
2242}
79e53945 2243
e2f0ba97
JB		 2244/**
2245 * Choose the appropriate DDC bus for control bus switch command for this
2246 * SDVO output based on the controlled output.
2247 *
2248 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2249 * outputs, then LVDS outputs.
2250 */
2251static void
b1083333 2252intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 2253 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 2254{
b1083333 2255 struct sdvo_device_mapping *mapping;
e2f0ba97 2256
eef4eacb 2257 if (sdvo->is_sdvob)
b1083333
AJ		 2258 mapping = &(dev_priv->sdvo_mappings[0]);
2259 else
2260 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 2261
b66d8424
CW		 2262 if (mapping->initialized)
2263 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2264 else
2265 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2266}
2267
e957d772
CW		 2268static void
2269intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2270 struct intel_sdvo *sdvo, u32 reg)
2271{
2272 struct sdvo_device_mapping *mapping;
46eb3036 2273 u8 pin;
e957d772 2274
eef4eacb 2275 if (sdvo->is_sdvob)
e957d772
CW		 2276 mapping = &dev_priv->sdvo_mappings[0];
2277 else
2278 mapping = &dev_priv->sdvo_mappings[1];
2279
6cb1612a 2280 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
e957d772 2281 pin = mapping->i2c_pin;
6cb1612a
JN		 2282 else
2283 pin = GMBUS_PORT_DPB;
e957d772 2284
6cb1612a
JN		 2285 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2286
2287 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2288 * our code totally fails once we start using gmbus. Hence fall back to
2289 * bit banging for now. */
2290 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2291}
2292
fbfcc4f3
JN		 2293/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2294static void
2295intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2296{
2297 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2298}
2299
e2f0ba97 2300static bool
e27d8538 2301intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2302{
97aaf910 2303 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2304}
2305
714605e4 2306static u8
eef4eacb 2307intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 2308{
2309 struct drm_i915_private *dev_priv = dev->dev_private;
2310 struct sdvo_device_mapping *my_mapping, *other_mapping;
2311
eef4eacb 2312 if (sdvo->is_sdvob) {
714605e4 2313 my_mapping = &dev_priv->sdvo_mappings[0];
2314 other_mapping = &dev_priv->sdvo_mappings[1];
2315 } else {
2316 my_mapping = &dev_priv->sdvo_mappings[1];
2317 other_mapping = &dev_priv->sdvo_mappings[0];
2318 }
2319
2320 /* If the BIOS described our SDVO device, take advantage of it. */
2321 if (my_mapping->slave_addr)
2322 return my_mapping->slave_addr;
2323
2324 /* If the BIOS only described a different SDVO device, use the
2325 * address that it isn't using.
2326 */
2327 if (other_mapping->slave_addr) {
2328 if (other_mapping->slave_addr == 0x70)
2329 return 0x72;
2330 else
2331 return 0x70;
2332 }
2333
2334 /* No SDVO device info is found for another DVO port,
2335 * so use mapping assumption we had before BIOS parsing.
2336 */
eef4eacb 2337 if (sdvo->is_sdvob)
714605e4 2338 return 0x70;
2339 else
2340 return 0x72;
2341}
2342
14571b4c 2343static void
df0e9248
CW		 2344intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2345 struct intel_sdvo *encoder)
14571b4c 2346{
df0e9248
CW		 2347 drm_connector_init(encoder->base.base.dev,
2348 &connector->base.base,
2349 &intel_sdvo_connector_funcs,
2350 connector->base.base.connector_type);
6070a4a9 2351
df0e9248
CW		 2352 drm_connector_helper_add(&connector->base.base,
2353 &intel_sdvo_connector_helper_funcs);
14571b4c 2354
8f4839e2 2355 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2356 connector->base.base.doublescan_allowed = 0;
2357 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2358 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2359
df0e9248
CW		 2360 intel_connector_attach_encoder(&connector->base, &encoder->base);
2361 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2362}
6070a4a9 2363
7f36e7ed 2364static void
55bc60db
VS		 2365intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2366 struct intel_sdvo_connector *connector)
7f36e7ed
CW		 2367{
2368 struct drm_device *dev = connector->base.base.dev;
2369
3f43c48d 2370 intel_attach_force_audio_property(&connector->base.base);
55bc60db 2371 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
e953fd7b 2372 intel_attach_broadcast_rgb_property(&connector->base.base);
55bc60db
VS		 2373 intel_sdvo->color_range_auto = true;
2374 }
7f36e7ed
CW		 2375}
2376
fb7a46f3 2377static bool
ea5b213a 2378intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2379{
4ef69c7a 2380 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2381 struct drm_connector *connector;
cc68c81a 2382 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2383 struct intel_connector *intel_connector;
615fb93f 2384 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2385
615fb93f
CW		 2386 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2387 if (!intel_sdvo_connector)
14571b4c
ZW		 2388 return false;
2389
14571b4c 2390 if (device == 0) {
ea5b213a 2391 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2392 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2393 } else if (device == 1) {
ea5b213a 2394 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2395 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2396 }
2397
615fb93f 2398 intel_connector = &intel_sdvo_connector->base;
14571b4c 2399 connector = &intel_connector->base;
5fa7ac9c
JN		 2400 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2401 intel_sdvo_connector->output_flag) {
5fa7ac9c 2402 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
cc68c81a
SF		 2403 /* Some SDVO devices have one-shot hotplug interrupts.
2404 * Ensure that they get re-enabled when an interrupt happens.
2405 */
2406 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2407 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2408 } else {
821450c6 2409 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2410 }
14571b4c
ZW		 2411 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2412 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2413
e27d8538 2414 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2415 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2416 intel_sdvo->is_hdmi = true;
14571b4c 2417 }
14571b4c 2418
df0e9248 2419 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221 2420 if (intel_sdvo->is_hdmi)
55bc60db 2421 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
14571b4c
ZW		 2422
2423 return true;
2424}
2425
2426static bool
ea5b213a 2427intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2428{
4ef69c7a
CW		 2429 struct drm_encoder *encoder = &intel_sdvo->base.base;
2430 struct drm_connector *connector;
2431 struct intel_connector *intel_connector;
2432 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2433
615fb93f
CW		 2434 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2435 if (!intel_sdvo_connector)
2436 return false;
14571b4c 2437
615fb93f 2438 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2439 connector = &intel_connector->base;
2440 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2441 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2442
4ef69c7a
CW		 2443 intel_sdvo->controlled_output |= type;
2444 intel_sdvo_connector->output_flag = type;
14571b4c 2445
4ef69c7a 2446 intel_sdvo->is_tv = true;
14571b4c 2447
df0e9248 2448 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2449
4ef69c7a 2450 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2451 goto err;
14571b4c 2452
4ef69c7a 2453 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2454 goto err;
14571b4c 2455
4ef69c7a 2456 return true;
32aad86f
CW		 2457
2458err:
123d5c01 2459 intel_sdvo_destroy(connector);
32aad86f 2460 return false;
14571b4c
ZW		 2461}
2462
2463static bool
ea5b213a 2464intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2465{
4ef69c7a
CW		 2466 struct drm_encoder *encoder = &intel_sdvo->base.base;
2467 struct drm_connector *connector;
2468 struct intel_connector *intel_connector;
2469 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2470
615fb93f
CW		 2471 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2472 if (!intel_sdvo_connector)
2473 return false;
14571b4c 2474
615fb93f 2475 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2476 connector = &intel_connector->base;
821450c6 2477 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2478 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2479 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2480
2481 if (device == 0) {
2482 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2483 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2484 } else if (device == 1) {
2485 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2486 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2487 }
2488
df0e9248
CW		 2489 intel_sdvo_connector_init(intel_sdvo_connector,
2490 intel_sdvo);
4ef69c7a 2491 return true;
14571b4c
ZW		 2492}
2493
2494static bool
ea5b213a 2495intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2496{
4ef69c7a
CW		 2497 struct drm_encoder *encoder = &intel_sdvo->base.base;
2498 struct drm_connector *connector;
2499 struct intel_connector *intel_connector;
2500 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2501
615fb93f
CW		 2502 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2503 if (!intel_sdvo_connector)
2504 return false;
14571b4c 2505
615fb93f
CW		 2506 intel_connector = &intel_sdvo_connector->base;
2507 connector = &intel_connector->base;
4ef69c7a
CW		 2508 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2509 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2510
2511 if (device == 0) {
2512 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2513 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2514 } else if (device == 1) {
2515 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2516 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2517 }
2518
df0e9248 2519 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2520 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2521 goto err;
2522
2523 return true;
2524
2525err:
123d5c01 2526 intel_sdvo_destroy(connector);
32aad86f 2527 return false;
14571b4c
ZW		 2528}
2529
2530static bool
ea5b213a 2531intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2532{
ea5b213a 2533 intel_sdvo->is_tv = false;
ea5b213a 2534 intel_sdvo->is_lvds = false;
fb7a46f3 2535
14571b4c 2536 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2537
14571b4c 2538 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2539 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2540 return false;
2541
2542 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2543 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2544 return false;
2545
2546 /* TV has no XXX1 function block */
a1f4b7ff 2547 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2548 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2549 return false;
2550
2551 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2552 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2553 return false;
fb7a46f3 2554
a0b1c7a5
CW		 2555 if (flags & SDVO_OUTPUT_YPRPB0)
2556 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2557 return false;
2558
14571b4c 2559 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2560 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2561 return false;
2562
2563 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2564 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2565 return false;
2566
2567 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2568 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2569 return false;
2570
2571 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2572 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2573 return false;
fb7a46f3 2574
14571b4c 2575 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2576 unsigned char bytes[2];
2577
ea5b213a
CW		 2578 intel_sdvo->controlled_output = 0;
2579 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2580 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2581 SDVO_NAME(intel_sdvo),
51c8b407 2582 bytes[0], bytes[1]);
14571b4c 2583 return false;
fb7a46f3 2584 }
27f8227b 2585 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2586
14571b4c 2587 return true;
fb7a46f3 2588}
2589
d0ddfbd3
JN		 2590static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2591{
2592 struct drm_device *dev = intel_sdvo->base.base.dev;
2593 struct drm_connector *connector, *tmp;
2594
2595 list_for_each_entry_safe(connector, tmp,
2596 &dev->mode_config.connector_list, head) {
2597 if (intel_attached_encoder(connector) == &intel_sdvo->base)
2598 intel_sdvo_destroy(connector);
2599 }
2600}
2601
32aad86f
CW		 2602static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2603 struct intel_sdvo_connector *intel_sdvo_connector,
2604 int type)
ce6feabd 2605{
4ef69c7a 2606 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2607 struct intel_sdvo_tv_format format;
2608 uint32_t format_map, i;
ce6feabd 2609
32aad86f
CW		 2610 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2611 return false;
ce6feabd 2612
1a3665c8 2613 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2614 if (!intel_sdvo_get_value(intel_sdvo,
2615 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2616 &format, sizeof(format)))
2617 return false;
ce6feabd 2618
32aad86f 2619 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2620
2621 if (format_map == 0)
32aad86f 2622 return false;
ce6feabd 2623
615fb93f 2624 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2625 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2626 if (format_map & (1 << i))
2627 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2628
2629
c5521706 2630 intel_sdvo_connector->tv_format =
32aad86f
CW		 2631 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2632 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2633 if (!intel_sdvo_connector->tv_format)
fcc8d672 2634 return false;
ce6feabd 2635
615fb93f 2636 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2637 drm_property_add_enum(
c5521706 2638 intel_sdvo_connector->tv_format, i,
40039750 2639 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2640
40039750 2641 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
662595df 2642 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
c5521706 2643 intel_sdvo_connector->tv_format, 0);
32aad86f 2644 return true;
ce6feabd
ZY		 2645
2646}
2647
c5521706
CW		 2648#define ENHANCEMENT(name, NAME) do { \
2649 if (enhancements.name) { \
2650 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2651 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2652 return false; \
2653 intel_sdvo_connector->max_##name = data_value[0]; \
2654 intel_sdvo_connector->cur_##name = response; \
2655 intel_sdvo_connector->name = \
d9bc3c02 2656 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2657 if (!intel_sdvo_connector->name) return false; \
662595df 2658 drm_object_attach_property(&connector->base, \
c5521706
CW		 2659 intel_sdvo_connector->name, \
2660 intel_sdvo_connector->cur_##name); \
2661 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2662 data_value[0], data_value[1], response); \
2663 } \
0206e353 2664} while (0)
c5521706
CW		 2665
2666static bool
2667intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2668 struct intel_sdvo_connector *intel_sdvo_connector,
2669 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2670{
4ef69c7a 2671 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2672 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2673 uint16_t response, data_value[2];
2674
c5521706
CW		 2675 /* when horizontal overscan is supported, Add the left/right property */
2676 if (enhancements.overscan_h) {
2677 if (!intel_sdvo_get_value(intel_sdvo,
2678 SDVO_CMD_GET_MAX_OVERSCAN_H,
2679 &data_value, 4))
2680 return false;
32aad86f 2681
c5521706
CW		 2682 if (!intel_sdvo_get_value(intel_sdvo,
2683 SDVO_CMD_GET_OVERSCAN_H,
2684 &response, 2))
2685 return false;
fcc8d672 2686
c5521706
CW		 2687 intel_sdvo_connector->max_hscan = data_value[0];
2688 intel_sdvo_connector->left_margin = data_value[0] - response;
2689 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2690 intel_sdvo_connector->left =
d9bc3c02 2691 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2692 if (!intel_sdvo_connector->left)
2693 return false;
fcc8d672 2694
662595df 2695 drm_object_attach_property(&connector->base,
c5521706
CW		 2696 intel_sdvo_connector->left,
2697 intel_sdvo_connector->left_margin);
fcc8d672 2698
c5521706 2699 intel_sdvo_connector->right =
d9bc3c02 2700 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2701 if (!intel_sdvo_connector->right)
2702 return false;
32aad86f 2703
662595df 2704 drm_object_attach_property(&connector->base,
c5521706
CW		 2705 intel_sdvo_connector->right,
2706 intel_sdvo_connector->right_margin);
2707 DRM_DEBUG_KMS("h_overscan: max %d, "
2708 "default %d, current %d\n",
2709 data_value[0], data_value[1], response);
2710 }
32aad86f 2711
c5521706
CW		 2712 if (enhancements.overscan_v) {
2713 if (!intel_sdvo_get_value(intel_sdvo,
2714 SDVO_CMD_GET_MAX_OVERSCAN_V,
2715 &data_value, 4))
2716 return false;
fcc8d672 2717
c5521706
CW		 2718 if (!intel_sdvo_get_value(intel_sdvo,
2719 SDVO_CMD_GET_OVERSCAN_V,
2720 &response, 2))
2721 return false;
32aad86f 2722
c5521706
CW		 2723 intel_sdvo_connector->max_vscan = data_value[0];
2724 intel_sdvo_connector->top_margin = data_value[0] - response;
2725 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2726 intel_sdvo_connector->top =
d9bc3c02
SH		 2727 drm_property_create_range(dev, 0,
2728 "top_margin", 0, data_value[0]);
c5521706
CW		 2729 if (!intel_sdvo_connector->top)
2730 return false;
32aad86f 2731
662595df 2732 drm_object_attach_property(&connector->base,
c5521706
CW		 2733 intel_sdvo_connector->top,
2734 intel_sdvo_connector->top_margin);
fcc8d672 2735
c5521706 2736 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2737 drm_property_create_range(dev, 0,
2738 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2739 if (!intel_sdvo_connector->bottom)
2740 return false;
32aad86f 2741
662595df 2742 drm_object_attach_property(&connector->base,
c5521706
CW		 2743 intel_sdvo_connector->bottom,
2744 intel_sdvo_connector->bottom_margin);
2745 DRM_DEBUG_KMS("v_overscan: max %d, "
2746 "default %d, current %d\n",
2747 data_value[0], data_value[1], response);
2748 }
32aad86f 2749
c5521706
CW		 2750 ENHANCEMENT(hpos, HPOS);
2751 ENHANCEMENT(vpos, VPOS);
2752 ENHANCEMENT(saturation, SATURATION);
2753 ENHANCEMENT(contrast, CONTRAST);
2754 ENHANCEMENT(hue, HUE);
2755 ENHANCEMENT(sharpness, SHARPNESS);
2756 ENHANCEMENT(brightness, BRIGHTNESS);
2757 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2758 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2759 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2760 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2761 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2762
e044218a
CW		 2763 if (enhancements.dot_crawl) {
2764 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2765 return false;
2766
2767 intel_sdvo_connector->max_dot_crawl = 1;
2768 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2769 intel_sdvo_connector->dot_crawl =
d9bc3c02 2770 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2771 if (!intel_sdvo_connector->dot_crawl)
2772 return false;
2773
662595df 2774 drm_object_attach_property(&connector->base,
e044218a
CW		 2775 intel_sdvo_connector->dot_crawl,
2776 intel_sdvo_connector->cur_dot_crawl);
2777 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2778 }
2779
c5521706
CW		 2780 return true;
2781}
32aad86f 2782
c5521706
CW		 2783static bool
2784intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2785 struct intel_sdvo_connector *intel_sdvo_connector,
2786 struct intel_sdvo_enhancements_reply enhancements)
2787{
4ef69c7a 2788 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2789 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2790 uint16_t response, data_value[2];
32aad86f 2791
c5521706 2792 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2793
c5521706
CW		 2794 return true;
2795}
2796#undef ENHANCEMENT
32aad86f 2797
c5521706
CW		 2798static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2799 struct intel_sdvo_connector *intel_sdvo_connector)
2800{
2801 union {
2802 struct intel_sdvo_enhancements_reply reply;
2803 uint16_t response;
2804 } enhancements;
32aad86f 2805
1a3665c8
CW		 2806 BUILD_BUG_ON(sizeof(enhancements) != 2);
2807
cf9a2f3a
CW		 2808 enhancements.response = 0;
2809 intel_sdvo_get_value(intel_sdvo,
2810 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2811 &enhancements, sizeof(enhancements));
c5521706
CW		 2812 if (enhancements.response == 0) {
2813 DRM_DEBUG_KMS("No enhancement is supported\n");
2814 return true;
b9219c5e 2815 }
32aad86f 2816
c5521706
CW		 2817 if (IS_TV(intel_sdvo_connector))
2818 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2819 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2820 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2821 else
2822 return true;
e957d772
CW		 2823}
2824
2825static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2826 struct i2c_msg *msgs,
2827 int num)
2828{
2829 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2830
e957d772
CW		 2831 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2832 return -EIO;
2833
2834 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2835}
2836
2837static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2838{
2839 struct intel_sdvo *sdvo = adapter->algo_data;
2840 return sdvo->i2c->algo->functionality(sdvo->i2c);
2841}
2842
2843static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2844 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2845 .functionality = intel_sdvo_ddc_proxy_func
2846};
2847
2848static bool
2849intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2850 struct drm_device *dev)
2851{
2852 sdvo->ddc.owner = THIS_MODULE;
2853 sdvo->ddc.class = I2C_CLASS_DDC;
2854 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2855 sdvo->ddc.dev.parent = &dev->pdev->dev;
2856 sdvo->ddc.algo_data = sdvo;
2857 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2858
2859 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2860}
2861
eef4eacb 2862bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2863{
b01f2c3a 2864 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2865 struct intel_encoder *intel_encoder;
ea5b213a 2866 struct intel_sdvo *intel_sdvo;
79e53945 2867 int i;
ea5b213a
CW		 2868 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2869 if (!intel_sdvo)
7d57382e 2870 return false;
79e53945 2871
56184e3d 2872 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2873 intel_sdvo->is_sdvob = is_sdvob;
2874 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2875 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
fbfcc4f3
JN		 2876 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
2877 goto err_i2c_bus;
e957d772 2878
56184e3d 2879 /* encoder type will be decided later */
ea5b213a 2880 intel_encoder = &intel_sdvo->base;
21d40d37 2881 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2882 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2883
79e53945
JB		 2884 /* Read the regs to test if we can talk to the device */
2885 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2886 u8 byte;
2887
2888 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2889 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2890 SDVO_NAME(intel_sdvo));
f899fc64 2891 goto err;
79e53945
JB		 2892 }
2893 }
2894
6cc5f341 2895 intel_encoder->compute_config = intel_sdvo_compute_config;
ce22c320 2896 intel_encoder->disable = intel_disable_sdvo;
6cc5f341 2897 intel_encoder->mode_set = intel_sdvo_mode_set;
ce22c320 2898 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 2899 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
045ac3b5 2900 intel_encoder->get_config = intel_sdvo_get_config;
ce22c320 2901
af901ca1 2902 /* In default case sdvo lvds is false */
32aad86f 2903 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2904 goto err;
79e53945 2905
ea5b213a
CW		 2906 if (intel_sdvo_output_setup(intel_sdvo,
2907 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 2908 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2909 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 2910 /* Output_setup can leave behind connectors! */
2911 goto err_output;
79e53945
JB		 2912 }
2913
7ba220ce
CW		 2914 /* Only enable the hotplug irq if we need it, to work around noisy
2915 * hotplug lines.
2916 */
2917 if (intel_sdvo->hotplug_active) {
2918 intel_encoder->hpd_pin =
2919 intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C;
2920 }
2921
e506d6fd
DV		 2922 /*
2923 * Cloning SDVO with anything is often impossible, since the SDVO
2924 * encoder can request a special input timing mode. And even if that's
2925 * not the case we have evidence that cloning a plain unscaled mode with
2926 * VGA doesn't really work. Furthermore the cloning flags are way too
2927 * simplistic anyway to express such constraints, so just give up on
2928 * cloning for SDVO encoders.
2929 */
2930 intel_sdvo->base.cloneable = false;
2931
ea5b213a 2932 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2933
79e53945 2934 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2935 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 2936 goto err_output;
79e53945 2937
32aad86f
CW		 2938 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2939 &intel_sdvo->pixel_clock_min,
2940 &intel_sdvo->pixel_clock_max))
d0ddfbd3 2941 goto err_output;
79e53945 2942
8a4c47f3 2943 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2944 "clock range %dMHz - %dMHz, "
2945 "input 1: %c, input 2: %c, "
2946 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2947 SDVO_NAME(intel_sdvo),
2948 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2949 intel_sdvo->caps.device_rev_id,
2950 intel_sdvo->pixel_clock_min / 1000,
2951 intel_sdvo->pixel_clock_max / 1000,
2952 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2953 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2954 /* check currently supported outputs */
ea5b213a 2955 intel_sdvo->caps.output_flags &
79e53945 2956 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2957 intel_sdvo->caps.output_flags &
79e53945 2958 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2959 return true;
79e53945 2960
d0ddfbd3
JN		 2961err_output:
2962 intel_sdvo_output_cleanup(intel_sdvo);
2963
f899fc64 2964err:
373a3cf7 2965 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2966 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 2967err_i2c_bus:
2968 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 2969 kfree(intel_sdvo);
79e53945 2970
7d57382e 2971 return false;
79e53945 2972}
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