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drm/i915/crt: Remove ->mode_set callback
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
ea5b213a 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
79e53945
JB		 37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 46 SDVO_TV_MASK)
14571b4c
ZW		 47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 50#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 51#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 52#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 53
79e53945 54
2e88e40b 55static const char *tv_format_names[] = {
ce6feabd
ZY		 56 "NTSC_M" , "NTSC_J" , "NTSC_443",
57 "PAL_B" , "PAL_D" , "PAL_G" ,
58 "PAL_H" , "PAL_I" , "PAL_M" ,
59 "PAL_N" , "PAL_NC" , "PAL_60" ,
60 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
61 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
62 "SECAM_60"
63};
64
65#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
66
ea5b213a
CW		 67struct intel_sdvo {
68 struct intel_encoder base;
69
f899fc64 70 struct i2c_adapter *i2c;
f9c10a9b 71 u8 slave_addr;
e2f0ba97 72
e957d772
CW		 73 struct i2c_adapter ddc;
74
e2f0ba97 75 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 76 uint32_t sdvo_reg;
79e53945 77
e2f0ba97
JB		 78 /* Active outputs controlled by this SDVO output */
79 uint16_t controlled_output;
79e53945 80
e2f0ba97
JB		 81 /*
82 * Capabilities of the SDVO device returned by
19d415a2 83 * intel_sdvo_get_capabilities()
e2f0ba97 84 */
79e53945 85 struct intel_sdvo_caps caps;
e2f0ba97
JB		 86
87 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 88 int pixel_clock_min, pixel_clock_max;
89
fb7a46f3 90 /*
91 * For multiple function SDVO device,
92 * this is for current attached outputs.
93 */
94 uint16_t attached_output;
95
cc68c81a
SF		 96 /*
97 * Hotplug activation bits for this device
98 */
5fa7ac9c 99 uint16_t hotplug_active;
cc68c81a 100
e953fd7b
CW		 101 /**
102 * This is used to select the color range of RBG outputs in HDMI mode.
103 * It is only valid when using TMDS encoding and 8 bit per color mode.
104 */
105 uint32_t color_range;
55bc60db 106 bool color_range_auto;
e953fd7b 107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
eef4eacb
DV		 117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
ce6feabd 120 /* This is for current tv format name */
40039750 121 int tv_format_index;
ce6feabd 122
e2f0ba97
JB		 123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
da79de97
CW		 127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
abedc077 129 bool rgb_quant_range_selectable;
12682a97 130
7086c87f 131 /**
6c9547ff
CW		 132 * This is set if we detect output of sdvo device as LVDS and
133 * have a valid fixed mode to use with the panel.
7086c87f
ML		 134 */
135 bool is_lvds;
e2f0ba97 136
12682a97 137 /**
138 * This is sdvo fixed pannel mode pointer
139 */
140 struct drm_display_mode *sdvo_lvds_fixed_mode;
141
c751ce4f 142 /* DDC bus used by this SDVO encoder */
e2f0ba97 143 uint8_t ddc_bus;
e751823d
EE		 144
145 /*
146 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
147 */
148 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 149};
150
151struct intel_sdvo_connector {
615fb93f
CW		 152 struct intel_connector base;
153
14571b4c
ZW		 154 /* Mark the type of connector */
155 uint16_t output_flag;
156
c3e5f67b 157 enum hdmi_force_audio force_audio;
7f36e7ed 158
14571b4c 159 /* This contains all current supported TV format */
40039750 160 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 161 int format_supported_num;
c5521706 162 struct drm_property *tv_format;
14571b4c 163
b9219c5e 164 /* add the property for the SDVO-TV */
c5521706
CW		 165 struct drm_property *left;
166 struct drm_property *right;
167 struct drm_property *top;
168 struct drm_property *bottom;
169 struct drm_property *hpos;
170 struct drm_property *vpos;
171 struct drm_property *contrast;
172 struct drm_property *saturation;
173 struct drm_property *hue;
174 struct drm_property *sharpness;
175 struct drm_property *flicker_filter;
176 struct drm_property *flicker_filter_adaptive;
177 struct drm_property *flicker_filter_2d;
178 struct drm_property *tv_chroma_filter;
179 struct drm_property *tv_luma_filter;
e044218a 180 struct drm_property *dot_crawl;
b9219c5e
ZY		 181
182 /* add the property for the SDVO-TV/LVDS */
c5521706 183 struct drm_property *brightness;
b9219c5e
ZY		 184
185 /* Add variable to record current setting for the above property */
186 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 187
b9219c5e
ZY		 188 /* this is to get the range of margin.*/
189 u32 max_hscan, max_vscan;
190 u32 max_hpos, cur_hpos;
191 u32 max_vpos, cur_vpos;
192 u32 cur_brightness, max_brightness;
193 u32 cur_contrast, max_contrast;
194 u32 cur_saturation, max_saturation;
195 u32 cur_hue, max_hue;
c5521706
CW		 196 u32 cur_sharpness, max_sharpness;
197 u32 cur_flicker_filter, max_flicker_filter;
198 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
199 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
200 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
201 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 202 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 203};
204
8aca63aa 205static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
ea5b213a 206{
8aca63aa 207 return container_of(encoder, struct intel_sdvo, base);
ea5b213a
CW		 208}
209
df0e9248
CW		 210static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
211{
8aca63aa 212 return to_sdvo(intel_attached_encoder(connector));
df0e9248
CW		 213}
214
615fb93f
CW		 215static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
216{
217 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
218}
219
fb7a46f3 220static bool
ea5b213a 221intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 222static bool
223intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
224 struct intel_sdvo_connector *intel_sdvo_connector,
225 int type);
226static bool
227intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
228 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 229
79e53945
JB		 230/**
231 * Writes the SDVOB or SDVOC with the given value, but always writes both
232 * SDVOB and SDVOC to work around apparent hardware issues (according to
233 * comments in the BIOS).
234 */
ea5b213a 235static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 236{
4ef69c7a 237 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 238 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 239 u32 bval = val, cval = val;
240 int i;
241
ea5b213a
CW		 242 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
243 I915_WRITE(intel_sdvo->sdvo_reg, val);
244 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 245 return;
246 }
247
e2debe91
PZ		 248 if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
249 cval = I915_READ(GEN3_SDVOC);
250 else
251 bval = I915_READ(GEN3_SDVOB);
252
79e53945
JB		 253 /*
254 * Write the registers twice for luck. Sometimes,
255 * writing them only once doesn't appear to 'stick'.
256 * The BIOS does this too. Yay, magic
257 */
258 for (i = 0; i < 2; i++)
259 {
e2debe91
PZ		 260 I915_WRITE(GEN3_SDVOB, bval);
261 I915_READ(GEN3_SDVOB);
262 I915_WRITE(GEN3_SDVOC, cval);
263 I915_READ(GEN3_SDVOC);
79e53945
JB		 264 }
265}
266
32aad86f 267static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 268{
79e53945
JB		 269 struct i2c_msg msgs[] = {
270 {
e957d772 271 .addr = intel_sdvo->slave_addr,
79e53945
JB		 272 .flags = 0,
273 .len = 1,
e957d772 274 .buf = &addr,
79e53945
JB		 275 },
276 {
e957d772 277 .addr = intel_sdvo->slave_addr,
79e53945
JB		 278 .flags = I2C_M_RD,
279 .len = 1,
e957d772 280 .buf = ch,
79e53945
JB		 281 }
282 };
32aad86f 283 int ret;
79e53945 284
f899fc64 285 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 286 return true;
79e53945 287
8a4c47f3 288 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 289 return false;
290}
291
79e53945
JB		 292#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
293/** Mapping of command numbers to names, for debug output */
005568be 294static const struct _sdvo_cmd_name {
e2f0ba97 295 u8 cmd;
2e88e40b 296 const char *name;
79e53945 297} sdvo_cmd_names[] = {
0206e353
AJ		 298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
341
342 /* Add the op code for SDVO enhancements */
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
387
388 /* HDMI op code */
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 409};
410
eef4eacb 411#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 412
ea5b213a 413static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 414 const void *args, int args_len)
79e53945 415{
84fcb469
DV		 416 int i, pos = 0;
417#define BUF_LEN 256
418 char buffer[BUF_LEN];
419
420#define BUF_PRINT(args...) \
421 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
422
79e53945 423
84fcb469
DV		 424 for (i = 0; i < args_len; i++) {
425 BUF_PRINT("%02X ", ((u8 *)args)[i]);
426 }
427 for (; i < 8; i++) {
428 BUF_PRINT(" ");
429 }
04ad327f 430 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 431 if (cmd == sdvo_cmd_names[i].cmd) {
84fcb469 432 BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 433 break;
434 }
435 }
84fcb469
DV		 436 if (i == ARRAY_SIZE(sdvo_cmd_names)) {
437 BUF_PRINT("(%02X)", cmd);
438 }
439 BUG_ON(pos >= BUF_LEN - 1);
440#undef BUF_PRINT
441#undef BUF_LEN
442
443 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
79e53945 444}
79e53945 445
e957d772
CW		 446static const char *cmd_status_names[] = {
447 "Power on",
448 "Success",
449 "Not supported",
450 "Invalid arg",
451 "Pending",
452 "Target not specified",
453 "Scaling not supported"
454};
455
32aad86f
CW		 456static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
457 const void *args, int args_len)
79e53945 458{
3bf3f452
BW		 459 u8 *buf, status;
460 struct i2c_msg *msgs;
461 int i, ret = true;
462
0274df3e 463 /* Would be simpler to allocate both in one go ? */
5c67eeb6 464 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3bf3f452
BW		 465 if (!buf)
466 return false;
467
468 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e
AC		 469 if (!msgs) {
470 kfree(buf);
3bf3f452 471 return false;
0274df3e 472 }
79e53945 473
ea5b213a 474 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 475
476 for (i = 0; i < args_len; i++) {
e957d772
CW		 477 msgs[i].addr = intel_sdvo->slave_addr;
478 msgs[i].flags = 0;
479 msgs[i].len = 2;
480 msgs[i].buf = buf + 2 *i;
481 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
482 buf[2*i + 1] = ((u8*)args)[i];
483 }
484 msgs[i].addr = intel_sdvo->slave_addr;
485 msgs[i].flags = 0;
486 msgs[i].len = 2;
487 msgs[i].buf = buf + 2*i;
488 buf[2*i + 0] = SDVO_I2C_OPCODE;
489 buf[2*i + 1] = cmd;
490
491 /* the following two are to read the response */
492 status = SDVO_I2C_CMD_STATUS;
493 msgs[i+1].addr = intel_sdvo->slave_addr;
494 msgs[i+1].flags = 0;
495 msgs[i+1].len = 1;
496 msgs[i+1].buf = &status;
497
498 msgs[i+2].addr = intel_sdvo->slave_addr;
499 msgs[i+2].flags = I2C_M_RD;
500 msgs[i+2].len = 1;
501 msgs[i+2].buf = &status;
502
503 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
504 if (ret < 0) {
505 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 506 ret = false;
507 goto out;
e957d772
CW		 508 }
509 if (ret != i+3) {
510 /* failure in I2C transfer */
511 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 512 ret = false;
e957d772
CW		 513 }
514
3bf3f452
BW		 515out:
516 kfree(msgs);
517 kfree(buf);
518 return ret;
79e53945
JB		 519}
520
b5c616a7
CW		 521static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
522 void *response, int response_len)
79e53945 523{
fc37381c 524 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 525 u8 status;
84fcb469
DV		 526 int i, pos = 0;
527#define BUF_LEN 256
528 char buffer[BUF_LEN];
79e53945 529
d121a5d2 530
b5c616a7
CW		 531 /*
532 * The documentation states that all commands will be
533 * processed within 15µs, and that we need only poll
534 * the status byte a maximum of 3 times in order for the
535 * command to be complete.
536 *
537 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 538 *
539 * Also beware that the first response by many devices is to
540 * reply PENDING and stall for time. TVs are notorious for
541 * requiring longer than specified to complete their replies.
542 * Originally (in the DDX long ago), the delay was only ever 15ms
543 * with an additional delay of 30ms applied for TVs added later after
544 * many experiments. To accommodate both sets of delays, we do a
545 * sequence of slow checks if the device is falling behind and fails
546 * to reply within 5*15µs.
b5c616a7 547 */
d121a5d2
CW		 548 if (!intel_sdvo_read_byte(intel_sdvo,
549 SDVO_I2C_CMD_STATUS,
550 &status))
551 goto log_fail;
552
1ad87e72 553 while ((status == SDVO_CMD_STATUS_PENDING ||
46a3f4a3 554 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
fc37381c
CW		 555 if (retry < 10)
556 msleep(15);
557 else
558 udelay(15);
559
b5c616a7
CW		 560 if (!intel_sdvo_read_byte(intel_sdvo,
561 SDVO_I2C_CMD_STATUS,
562 &status))
d121a5d2
CW		 563 goto log_fail;
564 }
b5c616a7 565
84fcb469
DV		 566#define BUF_PRINT(args...) \
567 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
568
79e53945 569 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
84fcb469 570 BUF_PRINT("(%s)", cmd_status_names[status]);
79e53945 571 else
84fcb469 572 BUF_PRINT("(??? %d)", status);
79e53945 573
b5c616a7
CW		 574 if (status != SDVO_CMD_STATUS_SUCCESS)
575 goto log_fail;
79e53945 576
b5c616a7
CW		 577 /* Read the command response */
578 for (i = 0; i < response_len; i++) {
579 if (!intel_sdvo_read_byte(intel_sdvo,
580 SDVO_I2C_RETURN_0 + i,
581 &((u8 *)response)[i]))
582 goto log_fail;
84fcb469 583 BUF_PRINT(" %02X", ((u8 *)response)[i]);
b5c616a7 584 }
84fcb469
DV		 585 BUG_ON(pos >= BUF_LEN - 1);
586#undef BUF_PRINT
587#undef BUF_LEN
588
589 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
b5c616a7 590 return true;
79e53945 591
b5c616a7 592log_fail:
84fcb469 593 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
b5c616a7 594 return false;
79e53945
JB		 595}
596
b358d0a6 597static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 598{
599 if (mode->clock >= 100000)
600 return 1;
601 else if (mode->clock >= 50000)
602 return 2;
603 else
604 return 4;
605}
606
e957d772
CW		 607static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
608 u8 ddc_bus)
79e53945 609{
d121a5d2 610 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 611 return intel_sdvo_write_cmd(intel_sdvo,
612 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
613 &ddc_bus, 1);
79e53945
JB		 614}
615
32aad86f 616static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 617{
d121a5d2
CW		 618 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
619 return false;
620
621 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 622}
79e53945 623
32aad86f
CW		 624static bool
625intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
626{
627 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
628 return false;
79e53945 629
32aad86f
CW		 630 return intel_sdvo_read_response(intel_sdvo, value, len);
631}
79e53945 632
32aad86f
CW		 633static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
634{
635 struct intel_sdvo_set_target_input_args targets = {0};
636 return intel_sdvo_set_value(intel_sdvo,
637 SDVO_CMD_SET_TARGET_INPUT,
638 &targets, sizeof(targets));
79e53945
JB		 639}
640
641/**
642 * Return whether each input is trained.
643 *
644 * This function is making an assumption about the layout of the response,
645 * which should be checked against the docs.
646 */
ea5b213a 647static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 648{
649 struct intel_sdvo_get_trained_inputs_response response;
79e53945 650
1a3665c8 651 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 652 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
653 &response, sizeof(response)))
79e53945
JB		 654 return false;
655
656 *input_1 = response.input0_trained;
657 *input_2 = response.input1_trained;
658 return true;
659}
660
ea5b213a 661static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 662 u16 outputs)
663{
32aad86f
CW		 664 return intel_sdvo_set_value(intel_sdvo,
665 SDVO_CMD_SET_ACTIVE_OUTPUTS,
666 &outputs, sizeof(outputs));
79e53945
JB		 667}
668
4ac41f47
DV		 669static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
670 u16 *outputs)
671{
672 return intel_sdvo_get_value(intel_sdvo,
673 SDVO_CMD_GET_ACTIVE_OUTPUTS,
674 outputs, sizeof(*outputs));
675}
676
ea5b213a 677static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 678 int mode)
679{
32aad86f 680 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 681
682 switch (mode) {
683 case DRM_MODE_DPMS_ON:
684 state = SDVO_ENCODER_STATE_ON;
685 break;
686 case DRM_MODE_DPMS_STANDBY:
687 state = SDVO_ENCODER_STATE_STANDBY;
688 break;
689 case DRM_MODE_DPMS_SUSPEND:
690 state = SDVO_ENCODER_STATE_SUSPEND;
691 break;
692 case DRM_MODE_DPMS_OFF:
693 state = SDVO_ENCODER_STATE_OFF;
694 break;
695 }
696
32aad86f
CW		 697 return intel_sdvo_set_value(intel_sdvo,
698 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 699}
700
ea5b213a 701static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 702 int *clock_min,
703 int *clock_max)
704{
705 struct intel_sdvo_pixel_clock_range clocks;
79e53945 706
1a3665c8 707 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 708 if (!intel_sdvo_get_value(intel_sdvo,
709 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
710 &clocks, sizeof(clocks)))
79e53945
JB		 711 return false;
712
713 /* Convert the values from units of 10 kHz to kHz. */
714 *clock_min = clocks.min * 10;
715 *clock_max = clocks.max * 10;
79e53945
JB		 716 return true;
717}
718
ea5b213a 719static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 720 u16 outputs)
721{
32aad86f
CW		 722 return intel_sdvo_set_value(intel_sdvo,
723 SDVO_CMD_SET_TARGET_OUTPUT,
724 &outputs, sizeof(outputs));
79e53945
JB		 725}
726
ea5b213a 727static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 728 struct intel_sdvo_dtd *dtd)
729{
32aad86f
CW		 730 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
731 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 732}
733
045ac3b5
JB		 734static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
735 struct intel_sdvo_dtd *dtd)
736{
737 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
738 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
739}
740
ea5b213a 741static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 742 struct intel_sdvo_dtd *dtd)
743{
ea5b213a 744 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 745 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
746}
747
ea5b213a 748static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 749 struct intel_sdvo_dtd *dtd)
750{
ea5b213a 751 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 752 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
753}
754
045ac3b5
JB		 755static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
756 struct intel_sdvo_dtd *dtd)
757{
758 return intel_sdvo_get_timing(intel_sdvo,
759 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
760}
761
e2f0ba97 762static bool
ea5b213a 763intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 764 uint16_t clock,
765 uint16_t width,
766 uint16_t height)
767{
768 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 769
e642c6f1 770 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 771 args.clock = clock;
772 args.width = width;
773 args.height = height;
e642c6f1 774 args.interlace = 0;
12682a97 775
ea5b213a
CW		 776 if (intel_sdvo->is_lvds &&
777 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
778 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 779 args.scaled = 1;
780
32aad86f
CW		 781 return intel_sdvo_set_value(intel_sdvo,
782 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
783 &args, sizeof(args));
e2f0ba97
JB		 784}
785
ea5b213a 786static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 787 struct intel_sdvo_dtd *dtd)
788{
1a3665c8
CW		 789 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
790 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 791 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
792 &dtd->part1, sizeof(dtd->part1)) &&
793 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
794 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 795}
79e53945 796
ea5b213a 797static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 798{
32aad86f 799 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 800}
801
e2f0ba97 802static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 803 const struct drm_display_mode *mode)
79e53945 804{
e2f0ba97
JB		 805 uint16_t width, height;
806 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
807 uint16_t h_sync_offset, v_sync_offset;
6651819b 808 int mode_clock;
79e53945 809
1c4a814e
DV		 810 memset(dtd, 0, sizeof(*dtd));
811
c6ebd4c0
DV		 812 width = mode->hdisplay;
813 height = mode->vdisplay;
79e53945
JB		 814
815 /* do some mode translations */
c6ebd4c0
DV		 816 h_blank_len = mode->htotal - mode->hdisplay;
817 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 818
c6ebd4c0
DV		 819 v_blank_len = mode->vtotal - mode->vdisplay;
820 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 821
c6ebd4c0
DV		 822 h_sync_offset = mode->hsync_start - mode->hdisplay;
823 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 824
6651819b 825 mode_clock = mode->clock;
6651819b
DV		 826 mode_clock /= 10;
827 dtd->part1.clock = mode_clock;
828
e2f0ba97
JB		 829 dtd->part1.h_active = width & 0xff;
830 dtd->part1.h_blank = h_blank_len & 0xff;
831 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 832 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 833 dtd->part1.v_active = height & 0xff;
834 dtd->part1.v_blank = v_blank_len & 0xff;
835 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 836 ((v_blank_len >> 8) & 0xf);
837
171a9e96 838 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 839 dtd->part2.h_sync_width = h_sync_len & 0xff;
840 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 841 (v_sync_len & 0xf);
e2f0ba97 842 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 843 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
844 ((v_sync_len & 0x30) >> 4);
845
e2f0ba97 846 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 847 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
848 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 849 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 850 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 851 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 852 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97 853
e2f0ba97 854 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
e2f0ba97
JB		 855}
856
1c4a814e 857static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
32aad86f 858 const struct intel_sdvo_dtd *dtd)
e2f0ba97 859{
1c4a814e
DV		 860 struct drm_display_mode mode = {};
861
862 mode.hdisplay = dtd->part1.h_active;
863 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
864 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
865 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
866 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
867 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
868 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
869 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
870
871 mode.vdisplay = dtd->part1.v_active;
872 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
873 mode.vsync_start = mode.vdisplay;
874 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
875 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
876 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
877 mode.vsync_end = mode.vsync_start +
e2f0ba97 878 (dtd->part2.v_sync_off_width & 0xf);
1c4a814e
DV		 879 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
880 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
881 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
e2f0ba97 882
1c4a814e 883 mode.clock = dtd->part1.clock * 10;
e2f0ba97 884
59d92bfa 885 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
1c4a814e 886 mode.flags |= DRM_MODE_FLAG_INTERLACE;
59d92bfa 887 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1c4a814e 888 mode.flags |= DRM_MODE_FLAG_PHSYNC;
3cea210f 889 else
1c4a814e 890 mode.flags |= DRM_MODE_FLAG_NHSYNC;
59d92bfa 891 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1c4a814e 892 mode.flags |= DRM_MODE_FLAG_PVSYNC;
3cea210f 893 else
1c4a814e
DV		 894 mode.flags |= DRM_MODE_FLAG_NVSYNC;
895
896 drm_mode_set_crtcinfo(&mode, 0);
897
898 drm_mode_copy(pmode, &mode);
e2f0ba97
JB		 899}
900
e27d8538 901static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 902{
e27d8538 903 struct intel_sdvo_encode encode;
e2f0ba97 904
1a3665c8 905 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 906 return intel_sdvo_get_value(intel_sdvo,
907 SDVO_CMD_GET_SUPP_ENCODE,
908 &encode, sizeof(encode));
e2f0ba97
JB		 909}
910
ea5b213a 911static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 912 uint8_t mode)
e2f0ba97 913{
32aad86f 914 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 915}
916
ea5b213a 917static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 918 uint8_t mode)
919{
32aad86f 920 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 921}
922
923#if 0
ea5b213a 924static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 925{
926 int i, j;
927 uint8_t set_buf_index[2];
928 uint8_t av_split;
929 uint8_t buf_size;
930 uint8_t buf[48];
931 uint8_t *pos;
932
32aad86f 933 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 934
935 for (i = 0; i <= av_split; i++) {
936 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 937 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 938 set_buf_index, 2);
c751ce4f
EA		 939 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
940 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 941
942 pos = buf;
943 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 944 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 945 NULL, 0);
c751ce4f 946 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 947 pos += 8;
948 }
949 }
950}
951#endif
952
b6e0e543
DV		 953static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
954 unsigned if_index, uint8_t tx_rate,
fff63867 955 const uint8_t *data, unsigned length)
b6e0e543
DV		 956{
957 uint8_t set_buf_index[2] = { if_index, 0 };
958 uint8_t hbuf_size, tmp[8];
959 int i;
960
961 if (!intel_sdvo_set_value(intel_sdvo,
962 SDVO_CMD_SET_HBUF_INDEX,
963 set_buf_index, 2))
964 return false;
965
966 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
967 &hbuf_size, 1))
968 return false;
969
970 /* Buffer size is 0 based, hooray! */
971 hbuf_size++;
972
973 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
974 if_index, length, hbuf_size);
975
976 for (i = 0; i < hbuf_size; i += 8) {
977 memset(tmp, 0, 8);
978 if (i < length)
979 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
980
981 if (!intel_sdvo_set_value(intel_sdvo,
982 SDVO_CMD_SET_HBUF_DATA,
983 tmp, 8))
984 return false;
985 }
986
987 return intel_sdvo_set_value(intel_sdvo,
988 SDVO_CMD_SET_HBUF_TXRATE,
989 &tx_rate, 1);
990}
991
abedc077
VS		 992static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
993 const struct drm_display_mode *adjusted_mode)
e2f0ba97 994{
15dcd350
DL		 995 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
996 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
998 union hdmi_infoframe frame;
999 int ret;
1000 ssize_t len;
1001
1002 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
1003 adjusted_mode);
1004 if (ret < 0) {
1005 DRM_ERROR("couldn't fill AVI infoframe\n");
1006 return false;
1007 }
3c17fe4b 1008
abedc077 1009 if (intel_sdvo->rgb_quant_range_selectable) {
50f3b016 1010 if (intel_crtc->config.limited_color_range)
15dcd350
DL		 1011 frame.avi.quantization_range =
1012 HDMI_QUANTIZATION_RANGE_LIMITED;
abedc077 1013 else
15dcd350
DL		 1014 frame.avi.quantization_range =
1015 HDMI_QUANTIZATION_RANGE_FULL;
abedc077
VS		 1016 }
1017
15dcd350
DL		 1018 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
1019 if (len < 0)
1020 return false;
81014b9d 1021
b6e0e543
DV		 1022 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1023 SDVO_HBUF_TX_VSYNC,
1024 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 1025}
1026
32aad86f 1027static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 1028{
ce6feabd 1029 struct intel_sdvo_tv_format format;
40039750 1030 uint32_t format_map;
ce6feabd 1031
40039750 1032 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1033 memset(&format, 0, sizeof(format));
32aad86f 1034 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1035
32aad86f
CW		 1036 BUILD_BUG_ON(sizeof(format) != 6);
1037 return intel_sdvo_set_value(intel_sdvo,
1038 SDVO_CMD_SET_TV_FORMAT,
1039 &format, sizeof(format));
7026d4ac
ZW		 1040}
1041
32aad86f
CW		 1042static bool
1043intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1044 const struct drm_display_mode *mode)
e2f0ba97 1045{
32aad86f 1046 struct intel_sdvo_dtd output_dtd;
79e53945 1047
32aad86f
CW		 1048 if (!intel_sdvo_set_target_output(intel_sdvo,
1049 intel_sdvo->attached_output))
1050 return false;
e2f0ba97 1051
32aad86f
CW		 1052 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1053 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1054 return false;
e2f0ba97 1055
32aad86f
CW		 1056 return true;
1057}
1058
c9a29698
DV		 1059/* Asks the sdvo controller for the preferred input mode given the output mode.
1060 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 1061static bool
c9a29698 1062intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1063 const struct drm_display_mode *mode,
c9a29698 1064 struct drm_display_mode *adjusted_mode)
32aad86f 1065{
c9a29698
DV		 1066 struct intel_sdvo_dtd input_dtd;
1067
32aad86f
CW		 1068 /* Reset the input timing to the screen. Assume always input 0. */
1069 if (!intel_sdvo_set_target_input(intel_sdvo))
1070 return false;
e2f0ba97 1071
32aad86f
CW		 1072 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1073 mode->clock / 10,
1074 mode->hdisplay,
1075 mode->vdisplay))
1076 return false;
e2f0ba97 1077
32aad86f 1078 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1079 &input_dtd))
32aad86f 1080 return false;
e2f0ba97 1081
c9a29698 1082 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1083 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1084
32aad86f
CW		 1085 return true;
1086}
12682a97 1087
70484559
DV		 1088static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
1089{
3c52f4eb 1090 unsigned dotclock = pipe_config->port_clock;
70484559
DV		 1091 struct dpll *clock = &pipe_config->dpll;
1092
1093 /* SDVO TV has fixed PLL values depend on its clock range,
1094 this mirrors vbios setting. */
1095 if (dotclock >= 100000 && dotclock < 140500) {
1096 clock->p1 = 2;
1097 clock->p2 = 10;
1098 clock->n = 3;
1099 clock->m1 = 16;
1100 clock->m2 = 8;
1101 } else if (dotclock >= 140500 && dotclock <= 200000) {
1102 clock->p1 = 1;
1103 clock->p2 = 10;
1104 clock->n = 6;
1105 clock->m1 = 12;
1106 clock->m2 = 8;
1107 } else {
1108 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1109 }
1110
1111 pipe_config->clock_set = true;
1112}
1113
6cc5f341
DV		 1114static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1115 struct intel_crtc_config *pipe_config)
32aad86f 1116{
8aca63aa 1117 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
6cc5f341
DV		 1118 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1119 struct drm_display_mode *mode = &pipe_config->requested_mode;
12682a97 1120
5d2d38dd
DV		 1121 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1122 pipe_config->pipe_bpp = 8*3;
1123
5bfe2ac0
DV		 1124 if (HAS_PCH_SPLIT(encoder->base.dev))
1125 pipe_config->has_pch_encoder = true;
1126
32aad86f
CW		 1127 /* We need to construct preferred input timings based on our
1128 * output timings. To do that, we have to set the output
1129 * timings, even though this isn't really the right place in
1130 * the sequence to do it. Oh well.
1131 */
1132 if (intel_sdvo->is_tv) {
1133 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1134 return false;
12682a97 1135
c9a29698
DV		 1136 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1137 mode,
1138 adjusted_mode);
09ede541 1139 pipe_config->sdvo_tv_clock = true;
ea5b213a 1140 } else if (intel_sdvo->is_lvds) {
32aad86f 1141 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1142 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1143 return false;
12682a97 1144
c9a29698
DV		 1145 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1146 mode,
1147 adjusted_mode);
e2f0ba97 1148 }
32aad86f
CW		 1149
1150 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1151 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1152 */
6cc5f341
DV		 1153 pipe_config->pixel_multiplier =
1154 intel_sdvo_get_pixel_multiplier(adjusted_mode);
32aad86f 1155
55bc60db
VS		 1156 if (intel_sdvo->color_range_auto) {
1157 /* See CEA-861-E - 5.1 Default Encoding Parameters */
4f3a8bc7
PZ		 1158 /* FIXME: This bit is only valid when using TMDS encoding and 8
1159 * bit per color mode. */
55bc60db 1160 if (intel_sdvo->has_hdmi_monitor &&
18316c8c 1161 drm_match_cea_mode(adjusted_mode) > 1)
4f3a8bc7 1162 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 1163 else
1164 intel_sdvo->color_range = 0;
1165 }
1166
3685a8f3 1167 if (intel_sdvo->color_range)
50f3b016 1168 pipe_config->limited_color_range = true;
3685a8f3 1169
70484559
DV		 1170 /* Clock computation needs to happen after pixel multiplier. */
1171 if (intel_sdvo->is_tv)
1172 i9xx_adjust_sdvo_tv_clock(pipe_config);
1173
e2f0ba97
JB		 1174 return true;
1175}
1176
6cc5f341 1177static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
e2f0ba97 1178{
6cc5f341 1179 struct drm_device *dev = intel_encoder->base.dev;
e2f0ba97 1180 struct drm_i915_private *dev_priv = dev->dev_private;
eeb47937 1181 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc);
6cc5f341 1182 struct drm_display_mode *adjusted_mode =
eeb47937
DV		 1183 &crtc->config.adjusted_mode;
1184 struct drm_display_mode *mode = &crtc->config.requested_mode;
8aca63aa 1185 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
6c9547ff 1186 u32 sdvox;
e2f0ba97 1187 struct intel_sdvo_in_out_map in_out;
6651819b 1188 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff 1189 int rate;
e2f0ba97
JB		 1190
1191 if (!mode)
1192 return;
1193
1194 /* First, set the input mapping for the first input to our controlled
1195 * output. This is only correct if we're a single-input device, in
1196 * which case the first input is the output from the appropriate SDVO
1197 * channel on the motherboard. In a two-input device, the first input
1198 * will be SDVOB and the second SDVOC.
1199 */
ea5b213a 1200 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1201 in_out.in1 = 0;
1202
c74696b9
PR		 1203 intel_sdvo_set_value(intel_sdvo,
1204 SDVO_CMD_SET_IN_OUT_MAP,
1205 &in_out, sizeof(in_out));
e2f0ba97 1206
6c9547ff
CW		 1207 /* Set the output timings to the screen */
1208 if (!intel_sdvo_set_target_output(intel_sdvo,
1209 intel_sdvo->attached_output))
1210 return;
e2f0ba97 1211
6651819b
DV		 1212 /* lvds has a special fixed output timing. */
1213 if (intel_sdvo->is_lvds)
1214 intel_sdvo_get_dtd_from_mode(&output_dtd,
1215 intel_sdvo->sdvo_lvds_fixed_mode);
1216 else
1217 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1218 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1219 DRM_INFO("Setting output timings on %s failed\n",
1220 SDVO_NAME(intel_sdvo));
79e53945
JB		 1221
1222 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1223 if (!intel_sdvo_set_target_input(intel_sdvo))
1224 return;
79e53945 1225
97aaf910
CW		 1226 if (intel_sdvo->has_hdmi_monitor) {
1227 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1228 intel_sdvo_set_colorimetry(intel_sdvo,
1229 SDVO_COLORIMETRY_RGB256);
abedc077 1230 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
97aaf910
CW		 1231 } else
1232 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1233
6c9547ff
CW		 1234 if (intel_sdvo->is_tv &&
1235 !intel_sdvo_set_tv_format(intel_sdvo))
1236 return;
e2f0ba97 1237
6651819b 1238 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
eeb47937 1239
e751823d
EE		 1240 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1241 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1242 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1243 DRM_INFO("Setting input timings on %s failed\n",
1244 SDVO_NAME(intel_sdvo));
79e53945 1245
eeb47937 1246 switch (crtc->config.pixel_multiplier) {
6c9547ff 1247 default:
ef1b460d 1248 WARN(1, "unknown pixel mutlipler specified\n");
32aad86f
CW		 1249 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1250 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1251 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1252 }
32aad86f
CW		 1253 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1254 return;
79e53945
JB		 1255
1256 /* Set the SDVO control regs. */
a6c45cf0 1257 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1258 /* The real mode polarity is set by the SDVO commands, using
1259 * struct intel_sdvo_dtd. */
1260 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
3685a8f3 1261 if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
e953fd7b 1262 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1263 if (INTEL_INFO(dev)->gen < 5)
1264 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1265 } else {
6c9547ff 1266 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1267 switch (intel_sdvo->sdvo_reg) {
e2debe91 1268 case GEN3_SDVOB:
e2f0ba97
JB		 1269 sdvox &= SDVOB_PRESERVE_MASK;
1270 break;
e2debe91 1271 case GEN3_SDVOC:
e2f0ba97
JB		 1272 sdvox &= SDVOC_PRESERVE_MASK;
1273 break;
1274 }
1275 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1276 }
3573c410
PZ		 1277
1278 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
eeb47937 1279 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
3573c410 1280 else
eeb47937 1281 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
3573c410 1282
da79de97 1283 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1284 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1285
a6c45cf0 1286 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1287 /* done in crtc_mode_set as the dpll_md reg must be written early */
1288 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1289 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1290 } else {
eeb47937 1291 sdvox |= (crtc->config.pixel_multiplier - 1)
6cc5f341 1292 << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1293 }
1294
6714afb1
CW		 1295 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1296 INTEL_INFO(dev)->gen < 5)
12682a97 1297 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1298 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1299}
1300
4ac41f47 1301static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1302{
4ac41f47
DV		 1303 struct intel_sdvo_connector *intel_sdvo_connector =
1304 to_intel_sdvo_connector(&connector->base);
1305 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
2f28c50b 1306 u16 active_outputs = 0;
4ac41f47
DV		 1307
1308 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1309
1310 if (active_outputs & intel_sdvo_connector->output_flag)
1311 return true;
1312 else
1313 return false;
1314}
1315
1316static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1317 enum pipe *pipe)
1318{
1319 struct drm_device *dev = encoder->base.dev;
79e53945 1320 struct drm_i915_private *dev_priv = dev->dev_private;
8aca63aa 1321 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2f28c50b 1322 u16 active_outputs = 0;
4ac41f47
DV		 1323 u32 tmp;
1324
1325 tmp = I915_READ(intel_sdvo->sdvo_reg);
7a7d1fb7 1326 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
4ac41f47 1327
7a7d1fb7 1328 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
4ac41f47
DV		 1329 return false;
1330
1331 if (HAS_PCH_CPT(dev))
1332 *pipe = PORT_TO_PIPE_CPT(tmp);
1333 else
1334 *pipe = PORT_TO_PIPE(tmp);
1335
1336 return true;
1337}
1338
045ac3b5
JB		 1339static void intel_sdvo_get_config(struct intel_encoder *encoder,
1340 struct intel_crtc_config *pipe_config)
1341{
6c49f241
DV		 1342 struct drm_device *dev = encoder->base.dev;
1343 struct drm_i915_private *dev_priv = dev->dev_private;
8aca63aa 1344 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
045ac3b5 1345 struct intel_sdvo_dtd dtd;
6c49f241 1346 int encoder_pixel_multiplier = 0;
18442d08 1347 int dotclock;
6c49f241
DV		 1348 u32 flags = 0, sdvox;
1349 u8 val;
045ac3b5
JB		 1350 bool ret;
1351
1352 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1353 if (!ret) {
bb760063
DV		 1354 /* Some sdvo encoders are not spec compliant and don't
1355 * implement the mandatory get_timings function. */
045ac3b5 1356 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
bb760063
DV		 1357 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1358 } else {
1359 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1360 flags |= DRM_MODE_FLAG_PHSYNC;
1361 else
1362 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1363
bb760063
DV		 1364 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1365 flags |= DRM_MODE_FLAG_PVSYNC;
1366 else
1367 flags |= DRM_MODE_FLAG_NVSYNC;
045ac3b5
JB		 1368 }
1369
045ac3b5 1370 pipe_config->adjusted_mode.flags |= flags;
045ac3b5 1371
fdafa9e2
DV		 1372 /*
1373 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1374 * the sdvo port register, on all other platforms it is part of the dpll
1375 * state. Since the general pipe state readout happens before the
1376 * encoder->get_config we so already have a valid pixel multplier on all
1377 * other platfroms.
1378 */
6c49f241
DV		 1379 if (IS_I915G(dev) || IS_I915GM(dev)) {
1380 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1381 pipe_config->pixel_multiplier =
1382 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1383 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1384 }
045ac3b5 1385
18442d08
VS		 1386 dotclock = pipe_config->port_clock / pipe_config->pixel_multiplier;
1387
1388 if (HAS_PCH_SPLIT(dev))
1389 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1390
241bfc38 1391 pipe_config->adjusted_mode.crtc_clock = dotclock;
18442d08 1392
6c49f241 1393 /* Cross check the port pixel multiplier with the sdvo encoder state. */
53b91408
DL		 1394 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1395 &val, 1)) {
1396 switch (val) {
1397 case SDVO_CLOCK_RATE_MULT_1X:
1398 encoder_pixel_multiplier = 1;
1399 break;
1400 case SDVO_CLOCK_RATE_MULT_2X:
1401 encoder_pixel_multiplier = 2;
1402 break;
1403 case SDVO_CLOCK_RATE_MULT_4X:
1404 encoder_pixel_multiplier = 4;
1405 break;
1406 }
6c49f241 1407 }
fdafa9e2 1408
6c49f241
DV		 1409 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1410 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1411 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
045ac3b5
JB		 1412}
1413
ce22c320
DV		 1414static void intel_disable_sdvo(struct intel_encoder *encoder)
1415{
1416 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
8aca63aa 1417 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
ce22c320
DV		 1418 u32 temp;
1419
1420 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1421 if (0)
1422 intel_sdvo_set_encoder_power_state(intel_sdvo,
1423 DRM_MODE_DPMS_OFF);
1424
1425 temp = I915_READ(intel_sdvo->sdvo_reg);
1426 if ((temp & SDVO_ENABLE) != 0) {
776ca7cf
CW		 1427 /* HW workaround for IBX, we need to move the port to
1428 * transcoder A before disabling it. */
1429 if (HAS_PCH_IBX(encoder->base.dev)) {
1430 struct drm_crtc *crtc = encoder->base.crtc;
1431 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1432
1433 if (temp & SDVO_PIPE_B_SELECT) {
1434 temp &= ~SDVO_PIPE_B_SELECT;
1435 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1436 POSTING_READ(intel_sdvo->sdvo_reg);
1437
1438 /* Again we need to write this twice. */
1439 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1440 POSTING_READ(intel_sdvo->sdvo_reg);
1441
1442 /* Transcoder selection bits only update
1443 * effectively on vblank. */
1444 if (crtc)
1445 intel_wait_for_vblank(encoder->base.dev, pipe);
1446 else
1447 msleep(50);
1448 }
1449 }
1450
ce22c320
DV		 1451 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1452 }
1453}
1454
1455static void intel_enable_sdvo(struct intel_encoder *encoder)
1456{
1457 struct drm_device *dev = encoder->base.dev;
1458 struct drm_i915_private *dev_priv = dev->dev_private;
8aca63aa 1459 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
ce22c320 1460 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 1461 u32 temp;
ce22c320
DV		 1462 bool input1, input2;
1463 int i;
d0a7b6de 1464 bool success;
ce22c320
DV		 1465
1466 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf
CW		 1467 if ((temp & SDVO_ENABLE) == 0) {
1468 /* HW workaround for IBX, we need to move the port
dc0fa718
PZ		 1469 * to transcoder A before disabling it, so restore it here. */
1470 if (HAS_PCH_IBX(dev))
1471 temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
776ca7cf 1472
ce22c320 1473 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
776ca7cf 1474 }
ce22c320
DV		 1475 for (i = 0; i < 2; i++)
1476 intel_wait_for_vblank(dev, intel_crtc->pipe);
1477
d0a7b6de 1478 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
ce22c320
DV		 1479 /* Warn if the device reported failure to sync.
1480 * A lot of SDVO devices fail to notify of sync, but it's
1481 * a given it the status is a success, we succeeded.
1482 */
d0a7b6de 1483 if (success && !input1) {
ce22c320
DV		 1484 DRM_DEBUG_KMS("First %s output reported failure to "
1485 "sync\n", SDVO_NAME(intel_sdvo));
1486 }
1487
1488 if (0)
1489 intel_sdvo_set_encoder_power_state(intel_sdvo,
1490 DRM_MODE_DPMS_ON);
1491 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1492}
1493
6b1c087b 1494/* Special dpms function to support cloning between dvo/sdvo/crt. */
b2cabb0e 1495static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
79e53945 1496{
b2cabb0e
DV		 1497 struct drm_crtc *crtc;
1498 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1499
1500 /* dvo supports only 2 dpms states. */
1501 if (mode != DRM_MODE_DPMS_ON)
1502 mode = DRM_MODE_DPMS_OFF;
1503
1504 if (mode == connector->dpms)
1505 return;
1506
1507 connector->dpms = mode;
1508
1509 /* Only need to change hw state when actually enabled */
1510 crtc = intel_sdvo->base.base.crtc;
1511 if (!crtc) {
1512 intel_sdvo->base.connectors_active = false;
1513 return;
1514 }
79e53945 1515
6b1c087b
JN		 1516 /* We set active outputs manually below in case pipe dpms doesn't change
1517 * due to cloning. */
79e53945 1518 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1519 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1520 if (0)
ea5b213a 1521 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945 1522
b2cabb0e
DV		 1523 intel_sdvo->base.connectors_active = false;
1524
1525 intel_crtc_update_dpms(crtc);
79e53945 1526 } else {
b2cabb0e
DV		 1527 intel_sdvo->base.connectors_active = true;
1528
1529 intel_crtc_update_dpms(crtc);
79e53945
JB		 1530
1531 if (0)
ea5b213a
CW		 1532 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1533 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945 1534 }
0a91ca29 1535
b980514c 1536 intel_modeset_check_state(connector->dev);
79e53945
JB		 1537}
1538
c19de8eb
DL		 1539static enum drm_mode_status
1540intel_sdvo_mode_valid(struct drm_connector *connector,
1541 struct drm_display_mode *mode)
79e53945 1542{
df0e9248 1543 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1544
1545 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1546 return MODE_NO_DBLESCAN;
1547
ea5b213a 1548 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1549 return MODE_CLOCK_LOW;
1550
ea5b213a 1551 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1552 return MODE_CLOCK_HIGH;
1553
8545423a 1554 if (intel_sdvo->is_lvds) {
ea5b213a 1555 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1556 return MODE_PANEL;
1557
ea5b213a 1558 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1559 return MODE_PANEL;
1560 }
1561
79e53945
JB		 1562 return MODE_OK;
1563}
1564
ea5b213a 1565static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1566{
1a3665c8 1567 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1568 if (!intel_sdvo_get_value(intel_sdvo,
1569 SDVO_CMD_GET_DEVICE_CAPS,
1570 caps, sizeof(*caps)))
1571 return false;
1572
1573 DRM_DEBUG_KMS("SDVO capabilities:\n"
1574 " vendor_id: %d\n"
1575 " device_id: %d\n"
1576 " device_rev_id: %d\n"
1577 " sdvo_version_major: %d\n"
1578 " sdvo_version_minor: %d\n"
1579 " sdvo_inputs_mask: %d\n"
1580 " smooth_scaling: %d\n"
1581 " sharp_scaling: %d\n"
1582 " up_scaling: %d\n"
1583 " down_scaling: %d\n"
1584 " stall_support: %d\n"
1585 " output_flags: %d\n",
1586 caps->vendor_id,
1587 caps->device_id,
1588 caps->device_rev_id,
1589 caps->sdvo_version_major,
1590 caps->sdvo_version_minor,
1591 caps->sdvo_inputs_mask,
1592 caps->smooth_scaling,
1593 caps->sharp_scaling,
1594 caps->up_scaling,
1595 caps->down_scaling,
1596 caps->stall_support,
1597 caps->output_flags);
1598
1599 return true;
79e53945
JB		 1600}
1601
5fa7ac9c 1602static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1603{
768b107e 1604 struct drm_device *dev = intel_sdvo->base.base.dev;
5fa7ac9c 1605 uint16_t hotplug;
79e53945 1606
768b107e
DV		 1607 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1608 * on the line. */
1609 if (IS_I945G(dev) || IS_I945GM(dev))
5fa7ac9c 1610 return 0;
768b107e 1611
5fa7ac9c
JN		 1612 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1613 &hotplug, sizeof(hotplug)))
1614 return 0;
768b107e 1615
5fa7ac9c 1616 return hotplug;
79e53945
JB		 1617}
1618
cc68c81a 1619static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1620{
8aca63aa 1621 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
79e53945 1622
5fa7ac9c
JN		 1623 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1624 &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1625}
1626
fb7a46f3 1627static bool
ea5b213a 1628intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1629{
bc65212c 1630 /* Is there more than one type of output? */
2294488d 1631 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1632}
1633
f899fc64 1634static struct edid *
e957d772 1635intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1636{
e957d772
CW		 1637 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1638 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1639}
1640
ff482d83
CW		 1641/* Mac mini hack -- use the same DDC as the analog connector */
1642static struct edid *
1643intel_sdvo_get_analog_edid(struct drm_connector *connector)
1644{
f899fc64 1645 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1646
0c1dab89 1647 return drm_get_edid(connector,
3bd7d909 1648 intel_gmbus_get_adapter(dev_priv,
41aa3448 1649 dev_priv->vbt.crt_ddc_pin));
ff482d83
CW		 1650}
1651
c43b5634 1652static enum drm_connector_status
8bf38485 1653intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1654{
df0e9248 1655 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1656 enum drm_connector_status status;
1657 struct edid *edid;
9dff6af8 1658
e957d772 1659 edid = intel_sdvo_get_edid(connector);
57cdaf90 1660
ea5b213a 1661 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1662 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1663
7c3f0a27
ZY		 1664 /*
1665 * Don't use the 1 as the argument of DDC bus switch to get
1666 * the EDID. It is used for SDVO SPD ROM.
1667 */
9d1a903d 1668 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1669 intel_sdvo->ddc_bus = ddc;
1670 edid = intel_sdvo_get_edid(connector);
1671 if (edid)
7c3f0a27 1672 break;
7c3f0a27 1673 }
e957d772
CW		 1674 /*
1675 * If we found the EDID on the other bus,
1676 * assume that is the correct DDC bus.
1677 */
1678 if (edid == NULL)
1679 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1680 }
9d1a903d
CW		 1681
1682 /*
1683 * When there is no edid and no monitor is connected with VGA
1684 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1685 */
ff482d83
CW		 1686 if (edid == NULL)
1687 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1688
2f551c84 1689 status = connector_status_unknown;
9dff6af8 1690 if (edid != NULL) {
149c36a3 1691 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1692 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1693 status = connector_status_connected;
da79de97
CW		 1694 if (intel_sdvo->is_hdmi) {
1695 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1696 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
abedc077
VS		 1697 intel_sdvo->rgb_quant_range_selectable =
1698 drm_rgb_quant_range_selectable(edid);
da79de97 1699 }
13946743
CW		 1700 } else
1701 status = connector_status_disconnected;
9d1a903d
CW		 1702 kfree(edid);
1703 }
7f36e7ed
CW		 1704
1705 if (status == connector_status_connected) {
1706 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1707 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1708 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1709 }
1710
2b8d33f7 1711 return status;
9dff6af8
ML		 1712}
1713
52220085
CW		 1714static bool
1715intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1716 struct edid *edid)
1717{
1718 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1719 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1720
1721 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1722 connector_is_digital, monitor_is_digital);
1723 return connector_is_digital == monitor_is_digital;
1724}
1725
7b334fcb 1726static enum drm_connector_status
930a9e28 1727intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1728{
fb7a46f3 1729 uint16_t response;
df0e9248 1730 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1731 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1732 enum drm_connector_status ret;
79e53945 1733
164c8598
CW		 1734 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1735 connector->base.id, drm_get_connector_name(connector));
1736
fc37381c
CW		 1737 if (!intel_sdvo_get_value(intel_sdvo,
1738 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1739 &response, 2))
32aad86f 1740 return connector_status_unknown;
79e53945 1741
e957d772
CW		 1742 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1743 response & 0xff, response >> 8,
1744 intel_sdvo_connector->output_flag);
e2f0ba97 1745
fb7a46f3 1746 if (response == 0)
79e53945 1747 return connector_status_disconnected;
fb7a46f3 1748
ea5b213a 1749 intel_sdvo->attached_output = response;
14571b4c 1750
97aaf910
CW		 1751 intel_sdvo->has_hdmi_monitor = false;
1752 intel_sdvo->has_hdmi_audio = false;
abedc077 1753 intel_sdvo->rgb_quant_range_selectable = false;
97aaf910 1754
615fb93f 1755 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1756 ret = connector_status_disconnected;
13946743 1757 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1758 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1759 else {
1760 struct edid *edid;
1761
1762 /* if we have an edid check it matches the connection */
1763 edid = intel_sdvo_get_edid(connector);
1764 if (edid == NULL)
1765 edid = intel_sdvo_get_analog_edid(connector);
1766 if (edid != NULL) {
52220085
CW		 1767 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1768 edid))
13946743 1769 ret = connector_status_connected;
52220085
CW		 1770 else
1771 ret = connector_status_disconnected;
1772
13946743
CW		 1773 kfree(edid);
1774 } else
1775 ret = connector_status_connected;
1776 }
14571b4c
ZW		 1777
1778 /* May update encoder flag for like clock for SDVO TV, etc.*/
1779 if (ret == connector_status_connected) {
ea5b213a
CW		 1780 intel_sdvo->is_tv = false;
1781 intel_sdvo->is_lvds = false;
14571b4c 1782
09ede541 1783 if (response & SDVO_TV_MASK)
ea5b213a 1784 intel_sdvo->is_tv = true;
14571b4c 1785 if (response & SDVO_LVDS_MASK)
8545423a 1786 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1787 }
14571b4c
ZW		 1788
1789 return ret;
79e53945
JB		 1790}
1791
e2f0ba97 1792static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1793{
ff482d83 1794 struct edid *edid;
79e53945 1795
46a3f4a3
CW		 1796 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1797 connector->base.id, drm_get_connector_name(connector));
1798
79e53945 1799 /* set the bus switch and get the modes */
e957d772 1800 edid = intel_sdvo_get_edid(connector);
79e53945 1801
57cdaf90
KP		 1802 /*
1803 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1804 * link between analog and digital outputs. So, if the regular SDVO
1805 * DDC fails, check to see if the analog output is disconnected, in
1806 * which case we'll look there for the digital DDC data.
e2f0ba97 1807 */
f899fc64
CW		 1808 if (edid == NULL)
1809 edid = intel_sdvo_get_analog_edid(connector);
1810
ff482d83 1811 if (edid != NULL) {
52220085
CW		 1812 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1813 edid)) {
0c1dab89
CW		 1814 drm_mode_connector_update_edid_property(connector, edid);
1815 drm_add_edid_modes(connector, edid);
1816 }
13946743 1817
ff482d83 1818 kfree(edid);
e2f0ba97 1819 }
e2f0ba97
JB		 1820}
1821
1822/*
1823 * Set of SDVO TV modes.
1824 * Note! This is in reply order (see loop in get_tv_modes).
1825 * XXX: all 60Hz refresh?
1826 */
b1f559ec 1827static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1828 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1829 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1830 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1831 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1832 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1833 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1834 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1835 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1837 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1838 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1840 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1841 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1843 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1844 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1845 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1846 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1847 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1848 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1849 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1850 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1851 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1852 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1853 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1854 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1855 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1856 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1857 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1858 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1859 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1860 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1861 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1862 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1863 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1864 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1865 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1866 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1867 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1868 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1869 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1870 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1871 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1872 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1873 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1874 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1875 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1876 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1877 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1878 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1879 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1880 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1881 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1882 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1883 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1884 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1885};
1886
1887static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1888{
df0e9248 1889 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1890 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1891 uint32_t reply = 0, format_map = 0;
1892 int i;
e2f0ba97 1893
46a3f4a3
CW		 1894 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1895 connector->base.id, drm_get_connector_name(connector));
1896
e2f0ba97
JB		 1897 /* Read the list of supported input resolutions for the selected TV
1898 * format.
1899 */
40039750 1900 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1901 memcpy(&tv_res, &format_map,
32aad86f 1902 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1903
32aad86f
CW		 1904 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1905 return;
ce6feabd 1906
32aad86f 1907 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1908 if (!intel_sdvo_write_cmd(intel_sdvo,
1909 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1910 &tv_res, sizeof(tv_res)))
1911 return;
1912 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1913 return;
1914
1915 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1916 if (reply & (1 << i)) {
1917 struct drm_display_mode *nmode;
1918 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1919 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1920 if (nmode)
1921 drm_mode_probed_add(connector, nmode);
1922 }
e2f0ba97
JB		 1923}
1924
7086c87f
ML		 1925static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1926{
df0e9248 1927 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1928 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1929 struct drm_display_mode *newmode;
7086c87f 1930
46a3f4a3
CW		 1931 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1932 connector->base.id, drm_get_connector_name(connector));
1933
7086c87f 1934 /*
c3456fb3 1935 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
4300a0f8 1936 * SDVO->LVDS transcoders can't cope with the EDID mode.
7086c87f 1937 */
41aa3448 1938 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
7086c87f 1939 newmode = drm_mode_duplicate(connector->dev,
41aa3448 1940 dev_priv->vbt.sdvo_lvds_vbt_mode);
7086c87f
ML		 1941 if (newmode != NULL) {
1942 /* Guarantee the mode is preferred */
1943 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1944 DRM_MODE_TYPE_DRIVER);
1945 drm_mode_probed_add(connector, newmode);
1946 }
1947 }
12682a97 1948
4300a0f8
DA		 1949 /*
1950 * Attempt to get the mode list from DDC.
1951 * Assume that the preferred modes are
1952 * arranged in priority order.
1953 */
1954 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
1955
12682a97 1956 list_for_each_entry(newmode, &connector->probed_modes, head) {
1957 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1958 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1959 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1960
8545423a 1961 intel_sdvo->is_lvds = true;
12682a97 1962 break;
1963 }
1964 }
7086c87f
ML		 1965}
1966
e2f0ba97
JB		 1967static int intel_sdvo_get_modes(struct drm_connector *connector)
1968{
615fb93f 1969 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1970
615fb93f 1971 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1972 intel_sdvo_get_tv_modes(connector);
615fb93f 1973 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1974 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1975 else
1976 intel_sdvo_get_ddc_modes(connector);
1977
32aad86f 1978 return !list_empty(&connector->probed_modes);
79e53945
JB		 1979}
1980
fcc8d672
CW		 1981static void
1982intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1983{
615fb93f 1984 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1985 struct drm_device *dev = connector->dev;
1986
c5521706
CW		 1987 if (intel_sdvo_connector->left)
1988 drm_property_destroy(dev, intel_sdvo_connector->left);
1989 if (intel_sdvo_connector->right)
1990 drm_property_destroy(dev, intel_sdvo_connector->right);
1991 if (intel_sdvo_connector->top)
1992 drm_property_destroy(dev, intel_sdvo_connector->top);
1993 if (intel_sdvo_connector->bottom)
1994 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1995 if (intel_sdvo_connector->hpos)
1996 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1997 if (intel_sdvo_connector->vpos)
1998 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1999 if (intel_sdvo_connector->saturation)
2000 drm_property_destroy(dev, intel_sdvo_connector->saturation);
2001 if (intel_sdvo_connector->contrast)
2002 drm_property_destroy(dev, intel_sdvo_connector->contrast);
2003 if (intel_sdvo_connector->hue)
2004 drm_property_destroy(dev, intel_sdvo_connector->hue);
2005 if (intel_sdvo_connector->sharpness)
2006 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
2007 if (intel_sdvo_connector->flicker_filter)
2008 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
2009 if (intel_sdvo_connector->flicker_filter_2d)
2010 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
2011 if (intel_sdvo_connector->flicker_filter_adaptive)
2012 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
2013 if (intel_sdvo_connector->tv_luma_filter)
2014 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
2015 if (intel_sdvo_connector->tv_chroma_filter)
2016 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 2017 if (intel_sdvo_connector->dot_crawl)
2018 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 2019 if (intel_sdvo_connector->brightness)
2020 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 2021}
2022
79e53945
JB		 2023static void intel_sdvo_destroy(struct drm_connector *connector)
2024{
615fb93f 2025 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 2026
c5521706 2027 if (intel_sdvo_connector->tv_format)
ce6feabd 2028 drm_property_destroy(connector->dev,
c5521706 2029 intel_sdvo_connector->tv_format);
b9219c5e 2030
d2a82a6f 2031 intel_sdvo_destroy_enhance_property(connector);
79e53945 2032 drm_connector_cleanup(connector);
4b745b1e 2033 kfree(intel_sdvo_connector);
79e53945
JB		 2034}
2035
1aad7ac0
CW		 2036static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
2037{
2038 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
2039 struct edid *edid;
2040 bool has_audio = false;
2041
2042 if (!intel_sdvo->is_hdmi)
2043 return false;
2044
2045 edid = intel_sdvo_get_edid(connector);
2046 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
2047 has_audio = drm_detect_monitor_audio(edid);
38ab8a20 2048 kfree(edid);
1aad7ac0
CW		 2049
2050 return has_audio;
2051}
2052
ce6feabd
ZY		 2053static int
2054intel_sdvo_set_property(struct drm_connector *connector,
2055 struct drm_property *property,
2056 uint64_t val)
2057{
df0e9248 2058 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 2059 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 2060 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 2061 uint16_t temp_value;
32aad86f
CW		 2062 uint8_t cmd;
2063 int ret;
ce6feabd 2064
662595df 2065 ret = drm_object_property_set_value(&connector->base, property, val);
32aad86f
CW		 2066 if (ret)
2067 return ret;
ce6feabd 2068
3f43c48d 2069 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2070 int i = val;
2071 bool has_audio;
2072
2073 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 2074 return 0;
2075
1aad7ac0 2076 intel_sdvo_connector->force_audio = i;
7f36e7ed 2077
c3e5f67b 2078 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2079 has_audio = intel_sdvo_detect_hdmi_audio(connector);
2080 else
c3e5f67b 2081 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 2082
1aad7ac0 2083 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 2084 return 0;
7f36e7ed 2085
1aad7ac0 2086 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 2087 goto done;
2088 }
2089
e953fd7b 2090 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 2091 bool old_auto = intel_sdvo->color_range_auto;
2092 uint32_t old_range = intel_sdvo->color_range;
2093
55bc60db
VS		 2094 switch (val) {
2095 case INTEL_BROADCAST_RGB_AUTO:
2096 intel_sdvo->color_range_auto = true;
2097 break;
2098 case INTEL_BROADCAST_RGB_FULL:
2099 intel_sdvo->color_range_auto = false;
2100 intel_sdvo->color_range = 0;
2101 break;
2102 case INTEL_BROADCAST_RGB_LIMITED:
2103 intel_sdvo->color_range_auto = false;
4f3a8bc7
PZ		 2104 /* FIXME: this bit is only valid when using TMDS
2105 * encoding and 8 bit per color mode. */
2106 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 2107 break;
2108 default:
2109 return -EINVAL;
2110 }
ae4edb80
DV		 2111
2112 if (old_auto == intel_sdvo->color_range_auto &&
2113 old_range == intel_sdvo->color_range)
2114 return 0;
2115
7f36e7ed
CW		 2116 goto done;
2117 }
2118
c5521706
CW		 2119#define CHECK_PROPERTY(name, NAME) \
2120 if (intel_sdvo_connector->name == property) { \
2121 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
2122 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
2123 cmd = SDVO_CMD_SET_##NAME; \
2124 intel_sdvo_connector->cur_##name = temp_value; \
2125 goto set_value; \
2126 }
2127
2128 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 2129 if (val >= TV_FORMAT_NUM)
2130 return -EINVAL;
2131
40039750 2132 if (intel_sdvo->tv_format_index ==
615fb93f 2133 intel_sdvo_connector->tv_format_supported[val])
32aad86f 2134 return 0;
ce6feabd 2135
40039750 2136 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 2137 goto done;
32aad86f 2138 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 2139 temp_value = val;
c5521706 2140 if (intel_sdvo_connector->left == property) {
662595df 2141 drm_object_property_set_value(&connector->base,
c5521706 2142 intel_sdvo_connector->right, val);
615fb93f 2143 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 2144 return 0;
b9219c5e 2145
615fb93f
CW		 2146 intel_sdvo_connector->left_margin = temp_value;
2147 intel_sdvo_connector->right_margin = temp_value;
2148 temp_value = intel_sdvo_connector->max_hscan -
c5521706 2149 intel_sdvo_connector->left_margin;
b9219c5e 2150 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2151 goto set_value;
2152 } else if (intel_sdvo_connector->right == property) {
662595df 2153 drm_object_property_set_value(&connector->base,
c5521706 2154 intel_sdvo_connector->left, val);
615fb93f 2155 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 2156 return 0;
b9219c5e 2157
615fb93f
CW		 2158 intel_sdvo_connector->left_margin = temp_value;
2159 intel_sdvo_connector->right_margin = temp_value;
2160 temp_value = intel_sdvo_connector->max_hscan -
2161 intel_sdvo_connector->left_margin;
b9219c5e 2162 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2163 goto set_value;
2164 } else if (intel_sdvo_connector->top == property) {
662595df 2165 drm_object_property_set_value(&connector->base,
c5521706 2166 intel_sdvo_connector->bottom, val);
615fb93f 2167 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 2168 return 0;
b9219c5e 2169
615fb93f
CW		 2170 intel_sdvo_connector->top_margin = temp_value;
2171 intel_sdvo_connector->bottom_margin = temp_value;
2172 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2173 intel_sdvo_connector->top_margin;
b9219c5e 2174 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2175 goto set_value;
2176 } else if (intel_sdvo_connector->bottom == property) {
662595df 2177 drm_object_property_set_value(&connector->base,
c5521706 2178 intel_sdvo_connector->top, val);
615fb93f 2179 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 2180 return 0;
2181
615fb93f
CW		 2182 intel_sdvo_connector->top_margin = temp_value;
2183 intel_sdvo_connector->bottom_margin = temp_value;
2184 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2185 intel_sdvo_connector->top_margin;
b9219c5e 2186 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2187 goto set_value;
2188 }
2189 CHECK_PROPERTY(hpos, HPOS)
2190 CHECK_PROPERTY(vpos, VPOS)
2191 CHECK_PROPERTY(saturation, SATURATION)
2192 CHECK_PROPERTY(contrast, CONTRAST)
2193 CHECK_PROPERTY(hue, HUE)
2194 CHECK_PROPERTY(brightness, BRIGHTNESS)
2195 CHECK_PROPERTY(sharpness, SHARPNESS)
2196 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
2197 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
2198 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
2199 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
2200 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 2201 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 2202 }
b9219c5e 2203
c5521706 2204 return -EINVAL; /* unknown property */
b9219c5e 2205
c5521706
CW		 2206set_value:
2207 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
2208 return -EIO;
b9219c5e 2209
b9219c5e 2210
c5521706 2211done:
c0c36b94
CW		 2212 if (intel_sdvo->base.base.crtc)
2213 intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
c5521706 2214
32aad86f 2215 return 0;
c5521706 2216#undef CHECK_PROPERTY
ce6feabd
ZY		 2217}
2218
79e53945 2219static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
b2cabb0e 2220 .dpms = intel_sdvo_dpms,
79e53945
JB		 2221 .detect = intel_sdvo_detect,
2222 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 2223 .set_property = intel_sdvo_set_property,
79e53945
JB		 2224 .destroy = intel_sdvo_destroy,
2225};
2226
2227static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2228 .get_modes = intel_sdvo_get_modes,
2229 .mode_valid = intel_sdvo_mode_valid,
df0e9248 2230 .best_encoder = intel_best_encoder,
79e53945
JB		 2231};
2232
b358d0a6 2233static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2234{
8aca63aa 2235 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
d2a82a6f 2236
ea5b213a 2237 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2238 drm_mode_destroy(encoder->dev,
ea5b213a 2239 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2240
e957d772 2241 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2242 intel_encoder_destroy(encoder);
79e53945
JB		 2243}
2244
2245static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2246 .destroy = intel_sdvo_enc_destroy,
2247};
2248
b66d8424
CW		 2249static void
2250intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2251{
2252 uint16_t mask = 0;
2253 unsigned int num_bits;
2254
2255 /* Make a mask of outputs less than or equal to our own priority in the
2256 * list.
2257 */
2258 switch (sdvo->controlled_output) {
2259 case SDVO_OUTPUT_LVDS1:
2260 mask |= SDVO_OUTPUT_LVDS1;
2261 case SDVO_OUTPUT_LVDS0:
2262 mask |= SDVO_OUTPUT_LVDS0;
2263 case SDVO_OUTPUT_TMDS1:
2264 mask |= SDVO_OUTPUT_TMDS1;
2265 case SDVO_OUTPUT_TMDS0:
2266 mask |= SDVO_OUTPUT_TMDS0;
2267 case SDVO_OUTPUT_RGB1:
2268 mask |= SDVO_OUTPUT_RGB1;
2269 case SDVO_OUTPUT_RGB0:
2270 mask |= SDVO_OUTPUT_RGB0;
2271 break;
2272 }
2273
2274 /* Count bits to find what number we are in the priority list. */
2275 mask &= sdvo->caps.output_flags;
2276 num_bits = hweight16(mask);
2277 /* If more than 3 outputs, default to DDC bus 3 for now. */
2278 if (num_bits > 3)
2279 num_bits = 3;
2280
2281 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2282 sdvo->ddc_bus = 1 << num_bits;
2283}
79e53945 2284
e2f0ba97
JB		 2285/**
2286 * Choose the appropriate DDC bus for control bus switch command for this
2287 * SDVO output based on the controlled output.
2288 *
2289 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2290 * outputs, then LVDS outputs.
2291 */
2292static void
b1083333 2293intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 2294 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 2295{
b1083333 2296 struct sdvo_device_mapping *mapping;
e2f0ba97 2297
eef4eacb 2298 if (sdvo->is_sdvob)
b1083333
AJ		 2299 mapping = &(dev_priv->sdvo_mappings[0]);
2300 else
2301 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 2302
b66d8424
CW		 2303 if (mapping->initialized)
2304 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2305 else
2306 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2307}
2308
e957d772
CW		 2309static void
2310intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2311 struct intel_sdvo *sdvo, u32 reg)
2312{
2313 struct sdvo_device_mapping *mapping;
46eb3036 2314 u8 pin;
e957d772 2315
eef4eacb 2316 if (sdvo->is_sdvob)
e957d772
CW		 2317 mapping = &dev_priv->sdvo_mappings[0];
2318 else
2319 mapping = &dev_priv->sdvo_mappings[1];
2320
6cb1612a 2321 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
e957d772 2322 pin = mapping->i2c_pin;
6cb1612a
JN		 2323 else
2324 pin = GMBUS_PORT_DPB;
e957d772 2325
6cb1612a
JN		 2326 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2327
2328 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2329 * our code totally fails once we start using gmbus. Hence fall back to
2330 * bit banging for now. */
2331 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2332}
2333
fbfcc4f3
JN		 2334/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2335static void
2336intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2337{
2338 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2339}
2340
e2f0ba97 2341static bool
e27d8538 2342intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2343{
97aaf910 2344 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2345}
2346
714605e4 2347static u8
eef4eacb 2348intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 2349{
2350 struct drm_i915_private *dev_priv = dev->dev_private;
2351 struct sdvo_device_mapping *my_mapping, *other_mapping;
2352
eef4eacb 2353 if (sdvo->is_sdvob) {
714605e4 2354 my_mapping = &dev_priv->sdvo_mappings[0];
2355 other_mapping = &dev_priv->sdvo_mappings[1];
2356 } else {
2357 my_mapping = &dev_priv->sdvo_mappings[1];
2358 other_mapping = &dev_priv->sdvo_mappings[0];
2359 }
2360
2361 /* If the BIOS described our SDVO device, take advantage of it. */
2362 if (my_mapping->slave_addr)
2363 return my_mapping->slave_addr;
2364
2365 /* If the BIOS only described a different SDVO device, use the
2366 * address that it isn't using.
2367 */
2368 if (other_mapping->slave_addr) {
2369 if (other_mapping->slave_addr == 0x70)
2370 return 0x72;
2371 else
2372 return 0x70;
2373 }
2374
2375 /* No SDVO device info is found for another DVO port,
2376 * so use mapping assumption we had before BIOS parsing.
2377 */
eef4eacb 2378 if (sdvo->is_sdvob)
714605e4 2379 return 0x70;
2380 else
2381 return 0x72;
2382}
2383
931c1c26
ID		 2384static void
2385intel_sdvo_connector_unregister(struct intel_connector *intel_connector)
2386{
2387 struct drm_connector *drm_connector;
2388 struct intel_sdvo *sdvo_encoder;
2389
2390 drm_connector = &intel_connector->base;
2391 sdvo_encoder = intel_attached_sdvo(&intel_connector->base);
2392
2393 sysfs_remove_link(&drm_connector->kdev->kobj,
2394 sdvo_encoder->ddc.dev.kobj.name);
2395 intel_connector_unregister(intel_connector);
2396}
2397
c393454d 2398static int
df0e9248
CW		 2399intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2400 struct intel_sdvo *encoder)
14571b4c 2401{
c393454d
ID		 2402 struct drm_connector *drm_connector;
2403 int ret;
2404
2405 drm_connector = &connector->base.base;
2406 ret = drm_connector_init(encoder->base.base.dev,
2407 drm_connector,
df0e9248
CW		 2408 &intel_sdvo_connector_funcs,
2409 connector->base.base.connector_type);
c393454d
ID		 2410 if (ret < 0)
2411 return ret;
6070a4a9 2412
c393454d 2413 drm_connector_helper_add(drm_connector,
df0e9248 2414 &intel_sdvo_connector_helper_funcs);
14571b4c 2415
8f4839e2 2416 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2417 connector->base.base.doublescan_allowed = 0;
2418 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2419 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
931c1c26 2420 connector->base.unregister = intel_sdvo_connector_unregister;
14571b4c 2421
df0e9248 2422 intel_connector_attach_encoder(&connector->base, &encoder->base);
c393454d
ID		 2423 ret = drm_sysfs_connector_add(drm_connector);
2424 if (ret < 0)
2425 goto err1;
2426
4d43e9bd
EE		 2427 ret = sysfs_create_link(&drm_connector->kdev->kobj,
2428 &encoder->ddc.dev.kobj,
931c1c26
ID		 2429 encoder->ddc.dev.kobj.name);
2430 if (ret < 0)
2431 goto err2;
2432
c393454d
ID		 2433 return 0;
2434
931c1c26
ID		 2435err2:
2436 drm_sysfs_connector_remove(drm_connector);
c393454d
ID		 2437err1:
2438 drm_connector_cleanup(drm_connector);
2439
2440 return ret;
14571b4c 2441}
6070a4a9 2442
7f36e7ed 2443static void
55bc60db
VS		 2444intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2445 struct intel_sdvo_connector *connector)
7f36e7ed
CW		 2446{
2447 struct drm_device *dev = connector->base.base.dev;
2448
3f43c48d 2449 intel_attach_force_audio_property(&connector->base.base);
55bc60db 2450 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
e953fd7b 2451 intel_attach_broadcast_rgb_property(&connector->base.base);
55bc60db
VS		 2452 intel_sdvo->color_range_auto = true;
2453 }
7f36e7ed
CW		 2454}
2455
fb7a46f3 2456static bool
ea5b213a 2457intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2458{
4ef69c7a 2459 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2460 struct drm_connector *connector;
cc68c81a 2461 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2462 struct intel_connector *intel_connector;
615fb93f 2463 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2464
46a3f4a3
CW		 2465 DRM_DEBUG_KMS("initialising DVI device %d\n", device);
2466
b14c5679 2467 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
615fb93f 2468 if (!intel_sdvo_connector)
14571b4c
ZW		 2469 return false;
2470
14571b4c 2471 if (device == 0) {
ea5b213a 2472 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2473 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2474 } else if (device == 1) {
ea5b213a 2475 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2476 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2477 }
2478
615fb93f 2479 intel_connector = &intel_sdvo_connector->base;
14571b4c 2480 connector = &intel_connector->base;
5fa7ac9c
JN		 2481 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2482 intel_sdvo_connector->output_flag) {
5fa7ac9c 2483 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
cc68c81a
SF		 2484 /* Some SDVO devices have one-shot hotplug interrupts.
2485 * Ensure that they get re-enabled when an interrupt happens.
2486 */
2487 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2488 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2489 } else {
821450c6 2490 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2491 }
14571b4c
ZW		 2492 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2493 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2494
e27d8538 2495 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2496 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2497 intel_sdvo->is_hdmi = true;
14571b4c 2498 }
14571b4c 2499
c393454d
ID		 2500 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2501 kfree(intel_sdvo_connector);
2502 return false;
2503 }
2504
f797d221 2505 if (intel_sdvo->is_hdmi)
55bc60db 2506 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
14571b4c
ZW		 2507
2508 return true;
2509}
2510
2511static bool
ea5b213a 2512intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2513{
4ef69c7a
CW		 2514 struct drm_encoder *encoder = &intel_sdvo->base.base;
2515 struct drm_connector *connector;
2516 struct intel_connector *intel_connector;
2517 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2518
46a3f4a3
CW		 2519 DRM_DEBUG_KMS("initialising TV type %d\n", type);
2520
b14c5679 2521 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
615fb93f
CW		 2522 if (!intel_sdvo_connector)
2523 return false;
14571b4c 2524
615fb93f 2525 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2526 connector = &intel_connector->base;
2527 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2528 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2529
4ef69c7a
CW		 2530 intel_sdvo->controlled_output |= type;
2531 intel_sdvo_connector->output_flag = type;
14571b4c 2532
4ef69c7a 2533 intel_sdvo->is_tv = true;
14571b4c 2534
c393454d
ID		 2535 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2536 kfree(intel_sdvo_connector);
2537 return false;
2538 }
14571b4c 2539
4ef69c7a 2540 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2541 goto err;
14571b4c 2542
4ef69c7a 2543 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2544 goto err;
14571b4c 2545
4ef69c7a 2546 return true;
32aad86f
CW		 2547
2548err:
d9255d57 2549 drm_sysfs_connector_remove(connector);
123d5c01 2550 intel_sdvo_destroy(connector);
32aad86f 2551 return false;
14571b4c
ZW		 2552}
2553
2554static bool
ea5b213a 2555intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2556{
4ef69c7a
CW		 2557 struct drm_encoder *encoder = &intel_sdvo->base.base;
2558 struct drm_connector *connector;
2559 struct intel_connector *intel_connector;
2560 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2561
46a3f4a3
CW		 2562 DRM_DEBUG_KMS("initialising analog device %d\n", device);
2563
b14c5679 2564 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
615fb93f
CW		 2565 if (!intel_sdvo_connector)
2566 return false;
14571b4c 2567
615fb93f 2568 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2569 connector = &intel_connector->base;
821450c6 2570 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2571 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2572 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2573
2574 if (device == 0) {
2575 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2576 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2577 } else if (device == 1) {
2578 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2579 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2580 }
2581
c393454d
ID		 2582 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2583 kfree(intel_sdvo_connector);
2584 return false;
2585 }
2586
4ef69c7a 2587 return true;
14571b4c
ZW		 2588}
2589
2590static bool
ea5b213a 2591intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2592{
4ef69c7a
CW		 2593 struct drm_encoder *encoder = &intel_sdvo->base.base;
2594 struct drm_connector *connector;
2595 struct intel_connector *intel_connector;
2596 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2597
46a3f4a3
CW		 2598 DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
2599
b14c5679 2600 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
615fb93f
CW		 2601 if (!intel_sdvo_connector)
2602 return false;
14571b4c 2603
615fb93f
CW		 2604 intel_connector = &intel_sdvo_connector->base;
2605 connector = &intel_connector->base;
4ef69c7a
CW		 2606 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2607 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2608
2609 if (device == 0) {
2610 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2611 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2612 } else if (device == 1) {
2613 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2614 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2615 }
2616
c393454d
ID		 2617 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2618 kfree(intel_sdvo_connector);
2619 return false;
2620 }
2621
4ef69c7a 2622 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2623 goto err;
2624
2625 return true;
2626
2627err:
d9255d57 2628 drm_sysfs_connector_remove(connector);
123d5c01 2629 intel_sdvo_destroy(connector);
32aad86f 2630 return false;
14571b4c
ZW		 2631}
2632
2633static bool
ea5b213a 2634intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2635{
ea5b213a 2636 intel_sdvo->is_tv = false;
ea5b213a 2637 intel_sdvo->is_lvds = false;
fb7a46f3 2638
14571b4c 2639 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2640
14571b4c 2641 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2642 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2643 return false;
2644
2645 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2646 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2647 return false;
2648
2649 /* TV has no XXX1 function block */
a1f4b7ff 2650 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2651 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2652 return false;
2653
2654 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2655 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2656 return false;
fb7a46f3 2657
a0b1c7a5
CW		 2658 if (flags & SDVO_OUTPUT_YPRPB0)
2659 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2660 return false;
2661
14571b4c 2662 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2663 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2664 return false;
2665
2666 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2667 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2668 return false;
2669
2670 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2671 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2672 return false;
2673
2674 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2675 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2676 return false;
fb7a46f3 2677
14571b4c 2678 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2679 unsigned char bytes[2];
2680
ea5b213a
CW		 2681 intel_sdvo->controlled_output = 0;
2682 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2683 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2684 SDVO_NAME(intel_sdvo),
51c8b407 2685 bytes[0], bytes[1]);
14571b4c 2686 return false;
fb7a46f3 2687 }
27f8227b 2688 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2689
14571b4c 2690 return true;
fb7a46f3 2691}
2692
d0ddfbd3
JN		 2693static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2694{
2695 struct drm_device *dev = intel_sdvo->base.base.dev;
2696 struct drm_connector *connector, *tmp;
2697
2698 list_for_each_entry_safe(connector, tmp,
2699 &dev->mode_config.connector_list, head) {
d9255d57
PZ		 2700 if (intel_attached_encoder(connector) == &intel_sdvo->base) {
2701 drm_sysfs_connector_remove(connector);
d0ddfbd3 2702 intel_sdvo_destroy(connector);
d9255d57 2703 }
d0ddfbd3
JN		 2704 }
2705}
2706
32aad86f
CW		 2707static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2708 struct intel_sdvo_connector *intel_sdvo_connector,
2709 int type)
ce6feabd 2710{
4ef69c7a 2711 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2712 struct intel_sdvo_tv_format format;
2713 uint32_t format_map, i;
ce6feabd 2714
32aad86f
CW		 2715 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2716 return false;
ce6feabd 2717
1a3665c8 2718 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2719 if (!intel_sdvo_get_value(intel_sdvo,
2720 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2721 &format, sizeof(format)))
2722 return false;
ce6feabd 2723
32aad86f 2724 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2725
2726 if (format_map == 0)
32aad86f 2727 return false;
ce6feabd 2728
615fb93f 2729 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2730 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2731 if (format_map & (1 << i))
2732 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2733
2734
c5521706 2735 intel_sdvo_connector->tv_format =
32aad86f
CW		 2736 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2737 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2738 if (!intel_sdvo_connector->tv_format)
fcc8d672 2739 return false;
ce6feabd 2740
615fb93f 2741 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2742 drm_property_add_enum(
c5521706 2743 intel_sdvo_connector->tv_format, i,
40039750 2744 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2745
40039750 2746 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
662595df 2747 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
c5521706 2748 intel_sdvo_connector->tv_format, 0);
32aad86f 2749 return true;
ce6feabd
ZY		 2750
2751}
2752
c5521706
CW		 2753#define ENHANCEMENT(name, NAME) do { \
2754 if (enhancements.name) { \
2755 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2756 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2757 return false; \
2758 intel_sdvo_connector->max_##name = data_value[0]; \
2759 intel_sdvo_connector->cur_##name = response; \
2760 intel_sdvo_connector->name = \
d9bc3c02 2761 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2762 if (!intel_sdvo_connector->name) return false; \
662595df 2763 drm_object_attach_property(&connector->base, \
c5521706
CW		 2764 intel_sdvo_connector->name, \
2765 intel_sdvo_connector->cur_##name); \
2766 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2767 data_value[0], data_value[1], response); \
2768 } \
0206e353 2769} while (0)
c5521706
CW		 2770
2771static bool
2772intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2773 struct intel_sdvo_connector *intel_sdvo_connector,
2774 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2775{
4ef69c7a 2776 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2777 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2778 uint16_t response, data_value[2];
2779
c5521706
CW		 2780 /* when horizontal overscan is supported, Add the left/right property */
2781 if (enhancements.overscan_h) {
2782 if (!intel_sdvo_get_value(intel_sdvo,
2783 SDVO_CMD_GET_MAX_OVERSCAN_H,
2784 &data_value, 4))
2785 return false;
32aad86f 2786
c5521706
CW		 2787 if (!intel_sdvo_get_value(intel_sdvo,
2788 SDVO_CMD_GET_OVERSCAN_H,
2789 &response, 2))
2790 return false;
fcc8d672 2791
c5521706
CW		 2792 intel_sdvo_connector->max_hscan = data_value[0];
2793 intel_sdvo_connector->left_margin = data_value[0] - response;
2794 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2795 intel_sdvo_connector->left =
d9bc3c02 2796 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2797 if (!intel_sdvo_connector->left)
2798 return false;
fcc8d672 2799
662595df 2800 drm_object_attach_property(&connector->base,
c5521706
CW		 2801 intel_sdvo_connector->left,
2802 intel_sdvo_connector->left_margin);
fcc8d672 2803
c5521706 2804 intel_sdvo_connector->right =
d9bc3c02 2805 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2806 if (!intel_sdvo_connector->right)
2807 return false;
32aad86f 2808
662595df 2809 drm_object_attach_property(&connector->base,
c5521706
CW		 2810 intel_sdvo_connector->right,
2811 intel_sdvo_connector->right_margin);
2812 DRM_DEBUG_KMS("h_overscan: max %d, "
2813 "default %d, current %d\n",
2814 data_value[0], data_value[1], response);
2815 }
32aad86f 2816
c5521706
CW		 2817 if (enhancements.overscan_v) {
2818 if (!intel_sdvo_get_value(intel_sdvo,
2819 SDVO_CMD_GET_MAX_OVERSCAN_V,
2820 &data_value, 4))
2821 return false;
fcc8d672 2822
c5521706
CW		 2823 if (!intel_sdvo_get_value(intel_sdvo,
2824 SDVO_CMD_GET_OVERSCAN_V,
2825 &response, 2))
2826 return false;
32aad86f 2827
c5521706
CW		 2828 intel_sdvo_connector->max_vscan = data_value[0];
2829 intel_sdvo_connector->top_margin = data_value[0] - response;
2830 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2831 intel_sdvo_connector->top =
d9bc3c02
SH		 2832 drm_property_create_range(dev, 0,
2833 "top_margin", 0, data_value[0]);
c5521706
CW		 2834 if (!intel_sdvo_connector->top)
2835 return false;
32aad86f 2836
662595df 2837 drm_object_attach_property(&connector->base,
c5521706
CW		 2838 intel_sdvo_connector->top,
2839 intel_sdvo_connector->top_margin);
fcc8d672 2840
c5521706 2841 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2842 drm_property_create_range(dev, 0,
2843 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2844 if (!intel_sdvo_connector->bottom)
2845 return false;
32aad86f 2846
662595df 2847 drm_object_attach_property(&connector->base,
c5521706
CW		 2848 intel_sdvo_connector->bottom,
2849 intel_sdvo_connector->bottom_margin);
2850 DRM_DEBUG_KMS("v_overscan: max %d, "
2851 "default %d, current %d\n",
2852 data_value[0], data_value[1], response);
2853 }
32aad86f 2854
c5521706
CW		 2855 ENHANCEMENT(hpos, HPOS);
2856 ENHANCEMENT(vpos, VPOS);
2857 ENHANCEMENT(saturation, SATURATION);
2858 ENHANCEMENT(contrast, CONTRAST);
2859 ENHANCEMENT(hue, HUE);
2860 ENHANCEMENT(sharpness, SHARPNESS);
2861 ENHANCEMENT(brightness, BRIGHTNESS);
2862 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2863 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2864 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2865 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2866 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2867
e044218a
CW		 2868 if (enhancements.dot_crawl) {
2869 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2870 return false;
2871
2872 intel_sdvo_connector->max_dot_crawl = 1;
2873 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2874 intel_sdvo_connector->dot_crawl =
d9bc3c02 2875 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2876 if (!intel_sdvo_connector->dot_crawl)
2877 return false;
2878
662595df 2879 drm_object_attach_property(&connector->base,
e044218a
CW		 2880 intel_sdvo_connector->dot_crawl,
2881 intel_sdvo_connector->cur_dot_crawl);
2882 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2883 }
2884
c5521706
CW		 2885 return true;
2886}
32aad86f 2887
c5521706
CW		 2888static bool
2889intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2890 struct intel_sdvo_connector *intel_sdvo_connector,
2891 struct intel_sdvo_enhancements_reply enhancements)
2892{
4ef69c7a 2893 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2894 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2895 uint16_t response, data_value[2];
32aad86f 2896
c5521706 2897 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2898
c5521706
CW		 2899 return true;
2900}
2901#undef ENHANCEMENT
32aad86f 2902
c5521706
CW		 2903static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2904 struct intel_sdvo_connector *intel_sdvo_connector)
2905{
2906 union {
2907 struct intel_sdvo_enhancements_reply reply;
2908 uint16_t response;
2909 } enhancements;
32aad86f 2910
1a3665c8
CW		 2911 BUILD_BUG_ON(sizeof(enhancements) != 2);
2912
cf9a2f3a
CW		 2913 enhancements.response = 0;
2914 intel_sdvo_get_value(intel_sdvo,
2915 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2916 &enhancements, sizeof(enhancements));
c5521706
CW		 2917 if (enhancements.response == 0) {
2918 DRM_DEBUG_KMS("No enhancement is supported\n");
2919 return true;
b9219c5e 2920 }
32aad86f 2921
c5521706
CW		 2922 if (IS_TV(intel_sdvo_connector))
2923 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2924 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2925 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2926 else
2927 return true;
e957d772
CW		 2928}
2929
2930static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2931 struct i2c_msg *msgs,
2932 int num)
2933{
2934 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2935
e957d772
CW		 2936 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2937 return -EIO;
2938
2939 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2940}
2941
2942static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2943{
2944 struct intel_sdvo *sdvo = adapter->algo_data;
2945 return sdvo->i2c->algo->functionality(sdvo->i2c);
2946}
2947
2948static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2949 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2950 .functionality = intel_sdvo_ddc_proxy_func
2951};
2952
2953static bool
2954intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2955 struct drm_device *dev)
2956{
2957 sdvo->ddc.owner = THIS_MODULE;
2958 sdvo->ddc.class = I2C_CLASS_DDC;
2959 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2960 sdvo->ddc.dev.parent = &dev->pdev->dev;
2961 sdvo->ddc.algo_data = sdvo;
2962 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2963
2964 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2965}
2966
eef4eacb 2967bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2968{
b01f2c3a 2969 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2970 struct intel_encoder *intel_encoder;
ea5b213a 2971 struct intel_sdvo *intel_sdvo;
79e53945 2972 int i;
b14c5679 2973 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
ea5b213a 2974 if (!intel_sdvo)
7d57382e 2975 return false;
79e53945 2976
56184e3d 2977 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2978 intel_sdvo->is_sdvob = is_sdvob;
2979 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2980 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
fbfcc4f3
JN		 2981 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
2982 goto err_i2c_bus;
e957d772 2983
56184e3d 2984 /* encoder type will be decided later */
ea5b213a 2985 intel_encoder = &intel_sdvo->base;
21d40d37 2986 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2987 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2988
79e53945
JB		 2989 /* Read the regs to test if we can talk to the device */
2990 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2991 u8 byte;
2992
2993 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2994 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2995 SDVO_NAME(intel_sdvo));
f899fc64 2996 goto err;
79e53945
JB		 2997 }
2998 }
2999
6cc5f341 3000 intel_encoder->compute_config = intel_sdvo_compute_config;
ce22c320 3001 intel_encoder->disable = intel_disable_sdvo;
6cc5f341 3002 intel_encoder->mode_set = intel_sdvo_mode_set;
ce22c320 3003 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 3004 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
045ac3b5 3005 intel_encoder->get_config = intel_sdvo_get_config;
ce22c320 3006
af901ca1 3007 /* In default case sdvo lvds is false */
32aad86f 3008 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 3009 goto err;
79e53945 3010
ea5b213a
CW		 3011 if (intel_sdvo_output_setup(intel_sdvo,
3012 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 3013 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
3014 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 3015 /* Output_setup can leave behind connectors! */
3016 goto err_output;
79e53945
JB		 3017 }
3018
7ba220ce
CW		 3019 /* Only enable the hotplug irq if we need it, to work around noisy
3020 * hotplug lines.
3021 */
3022 if (intel_sdvo->hotplug_active) {
3023 intel_encoder->hpd_pin =
3024 intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C;
3025 }
3026
e506d6fd
DV		 3027 /*
3028 * Cloning SDVO with anything is often impossible, since the SDVO
3029 * encoder can request a special input timing mode. And even if that's
3030 * not the case we have evidence that cloning a plain unscaled mode with
3031 * VGA doesn't really work. Furthermore the cloning flags are way too
3032 * simplistic anyway to express such constraints, so just give up on
3033 * cloning for SDVO encoders.
3034 */
bc079e8b 3035 intel_sdvo->base.cloneable = 0;
e506d6fd 3036
ea5b213a 3037 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 3038
79e53945 3039 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 3040 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 3041 goto err_output;
79e53945 3042
32aad86f
CW		 3043 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3044 &intel_sdvo->pixel_clock_min,
3045 &intel_sdvo->pixel_clock_max))
d0ddfbd3 3046 goto err_output;
79e53945 3047
8a4c47f3 3048 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 3049 "clock range %dMHz - %dMHz, "
3050 "input 1: %c, input 2: %c, "
3051 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 3052 SDVO_NAME(intel_sdvo),
3053 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3054 intel_sdvo->caps.device_rev_id,
3055 intel_sdvo->pixel_clock_min / 1000,
3056 intel_sdvo->pixel_clock_max / 1000,
3057 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3058 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 3059 /* check currently supported outputs */
ea5b213a 3060 intel_sdvo->caps.output_flags &
79e53945 3061 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 3062 intel_sdvo->caps.output_flags &
79e53945 3063 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 3064 return true;
79e53945 3065
d0ddfbd3
JN		 3066err_output:
3067 intel_sdvo_output_cleanup(intel_sdvo);
3068
f899fc64 3069err:
373a3cf7 3070 drm_encoder_cleanup(&intel_encoder->base);
e957d772 3071 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 3072err_i2c_bus:
3073 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 3074 kfree(intel_sdvo);
79e53945 3075
7d57382e 3076 return false;
79e53945 3077}
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