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79e53945 JB |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2007 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Eric Anholt <eric@anholt.net> | |
27 | */ | |
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
79e53945 | 30 | #include <linux/delay.h> |
2d1a8a48 | 31 | #include <linux/export.h> |
760285e7 DH |
32 | #include <drm/drmP.h> |
33 | #include <drm/drm_crtc.h> | |
34 | #include <drm/drm_edid.h> | |
ea5b213a | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
79e53945 JB |
37 | #include "i915_drv.h" |
38 | #include "intel_sdvo_regs.h" | |
39 | ||
14571b4c ZW |
40 | #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) |
41 | #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) | |
42 | #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) | |
a0b1c7a5 | 43 | #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) |
14571b4c ZW |
44 | |
45 | #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ | |
0206e353 | 46 | SDVO_TV_MASK) |
14571b4c ZW |
47 | |
48 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) | |
13946743 | 49 | #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) |
14571b4c | 50 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) |
32aad86f | 51 | #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) |
52220085 | 52 | #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) |
14571b4c | 53 | |
79e53945 | 54 | |
2e88e40b | 55 | static const char *tv_format_names[] = { |
ce6feabd ZY |
56 | "NTSC_M" , "NTSC_J" , "NTSC_443", |
57 | "PAL_B" , "PAL_D" , "PAL_G" , | |
58 | "PAL_H" , "PAL_I" , "PAL_M" , | |
59 | "PAL_N" , "PAL_NC" , "PAL_60" , | |
60 | "SECAM_B" , "SECAM_D" , "SECAM_G" , | |
61 | "SECAM_K" , "SECAM_K1", "SECAM_L" , | |
62 | "SECAM_60" | |
63 | }; | |
64 | ||
65 | #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) | |
66 | ||
ea5b213a CW |
67 | struct intel_sdvo { |
68 | struct intel_encoder base; | |
69 | ||
f899fc64 | 70 | struct i2c_adapter *i2c; |
f9c10a9b | 71 | u8 slave_addr; |
e2f0ba97 | 72 | |
e957d772 CW |
73 | struct i2c_adapter ddc; |
74 | ||
e2f0ba97 | 75 | /* Register for the SDVO device: SDVOB or SDVOC */ |
eef4eacb | 76 | uint32_t sdvo_reg; |
79e53945 | 77 | |
e2f0ba97 JB |
78 | /* Active outputs controlled by this SDVO output */ |
79 | uint16_t controlled_output; | |
79e53945 | 80 | |
e2f0ba97 JB |
81 | /* |
82 | * Capabilities of the SDVO device returned by | |
83 | * i830_sdvo_get_capabilities() | |
84 | */ | |
79e53945 | 85 | struct intel_sdvo_caps caps; |
e2f0ba97 JB |
86 | |
87 | /* Pixel clock limitations reported by the SDVO device, in kHz */ | |
79e53945 JB |
88 | int pixel_clock_min, pixel_clock_max; |
89 | ||
fb7a46f3 | 90 | /* |
91 | * For multiple function SDVO device, | |
92 | * this is for current attached outputs. | |
93 | */ | |
94 | uint16_t attached_output; | |
95 | ||
cc68c81a SF |
96 | /* |
97 | * Hotplug activation bits for this device | |
98 | */ | |
5fa7ac9c | 99 | uint16_t hotplug_active; |
cc68c81a | 100 | |
e953fd7b CW |
101 | /** |
102 | * This is used to select the color range of RBG outputs in HDMI mode. | |
103 | * It is only valid when using TMDS encoding and 8 bit per color mode. | |
104 | */ | |
105 | uint32_t color_range; | |
55bc60db | 106 | bool color_range_auto; |
e953fd7b | 107 | |
e2f0ba97 JB |
108 | /** |
109 | * This is set if we're going to treat the device as TV-out. | |
110 | * | |
111 | * While we have these nice friendly flags for output types that ought | |
112 | * to decide this for us, the S-Video output on our HDMI+S-Video card | |
113 | * shows up as RGB1 (VGA). | |
114 | */ | |
115 | bool is_tv; | |
116 | ||
eef4eacb DV |
117 | /* On different gens SDVOB is at different places. */ |
118 | bool is_sdvob; | |
119 | ||
ce6feabd | 120 | /* This is for current tv format name */ |
40039750 | 121 | int tv_format_index; |
ce6feabd | 122 | |
e2f0ba97 JB |
123 | /** |
124 | * This is set if we treat the device as HDMI, instead of DVI. | |
125 | */ | |
126 | bool is_hdmi; | |
da79de97 CW |
127 | bool has_hdmi_monitor; |
128 | bool has_hdmi_audio; | |
abedc077 | 129 | bool rgb_quant_range_selectable; |
12682a97 | 130 | |
7086c87f | 131 | /** |
6c9547ff CW |
132 | * This is set if we detect output of sdvo device as LVDS and |
133 | * have a valid fixed mode to use with the panel. | |
7086c87f ML |
134 | */ |
135 | bool is_lvds; | |
e2f0ba97 | 136 | |
12682a97 | 137 | /** |
138 | * This is sdvo fixed pannel mode pointer | |
139 | */ | |
140 | struct drm_display_mode *sdvo_lvds_fixed_mode; | |
141 | ||
c751ce4f | 142 | /* DDC bus used by this SDVO encoder */ |
e2f0ba97 | 143 | uint8_t ddc_bus; |
e751823d EE |
144 | |
145 | /* | |
146 | * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd | |
147 | */ | |
148 | uint8_t dtd_sdvo_flags; | |
14571b4c ZW |
149 | }; |
150 | ||
151 | struct intel_sdvo_connector { | |
615fb93f CW |
152 | struct intel_connector base; |
153 | ||
14571b4c ZW |
154 | /* Mark the type of connector */ |
155 | uint16_t output_flag; | |
156 | ||
c3e5f67b | 157 | enum hdmi_force_audio force_audio; |
7f36e7ed | 158 | |
14571b4c | 159 | /* This contains all current supported TV format */ |
40039750 | 160 | u8 tv_format_supported[TV_FORMAT_NUM]; |
14571b4c | 161 | int format_supported_num; |
c5521706 | 162 | struct drm_property *tv_format; |
14571b4c | 163 | |
b9219c5e | 164 | /* add the property for the SDVO-TV */ |
c5521706 CW |
165 | struct drm_property *left; |
166 | struct drm_property *right; | |
167 | struct drm_property *top; | |
168 | struct drm_property *bottom; | |
169 | struct drm_property *hpos; | |
170 | struct drm_property *vpos; | |
171 | struct drm_property *contrast; | |
172 | struct drm_property *saturation; | |
173 | struct drm_property *hue; | |
174 | struct drm_property *sharpness; | |
175 | struct drm_property *flicker_filter; | |
176 | struct drm_property *flicker_filter_adaptive; | |
177 | struct drm_property *flicker_filter_2d; | |
178 | struct drm_property *tv_chroma_filter; | |
179 | struct drm_property *tv_luma_filter; | |
e044218a | 180 | struct drm_property *dot_crawl; |
b9219c5e ZY |
181 | |
182 | /* add the property for the SDVO-TV/LVDS */ | |
c5521706 | 183 | struct drm_property *brightness; |
b9219c5e ZY |
184 | |
185 | /* Add variable to record current setting for the above property */ | |
186 | u32 left_margin, right_margin, top_margin, bottom_margin; | |
c5521706 | 187 | |
b9219c5e ZY |
188 | /* this is to get the range of margin.*/ |
189 | u32 max_hscan, max_vscan; | |
190 | u32 max_hpos, cur_hpos; | |
191 | u32 max_vpos, cur_vpos; | |
192 | u32 cur_brightness, max_brightness; | |
193 | u32 cur_contrast, max_contrast; | |
194 | u32 cur_saturation, max_saturation; | |
195 | u32 cur_hue, max_hue; | |
c5521706 CW |
196 | u32 cur_sharpness, max_sharpness; |
197 | u32 cur_flicker_filter, max_flicker_filter; | |
198 | u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; | |
199 | u32 cur_flicker_filter_2d, max_flicker_filter_2d; | |
200 | u32 cur_tv_chroma_filter, max_tv_chroma_filter; | |
201 | u32 cur_tv_luma_filter, max_tv_luma_filter; | |
e044218a | 202 | u32 cur_dot_crawl, max_dot_crawl; |
79e53945 JB |
203 | }; |
204 | ||
890f3359 | 205 | static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder) |
ea5b213a | 206 | { |
4ef69c7a | 207 | return container_of(encoder, struct intel_sdvo, base.base); |
ea5b213a CW |
208 | } |
209 | ||
df0e9248 CW |
210 | static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) |
211 | { | |
212 | return container_of(intel_attached_encoder(connector), | |
213 | struct intel_sdvo, base); | |
214 | } | |
215 | ||
615fb93f CW |
216 | static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) |
217 | { | |
218 | return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); | |
219 | } | |
220 | ||
fb7a46f3 | 221 | static bool |
ea5b213a | 222 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); |
32aad86f CW |
223 | static bool |
224 | intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, | |
225 | struct intel_sdvo_connector *intel_sdvo_connector, | |
226 | int type); | |
227 | static bool | |
228 | intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, | |
229 | struct intel_sdvo_connector *intel_sdvo_connector); | |
fb7a46f3 | 230 | |
79e53945 JB |
231 | /** |
232 | * Writes the SDVOB or SDVOC with the given value, but always writes both | |
233 | * SDVOB and SDVOC to work around apparent hardware issues (according to | |
234 | * comments in the BIOS). | |
235 | */ | |
ea5b213a | 236 | static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) |
79e53945 | 237 | { |
4ef69c7a | 238 | struct drm_device *dev = intel_sdvo->base.base.dev; |
79e53945 | 239 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
240 | u32 bval = val, cval = val; |
241 | int i; | |
242 | ||
ea5b213a CW |
243 | if (intel_sdvo->sdvo_reg == PCH_SDVOB) { |
244 | I915_WRITE(intel_sdvo->sdvo_reg, val); | |
245 | I915_READ(intel_sdvo->sdvo_reg); | |
461ed3ca ZY |
246 | return; |
247 | } | |
248 | ||
e2debe91 PZ |
249 | if (intel_sdvo->sdvo_reg == GEN3_SDVOB) |
250 | cval = I915_READ(GEN3_SDVOC); | |
251 | else | |
252 | bval = I915_READ(GEN3_SDVOB); | |
253 | ||
79e53945 JB |
254 | /* |
255 | * Write the registers twice for luck. Sometimes, | |
256 | * writing them only once doesn't appear to 'stick'. | |
257 | * The BIOS does this too. Yay, magic | |
258 | */ | |
259 | for (i = 0; i < 2; i++) | |
260 | { | |
e2debe91 PZ |
261 | I915_WRITE(GEN3_SDVOB, bval); |
262 | I915_READ(GEN3_SDVOB); | |
263 | I915_WRITE(GEN3_SDVOC, cval); | |
264 | I915_READ(GEN3_SDVOC); | |
79e53945 JB |
265 | } |
266 | } | |
267 | ||
32aad86f | 268 | static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) |
79e53945 | 269 | { |
79e53945 JB |
270 | struct i2c_msg msgs[] = { |
271 | { | |
e957d772 | 272 | .addr = intel_sdvo->slave_addr, |
79e53945 JB |
273 | .flags = 0, |
274 | .len = 1, | |
e957d772 | 275 | .buf = &addr, |
79e53945 JB |
276 | }, |
277 | { | |
e957d772 | 278 | .addr = intel_sdvo->slave_addr, |
79e53945 JB |
279 | .flags = I2C_M_RD, |
280 | .len = 1, | |
e957d772 | 281 | .buf = ch, |
79e53945 JB |
282 | } |
283 | }; | |
32aad86f | 284 | int ret; |
79e53945 | 285 | |
f899fc64 | 286 | if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) |
79e53945 | 287 | return true; |
79e53945 | 288 | |
8a4c47f3 | 289 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); |
79e53945 JB |
290 | return false; |
291 | } | |
292 | ||
79e53945 JB |
293 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} |
294 | /** Mapping of command numbers to names, for debug output */ | |
005568be | 295 | static const struct _sdvo_cmd_name { |
e2f0ba97 | 296 | u8 cmd; |
2e88e40b | 297 | const char *name; |
79e53945 | 298 | } sdvo_cmd_names[] = { |
0206e353 AJ |
299 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), |
300 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), | |
301 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), | |
302 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), | |
303 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), | |
304 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), | |
305 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), | |
306 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), | |
307 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), | |
308 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), | |
309 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), | |
310 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), | |
311 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), | |
312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), | |
313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), | |
314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), | |
315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), | |
316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), | |
318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), | |
320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), | |
321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), | |
322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), | |
323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), | |
324 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), | |
325 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), | |
326 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), | |
327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), | |
328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), | |
329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), | |
330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), | |
331 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), | |
332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), | |
333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), | |
334 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), | |
335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), | |
336 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), | |
337 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), | |
338 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), | |
339 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), | |
340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), | |
341 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), | |
342 | ||
343 | /* Add the op code for SDVO enhancements */ | |
344 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), | |
345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), | |
346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), | |
347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), | |
348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), | |
349 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), | |
350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), | |
351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), | |
352 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), | |
353 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), | |
354 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), | |
355 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), | |
356 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), | |
357 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), | |
358 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), | |
359 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), | |
360 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), | |
361 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), | |
362 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), | |
363 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), | |
364 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), | |
365 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), | |
366 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), | |
367 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), | |
368 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), | |
369 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), | |
370 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), | |
371 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), | |
372 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), | |
373 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), | |
374 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), | |
375 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), | |
376 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), | |
377 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), | |
378 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), | |
379 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), | |
380 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), | |
381 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), | |
382 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), | |
383 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), | |
384 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), | |
385 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), | |
386 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), | |
387 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), | |
388 | ||
389 | /* HDMI op code */ | |
390 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), | |
391 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), | |
392 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), | |
393 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), | |
394 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), | |
395 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), | |
396 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), | |
397 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), | |
398 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), | |
399 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), | |
400 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), | |
401 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), | |
402 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), | |
403 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), | |
404 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), | |
405 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), | |
406 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), | |
407 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), | |
408 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), | |
409 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), | |
79e53945 JB |
410 | }; |
411 | ||
eef4eacb | 412 | #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC") |
79e53945 | 413 | |
ea5b213a | 414 | static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, |
32aad86f | 415 | const void *args, int args_len) |
79e53945 | 416 | { |
79e53945 JB |
417 | int i; |
418 | ||
8a4c47f3 | 419 | DRM_DEBUG_KMS("%s: W: %02X ", |
ea5b213a | 420 | SDVO_NAME(intel_sdvo), cmd); |
79e53945 | 421 | for (i = 0; i < args_len; i++) |
342dc382 | 422 | DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); |
79e53945 | 423 | for (; i < 8; i++) |
342dc382 | 424 | DRM_LOG_KMS(" "); |
04ad327f | 425 | for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { |
79e53945 | 426 | if (cmd == sdvo_cmd_names[i].cmd) { |
342dc382 | 427 | DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name); |
79e53945 JB |
428 | break; |
429 | } | |
430 | } | |
04ad327f | 431 | if (i == ARRAY_SIZE(sdvo_cmd_names)) |
342dc382 | 432 | DRM_LOG_KMS("(%02X)", cmd); |
433 | DRM_LOG_KMS("\n"); | |
79e53945 | 434 | } |
79e53945 | 435 | |
e957d772 CW |
436 | static const char *cmd_status_names[] = { |
437 | "Power on", | |
438 | "Success", | |
439 | "Not supported", | |
440 | "Invalid arg", | |
441 | "Pending", | |
442 | "Target not specified", | |
443 | "Scaling not supported" | |
444 | }; | |
445 | ||
32aad86f CW |
446 | static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, |
447 | const void *args, int args_len) | |
79e53945 | 448 | { |
3bf3f452 BW |
449 | u8 *buf, status; |
450 | struct i2c_msg *msgs; | |
451 | int i, ret = true; | |
452 | ||
0274df3e | 453 | /* Would be simpler to allocate both in one go ? */ |
5c67eeb6 | 454 | buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); |
3bf3f452 BW |
455 | if (!buf) |
456 | return false; | |
457 | ||
458 | msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); | |
0274df3e AC |
459 | if (!msgs) { |
460 | kfree(buf); | |
3bf3f452 | 461 | return false; |
0274df3e | 462 | } |
79e53945 | 463 | |
ea5b213a | 464 | intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); |
79e53945 JB |
465 | |
466 | for (i = 0; i < args_len; i++) { | |
e957d772 CW |
467 | msgs[i].addr = intel_sdvo->slave_addr; |
468 | msgs[i].flags = 0; | |
469 | msgs[i].len = 2; | |
470 | msgs[i].buf = buf + 2 *i; | |
471 | buf[2*i + 0] = SDVO_I2C_ARG_0 - i; | |
472 | buf[2*i + 1] = ((u8*)args)[i]; | |
473 | } | |
474 | msgs[i].addr = intel_sdvo->slave_addr; | |
475 | msgs[i].flags = 0; | |
476 | msgs[i].len = 2; | |
477 | msgs[i].buf = buf + 2*i; | |
478 | buf[2*i + 0] = SDVO_I2C_OPCODE; | |
479 | buf[2*i + 1] = cmd; | |
480 | ||
481 | /* the following two are to read the response */ | |
482 | status = SDVO_I2C_CMD_STATUS; | |
483 | msgs[i+1].addr = intel_sdvo->slave_addr; | |
484 | msgs[i+1].flags = 0; | |
485 | msgs[i+1].len = 1; | |
486 | msgs[i+1].buf = &status; | |
487 | ||
488 | msgs[i+2].addr = intel_sdvo->slave_addr; | |
489 | msgs[i+2].flags = I2C_M_RD; | |
490 | msgs[i+2].len = 1; | |
491 | msgs[i+2].buf = &status; | |
492 | ||
493 | ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); | |
494 | if (ret < 0) { | |
495 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); | |
3bf3f452 BW |
496 | ret = false; |
497 | goto out; | |
e957d772 CW |
498 | } |
499 | if (ret != i+3) { | |
500 | /* failure in I2C transfer */ | |
501 | DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); | |
3bf3f452 | 502 | ret = false; |
e957d772 CW |
503 | } |
504 | ||
3bf3f452 BW |
505 | out: |
506 | kfree(msgs); | |
507 | kfree(buf); | |
508 | return ret; | |
79e53945 JB |
509 | } |
510 | ||
b5c616a7 CW |
511 | static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, |
512 | void *response, int response_len) | |
79e53945 | 513 | { |
fc37381c | 514 | u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ |
b5c616a7 | 515 | u8 status; |
33b52961 | 516 | int i; |
79e53945 | 517 | |
d121a5d2 CW |
518 | DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo)); |
519 | ||
b5c616a7 CW |
520 | /* |
521 | * The documentation states that all commands will be | |
522 | * processed within 15µs, and that we need only poll | |
523 | * the status byte a maximum of 3 times in order for the | |
524 | * command to be complete. | |
525 | * | |
526 | * Check 5 times in case the hardware failed to read the docs. | |
fc37381c CW |
527 | * |
528 | * Also beware that the first response by many devices is to | |
529 | * reply PENDING and stall for time. TVs are notorious for | |
530 | * requiring longer than specified to complete their replies. | |
531 | * Originally (in the DDX long ago), the delay was only ever 15ms | |
532 | * with an additional delay of 30ms applied for TVs added later after | |
533 | * many experiments. To accommodate both sets of delays, we do a | |
534 | * sequence of slow checks if the device is falling behind and fails | |
535 | * to reply within 5*15µs. | |
b5c616a7 | 536 | */ |
d121a5d2 CW |
537 | if (!intel_sdvo_read_byte(intel_sdvo, |
538 | SDVO_I2C_CMD_STATUS, | |
539 | &status)) | |
540 | goto log_fail; | |
541 | ||
fc37381c CW |
542 | while (status == SDVO_CMD_STATUS_PENDING && --retry) { |
543 | if (retry < 10) | |
544 | msleep(15); | |
545 | else | |
546 | udelay(15); | |
547 | ||
b5c616a7 CW |
548 | if (!intel_sdvo_read_byte(intel_sdvo, |
549 | SDVO_I2C_CMD_STATUS, | |
550 | &status)) | |
d121a5d2 CW |
551 | goto log_fail; |
552 | } | |
b5c616a7 | 553 | |
79e53945 | 554 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
342dc382 | 555 | DRM_LOG_KMS("(%s)", cmd_status_names[status]); |
79e53945 | 556 | else |
342dc382 | 557 | DRM_LOG_KMS("(??? %d)", status); |
79e53945 | 558 | |
b5c616a7 CW |
559 | if (status != SDVO_CMD_STATUS_SUCCESS) |
560 | goto log_fail; | |
79e53945 | 561 | |
b5c616a7 CW |
562 | /* Read the command response */ |
563 | for (i = 0; i < response_len; i++) { | |
564 | if (!intel_sdvo_read_byte(intel_sdvo, | |
565 | SDVO_I2C_RETURN_0 + i, | |
566 | &((u8 *)response)[i])) | |
567 | goto log_fail; | |
e957d772 | 568 | DRM_LOG_KMS(" %02X", ((u8 *)response)[i]); |
b5c616a7 | 569 | } |
b5c616a7 | 570 | DRM_LOG_KMS("\n"); |
b5c616a7 | 571 | return true; |
79e53945 | 572 | |
b5c616a7 | 573 | log_fail: |
d121a5d2 | 574 | DRM_LOG_KMS("... failed\n"); |
b5c616a7 | 575 | return false; |
79e53945 JB |
576 | } |
577 | ||
b358d0a6 | 578 | static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) |
79e53945 JB |
579 | { |
580 | if (mode->clock >= 100000) | |
581 | return 1; | |
582 | else if (mode->clock >= 50000) | |
583 | return 2; | |
584 | else | |
585 | return 4; | |
586 | } | |
587 | ||
e957d772 CW |
588 | static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, |
589 | u8 ddc_bus) | |
79e53945 | 590 | { |
d121a5d2 | 591 | /* This must be the immediately preceding write before the i2c xfer */ |
e957d772 CW |
592 | return intel_sdvo_write_cmd(intel_sdvo, |
593 | SDVO_CMD_SET_CONTROL_BUS_SWITCH, | |
594 | &ddc_bus, 1); | |
79e53945 JB |
595 | } |
596 | ||
32aad86f | 597 | static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) |
79e53945 | 598 | { |
d121a5d2 CW |
599 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) |
600 | return false; | |
601 | ||
602 | return intel_sdvo_read_response(intel_sdvo, NULL, 0); | |
32aad86f | 603 | } |
79e53945 | 604 | |
32aad86f CW |
605 | static bool |
606 | intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) | |
607 | { | |
608 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) | |
609 | return false; | |
79e53945 | 610 | |
32aad86f CW |
611 | return intel_sdvo_read_response(intel_sdvo, value, len); |
612 | } | |
79e53945 | 613 | |
32aad86f CW |
614 | static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) |
615 | { | |
616 | struct intel_sdvo_set_target_input_args targets = {0}; | |
617 | return intel_sdvo_set_value(intel_sdvo, | |
618 | SDVO_CMD_SET_TARGET_INPUT, | |
619 | &targets, sizeof(targets)); | |
79e53945 JB |
620 | } |
621 | ||
622 | /** | |
623 | * Return whether each input is trained. | |
624 | * | |
625 | * This function is making an assumption about the layout of the response, | |
626 | * which should be checked against the docs. | |
627 | */ | |
ea5b213a | 628 | static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) |
79e53945 JB |
629 | { |
630 | struct intel_sdvo_get_trained_inputs_response response; | |
79e53945 | 631 | |
1a3665c8 | 632 | BUILD_BUG_ON(sizeof(response) != 1); |
32aad86f CW |
633 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, |
634 | &response, sizeof(response))) | |
79e53945 JB |
635 | return false; |
636 | ||
637 | *input_1 = response.input0_trained; | |
638 | *input_2 = response.input1_trained; | |
639 | return true; | |
640 | } | |
641 | ||
ea5b213a | 642 | static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
643 | u16 outputs) |
644 | { | |
32aad86f CW |
645 | return intel_sdvo_set_value(intel_sdvo, |
646 | SDVO_CMD_SET_ACTIVE_OUTPUTS, | |
647 | &outputs, sizeof(outputs)); | |
79e53945 JB |
648 | } |
649 | ||
4ac41f47 DV |
650 | static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, |
651 | u16 *outputs) | |
652 | { | |
653 | return intel_sdvo_get_value(intel_sdvo, | |
654 | SDVO_CMD_GET_ACTIVE_OUTPUTS, | |
655 | outputs, sizeof(*outputs)); | |
656 | } | |
657 | ||
ea5b213a | 658 | static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
659 | int mode) |
660 | { | |
32aad86f | 661 | u8 state = SDVO_ENCODER_STATE_ON; |
79e53945 JB |
662 | |
663 | switch (mode) { | |
664 | case DRM_MODE_DPMS_ON: | |
665 | state = SDVO_ENCODER_STATE_ON; | |
666 | break; | |
667 | case DRM_MODE_DPMS_STANDBY: | |
668 | state = SDVO_ENCODER_STATE_STANDBY; | |
669 | break; | |
670 | case DRM_MODE_DPMS_SUSPEND: | |
671 | state = SDVO_ENCODER_STATE_SUSPEND; | |
672 | break; | |
673 | case DRM_MODE_DPMS_OFF: | |
674 | state = SDVO_ENCODER_STATE_OFF; | |
675 | break; | |
676 | } | |
677 | ||
32aad86f CW |
678 | return intel_sdvo_set_value(intel_sdvo, |
679 | SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); | |
79e53945 JB |
680 | } |
681 | ||
ea5b213a | 682 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
683 | int *clock_min, |
684 | int *clock_max) | |
685 | { | |
686 | struct intel_sdvo_pixel_clock_range clocks; | |
79e53945 | 687 | |
1a3665c8 | 688 | BUILD_BUG_ON(sizeof(clocks) != 4); |
32aad86f CW |
689 | if (!intel_sdvo_get_value(intel_sdvo, |
690 | SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, | |
691 | &clocks, sizeof(clocks))) | |
79e53945 JB |
692 | return false; |
693 | ||
694 | /* Convert the values from units of 10 kHz to kHz. */ | |
695 | *clock_min = clocks.min * 10; | |
696 | *clock_max = clocks.max * 10; | |
79e53945 JB |
697 | return true; |
698 | } | |
699 | ||
ea5b213a | 700 | static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
701 | u16 outputs) |
702 | { | |
32aad86f CW |
703 | return intel_sdvo_set_value(intel_sdvo, |
704 | SDVO_CMD_SET_TARGET_OUTPUT, | |
705 | &outputs, sizeof(outputs)); | |
79e53945 JB |
706 | } |
707 | ||
ea5b213a | 708 | static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
79e53945 JB |
709 | struct intel_sdvo_dtd *dtd) |
710 | { | |
32aad86f CW |
711 | return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
712 | intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); | |
79e53945 JB |
713 | } |
714 | ||
ea5b213a | 715 | static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
716 | struct intel_sdvo_dtd *dtd) |
717 | { | |
ea5b213a | 718 | return intel_sdvo_set_timing(intel_sdvo, |
79e53945 JB |
719 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); |
720 | } | |
721 | ||
ea5b213a | 722 | static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
723 | struct intel_sdvo_dtd *dtd) |
724 | { | |
ea5b213a | 725 | return intel_sdvo_set_timing(intel_sdvo, |
79e53945 JB |
726 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); |
727 | } | |
728 | ||
e2f0ba97 | 729 | static bool |
ea5b213a | 730 | intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
731 | uint16_t clock, |
732 | uint16_t width, | |
733 | uint16_t height) | |
734 | { | |
735 | struct intel_sdvo_preferred_input_timing_args args; | |
e2f0ba97 | 736 | |
e642c6f1 | 737 | memset(&args, 0, sizeof(args)); |
e2f0ba97 JB |
738 | args.clock = clock; |
739 | args.width = width; | |
740 | args.height = height; | |
e642c6f1 | 741 | args.interlace = 0; |
12682a97 | 742 | |
ea5b213a CW |
743 | if (intel_sdvo->is_lvds && |
744 | (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || | |
745 | intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) | |
12682a97 | 746 | args.scaled = 1; |
747 | ||
32aad86f CW |
748 | return intel_sdvo_set_value(intel_sdvo, |
749 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, | |
750 | &args, sizeof(args)); | |
e2f0ba97 JB |
751 | } |
752 | ||
ea5b213a | 753 | static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
754 | struct intel_sdvo_dtd *dtd) |
755 | { | |
1a3665c8 CW |
756 | BUILD_BUG_ON(sizeof(dtd->part1) != 8); |
757 | BUILD_BUG_ON(sizeof(dtd->part2) != 8); | |
32aad86f CW |
758 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, |
759 | &dtd->part1, sizeof(dtd->part1)) && | |
760 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, | |
761 | &dtd->part2, sizeof(dtd->part2)); | |
e2f0ba97 | 762 | } |
79e53945 | 763 | |
ea5b213a | 764 | static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) |
79e53945 | 765 | { |
32aad86f | 766 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); |
79e53945 JB |
767 | } |
768 | ||
e2f0ba97 | 769 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
32aad86f | 770 | const struct drm_display_mode *mode) |
79e53945 | 771 | { |
e2f0ba97 JB |
772 | uint16_t width, height; |
773 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; | |
774 | uint16_t h_sync_offset, v_sync_offset; | |
6651819b | 775 | int mode_clock; |
79e53945 | 776 | |
c6ebd4c0 DV |
777 | width = mode->hdisplay; |
778 | height = mode->vdisplay; | |
79e53945 JB |
779 | |
780 | /* do some mode translations */ | |
c6ebd4c0 DV |
781 | h_blank_len = mode->htotal - mode->hdisplay; |
782 | h_sync_len = mode->hsync_end - mode->hsync_start; | |
79e53945 | 783 | |
c6ebd4c0 DV |
784 | v_blank_len = mode->vtotal - mode->vdisplay; |
785 | v_sync_len = mode->vsync_end - mode->vsync_start; | |
79e53945 | 786 | |
c6ebd4c0 DV |
787 | h_sync_offset = mode->hsync_start - mode->hdisplay; |
788 | v_sync_offset = mode->vsync_start - mode->vdisplay; | |
79e53945 | 789 | |
6651819b | 790 | mode_clock = mode->clock; |
6651819b DV |
791 | mode_clock /= 10; |
792 | dtd->part1.clock = mode_clock; | |
793 | ||
e2f0ba97 JB |
794 | dtd->part1.h_active = width & 0xff; |
795 | dtd->part1.h_blank = h_blank_len & 0xff; | |
796 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | | |
79e53945 | 797 | ((h_blank_len >> 8) & 0xf); |
e2f0ba97 JB |
798 | dtd->part1.v_active = height & 0xff; |
799 | dtd->part1.v_blank = v_blank_len & 0xff; | |
800 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | | |
79e53945 JB |
801 | ((v_blank_len >> 8) & 0xf); |
802 | ||
171a9e96 | 803 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
e2f0ba97 JB |
804 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
805 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | | |
79e53945 | 806 | (v_sync_len & 0xf); |
e2f0ba97 | 807 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
79e53945 JB |
808 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
809 | ((v_sync_len & 0x30) >> 4); | |
810 | ||
e2f0ba97 | 811 | dtd->part2.dtd_flags = 0x18; |
59d92bfa DV |
812 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
813 | dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; | |
79e53945 | 814 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
59d92bfa | 815 | dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; |
79e53945 | 816 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
59d92bfa | 817 | dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; |
e2f0ba97 JB |
818 | |
819 | dtd->part2.sdvo_flags = 0; | |
820 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; | |
821 | dtd->part2.reserved = 0; | |
822 | } | |
823 | ||
824 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode, | |
32aad86f | 825 | const struct intel_sdvo_dtd *dtd) |
e2f0ba97 | 826 | { |
e2f0ba97 JB |
827 | mode->hdisplay = dtd->part1.h_active; |
828 | mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; | |
829 | mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off; | |
171a9e96 | 830 | mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; |
e2f0ba97 JB |
831 | mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width; |
832 | mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; | |
833 | mode->htotal = mode->hdisplay + dtd->part1.h_blank; | |
834 | mode->htotal += (dtd->part1.h_high & 0xf) << 8; | |
835 | ||
836 | mode->vdisplay = dtd->part1.v_active; | |
837 | mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; | |
838 | mode->vsync_start = mode->vdisplay; | |
839 | mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; | |
171a9e96 | 840 | mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; |
e2f0ba97 JB |
841 | mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0; |
842 | mode->vsync_end = mode->vsync_start + | |
843 | (dtd->part2.v_sync_off_width & 0xf); | |
844 | mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; | |
845 | mode->vtotal = mode->vdisplay + dtd->part1.v_blank; | |
846 | mode->vtotal += (dtd->part1.v_high & 0xf) << 8; | |
847 | ||
848 | mode->clock = dtd->part1.clock * 10; | |
849 | ||
171a9e96 | 850 | mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); |
59d92bfa DV |
851 | if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) |
852 | mode->flags |= DRM_MODE_FLAG_INTERLACE; | |
853 | if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) | |
e2f0ba97 | 854 | mode->flags |= DRM_MODE_FLAG_PHSYNC; |
59d92bfa | 855 | if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) |
e2f0ba97 JB |
856 | mode->flags |= DRM_MODE_FLAG_PVSYNC; |
857 | } | |
858 | ||
e27d8538 | 859 | static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) |
e2f0ba97 | 860 | { |
e27d8538 | 861 | struct intel_sdvo_encode encode; |
e2f0ba97 | 862 | |
1a3665c8 | 863 | BUILD_BUG_ON(sizeof(encode) != 2); |
e27d8538 CW |
864 | return intel_sdvo_get_value(intel_sdvo, |
865 | SDVO_CMD_GET_SUPP_ENCODE, | |
866 | &encode, sizeof(encode)); | |
e2f0ba97 JB |
867 | } |
868 | ||
ea5b213a | 869 | static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, |
c751ce4f | 870 | uint8_t mode) |
e2f0ba97 | 871 | { |
32aad86f | 872 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); |
e2f0ba97 JB |
873 | } |
874 | ||
ea5b213a | 875 | static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
876 | uint8_t mode) |
877 | { | |
32aad86f | 878 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); |
e2f0ba97 JB |
879 | } |
880 | ||
881 | #if 0 | |
ea5b213a | 882 | static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) |
e2f0ba97 JB |
883 | { |
884 | int i, j; | |
885 | uint8_t set_buf_index[2]; | |
886 | uint8_t av_split; | |
887 | uint8_t buf_size; | |
888 | uint8_t buf[48]; | |
889 | uint8_t *pos; | |
890 | ||
32aad86f | 891 | intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); |
e2f0ba97 JB |
892 | |
893 | for (i = 0; i <= av_split; i++) { | |
894 | set_buf_index[0] = i; set_buf_index[1] = 0; | |
c751ce4f | 895 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, |
e2f0ba97 | 896 | set_buf_index, 2); |
c751ce4f EA |
897 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); |
898 | intel_sdvo_read_response(encoder, &buf_size, 1); | |
e2f0ba97 JB |
899 | |
900 | pos = buf; | |
901 | for (j = 0; j <= buf_size; j += 8) { | |
c751ce4f | 902 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, |
e2f0ba97 | 903 | NULL, 0); |
c751ce4f | 904 | intel_sdvo_read_response(encoder, pos, 8); |
e2f0ba97 JB |
905 | pos += 8; |
906 | } | |
907 | } | |
908 | } | |
909 | #endif | |
910 | ||
b6e0e543 DV |
911 | static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, |
912 | unsigned if_index, uint8_t tx_rate, | |
913 | uint8_t *data, unsigned length) | |
914 | { | |
915 | uint8_t set_buf_index[2] = { if_index, 0 }; | |
916 | uint8_t hbuf_size, tmp[8]; | |
917 | int i; | |
918 | ||
919 | if (!intel_sdvo_set_value(intel_sdvo, | |
920 | SDVO_CMD_SET_HBUF_INDEX, | |
921 | set_buf_index, 2)) | |
922 | return false; | |
923 | ||
924 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, | |
925 | &hbuf_size, 1)) | |
926 | return false; | |
927 | ||
928 | /* Buffer size is 0 based, hooray! */ | |
929 | hbuf_size++; | |
930 | ||
931 | DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n", | |
932 | if_index, length, hbuf_size); | |
933 | ||
934 | for (i = 0; i < hbuf_size; i += 8) { | |
935 | memset(tmp, 0, 8); | |
936 | if (i < length) | |
937 | memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); | |
938 | ||
939 | if (!intel_sdvo_set_value(intel_sdvo, | |
940 | SDVO_CMD_SET_HBUF_DATA, | |
941 | tmp, 8)) | |
942 | return false; | |
943 | } | |
944 | ||
945 | return intel_sdvo_set_value(intel_sdvo, | |
946 | SDVO_CMD_SET_HBUF_TXRATE, | |
947 | &tx_rate, 1); | |
948 | } | |
949 | ||
abedc077 VS |
950 | static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, |
951 | const struct drm_display_mode *adjusted_mode) | |
e2f0ba97 JB |
952 | { |
953 | struct dip_infoframe avi_if = { | |
954 | .type = DIP_TYPE_AVI, | |
3c17fe4b | 955 | .ver = DIP_VERSION_AVI, |
e2f0ba97 JB |
956 | .len = DIP_LEN_AVI, |
957 | }; | |
81014b9d | 958 | uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)]; |
50f3b016 | 959 | struct intel_crtc *intel_crtc = to_intel_crtc(intel_sdvo->base.base.crtc); |
3c17fe4b | 960 | |
abedc077 | 961 | if (intel_sdvo->rgb_quant_range_selectable) { |
50f3b016 | 962 | if (intel_crtc->config.limited_color_range) |
abedc077 VS |
963 | avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED; |
964 | else | |
965 | avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL; | |
966 | } | |
967 | ||
96b219fa VS |
968 | avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode); |
969 | ||
3c17fe4b DH |
970 | intel_dip_infoframe_csum(&avi_if); |
971 | ||
81014b9d DV |
972 | /* sdvo spec says that the ecc is handled by the hw, and it looks like |
973 | * we must not send the ecc field, either. */ | |
974 | memcpy(sdvo_data, &avi_if, 3); | |
975 | sdvo_data[3] = avi_if.checksum; | |
976 | memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi)); | |
977 | ||
b6e0e543 DV |
978 | return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, |
979 | SDVO_HBUF_TX_VSYNC, | |
980 | sdvo_data, sizeof(sdvo_data)); | |
e2f0ba97 JB |
981 | } |
982 | ||
32aad86f | 983 | static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) |
7026d4ac | 984 | { |
ce6feabd | 985 | struct intel_sdvo_tv_format format; |
40039750 | 986 | uint32_t format_map; |
ce6feabd | 987 | |
40039750 | 988 | format_map = 1 << intel_sdvo->tv_format_index; |
ce6feabd | 989 | memset(&format, 0, sizeof(format)); |
32aad86f | 990 | memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); |
ce6feabd | 991 | |
32aad86f CW |
992 | BUILD_BUG_ON(sizeof(format) != 6); |
993 | return intel_sdvo_set_value(intel_sdvo, | |
994 | SDVO_CMD_SET_TV_FORMAT, | |
995 | &format, sizeof(format)); | |
7026d4ac ZW |
996 | } |
997 | ||
32aad86f CW |
998 | static bool |
999 | intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, | |
e811f5ae | 1000 | const struct drm_display_mode *mode) |
e2f0ba97 | 1001 | { |
32aad86f | 1002 | struct intel_sdvo_dtd output_dtd; |
79e53945 | 1003 | |
32aad86f CW |
1004 | if (!intel_sdvo_set_target_output(intel_sdvo, |
1005 | intel_sdvo->attached_output)) | |
1006 | return false; | |
e2f0ba97 | 1007 | |
32aad86f CW |
1008 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
1009 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) | |
1010 | return false; | |
e2f0ba97 | 1011 | |
32aad86f CW |
1012 | return true; |
1013 | } | |
1014 | ||
c9a29698 DV |
1015 | /* Asks the sdvo controller for the preferred input mode given the output mode. |
1016 | * Unfortunately we have to set up the full output mode to do that. */ | |
32aad86f | 1017 | static bool |
c9a29698 | 1018 | intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, |
e811f5ae | 1019 | const struct drm_display_mode *mode, |
c9a29698 | 1020 | struct drm_display_mode *adjusted_mode) |
32aad86f | 1021 | { |
c9a29698 DV |
1022 | struct intel_sdvo_dtd input_dtd; |
1023 | ||
32aad86f CW |
1024 | /* Reset the input timing to the screen. Assume always input 0. */ |
1025 | if (!intel_sdvo_set_target_input(intel_sdvo)) | |
1026 | return false; | |
e2f0ba97 | 1027 | |
32aad86f CW |
1028 | if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, |
1029 | mode->clock / 10, | |
1030 | mode->hdisplay, | |
1031 | mode->vdisplay)) | |
1032 | return false; | |
e2f0ba97 | 1033 | |
32aad86f | 1034 | if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, |
c9a29698 | 1035 | &input_dtd)) |
32aad86f | 1036 | return false; |
e2f0ba97 | 1037 | |
c9a29698 | 1038 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); |
e751823d | 1039 | intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; |
79e53945 | 1040 | |
32aad86f CW |
1041 | return true; |
1042 | } | |
12682a97 | 1043 | |
70484559 DV |
1044 | static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config) |
1045 | { | |
1046 | unsigned dotclock = pipe_config->adjusted_mode.clock; | |
1047 | struct dpll *clock = &pipe_config->dpll; | |
1048 | ||
1049 | /* SDVO TV has fixed PLL values depend on its clock range, | |
1050 | this mirrors vbios setting. */ | |
1051 | if (dotclock >= 100000 && dotclock < 140500) { | |
1052 | clock->p1 = 2; | |
1053 | clock->p2 = 10; | |
1054 | clock->n = 3; | |
1055 | clock->m1 = 16; | |
1056 | clock->m2 = 8; | |
1057 | } else if (dotclock >= 140500 && dotclock <= 200000) { | |
1058 | clock->p1 = 1; | |
1059 | clock->p2 = 10; | |
1060 | clock->n = 6; | |
1061 | clock->m1 = 12; | |
1062 | clock->m2 = 8; | |
1063 | } else { | |
1064 | WARN(1, "SDVO TV clock out of range: %i\n", dotclock); | |
1065 | } | |
1066 | ||
1067 | pipe_config->clock_set = true; | |
1068 | } | |
1069 | ||
6cc5f341 DV |
1070 | static bool intel_sdvo_compute_config(struct intel_encoder *encoder, |
1071 | struct intel_crtc_config *pipe_config) | |
32aad86f | 1072 | { |
6cc5f341 DV |
1073 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); |
1074 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; | |
1075 | struct drm_display_mode *mode = &pipe_config->requested_mode; | |
12682a97 | 1076 | |
5d2d38dd DV |
1077 | DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); |
1078 | pipe_config->pipe_bpp = 8*3; | |
1079 | ||
5bfe2ac0 DV |
1080 | if (HAS_PCH_SPLIT(encoder->base.dev)) |
1081 | pipe_config->has_pch_encoder = true; | |
1082 | ||
32aad86f CW |
1083 | /* We need to construct preferred input timings based on our |
1084 | * output timings. To do that, we have to set the output | |
1085 | * timings, even though this isn't really the right place in | |
1086 | * the sequence to do it. Oh well. | |
1087 | */ | |
1088 | if (intel_sdvo->is_tv) { | |
1089 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) | |
1090 | return false; | |
12682a97 | 1091 | |
c9a29698 DV |
1092 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
1093 | mode, | |
1094 | adjusted_mode); | |
ea5b213a | 1095 | } else if (intel_sdvo->is_lvds) { |
32aad86f | 1096 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, |
6c9547ff | 1097 | intel_sdvo->sdvo_lvds_fixed_mode)) |
e2f0ba97 | 1098 | return false; |
12682a97 | 1099 | |
c9a29698 DV |
1100 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
1101 | mode, | |
1102 | adjusted_mode); | |
e2f0ba97 | 1103 | } |
32aad86f CW |
1104 | |
1105 | /* Make the CRTC code factor in the SDVO pixel multiplier. The | |
6c9547ff | 1106 | * SDVO device will factor out the multiplier during mode_set. |
32aad86f | 1107 | */ |
6cc5f341 DV |
1108 | pipe_config->pixel_multiplier = |
1109 | intel_sdvo_get_pixel_multiplier(adjusted_mode); | |
1110 | adjusted_mode->clock *= pipe_config->pixel_multiplier; | |
32aad86f | 1111 | |
55bc60db VS |
1112 | if (intel_sdvo->color_range_auto) { |
1113 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
4f3a8bc7 PZ |
1114 | /* FIXME: This bit is only valid when using TMDS encoding and 8 |
1115 | * bit per color mode. */ | |
55bc60db | 1116 | if (intel_sdvo->has_hdmi_monitor && |
18316c8c | 1117 | drm_match_cea_mode(adjusted_mode) > 1) |
4f3a8bc7 | 1118 | intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; |
55bc60db VS |
1119 | else |
1120 | intel_sdvo->color_range = 0; | |
1121 | } | |
1122 | ||
3685a8f3 | 1123 | if (intel_sdvo->color_range) |
50f3b016 | 1124 | pipe_config->limited_color_range = true; |
3685a8f3 | 1125 | |
70484559 DV |
1126 | /* Clock computation needs to happen after pixel multiplier. */ |
1127 | if (intel_sdvo->is_tv) | |
1128 | i9xx_adjust_sdvo_tv_clock(pipe_config); | |
1129 | ||
e2f0ba97 JB |
1130 | return true; |
1131 | } | |
1132 | ||
6cc5f341 | 1133 | static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder) |
e2f0ba97 | 1134 | { |
6cc5f341 | 1135 | struct drm_device *dev = intel_encoder->base.dev; |
e2f0ba97 | 1136 | struct drm_i915_private *dev_priv = dev->dev_private; |
6cc5f341 | 1137 | struct drm_crtc *crtc = intel_encoder->base.crtc; |
e2f0ba97 | 1138 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6cc5f341 DV |
1139 | struct drm_display_mode *adjusted_mode = |
1140 | &intel_crtc->config.adjusted_mode; | |
1141 | struct drm_display_mode *mode = &intel_crtc->config.requested_mode; | |
1142 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(&intel_encoder->base); | |
6c9547ff | 1143 | u32 sdvox; |
e2f0ba97 | 1144 | struct intel_sdvo_in_out_map in_out; |
6651819b | 1145 | struct intel_sdvo_dtd input_dtd, output_dtd; |
6c9547ff | 1146 | int rate; |
e2f0ba97 JB |
1147 | |
1148 | if (!mode) | |
1149 | return; | |
1150 | ||
1151 | /* First, set the input mapping for the first input to our controlled | |
1152 | * output. This is only correct if we're a single-input device, in | |
1153 | * which case the first input is the output from the appropriate SDVO | |
1154 | * channel on the motherboard. In a two-input device, the first input | |
1155 | * will be SDVOB and the second SDVOC. | |
1156 | */ | |
ea5b213a | 1157 | in_out.in0 = intel_sdvo->attached_output; |
e2f0ba97 JB |
1158 | in_out.in1 = 0; |
1159 | ||
c74696b9 PR |
1160 | intel_sdvo_set_value(intel_sdvo, |
1161 | SDVO_CMD_SET_IN_OUT_MAP, | |
1162 | &in_out, sizeof(in_out)); | |
e2f0ba97 | 1163 | |
6c9547ff CW |
1164 | /* Set the output timings to the screen */ |
1165 | if (!intel_sdvo_set_target_output(intel_sdvo, | |
1166 | intel_sdvo->attached_output)) | |
1167 | return; | |
e2f0ba97 | 1168 | |
6651819b DV |
1169 | /* lvds has a special fixed output timing. */ |
1170 | if (intel_sdvo->is_lvds) | |
1171 | intel_sdvo_get_dtd_from_mode(&output_dtd, | |
1172 | intel_sdvo->sdvo_lvds_fixed_mode); | |
1173 | else | |
1174 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); | |
c8d4bb54 DV |
1175 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
1176 | DRM_INFO("Setting output timings on %s failed\n", | |
1177 | SDVO_NAME(intel_sdvo)); | |
79e53945 JB |
1178 | |
1179 | /* Set the input timing to the screen. Assume always input 0. */ | |
32aad86f CW |
1180 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
1181 | return; | |
79e53945 | 1182 | |
97aaf910 CW |
1183 | if (intel_sdvo->has_hdmi_monitor) { |
1184 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); | |
1185 | intel_sdvo_set_colorimetry(intel_sdvo, | |
1186 | SDVO_COLORIMETRY_RGB256); | |
abedc077 | 1187 | intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode); |
97aaf910 CW |
1188 | } else |
1189 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); | |
7026d4ac | 1190 | |
6c9547ff CW |
1191 | if (intel_sdvo->is_tv && |
1192 | !intel_sdvo_set_tv_format(intel_sdvo)) | |
1193 | return; | |
e2f0ba97 | 1194 | |
6651819b DV |
1195 | /* We have tried to get input timing in mode_fixup, and filled into |
1196 | * adjusted_mode. | |
1197 | */ | |
1198 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); | |
e751823d EE |
1199 | if (intel_sdvo->is_tv || intel_sdvo->is_lvds) |
1200 | input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; | |
c8d4bb54 DV |
1201 | if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) |
1202 | DRM_INFO("Setting input timings on %s failed\n", | |
1203 | SDVO_NAME(intel_sdvo)); | |
79e53945 | 1204 | |
6cc5f341 | 1205 | switch (intel_crtc->config.pixel_multiplier) { |
6c9547ff | 1206 | default: |
32aad86f CW |
1207 | case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; |
1208 | case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; | |
1209 | case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; | |
79e53945 | 1210 | } |
32aad86f CW |
1211 | if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) |
1212 | return; | |
79e53945 JB |
1213 | |
1214 | /* Set the SDVO control regs. */ | |
a6c45cf0 | 1215 | if (INTEL_INFO(dev)->gen >= 4) { |
ba68e086 PZ |
1216 | /* The real mode polarity is set by the SDVO commands, using |
1217 | * struct intel_sdvo_dtd. */ | |
1218 | sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; | |
3685a8f3 | 1219 | if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi) |
e953fd7b | 1220 | sdvox |= intel_sdvo->color_range; |
6714afb1 CW |
1221 | if (INTEL_INFO(dev)->gen < 5) |
1222 | sdvox |= SDVO_BORDER_ENABLE; | |
e2f0ba97 | 1223 | } else { |
6c9547ff | 1224 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
ea5b213a | 1225 | switch (intel_sdvo->sdvo_reg) { |
e2debe91 | 1226 | case GEN3_SDVOB: |
e2f0ba97 JB |
1227 | sdvox &= SDVOB_PRESERVE_MASK; |
1228 | break; | |
e2debe91 | 1229 | case GEN3_SDVOC: |
e2f0ba97 JB |
1230 | sdvox &= SDVOC_PRESERVE_MASK; |
1231 | break; | |
1232 | } | |
1233 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; | |
1234 | } | |
3573c410 PZ |
1235 | |
1236 | if (INTEL_PCH_TYPE(dev) >= PCH_CPT) | |
dc0fa718 | 1237 | sdvox |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe); |
3573c410 | 1238 | else |
dc0fa718 | 1239 | sdvox |= SDVO_PIPE_SEL(intel_crtc->pipe); |
3573c410 | 1240 | |
da79de97 | 1241 | if (intel_sdvo->has_hdmi_audio) |
6c9547ff | 1242 | sdvox |= SDVO_AUDIO_ENABLE; |
79e53945 | 1243 | |
a6c45cf0 | 1244 | if (INTEL_INFO(dev)->gen >= 4) { |
e2f0ba97 JB |
1245 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
1246 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { | |
1247 | /* done in crtc_mode_set as it lives inside the dpll register */ | |
79e53945 | 1248 | } else { |
6cc5f341 DV |
1249 | sdvox |= (intel_crtc->config.pixel_multiplier - 1) |
1250 | << SDVO_PORT_MULTIPLY_SHIFT; | |
79e53945 JB |
1251 | } |
1252 | ||
6714afb1 CW |
1253 | if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && |
1254 | INTEL_INFO(dev)->gen < 5) | |
12682a97 | 1255 | sdvox |= SDVO_STALL_SELECT; |
ea5b213a | 1256 | intel_sdvo_write_sdvox(intel_sdvo, sdvox); |
79e53945 JB |
1257 | } |
1258 | ||
4ac41f47 | 1259 | static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) |
79e53945 | 1260 | { |
4ac41f47 DV |
1261 | struct intel_sdvo_connector *intel_sdvo_connector = |
1262 | to_intel_sdvo_connector(&connector->base); | |
1263 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); | |
1264 | u16 active_outputs; | |
1265 | ||
1266 | intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); | |
1267 | ||
1268 | if (active_outputs & intel_sdvo_connector->output_flag) | |
1269 | return true; | |
1270 | else | |
1271 | return false; | |
1272 | } | |
1273 | ||
1274 | static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, | |
1275 | enum pipe *pipe) | |
1276 | { | |
1277 | struct drm_device *dev = encoder->base.dev; | |
79e53945 | 1278 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ac41f47 | 1279 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); |
7a7d1fb7 | 1280 | u16 active_outputs; |
4ac41f47 DV |
1281 | u32 tmp; |
1282 | ||
1283 | tmp = I915_READ(intel_sdvo->sdvo_reg); | |
7a7d1fb7 | 1284 | intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); |
4ac41f47 | 1285 | |
7a7d1fb7 | 1286 | if (!(tmp & SDVO_ENABLE) && (active_outputs == 0)) |
4ac41f47 DV |
1287 | return false; |
1288 | ||
1289 | if (HAS_PCH_CPT(dev)) | |
1290 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
1291 | else | |
1292 | *pipe = PORT_TO_PIPE(tmp); | |
1293 | ||
1294 | return true; | |
1295 | } | |
1296 | ||
ce22c320 DV |
1297 | static void intel_disable_sdvo(struct intel_encoder *encoder) |
1298 | { | |
1299 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
1300 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); | |
1301 | u32 temp; | |
1302 | ||
1303 | intel_sdvo_set_active_outputs(intel_sdvo, 0); | |
1304 | if (0) | |
1305 | intel_sdvo_set_encoder_power_state(intel_sdvo, | |
1306 | DRM_MODE_DPMS_OFF); | |
1307 | ||
1308 | temp = I915_READ(intel_sdvo->sdvo_reg); | |
1309 | if ((temp & SDVO_ENABLE) != 0) { | |
776ca7cf CW |
1310 | /* HW workaround for IBX, we need to move the port to |
1311 | * transcoder A before disabling it. */ | |
1312 | if (HAS_PCH_IBX(encoder->base.dev)) { | |
1313 | struct drm_crtc *crtc = encoder->base.crtc; | |
1314 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
1315 | ||
1316 | if (temp & SDVO_PIPE_B_SELECT) { | |
1317 | temp &= ~SDVO_PIPE_B_SELECT; | |
1318 | I915_WRITE(intel_sdvo->sdvo_reg, temp); | |
1319 | POSTING_READ(intel_sdvo->sdvo_reg); | |
1320 | ||
1321 | /* Again we need to write this twice. */ | |
1322 | I915_WRITE(intel_sdvo->sdvo_reg, temp); | |
1323 | POSTING_READ(intel_sdvo->sdvo_reg); | |
1324 | ||
1325 | /* Transcoder selection bits only update | |
1326 | * effectively on vblank. */ | |
1327 | if (crtc) | |
1328 | intel_wait_for_vblank(encoder->base.dev, pipe); | |
1329 | else | |
1330 | msleep(50); | |
1331 | } | |
1332 | } | |
1333 | ||
ce22c320 DV |
1334 | intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); |
1335 | } | |
1336 | } | |
1337 | ||
1338 | static void intel_enable_sdvo(struct intel_encoder *encoder) | |
1339 | { | |
1340 | struct drm_device *dev = encoder->base.dev; | |
1341 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1342 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); | |
1343 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
79e53945 | 1344 | u32 temp; |
ce22c320 DV |
1345 | bool input1, input2; |
1346 | int i; | |
1347 | u8 status; | |
1348 | ||
1349 | temp = I915_READ(intel_sdvo->sdvo_reg); | |
776ca7cf CW |
1350 | if ((temp & SDVO_ENABLE) == 0) { |
1351 | /* HW workaround for IBX, we need to move the port | |
dc0fa718 PZ |
1352 | * to transcoder A before disabling it, so restore it here. */ |
1353 | if (HAS_PCH_IBX(dev)) | |
1354 | temp |= SDVO_PIPE_SEL(intel_crtc->pipe); | |
776ca7cf | 1355 | |
ce22c320 | 1356 | intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); |
776ca7cf | 1357 | } |
ce22c320 DV |
1358 | for (i = 0; i < 2; i++) |
1359 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1360 | ||
1361 | status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); | |
1362 | /* Warn if the device reported failure to sync. | |
1363 | * A lot of SDVO devices fail to notify of sync, but it's | |
1364 | * a given it the status is a success, we succeeded. | |
1365 | */ | |
1366 | if (status == SDVO_CMD_STATUS_SUCCESS && !input1) { | |
1367 | DRM_DEBUG_KMS("First %s output reported failure to " | |
1368 | "sync\n", SDVO_NAME(intel_sdvo)); | |
1369 | } | |
1370 | ||
1371 | if (0) | |
1372 | intel_sdvo_set_encoder_power_state(intel_sdvo, | |
1373 | DRM_MODE_DPMS_ON); | |
1374 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); | |
1375 | } | |
1376 | ||
b2cabb0e | 1377 | static void intel_sdvo_dpms(struct drm_connector *connector, int mode) |
79e53945 | 1378 | { |
b2cabb0e DV |
1379 | struct drm_crtc *crtc; |
1380 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); | |
1381 | ||
1382 | /* dvo supports only 2 dpms states. */ | |
1383 | if (mode != DRM_MODE_DPMS_ON) | |
1384 | mode = DRM_MODE_DPMS_OFF; | |
1385 | ||
1386 | if (mode == connector->dpms) | |
1387 | return; | |
1388 | ||
1389 | connector->dpms = mode; | |
1390 | ||
1391 | /* Only need to change hw state when actually enabled */ | |
1392 | crtc = intel_sdvo->base.base.crtc; | |
1393 | if (!crtc) { | |
1394 | intel_sdvo->base.connectors_active = false; | |
1395 | return; | |
1396 | } | |
79e53945 JB |
1397 | |
1398 | if (mode != DRM_MODE_DPMS_ON) { | |
ea5b213a | 1399 | intel_sdvo_set_active_outputs(intel_sdvo, 0); |
79e53945 | 1400 | if (0) |
ea5b213a | 1401 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
79e53945 | 1402 | |
b2cabb0e DV |
1403 | intel_sdvo->base.connectors_active = false; |
1404 | ||
1405 | intel_crtc_update_dpms(crtc); | |
79e53945 | 1406 | } else { |
b2cabb0e DV |
1407 | intel_sdvo->base.connectors_active = true; |
1408 | ||
1409 | intel_crtc_update_dpms(crtc); | |
79e53945 JB |
1410 | |
1411 | if (0) | |
ea5b213a CW |
1412 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
1413 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); | |
79e53945 | 1414 | } |
0a91ca29 | 1415 | |
b980514c | 1416 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
1417 | } |
1418 | ||
79e53945 JB |
1419 | static int intel_sdvo_mode_valid(struct drm_connector *connector, |
1420 | struct drm_display_mode *mode) | |
1421 | { | |
df0e9248 | 1422 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
79e53945 JB |
1423 | |
1424 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1425 | return MODE_NO_DBLESCAN; | |
1426 | ||
ea5b213a | 1427 | if (intel_sdvo->pixel_clock_min > mode->clock) |
79e53945 JB |
1428 | return MODE_CLOCK_LOW; |
1429 | ||
ea5b213a | 1430 | if (intel_sdvo->pixel_clock_max < mode->clock) |
79e53945 JB |
1431 | return MODE_CLOCK_HIGH; |
1432 | ||
8545423a | 1433 | if (intel_sdvo->is_lvds) { |
ea5b213a | 1434 | if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) |
12682a97 | 1435 | return MODE_PANEL; |
1436 | ||
ea5b213a | 1437 | if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) |
12682a97 | 1438 | return MODE_PANEL; |
1439 | } | |
1440 | ||
79e53945 JB |
1441 | return MODE_OK; |
1442 | } | |
1443 | ||
ea5b213a | 1444 | static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) |
79e53945 | 1445 | { |
1a3665c8 | 1446 | BUILD_BUG_ON(sizeof(*caps) != 8); |
e957d772 CW |
1447 | if (!intel_sdvo_get_value(intel_sdvo, |
1448 | SDVO_CMD_GET_DEVICE_CAPS, | |
1449 | caps, sizeof(*caps))) | |
1450 | return false; | |
1451 | ||
1452 | DRM_DEBUG_KMS("SDVO capabilities:\n" | |
1453 | " vendor_id: %d\n" | |
1454 | " device_id: %d\n" | |
1455 | " device_rev_id: %d\n" | |
1456 | " sdvo_version_major: %d\n" | |
1457 | " sdvo_version_minor: %d\n" | |
1458 | " sdvo_inputs_mask: %d\n" | |
1459 | " smooth_scaling: %d\n" | |
1460 | " sharp_scaling: %d\n" | |
1461 | " up_scaling: %d\n" | |
1462 | " down_scaling: %d\n" | |
1463 | " stall_support: %d\n" | |
1464 | " output_flags: %d\n", | |
1465 | caps->vendor_id, | |
1466 | caps->device_id, | |
1467 | caps->device_rev_id, | |
1468 | caps->sdvo_version_major, | |
1469 | caps->sdvo_version_minor, | |
1470 | caps->sdvo_inputs_mask, | |
1471 | caps->smooth_scaling, | |
1472 | caps->sharp_scaling, | |
1473 | caps->up_scaling, | |
1474 | caps->down_scaling, | |
1475 | caps->stall_support, | |
1476 | caps->output_flags); | |
1477 | ||
1478 | return true; | |
79e53945 JB |
1479 | } |
1480 | ||
5fa7ac9c | 1481 | static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) |
79e53945 | 1482 | { |
768b107e | 1483 | struct drm_device *dev = intel_sdvo->base.base.dev; |
5fa7ac9c | 1484 | uint16_t hotplug; |
79e53945 | 1485 | |
768b107e DV |
1486 | /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise |
1487 | * on the line. */ | |
1488 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
5fa7ac9c | 1489 | return 0; |
768b107e | 1490 | |
5fa7ac9c JN |
1491 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, |
1492 | &hotplug, sizeof(hotplug))) | |
1493 | return 0; | |
768b107e | 1494 | |
5fa7ac9c | 1495 | return hotplug; |
79e53945 JB |
1496 | } |
1497 | ||
cc68c81a | 1498 | static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) |
79e53945 | 1499 | { |
cc68c81a | 1500 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base); |
79e53945 | 1501 | |
5fa7ac9c JN |
1502 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, |
1503 | &intel_sdvo->hotplug_active, 2); | |
79e53945 JB |
1504 | } |
1505 | ||
fb7a46f3 | 1506 | static bool |
ea5b213a | 1507 | intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) |
fb7a46f3 | 1508 | { |
bc65212c | 1509 | /* Is there more than one type of output? */ |
2294488d | 1510 | return hweight16(intel_sdvo->caps.output_flags) > 1; |
fb7a46f3 | 1511 | } |
1512 | ||
f899fc64 | 1513 | static struct edid * |
e957d772 | 1514 | intel_sdvo_get_edid(struct drm_connector *connector) |
f899fc64 | 1515 | { |
e957d772 CW |
1516 | struct intel_sdvo *sdvo = intel_attached_sdvo(connector); |
1517 | return drm_get_edid(connector, &sdvo->ddc); | |
f899fc64 CW |
1518 | } |
1519 | ||
ff482d83 CW |
1520 | /* Mac mini hack -- use the same DDC as the analog connector */ |
1521 | static struct edid * | |
1522 | intel_sdvo_get_analog_edid(struct drm_connector *connector) | |
1523 | { | |
f899fc64 | 1524 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
ff482d83 | 1525 | |
0c1dab89 | 1526 | return drm_get_edid(connector, |
3bd7d909 DK |
1527 | intel_gmbus_get_adapter(dev_priv, |
1528 | dev_priv->crt_ddc_pin)); | |
ff482d83 CW |
1529 | } |
1530 | ||
c43b5634 | 1531 | static enum drm_connector_status |
8bf38485 | 1532 | intel_sdvo_tmds_sink_detect(struct drm_connector *connector) |
9dff6af8 | 1533 | { |
df0e9248 | 1534 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
9d1a903d CW |
1535 | enum drm_connector_status status; |
1536 | struct edid *edid; | |
9dff6af8 | 1537 | |
e957d772 | 1538 | edid = intel_sdvo_get_edid(connector); |
57cdaf90 | 1539 | |
ea5b213a | 1540 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { |
e957d772 | 1541 | u8 ddc, saved_ddc = intel_sdvo->ddc_bus; |
9d1a903d | 1542 | |
7c3f0a27 ZY |
1543 | /* |
1544 | * Don't use the 1 as the argument of DDC bus switch to get | |
1545 | * the EDID. It is used for SDVO SPD ROM. | |
1546 | */ | |
9d1a903d | 1547 | for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { |
e957d772 CW |
1548 | intel_sdvo->ddc_bus = ddc; |
1549 | edid = intel_sdvo_get_edid(connector); | |
1550 | if (edid) | |
7c3f0a27 | 1551 | break; |
7c3f0a27 | 1552 | } |
e957d772 CW |
1553 | /* |
1554 | * If we found the EDID on the other bus, | |
1555 | * assume that is the correct DDC bus. | |
1556 | */ | |
1557 | if (edid == NULL) | |
1558 | intel_sdvo->ddc_bus = saved_ddc; | |
7c3f0a27 | 1559 | } |
9d1a903d CW |
1560 | |
1561 | /* | |
1562 | * When there is no edid and no monitor is connected with VGA | |
1563 | * port, try to use the CRT ddc to read the EDID for DVI-connector. | |
57cdaf90 | 1564 | */ |
ff482d83 CW |
1565 | if (edid == NULL) |
1566 | edid = intel_sdvo_get_analog_edid(connector); | |
149c36a3 | 1567 | |
2f551c84 | 1568 | status = connector_status_unknown; |
9dff6af8 | 1569 | if (edid != NULL) { |
149c36a3 | 1570 | /* DDC bus is shared, match EDID to connector type */ |
9d1a903d CW |
1571 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
1572 | status = connector_status_connected; | |
da79de97 CW |
1573 | if (intel_sdvo->is_hdmi) { |
1574 | intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); | |
1575 | intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); | |
abedc077 VS |
1576 | intel_sdvo->rgb_quant_range_selectable = |
1577 | drm_rgb_quant_range_selectable(edid); | |
da79de97 | 1578 | } |
13946743 CW |
1579 | } else |
1580 | status = connector_status_disconnected; | |
9d1a903d CW |
1581 | kfree(edid); |
1582 | } | |
7f36e7ed CW |
1583 | |
1584 | if (status == connector_status_connected) { | |
1585 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); | |
c3e5f67b DV |
1586 | if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) |
1587 | intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); | |
7f36e7ed CW |
1588 | } |
1589 | ||
2b8d33f7 | 1590 | return status; |
9dff6af8 ML |
1591 | } |
1592 | ||
52220085 CW |
1593 | static bool |
1594 | intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, | |
1595 | struct edid *edid) | |
1596 | { | |
1597 | bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); | |
1598 | bool connector_is_digital = !!IS_DIGITAL(sdvo); | |
1599 | ||
1600 | DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", | |
1601 | connector_is_digital, monitor_is_digital); | |
1602 | return connector_is_digital == monitor_is_digital; | |
1603 | } | |
1604 | ||
7b334fcb | 1605 | static enum drm_connector_status |
930a9e28 | 1606 | intel_sdvo_detect(struct drm_connector *connector, bool force) |
79e53945 | 1607 | { |
fb7a46f3 | 1608 | uint16_t response; |
df0e9248 | 1609 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
615fb93f | 1610 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
14571b4c | 1611 | enum drm_connector_status ret; |
79e53945 | 1612 | |
fc37381c CW |
1613 | if (!intel_sdvo_get_value(intel_sdvo, |
1614 | SDVO_CMD_GET_ATTACHED_DISPLAYS, | |
1615 | &response, 2)) | |
32aad86f | 1616 | return connector_status_unknown; |
79e53945 | 1617 | |
e957d772 CW |
1618 | DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", |
1619 | response & 0xff, response >> 8, | |
1620 | intel_sdvo_connector->output_flag); | |
e2f0ba97 | 1621 | |
fb7a46f3 | 1622 | if (response == 0) |
79e53945 | 1623 | return connector_status_disconnected; |
fb7a46f3 | 1624 | |
ea5b213a | 1625 | intel_sdvo->attached_output = response; |
14571b4c | 1626 | |
97aaf910 CW |
1627 | intel_sdvo->has_hdmi_monitor = false; |
1628 | intel_sdvo->has_hdmi_audio = false; | |
abedc077 | 1629 | intel_sdvo->rgb_quant_range_selectable = false; |
97aaf910 | 1630 | |
615fb93f | 1631 | if ((intel_sdvo_connector->output_flag & response) == 0) |
14571b4c | 1632 | ret = connector_status_disconnected; |
13946743 | 1633 | else if (IS_TMDS(intel_sdvo_connector)) |
8bf38485 | 1634 | ret = intel_sdvo_tmds_sink_detect(connector); |
13946743 CW |
1635 | else { |
1636 | struct edid *edid; | |
1637 | ||
1638 | /* if we have an edid check it matches the connection */ | |
1639 | edid = intel_sdvo_get_edid(connector); | |
1640 | if (edid == NULL) | |
1641 | edid = intel_sdvo_get_analog_edid(connector); | |
1642 | if (edid != NULL) { | |
52220085 CW |
1643 | if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, |
1644 | edid)) | |
13946743 | 1645 | ret = connector_status_connected; |
52220085 CW |
1646 | else |
1647 | ret = connector_status_disconnected; | |
1648 | ||
13946743 CW |
1649 | kfree(edid); |
1650 | } else | |
1651 | ret = connector_status_connected; | |
1652 | } | |
14571b4c ZW |
1653 | |
1654 | /* May update encoder flag for like clock for SDVO TV, etc.*/ | |
1655 | if (ret == connector_status_connected) { | |
ea5b213a CW |
1656 | intel_sdvo->is_tv = false; |
1657 | intel_sdvo->is_lvds = false; | |
1658 | intel_sdvo->base.needs_tv_clock = false; | |
14571b4c ZW |
1659 | |
1660 | if (response & SDVO_TV_MASK) { | |
ea5b213a CW |
1661 | intel_sdvo->is_tv = true; |
1662 | intel_sdvo->base.needs_tv_clock = true; | |
14571b4c ZW |
1663 | } |
1664 | if (response & SDVO_LVDS_MASK) | |
8545423a | 1665 | intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; |
fb7a46f3 | 1666 | } |
14571b4c ZW |
1667 | |
1668 | return ret; | |
79e53945 JB |
1669 | } |
1670 | ||
e2f0ba97 | 1671 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
79e53945 | 1672 | { |
ff482d83 | 1673 | struct edid *edid; |
79e53945 JB |
1674 | |
1675 | /* set the bus switch and get the modes */ | |
e957d772 | 1676 | edid = intel_sdvo_get_edid(connector); |
79e53945 | 1677 | |
57cdaf90 KP |
1678 | /* |
1679 | * Mac mini hack. On this device, the DVI-I connector shares one DDC | |
1680 | * link between analog and digital outputs. So, if the regular SDVO | |
1681 | * DDC fails, check to see if the analog output is disconnected, in | |
1682 | * which case we'll look there for the digital DDC data. | |
e2f0ba97 | 1683 | */ |
f899fc64 CW |
1684 | if (edid == NULL) |
1685 | edid = intel_sdvo_get_analog_edid(connector); | |
1686 | ||
ff482d83 | 1687 | if (edid != NULL) { |
52220085 CW |
1688 | if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), |
1689 | edid)) { | |
0c1dab89 CW |
1690 | drm_mode_connector_update_edid_property(connector, edid); |
1691 | drm_add_edid_modes(connector, edid); | |
1692 | } | |
13946743 | 1693 | |
ff482d83 | 1694 | kfree(edid); |
e2f0ba97 | 1695 | } |
e2f0ba97 JB |
1696 | } |
1697 | ||
1698 | /* | |
1699 | * Set of SDVO TV modes. | |
1700 | * Note! This is in reply order (see loop in get_tv_modes). | |
1701 | * XXX: all 60Hz refresh? | |
1702 | */ | |
b1f559ec | 1703 | static const struct drm_display_mode sdvo_tv_modes[] = { |
7026d4ac ZW |
1704 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
1705 | 416, 0, 200, 201, 232, 233, 0, | |
e2f0ba97 | 1706 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1707 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
1708 | 416, 0, 240, 241, 272, 273, 0, | |
e2f0ba97 | 1709 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1710 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
1711 | 496, 0, 300, 301, 332, 333, 0, | |
e2f0ba97 | 1712 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1713 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
1714 | 736, 0, 350, 351, 382, 383, 0, | |
e2f0ba97 | 1715 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1716 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
1717 | 736, 0, 400, 401, 432, 433, 0, | |
e2f0ba97 | 1718 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1719 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
1720 | 736, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1721 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1722 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
1723 | 800, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1724 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1725 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
1726 | 800, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1727 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1728 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
1729 | 816, 0, 350, 351, 382, 383, 0, | |
e2f0ba97 | 1730 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1731 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
1732 | 816, 0, 400, 401, 432, 433, 0, | |
e2f0ba97 | 1733 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1734 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
1735 | 816, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1736 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1737 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
1738 | 816, 0, 540, 541, 572, 573, 0, | |
e2f0ba97 | 1739 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1740 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
1741 | 816, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1742 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1743 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
1744 | 864, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1745 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1746 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
1747 | 896, 0, 600, 601, 632, 633, 0, | |
e2f0ba97 | 1748 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1749 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
1750 | 928, 0, 624, 625, 656, 657, 0, | |
e2f0ba97 | 1751 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1752 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
1753 | 1016, 0, 766, 767, 798, 799, 0, | |
e2f0ba97 | 1754 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1755 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
1756 | 1120, 0, 768, 769, 800, 801, 0, | |
e2f0ba97 | 1757 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1758 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
1759 | 1376, 0, 1024, 1025, 1056, 1057, 0, | |
e2f0ba97 JB |
1760 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1761 | }; | |
1762 | ||
1763 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) | |
1764 | { | |
df0e9248 | 1765 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
7026d4ac | 1766 | struct intel_sdvo_sdtv_resolution_request tv_res; |
ce6feabd ZY |
1767 | uint32_t reply = 0, format_map = 0; |
1768 | int i; | |
e2f0ba97 JB |
1769 | |
1770 | /* Read the list of supported input resolutions for the selected TV | |
1771 | * format. | |
1772 | */ | |
40039750 | 1773 | format_map = 1 << intel_sdvo->tv_format_index; |
ce6feabd | 1774 | memcpy(&tv_res, &format_map, |
32aad86f | 1775 | min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); |
ce6feabd | 1776 | |
32aad86f CW |
1777 | if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) |
1778 | return; | |
ce6feabd | 1779 | |
32aad86f | 1780 | BUILD_BUG_ON(sizeof(tv_res) != 3); |
e957d772 CW |
1781 | if (!intel_sdvo_write_cmd(intel_sdvo, |
1782 | SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, | |
32aad86f CW |
1783 | &tv_res, sizeof(tv_res))) |
1784 | return; | |
1785 | if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) | |
e2f0ba97 JB |
1786 | return; |
1787 | ||
1788 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) | |
7026d4ac ZW |
1789 | if (reply & (1 << i)) { |
1790 | struct drm_display_mode *nmode; | |
1791 | nmode = drm_mode_duplicate(connector->dev, | |
32aad86f | 1792 | &sdvo_tv_modes[i]); |
7026d4ac ZW |
1793 | if (nmode) |
1794 | drm_mode_probed_add(connector, nmode); | |
1795 | } | |
e2f0ba97 JB |
1796 | } |
1797 | ||
7086c87f ML |
1798 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
1799 | { | |
df0e9248 | 1800 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
7086c87f | 1801 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
12682a97 | 1802 | struct drm_display_mode *newmode; |
7086c87f ML |
1803 | |
1804 | /* | |
1805 | * Attempt to get the mode list from DDC. | |
1806 | * Assume that the preferred modes are | |
1807 | * arranged in priority order. | |
1808 | */ | |
f899fc64 | 1809 | intel_ddc_get_modes(connector, intel_sdvo->i2c); |
7086c87f | 1810 | if (list_empty(&connector->probed_modes) == false) |
12682a97 | 1811 | goto end; |
7086c87f ML |
1812 | |
1813 | /* Fetch modes from VBT */ | |
1814 | if (dev_priv->sdvo_lvds_vbt_mode != NULL) { | |
7086c87f ML |
1815 | newmode = drm_mode_duplicate(connector->dev, |
1816 | dev_priv->sdvo_lvds_vbt_mode); | |
1817 | if (newmode != NULL) { | |
1818 | /* Guarantee the mode is preferred */ | |
1819 | newmode->type = (DRM_MODE_TYPE_PREFERRED | | |
1820 | DRM_MODE_TYPE_DRIVER); | |
1821 | drm_mode_probed_add(connector, newmode); | |
1822 | } | |
1823 | } | |
12682a97 | 1824 | |
1825 | end: | |
1826 | list_for_each_entry(newmode, &connector->probed_modes, head) { | |
1827 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { | |
ea5b213a | 1828 | intel_sdvo->sdvo_lvds_fixed_mode = |
12682a97 | 1829 | drm_mode_duplicate(connector->dev, newmode); |
6c9547ff | 1830 | |
8545423a | 1831 | intel_sdvo->is_lvds = true; |
12682a97 | 1832 | break; |
1833 | } | |
1834 | } | |
1835 | ||
7086c87f ML |
1836 | } |
1837 | ||
e2f0ba97 JB |
1838 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
1839 | { | |
615fb93f | 1840 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
e2f0ba97 | 1841 | |
615fb93f | 1842 | if (IS_TV(intel_sdvo_connector)) |
e2f0ba97 | 1843 | intel_sdvo_get_tv_modes(connector); |
615fb93f | 1844 | else if (IS_LVDS(intel_sdvo_connector)) |
7086c87f | 1845 | intel_sdvo_get_lvds_modes(connector); |
e2f0ba97 JB |
1846 | else |
1847 | intel_sdvo_get_ddc_modes(connector); | |
1848 | ||
32aad86f | 1849 | return !list_empty(&connector->probed_modes); |
79e53945 JB |
1850 | } |
1851 | ||
fcc8d672 CW |
1852 | static void |
1853 | intel_sdvo_destroy_enhance_property(struct drm_connector *connector) | |
b9219c5e | 1854 | { |
615fb93f | 1855 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
b9219c5e ZY |
1856 | struct drm_device *dev = connector->dev; |
1857 | ||
c5521706 CW |
1858 | if (intel_sdvo_connector->left) |
1859 | drm_property_destroy(dev, intel_sdvo_connector->left); | |
1860 | if (intel_sdvo_connector->right) | |
1861 | drm_property_destroy(dev, intel_sdvo_connector->right); | |
1862 | if (intel_sdvo_connector->top) | |
1863 | drm_property_destroy(dev, intel_sdvo_connector->top); | |
1864 | if (intel_sdvo_connector->bottom) | |
1865 | drm_property_destroy(dev, intel_sdvo_connector->bottom); | |
1866 | if (intel_sdvo_connector->hpos) | |
1867 | drm_property_destroy(dev, intel_sdvo_connector->hpos); | |
1868 | if (intel_sdvo_connector->vpos) | |
1869 | drm_property_destroy(dev, intel_sdvo_connector->vpos); | |
1870 | if (intel_sdvo_connector->saturation) | |
1871 | drm_property_destroy(dev, intel_sdvo_connector->saturation); | |
1872 | if (intel_sdvo_connector->contrast) | |
1873 | drm_property_destroy(dev, intel_sdvo_connector->contrast); | |
1874 | if (intel_sdvo_connector->hue) | |
1875 | drm_property_destroy(dev, intel_sdvo_connector->hue); | |
1876 | if (intel_sdvo_connector->sharpness) | |
1877 | drm_property_destroy(dev, intel_sdvo_connector->sharpness); | |
1878 | if (intel_sdvo_connector->flicker_filter) | |
1879 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter); | |
1880 | if (intel_sdvo_connector->flicker_filter_2d) | |
1881 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d); | |
1882 | if (intel_sdvo_connector->flicker_filter_adaptive) | |
1883 | drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive); | |
1884 | if (intel_sdvo_connector->tv_luma_filter) | |
1885 | drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter); | |
1886 | if (intel_sdvo_connector->tv_chroma_filter) | |
1887 | drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter); | |
e044218a CW |
1888 | if (intel_sdvo_connector->dot_crawl) |
1889 | drm_property_destroy(dev, intel_sdvo_connector->dot_crawl); | |
c5521706 CW |
1890 | if (intel_sdvo_connector->brightness) |
1891 | drm_property_destroy(dev, intel_sdvo_connector->brightness); | |
b9219c5e ZY |
1892 | } |
1893 | ||
79e53945 JB |
1894 | static void intel_sdvo_destroy(struct drm_connector *connector) |
1895 | { | |
615fb93f | 1896 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
79e53945 | 1897 | |
c5521706 | 1898 | if (intel_sdvo_connector->tv_format) |
ce6feabd | 1899 | drm_property_destroy(connector->dev, |
c5521706 | 1900 | intel_sdvo_connector->tv_format); |
b9219c5e | 1901 | |
d2a82a6f | 1902 | intel_sdvo_destroy_enhance_property(connector); |
79e53945 JB |
1903 | drm_sysfs_connector_remove(connector); |
1904 | drm_connector_cleanup(connector); | |
4b745b1e | 1905 | kfree(intel_sdvo_connector); |
79e53945 JB |
1906 | } |
1907 | ||
1aad7ac0 CW |
1908 | static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) |
1909 | { | |
1910 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); | |
1911 | struct edid *edid; | |
1912 | bool has_audio = false; | |
1913 | ||
1914 | if (!intel_sdvo->is_hdmi) | |
1915 | return false; | |
1916 | ||
1917 | edid = intel_sdvo_get_edid(connector); | |
1918 | if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) | |
1919 | has_audio = drm_detect_monitor_audio(edid); | |
38ab8a20 | 1920 | kfree(edid); |
1aad7ac0 CW |
1921 | |
1922 | return has_audio; | |
1923 | } | |
1924 | ||
ce6feabd ZY |
1925 | static int |
1926 | intel_sdvo_set_property(struct drm_connector *connector, | |
1927 | struct drm_property *property, | |
1928 | uint64_t val) | |
1929 | { | |
df0e9248 | 1930 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
615fb93f | 1931 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
e953fd7b | 1932 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
b9219c5e | 1933 | uint16_t temp_value; |
32aad86f CW |
1934 | uint8_t cmd; |
1935 | int ret; | |
ce6feabd | 1936 | |
662595df | 1937 | ret = drm_object_property_set_value(&connector->base, property, val); |
32aad86f CW |
1938 | if (ret) |
1939 | return ret; | |
ce6feabd | 1940 | |
3f43c48d | 1941 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
1942 | int i = val; |
1943 | bool has_audio; | |
1944 | ||
1945 | if (i == intel_sdvo_connector->force_audio) | |
7f36e7ed CW |
1946 | return 0; |
1947 | ||
1aad7ac0 | 1948 | intel_sdvo_connector->force_audio = i; |
7f36e7ed | 1949 | |
c3e5f67b | 1950 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
1951 | has_audio = intel_sdvo_detect_hdmi_audio(connector); |
1952 | else | |
c3e5f67b | 1953 | has_audio = (i == HDMI_AUDIO_ON); |
7f36e7ed | 1954 | |
1aad7ac0 | 1955 | if (has_audio == intel_sdvo->has_hdmi_audio) |
7f36e7ed | 1956 | return 0; |
7f36e7ed | 1957 | |
1aad7ac0 | 1958 | intel_sdvo->has_hdmi_audio = has_audio; |
7f36e7ed CW |
1959 | goto done; |
1960 | } | |
1961 | ||
e953fd7b | 1962 | if (property == dev_priv->broadcast_rgb_property) { |
55bc60db VS |
1963 | switch (val) { |
1964 | case INTEL_BROADCAST_RGB_AUTO: | |
1965 | intel_sdvo->color_range_auto = true; | |
1966 | break; | |
1967 | case INTEL_BROADCAST_RGB_FULL: | |
1968 | intel_sdvo->color_range_auto = false; | |
1969 | intel_sdvo->color_range = 0; | |
1970 | break; | |
1971 | case INTEL_BROADCAST_RGB_LIMITED: | |
1972 | intel_sdvo->color_range_auto = false; | |
4f3a8bc7 PZ |
1973 | /* FIXME: this bit is only valid when using TMDS |
1974 | * encoding and 8 bit per color mode. */ | |
1975 | intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; | |
55bc60db VS |
1976 | break; |
1977 | default: | |
1978 | return -EINVAL; | |
1979 | } | |
7f36e7ed CW |
1980 | goto done; |
1981 | } | |
1982 | ||
c5521706 CW |
1983 | #define CHECK_PROPERTY(name, NAME) \ |
1984 | if (intel_sdvo_connector->name == property) { \ | |
1985 | if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ | |
1986 | if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ | |
1987 | cmd = SDVO_CMD_SET_##NAME; \ | |
1988 | intel_sdvo_connector->cur_##name = temp_value; \ | |
1989 | goto set_value; \ | |
1990 | } | |
1991 | ||
1992 | if (property == intel_sdvo_connector->tv_format) { | |
32aad86f CW |
1993 | if (val >= TV_FORMAT_NUM) |
1994 | return -EINVAL; | |
1995 | ||
40039750 | 1996 | if (intel_sdvo->tv_format_index == |
615fb93f | 1997 | intel_sdvo_connector->tv_format_supported[val]) |
32aad86f | 1998 | return 0; |
ce6feabd | 1999 | |
40039750 | 2000 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; |
c5521706 | 2001 | goto done; |
32aad86f | 2002 | } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { |
b9219c5e | 2003 | temp_value = val; |
c5521706 | 2004 | if (intel_sdvo_connector->left == property) { |
662595df | 2005 | drm_object_property_set_value(&connector->base, |
c5521706 | 2006 | intel_sdvo_connector->right, val); |
615fb93f | 2007 | if (intel_sdvo_connector->left_margin == temp_value) |
32aad86f | 2008 | return 0; |
b9219c5e | 2009 | |
615fb93f CW |
2010 | intel_sdvo_connector->left_margin = temp_value; |
2011 | intel_sdvo_connector->right_margin = temp_value; | |
2012 | temp_value = intel_sdvo_connector->max_hscan - | |
c5521706 | 2013 | intel_sdvo_connector->left_margin; |
b9219c5e | 2014 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
c5521706 CW |
2015 | goto set_value; |
2016 | } else if (intel_sdvo_connector->right == property) { | |
662595df | 2017 | drm_object_property_set_value(&connector->base, |
c5521706 | 2018 | intel_sdvo_connector->left, val); |
615fb93f | 2019 | if (intel_sdvo_connector->right_margin == temp_value) |
32aad86f | 2020 | return 0; |
b9219c5e | 2021 | |
615fb93f CW |
2022 | intel_sdvo_connector->left_margin = temp_value; |
2023 | intel_sdvo_connector->right_margin = temp_value; | |
2024 | temp_value = intel_sdvo_connector->max_hscan - | |
2025 | intel_sdvo_connector->left_margin; | |
b9219c5e | 2026 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
c5521706 CW |
2027 | goto set_value; |
2028 | } else if (intel_sdvo_connector->top == property) { | |
662595df | 2029 | drm_object_property_set_value(&connector->base, |
c5521706 | 2030 | intel_sdvo_connector->bottom, val); |
615fb93f | 2031 | if (intel_sdvo_connector->top_margin == temp_value) |
32aad86f | 2032 | return 0; |
b9219c5e | 2033 | |
615fb93f CW |
2034 | intel_sdvo_connector->top_margin = temp_value; |
2035 | intel_sdvo_connector->bottom_margin = temp_value; | |
2036 | temp_value = intel_sdvo_connector->max_vscan - | |
c5521706 | 2037 | intel_sdvo_connector->top_margin; |
b9219c5e | 2038 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
c5521706 CW |
2039 | goto set_value; |
2040 | } else if (intel_sdvo_connector->bottom == property) { | |
662595df | 2041 | drm_object_property_set_value(&connector->base, |
c5521706 | 2042 | intel_sdvo_connector->top, val); |
615fb93f | 2043 | if (intel_sdvo_connector->bottom_margin == temp_value) |
32aad86f CW |
2044 | return 0; |
2045 | ||
615fb93f CW |
2046 | intel_sdvo_connector->top_margin = temp_value; |
2047 | intel_sdvo_connector->bottom_margin = temp_value; | |
2048 | temp_value = intel_sdvo_connector->max_vscan - | |
c5521706 | 2049 | intel_sdvo_connector->top_margin; |
b9219c5e | 2050 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
c5521706 CW |
2051 | goto set_value; |
2052 | } | |
2053 | CHECK_PROPERTY(hpos, HPOS) | |
2054 | CHECK_PROPERTY(vpos, VPOS) | |
2055 | CHECK_PROPERTY(saturation, SATURATION) | |
2056 | CHECK_PROPERTY(contrast, CONTRAST) | |
2057 | CHECK_PROPERTY(hue, HUE) | |
2058 | CHECK_PROPERTY(brightness, BRIGHTNESS) | |
2059 | CHECK_PROPERTY(sharpness, SHARPNESS) | |
2060 | CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) | |
2061 | CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) | |
2062 | CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) | |
2063 | CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) | |
2064 | CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) | |
e044218a | 2065 | CHECK_PROPERTY(dot_crawl, DOT_CRAWL) |
c5521706 | 2066 | } |
b9219c5e | 2067 | |
c5521706 | 2068 | return -EINVAL; /* unknown property */ |
b9219c5e | 2069 | |
c5521706 CW |
2070 | set_value: |
2071 | if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) | |
2072 | return -EIO; | |
b9219c5e | 2073 | |
b9219c5e | 2074 | |
c5521706 | 2075 | done: |
c0c36b94 CW |
2076 | if (intel_sdvo->base.base.crtc) |
2077 | intel_crtc_restore_mode(intel_sdvo->base.base.crtc); | |
c5521706 | 2078 | |
32aad86f | 2079 | return 0; |
c5521706 | 2080 | #undef CHECK_PROPERTY |
ce6feabd ZY |
2081 | } |
2082 | ||
79e53945 | 2083 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { |
b2cabb0e | 2084 | .dpms = intel_sdvo_dpms, |
79e53945 JB |
2085 | .detect = intel_sdvo_detect, |
2086 | .fill_modes = drm_helper_probe_single_connector_modes, | |
ce6feabd | 2087 | .set_property = intel_sdvo_set_property, |
79e53945 JB |
2088 | .destroy = intel_sdvo_destroy, |
2089 | }; | |
2090 | ||
2091 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { | |
2092 | .get_modes = intel_sdvo_get_modes, | |
2093 | .mode_valid = intel_sdvo_mode_valid, | |
df0e9248 | 2094 | .best_encoder = intel_best_encoder, |
79e53945 JB |
2095 | }; |
2096 | ||
b358d0a6 | 2097 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
79e53945 | 2098 | { |
890f3359 | 2099 | struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder); |
d2a82a6f | 2100 | |
ea5b213a | 2101 | if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) |
d2a82a6f | 2102 | drm_mode_destroy(encoder->dev, |
ea5b213a | 2103 | intel_sdvo->sdvo_lvds_fixed_mode); |
d2a82a6f | 2104 | |
e957d772 | 2105 | i2c_del_adapter(&intel_sdvo->ddc); |
ea5b213a | 2106 | intel_encoder_destroy(encoder); |
79e53945 JB |
2107 | } |
2108 | ||
2109 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { | |
2110 | .destroy = intel_sdvo_enc_destroy, | |
2111 | }; | |
2112 | ||
b66d8424 CW |
2113 | static void |
2114 | intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) | |
2115 | { | |
2116 | uint16_t mask = 0; | |
2117 | unsigned int num_bits; | |
2118 | ||
2119 | /* Make a mask of outputs less than or equal to our own priority in the | |
2120 | * list. | |
2121 | */ | |
2122 | switch (sdvo->controlled_output) { | |
2123 | case SDVO_OUTPUT_LVDS1: | |
2124 | mask |= SDVO_OUTPUT_LVDS1; | |
2125 | case SDVO_OUTPUT_LVDS0: | |
2126 | mask |= SDVO_OUTPUT_LVDS0; | |
2127 | case SDVO_OUTPUT_TMDS1: | |
2128 | mask |= SDVO_OUTPUT_TMDS1; | |
2129 | case SDVO_OUTPUT_TMDS0: | |
2130 | mask |= SDVO_OUTPUT_TMDS0; | |
2131 | case SDVO_OUTPUT_RGB1: | |
2132 | mask |= SDVO_OUTPUT_RGB1; | |
2133 | case SDVO_OUTPUT_RGB0: | |
2134 | mask |= SDVO_OUTPUT_RGB0; | |
2135 | break; | |
2136 | } | |
2137 | ||
2138 | /* Count bits to find what number we are in the priority list. */ | |
2139 | mask &= sdvo->caps.output_flags; | |
2140 | num_bits = hweight16(mask); | |
2141 | /* If more than 3 outputs, default to DDC bus 3 for now. */ | |
2142 | if (num_bits > 3) | |
2143 | num_bits = 3; | |
2144 | ||
2145 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ | |
2146 | sdvo->ddc_bus = 1 << num_bits; | |
2147 | } | |
79e53945 | 2148 | |
e2f0ba97 JB |
2149 | /** |
2150 | * Choose the appropriate DDC bus for control bus switch command for this | |
2151 | * SDVO output based on the controlled output. | |
2152 | * | |
2153 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS | |
2154 | * outputs, then LVDS outputs. | |
2155 | */ | |
2156 | static void | |
b1083333 | 2157 | intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, |
ea5b213a | 2158 | struct intel_sdvo *sdvo, u32 reg) |
e2f0ba97 | 2159 | { |
b1083333 | 2160 | struct sdvo_device_mapping *mapping; |
e2f0ba97 | 2161 | |
eef4eacb | 2162 | if (sdvo->is_sdvob) |
b1083333 AJ |
2163 | mapping = &(dev_priv->sdvo_mappings[0]); |
2164 | else | |
2165 | mapping = &(dev_priv->sdvo_mappings[1]); | |
e2f0ba97 | 2166 | |
b66d8424 CW |
2167 | if (mapping->initialized) |
2168 | sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); | |
2169 | else | |
2170 | intel_sdvo_guess_ddc_bus(sdvo); | |
e2f0ba97 JB |
2171 | } |
2172 | ||
e957d772 CW |
2173 | static void |
2174 | intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, | |
2175 | struct intel_sdvo *sdvo, u32 reg) | |
2176 | { | |
2177 | struct sdvo_device_mapping *mapping; | |
46eb3036 | 2178 | u8 pin; |
e957d772 | 2179 | |
eef4eacb | 2180 | if (sdvo->is_sdvob) |
e957d772 CW |
2181 | mapping = &dev_priv->sdvo_mappings[0]; |
2182 | else | |
2183 | mapping = &dev_priv->sdvo_mappings[1]; | |
2184 | ||
6cb1612a | 2185 | if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin)) |
e957d772 | 2186 | pin = mapping->i2c_pin; |
6cb1612a JN |
2187 | else |
2188 | pin = GMBUS_PORT_DPB; | |
e957d772 | 2189 | |
6cb1612a JN |
2190 | sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); |
2191 | ||
2192 | /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow | |
2193 | * our code totally fails once we start using gmbus. Hence fall back to | |
2194 | * bit banging for now. */ | |
2195 | intel_gmbus_force_bit(sdvo->i2c, true); | |
e957d772 CW |
2196 | } |
2197 | ||
fbfcc4f3 JN |
2198 | /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ |
2199 | static void | |
2200 | intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) | |
2201 | { | |
2202 | intel_gmbus_force_bit(sdvo->i2c, false); | |
e957d772 CW |
2203 | } |
2204 | ||
e2f0ba97 | 2205 | static bool |
e27d8538 | 2206 | intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) |
e2f0ba97 | 2207 | { |
97aaf910 | 2208 | return intel_sdvo_check_supp_encode(intel_sdvo); |
e2f0ba97 JB |
2209 | } |
2210 | ||
714605e4 | 2211 | static u8 |
eef4eacb | 2212 | intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) |
714605e4 | 2213 | { |
2214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2215 | struct sdvo_device_mapping *my_mapping, *other_mapping; | |
2216 | ||
eef4eacb | 2217 | if (sdvo->is_sdvob) { |
714605e4 | 2218 | my_mapping = &dev_priv->sdvo_mappings[0]; |
2219 | other_mapping = &dev_priv->sdvo_mappings[1]; | |
2220 | } else { | |
2221 | my_mapping = &dev_priv->sdvo_mappings[1]; | |
2222 | other_mapping = &dev_priv->sdvo_mappings[0]; | |
2223 | } | |
2224 | ||
2225 | /* If the BIOS described our SDVO device, take advantage of it. */ | |
2226 | if (my_mapping->slave_addr) | |
2227 | return my_mapping->slave_addr; | |
2228 | ||
2229 | /* If the BIOS only described a different SDVO device, use the | |
2230 | * address that it isn't using. | |
2231 | */ | |
2232 | if (other_mapping->slave_addr) { | |
2233 | if (other_mapping->slave_addr == 0x70) | |
2234 | return 0x72; | |
2235 | else | |
2236 | return 0x70; | |
2237 | } | |
2238 | ||
2239 | /* No SDVO device info is found for another DVO port, | |
2240 | * so use mapping assumption we had before BIOS parsing. | |
2241 | */ | |
eef4eacb | 2242 | if (sdvo->is_sdvob) |
714605e4 | 2243 | return 0x70; |
2244 | else | |
2245 | return 0x72; | |
2246 | } | |
2247 | ||
14571b4c | 2248 | static void |
df0e9248 CW |
2249 | intel_sdvo_connector_init(struct intel_sdvo_connector *connector, |
2250 | struct intel_sdvo *encoder) | |
14571b4c | 2251 | { |
df0e9248 CW |
2252 | drm_connector_init(encoder->base.base.dev, |
2253 | &connector->base.base, | |
2254 | &intel_sdvo_connector_funcs, | |
2255 | connector->base.base.connector_type); | |
6070a4a9 | 2256 | |
df0e9248 CW |
2257 | drm_connector_helper_add(&connector->base.base, |
2258 | &intel_sdvo_connector_helper_funcs); | |
14571b4c | 2259 | |
8f4839e2 | 2260 | connector->base.base.interlace_allowed = 1; |
df0e9248 CW |
2261 | connector->base.base.doublescan_allowed = 0; |
2262 | connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; | |
4ac41f47 | 2263 | connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; |
14571b4c | 2264 | |
df0e9248 CW |
2265 | intel_connector_attach_encoder(&connector->base, &encoder->base); |
2266 | drm_sysfs_connector_add(&connector->base.base); | |
14571b4c | 2267 | } |
6070a4a9 | 2268 | |
7f36e7ed | 2269 | static void |
55bc60db VS |
2270 | intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, |
2271 | struct intel_sdvo_connector *connector) | |
7f36e7ed CW |
2272 | { |
2273 | struct drm_device *dev = connector->base.base.dev; | |
2274 | ||
3f43c48d | 2275 | intel_attach_force_audio_property(&connector->base.base); |
55bc60db | 2276 | if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { |
e953fd7b | 2277 | intel_attach_broadcast_rgb_property(&connector->base.base); |
55bc60db VS |
2278 | intel_sdvo->color_range_auto = true; |
2279 | } | |
7f36e7ed CW |
2280 | } |
2281 | ||
fb7a46f3 | 2282 | static bool |
ea5b213a | 2283 | intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) |
fb7a46f3 | 2284 | { |
4ef69c7a | 2285 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
14571b4c | 2286 | struct drm_connector *connector; |
cc68c81a | 2287 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
14571b4c | 2288 | struct intel_connector *intel_connector; |
615fb93f | 2289 | struct intel_sdvo_connector *intel_sdvo_connector; |
14571b4c | 2290 | |
615fb93f CW |
2291 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
2292 | if (!intel_sdvo_connector) | |
14571b4c ZW |
2293 | return false; |
2294 | ||
14571b4c | 2295 | if (device == 0) { |
ea5b213a | 2296 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; |
615fb93f | 2297 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; |
14571b4c | 2298 | } else if (device == 1) { |
ea5b213a | 2299 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; |
615fb93f | 2300 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; |
14571b4c ZW |
2301 | } |
2302 | ||
615fb93f | 2303 | intel_connector = &intel_sdvo_connector->base; |
14571b4c | 2304 | connector = &intel_connector->base; |
5fa7ac9c JN |
2305 | if (intel_sdvo_get_hotplug_support(intel_sdvo) & |
2306 | intel_sdvo_connector->output_flag) { | |
5fa7ac9c | 2307 | intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; |
cc68c81a SF |
2308 | /* Some SDVO devices have one-shot hotplug interrupts. |
2309 | * Ensure that they get re-enabled when an interrupt happens. | |
2310 | */ | |
2311 | intel_encoder->hot_plug = intel_sdvo_enable_hotplug; | |
2312 | intel_sdvo_enable_hotplug(intel_encoder); | |
5fa7ac9c | 2313 | } else { |
821450c6 | 2314 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; |
5fa7ac9c | 2315 | } |
14571b4c ZW |
2316 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; |
2317 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; | |
2318 | ||
e27d8538 | 2319 | if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { |
14571b4c | 2320 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; |
e27d8538 | 2321 | intel_sdvo->is_hdmi = true; |
14571b4c | 2322 | } |
14571b4c | 2323 | |
df0e9248 | 2324 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
f797d221 | 2325 | if (intel_sdvo->is_hdmi) |
55bc60db | 2326 | intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); |
14571b4c ZW |
2327 | |
2328 | return true; | |
2329 | } | |
2330 | ||
2331 | static bool | |
ea5b213a | 2332 | intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) |
14571b4c | 2333 | { |
4ef69c7a CW |
2334 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2335 | struct drm_connector *connector; | |
2336 | struct intel_connector *intel_connector; | |
2337 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2338 | |
615fb93f CW |
2339 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
2340 | if (!intel_sdvo_connector) | |
2341 | return false; | |
14571b4c | 2342 | |
615fb93f | 2343 | intel_connector = &intel_sdvo_connector->base; |
4ef69c7a CW |
2344 | connector = &intel_connector->base; |
2345 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; | |
2346 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; | |
14571b4c | 2347 | |
4ef69c7a CW |
2348 | intel_sdvo->controlled_output |= type; |
2349 | intel_sdvo_connector->output_flag = type; | |
14571b4c | 2350 | |
4ef69c7a CW |
2351 | intel_sdvo->is_tv = true; |
2352 | intel_sdvo->base.needs_tv_clock = true; | |
14571b4c | 2353 | |
df0e9248 | 2354 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
14571b4c | 2355 | |
4ef69c7a | 2356 | if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) |
32aad86f | 2357 | goto err; |
14571b4c | 2358 | |
4ef69c7a | 2359 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
32aad86f | 2360 | goto err; |
14571b4c | 2361 | |
4ef69c7a | 2362 | return true; |
32aad86f CW |
2363 | |
2364 | err: | |
123d5c01 | 2365 | intel_sdvo_destroy(connector); |
32aad86f | 2366 | return false; |
14571b4c ZW |
2367 | } |
2368 | ||
2369 | static bool | |
ea5b213a | 2370 | intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) |
14571b4c | 2371 | { |
4ef69c7a CW |
2372 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2373 | struct drm_connector *connector; | |
2374 | struct intel_connector *intel_connector; | |
2375 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2376 | |
615fb93f CW |
2377 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
2378 | if (!intel_sdvo_connector) | |
2379 | return false; | |
14571b4c | 2380 | |
615fb93f | 2381 | intel_connector = &intel_sdvo_connector->base; |
4ef69c7a | 2382 | connector = &intel_connector->base; |
821450c6 | 2383 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
4ef69c7a CW |
2384 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; |
2385 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; | |
2386 | ||
2387 | if (device == 0) { | |
2388 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; | |
2389 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; | |
2390 | } else if (device == 1) { | |
2391 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; | |
2392 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; | |
2393 | } | |
2394 | ||
df0e9248 CW |
2395 | intel_sdvo_connector_init(intel_sdvo_connector, |
2396 | intel_sdvo); | |
4ef69c7a | 2397 | return true; |
14571b4c ZW |
2398 | } |
2399 | ||
2400 | static bool | |
ea5b213a | 2401 | intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) |
14571b4c | 2402 | { |
4ef69c7a CW |
2403 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2404 | struct drm_connector *connector; | |
2405 | struct intel_connector *intel_connector; | |
2406 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2407 | |
615fb93f CW |
2408 | intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL); |
2409 | if (!intel_sdvo_connector) | |
2410 | return false; | |
14571b4c | 2411 | |
615fb93f CW |
2412 | intel_connector = &intel_sdvo_connector->base; |
2413 | connector = &intel_connector->base; | |
4ef69c7a CW |
2414 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; |
2415 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; | |
2416 | ||
2417 | if (device == 0) { | |
2418 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; | |
2419 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; | |
2420 | } else if (device == 1) { | |
2421 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; | |
2422 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; | |
2423 | } | |
2424 | ||
df0e9248 | 2425 | intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo); |
4ef69c7a | 2426 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
32aad86f CW |
2427 | goto err; |
2428 | ||
2429 | return true; | |
2430 | ||
2431 | err: | |
123d5c01 | 2432 | intel_sdvo_destroy(connector); |
32aad86f | 2433 | return false; |
14571b4c ZW |
2434 | } |
2435 | ||
2436 | static bool | |
ea5b213a | 2437 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) |
14571b4c | 2438 | { |
ea5b213a CW |
2439 | intel_sdvo->is_tv = false; |
2440 | intel_sdvo->base.needs_tv_clock = false; | |
2441 | intel_sdvo->is_lvds = false; | |
fb7a46f3 | 2442 | |
14571b4c | 2443 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ |
fb7a46f3 | 2444 | |
14571b4c | 2445 | if (flags & SDVO_OUTPUT_TMDS0) |
ea5b213a | 2446 | if (!intel_sdvo_dvi_init(intel_sdvo, 0)) |
14571b4c ZW |
2447 | return false; |
2448 | ||
2449 | if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) | |
ea5b213a | 2450 | if (!intel_sdvo_dvi_init(intel_sdvo, 1)) |
14571b4c ZW |
2451 | return false; |
2452 | ||
2453 | /* TV has no XXX1 function block */ | |
a1f4b7ff | 2454 | if (flags & SDVO_OUTPUT_SVID0) |
ea5b213a | 2455 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) |
14571b4c ZW |
2456 | return false; |
2457 | ||
2458 | if (flags & SDVO_OUTPUT_CVBS0) | |
ea5b213a | 2459 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) |
14571b4c | 2460 | return false; |
fb7a46f3 | 2461 | |
a0b1c7a5 CW |
2462 | if (flags & SDVO_OUTPUT_YPRPB0) |
2463 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) | |
2464 | return false; | |
2465 | ||
14571b4c | 2466 | if (flags & SDVO_OUTPUT_RGB0) |
ea5b213a | 2467 | if (!intel_sdvo_analog_init(intel_sdvo, 0)) |
14571b4c ZW |
2468 | return false; |
2469 | ||
2470 | if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) | |
ea5b213a | 2471 | if (!intel_sdvo_analog_init(intel_sdvo, 1)) |
14571b4c ZW |
2472 | return false; |
2473 | ||
2474 | if (flags & SDVO_OUTPUT_LVDS0) | |
ea5b213a | 2475 | if (!intel_sdvo_lvds_init(intel_sdvo, 0)) |
14571b4c ZW |
2476 | return false; |
2477 | ||
2478 | if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) | |
ea5b213a | 2479 | if (!intel_sdvo_lvds_init(intel_sdvo, 1)) |
14571b4c | 2480 | return false; |
fb7a46f3 | 2481 | |
14571b4c | 2482 | if ((flags & SDVO_OUTPUT_MASK) == 0) { |
fb7a46f3 | 2483 | unsigned char bytes[2]; |
2484 | ||
ea5b213a CW |
2485 | intel_sdvo->controlled_output = 0; |
2486 | memcpy(bytes, &intel_sdvo->caps.output_flags, 2); | |
51c8b407 | 2487 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", |
ea5b213a | 2488 | SDVO_NAME(intel_sdvo), |
51c8b407 | 2489 | bytes[0], bytes[1]); |
14571b4c | 2490 | return false; |
fb7a46f3 | 2491 | } |
27f8227b | 2492 | intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
fb7a46f3 | 2493 | |
14571b4c | 2494 | return true; |
fb7a46f3 | 2495 | } |
2496 | ||
d0ddfbd3 JN |
2497 | static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) |
2498 | { | |
2499 | struct drm_device *dev = intel_sdvo->base.base.dev; | |
2500 | struct drm_connector *connector, *tmp; | |
2501 | ||
2502 | list_for_each_entry_safe(connector, tmp, | |
2503 | &dev->mode_config.connector_list, head) { | |
2504 | if (intel_attached_encoder(connector) == &intel_sdvo->base) | |
2505 | intel_sdvo_destroy(connector); | |
2506 | } | |
2507 | } | |
2508 | ||
32aad86f CW |
2509 | static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
2510 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2511 | int type) | |
ce6feabd | 2512 | { |
4ef69c7a | 2513 | struct drm_device *dev = intel_sdvo->base.base.dev; |
ce6feabd ZY |
2514 | struct intel_sdvo_tv_format format; |
2515 | uint32_t format_map, i; | |
ce6feabd | 2516 | |
32aad86f CW |
2517 | if (!intel_sdvo_set_target_output(intel_sdvo, type)) |
2518 | return false; | |
ce6feabd | 2519 | |
1a3665c8 | 2520 | BUILD_BUG_ON(sizeof(format) != 6); |
32aad86f CW |
2521 | if (!intel_sdvo_get_value(intel_sdvo, |
2522 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, | |
2523 | &format, sizeof(format))) | |
2524 | return false; | |
ce6feabd | 2525 | |
32aad86f | 2526 | memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); |
ce6feabd ZY |
2527 | |
2528 | if (format_map == 0) | |
32aad86f | 2529 | return false; |
ce6feabd | 2530 | |
615fb93f | 2531 | intel_sdvo_connector->format_supported_num = 0; |
ce6feabd | 2532 | for (i = 0 ; i < TV_FORMAT_NUM; i++) |
40039750 CW |
2533 | if (format_map & (1 << i)) |
2534 | intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; | |
ce6feabd ZY |
2535 | |
2536 | ||
c5521706 | 2537 | intel_sdvo_connector->tv_format = |
32aad86f CW |
2538 | drm_property_create(dev, DRM_MODE_PROP_ENUM, |
2539 | "mode", intel_sdvo_connector->format_supported_num); | |
c5521706 | 2540 | if (!intel_sdvo_connector->tv_format) |
fcc8d672 | 2541 | return false; |
ce6feabd | 2542 | |
615fb93f | 2543 | for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) |
ce6feabd | 2544 | drm_property_add_enum( |
c5521706 | 2545 | intel_sdvo_connector->tv_format, i, |
40039750 | 2546 | i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); |
ce6feabd | 2547 | |
40039750 | 2548 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; |
662595df | 2549 | drm_object_attach_property(&intel_sdvo_connector->base.base.base, |
c5521706 | 2550 | intel_sdvo_connector->tv_format, 0); |
32aad86f | 2551 | return true; |
ce6feabd ZY |
2552 | |
2553 | } | |
2554 | ||
c5521706 CW |
2555 | #define ENHANCEMENT(name, NAME) do { \ |
2556 | if (enhancements.name) { \ | |
2557 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ | |
2558 | !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ | |
2559 | return false; \ | |
2560 | intel_sdvo_connector->max_##name = data_value[0]; \ | |
2561 | intel_sdvo_connector->cur_##name = response; \ | |
2562 | intel_sdvo_connector->name = \ | |
d9bc3c02 | 2563 | drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ |
c5521706 | 2564 | if (!intel_sdvo_connector->name) return false; \ |
662595df | 2565 | drm_object_attach_property(&connector->base, \ |
c5521706 CW |
2566 | intel_sdvo_connector->name, \ |
2567 | intel_sdvo_connector->cur_##name); \ | |
2568 | DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ | |
2569 | data_value[0], data_value[1], response); \ | |
2570 | } \ | |
0206e353 | 2571 | } while (0) |
c5521706 CW |
2572 | |
2573 | static bool | |
2574 | intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, | |
2575 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2576 | struct intel_sdvo_enhancements_reply enhancements) | |
b9219c5e | 2577 | { |
4ef69c7a | 2578 | struct drm_device *dev = intel_sdvo->base.base.dev; |
32aad86f | 2579 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
b9219c5e ZY |
2580 | uint16_t response, data_value[2]; |
2581 | ||
c5521706 CW |
2582 | /* when horizontal overscan is supported, Add the left/right property */ |
2583 | if (enhancements.overscan_h) { | |
2584 | if (!intel_sdvo_get_value(intel_sdvo, | |
2585 | SDVO_CMD_GET_MAX_OVERSCAN_H, | |
2586 | &data_value, 4)) | |
2587 | return false; | |
32aad86f | 2588 | |
c5521706 CW |
2589 | if (!intel_sdvo_get_value(intel_sdvo, |
2590 | SDVO_CMD_GET_OVERSCAN_H, | |
2591 | &response, 2)) | |
2592 | return false; | |
fcc8d672 | 2593 | |
c5521706 CW |
2594 | intel_sdvo_connector->max_hscan = data_value[0]; |
2595 | intel_sdvo_connector->left_margin = data_value[0] - response; | |
2596 | intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; | |
2597 | intel_sdvo_connector->left = | |
d9bc3c02 | 2598 | drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); |
c5521706 CW |
2599 | if (!intel_sdvo_connector->left) |
2600 | return false; | |
fcc8d672 | 2601 | |
662595df | 2602 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2603 | intel_sdvo_connector->left, |
2604 | intel_sdvo_connector->left_margin); | |
fcc8d672 | 2605 | |
c5521706 | 2606 | intel_sdvo_connector->right = |
d9bc3c02 | 2607 | drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); |
c5521706 CW |
2608 | if (!intel_sdvo_connector->right) |
2609 | return false; | |
32aad86f | 2610 | |
662595df | 2611 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2612 | intel_sdvo_connector->right, |
2613 | intel_sdvo_connector->right_margin); | |
2614 | DRM_DEBUG_KMS("h_overscan: max %d, " | |
2615 | "default %d, current %d\n", | |
2616 | data_value[0], data_value[1], response); | |
2617 | } | |
32aad86f | 2618 | |
c5521706 CW |
2619 | if (enhancements.overscan_v) { |
2620 | if (!intel_sdvo_get_value(intel_sdvo, | |
2621 | SDVO_CMD_GET_MAX_OVERSCAN_V, | |
2622 | &data_value, 4)) | |
2623 | return false; | |
fcc8d672 | 2624 | |
c5521706 CW |
2625 | if (!intel_sdvo_get_value(intel_sdvo, |
2626 | SDVO_CMD_GET_OVERSCAN_V, | |
2627 | &response, 2)) | |
2628 | return false; | |
32aad86f | 2629 | |
c5521706 CW |
2630 | intel_sdvo_connector->max_vscan = data_value[0]; |
2631 | intel_sdvo_connector->top_margin = data_value[0] - response; | |
2632 | intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; | |
2633 | intel_sdvo_connector->top = | |
d9bc3c02 SH |
2634 | drm_property_create_range(dev, 0, |
2635 | "top_margin", 0, data_value[0]); | |
c5521706 CW |
2636 | if (!intel_sdvo_connector->top) |
2637 | return false; | |
32aad86f | 2638 | |
662595df | 2639 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2640 | intel_sdvo_connector->top, |
2641 | intel_sdvo_connector->top_margin); | |
fcc8d672 | 2642 | |
c5521706 | 2643 | intel_sdvo_connector->bottom = |
d9bc3c02 SH |
2644 | drm_property_create_range(dev, 0, |
2645 | "bottom_margin", 0, data_value[0]); | |
c5521706 CW |
2646 | if (!intel_sdvo_connector->bottom) |
2647 | return false; | |
32aad86f | 2648 | |
662595df | 2649 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2650 | intel_sdvo_connector->bottom, |
2651 | intel_sdvo_connector->bottom_margin); | |
2652 | DRM_DEBUG_KMS("v_overscan: max %d, " | |
2653 | "default %d, current %d\n", | |
2654 | data_value[0], data_value[1], response); | |
2655 | } | |
32aad86f | 2656 | |
c5521706 CW |
2657 | ENHANCEMENT(hpos, HPOS); |
2658 | ENHANCEMENT(vpos, VPOS); | |
2659 | ENHANCEMENT(saturation, SATURATION); | |
2660 | ENHANCEMENT(contrast, CONTRAST); | |
2661 | ENHANCEMENT(hue, HUE); | |
2662 | ENHANCEMENT(sharpness, SHARPNESS); | |
2663 | ENHANCEMENT(brightness, BRIGHTNESS); | |
2664 | ENHANCEMENT(flicker_filter, FLICKER_FILTER); | |
2665 | ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); | |
2666 | ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); | |
2667 | ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); | |
2668 | ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); | |
fcc8d672 | 2669 | |
e044218a CW |
2670 | if (enhancements.dot_crawl) { |
2671 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) | |
2672 | return false; | |
2673 | ||
2674 | intel_sdvo_connector->max_dot_crawl = 1; | |
2675 | intel_sdvo_connector->cur_dot_crawl = response & 0x1; | |
2676 | intel_sdvo_connector->dot_crawl = | |
d9bc3c02 | 2677 | drm_property_create_range(dev, 0, "dot_crawl", 0, 1); |
e044218a CW |
2678 | if (!intel_sdvo_connector->dot_crawl) |
2679 | return false; | |
2680 | ||
662595df | 2681 | drm_object_attach_property(&connector->base, |
e044218a CW |
2682 | intel_sdvo_connector->dot_crawl, |
2683 | intel_sdvo_connector->cur_dot_crawl); | |
2684 | DRM_DEBUG_KMS("dot crawl: current %d\n", response); | |
2685 | } | |
2686 | ||
c5521706 CW |
2687 | return true; |
2688 | } | |
32aad86f | 2689 | |
c5521706 CW |
2690 | static bool |
2691 | intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, | |
2692 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2693 | struct intel_sdvo_enhancements_reply enhancements) | |
2694 | { | |
4ef69c7a | 2695 | struct drm_device *dev = intel_sdvo->base.base.dev; |
c5521706 CW |
2696 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
2697 | uint16_t response, data_value[2]; | |
32aad86f | 2698 | |
c5521706 | 2699 | ENHANCEMENT(brightness, BRIGHTNESS); |
fcc8d672 | 2700 | |
c5521706 CW |
2701 | return true; |
2702 | } | |
2703 | #undef ENHANCEMENT | |
32aad86f | 2704 | |
c5521706 CW |
2705 | static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
2706 | struct intel_sdvo_connector *intel_sdvo_connector) | |
2707 | { | |
2708 | union { | |
2709 | struct intel_sdvo_enhancements_reply reply; | |
2710 | uint16_t response; | |
2711 | } enhancements; | |
32aad86f | 2712 | |
1a3665c8 CW |
2713 | BUILD_BUG_ON(sizeof(enhancements) != 2); |
2714 | ||
cf9a2f3a CW |
2715 | enhancements.response = 0; |
2716 | intel_sdvo_get_value(intel_sdvo, | |
2717 | SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, | |
2718 | &enhancements, sizeof(enhancements)); | |
c5521706 CW |
2719 | if (enhancements.response == 0) { |
2720 | DRM_DEBUG_KMS("No enhancement is supported\n"); | |
2721 | return true; | |
b9219c5e | 2722 | } |
32aad86f | 2723 | |
c5521706 CW |
2724 | if (IS_TV(intel_sdvo_connector)) |
2725 | return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); | |
0206e353 | 2726 | else if (IS_LVDS(intel_sdvo_connector)) |
c5521706 CW |
2727 | return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
2728 | else | |
2729 | return true; | |
e957d772 CW |
2730 | } |
2731 | ||
2732 | static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, | |
2733 | struct i2c_msg *msgs, | |
2734 | int num) | |
2735 | { | |
2736 | struct intel_sdvo *sdvo = adapter->algo_data; | |
fcc8d672 | 2737 | |
e957d772 CW |
2738 | if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) |
2739 | return -EIO; | |
2740 | ||
2741 | return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); | |
2742 | } | |
2743 | ||
2744 | static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) | |
2745 | { | |
2746 | struct intel_sdvo *sdvo = adapter->algo_data; | |
2747 | return sdvo->i2c->algo->functionality(sdvo->i2c); | |
2748 | } | |
2749 | ||
2750 | static const struct i2c_algorithm intel_sdvo_ddc_proxy = { | |
2751 | .master_xfer = intel_sdvo_ddc_proxy_xfer, | |
2752 | .functionality = intel_sdvo_ddc_proxy_func | |
2753 | }; | |
2754 | ||
2755 | static bool | |
2756 | intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, | |
2757 | struct drm_device *dev) | |
2758 | { | |
2759 | sdvo->ddc.owner = THIS_MODULE; | |
2760 | sdvo->ddc.class = I2C_CLASS_DDC; | |
2761 | snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); | |
2762 | sdvo->ddc.dev.parent = &dev->pdev->dev; | |
2763 | sdvo->ddc.algo_data = sdvo; | |
2764 | sdvo->ddc.algo = &intel_sdvo_ddc_proxy; | |
2765 | ||
2766 | return i2c_add_adapter(&sdvo->ddc) == 0; | |
b9219c5e ZY |
2767 | } |
2768 | ||
eef4eacb | 2769 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) |
79e53945 | 2770 | { |
b01f2c3a | 2771 | struct drm_i915_private *dev_priv = dev->dev_private; |
21d40d37 | 2772 | struct intel_encoder *intel_encoder; |
ea5b213a | 2773 | struct intel_sdvo *intel_sdvo; |
084b612e | 2774 | u32 hotplug_mask; |
79e53945 | 2775 | int i; |
ea5b213a CW |
2776 | intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL); |
2777 | if (!intel_sdvo) | |
7d57382e | 2778 | return false; |
79e53945 | 2779 | |
56184e3d | 2780 | intel_sdvo->sdvo_reg = sdvo_reg; |
eef4eacb DV |
2781 | intel_sdvo->is_sdvob = is_sdvob; |
2782 | intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; | |
56184e3d | 2783 | intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg); |
fbfcc4f3 JN |
2784 | if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) |
2785 | goto err_i2c_bus; | |
e957d772 | 2786 | |
56184e3d | 2787 | /* encoder type will be decided later */ |
ea5b213a | 2788 | intel_encoder = &intel_sdvo->base; |
21d40d37 | 2789 | intel_encoder->type = INTEL_OUTPUT_SDVO; |
373a3cf7 | 2790 | drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); |
79e53945 | 2791 | |
79e53945 JB |
2792 | /* Read the regs to test if we can talk to the device */ |
2793 | for (i = 0; i < 0x40; i++) { | |
f899fc64 CW |
2794 | u8 byte; |
2795 | ||
2796 | if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { | |
eef4eacb DV |
2797 | DRM_DEBUG_KMS("No SDVO device found on %s\n", |
2798 | SDVO_NAME(intel_sdvo)); | |
f899fc64 | 2799 | goto err; |
79e53945 JB |
2800 | } |
2801 | } | |
2802 | ||
084b612e CW |
2803 | hotplug_mask = 0; |
2804 | if (IS_G4X(dev)) { | |
2805 | hotplug_mask = intel_sdvo->is_sdvob ? | |
2806 | SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X; | |
2807 | } else if (IS_GEN4(dev)) { | |
2808 | hotplug_mask = intel_sdvo->is_sdvob ? | |
2809 | SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965; | |
2810 | } else { | |
2811 | hotplug_mask = intel_sdvo->is_sdvob ? | |
2812 | SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915; | |
2813 | } | |
619ac3b7 | 2814 | |
4f770a5b EE |
2815 | /* Only enable the hotplug irq if we need it, to work around noisy |
2816 | * hotplug lines. | |
2817 | */ | |
1d843f9d EE |
2818 | if (intel_sdvo->hotplug_active) |
2819 | intel_encoder->hpd_pin = HPD_SDVO_B ? HPD_SDVO_B : HPD_SDVO_C; | |
2820 | ||
6cc5f341 | 2821 | intel_encoder->compute_config = intel_sdvo_compute_config; |
ce22c320 | 2822 | intel_encoder->disable = intel_disable_sdvo; |
6cc5f341 | 2823 | intel_encoder->mode_set = intel_sdvo_mode_set; |
ce22c320 | 2824 | intel_encoder->enable = intel_enable_sdvo; |
4ac41f47 | 2825 | intel_encoder->get_hw_state = intel_sdvo_get_hw_state; |
ce22c320 | 2826 | |
af901ca1 | 2827 | /* In default case sdvo lvds is false */ |
32aad86f | 2828 | if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) |
f899fc64 | 2829 | goto err; |
79e53945 | 2830 | |
ea5b213a CW |
2831 | if (intel_sdvo_output_setup(intel_sdvo, |
2832 | intel_sdvo->caps.output_flags) != true) { | |
eef4eacb DV |
2833 | DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", |
2834 | SDVO_NAME(intel_sdvo)); | |
d0ddfbd3 JN |
2835 | /* Output_setup can leave behind connectors! */ |
2836 | goto err_output; | |
79e53945 JB |
2837 | } |
2838 | ||
e506d6fd DV |
2839 | /* |
2840 | * Cloning SDVO with anything is often impossible, since the SDVO | |
2841 | * encoder can request a special input timing mode. And even if that's | |
2842 | * not the case we have evidence that cloning a plain unscaled mode with | |
2843 | * VGA doesn't really work. Furthermore the cloning flags are way too | |
2844 | * simplistic anyway to express such constraints, so just give up on | |
2845 | * cloning for SDVO encoders. | |
2846 | */ | |
2847 | intel_sdvo->base.cloneable = false; | |
2848 | ||
ea5b213a | 2849 | intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); |
e2f0ba97 | 2850 | |
79e53945 | 2851 | /* Set the input timing to the screen. Assume always input 0. */ |
32aad86f | 2852 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
d0ddfbd3 | 2853 | goto err_output; |
79e53945 | 2854 | |
32aad86f CW |
2855 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
2856 | &intel_sdvo->pixel_clock_min, | |
2857 | &intel_sdvo->pixel_clock_max)) | |
d0ddfbd3 | 2858 | goto err_output; |
79e53945 | 2859 | |
8a4c47f3 | 2860 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
342dc382 | 2861 | "clock range %dMHz - %dMHz, " |
2862 | "input 1: %c, input 2: %c, " | |
2863 | "output 1: %c, output 2: %c\n", | |
ea5b213a CW |
2864 | SDVO_NAME(intel_sdvo), |
2865 | intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, | |
2866 | intel_sdvo->caps.device_rev_id, | |
2867 | intel_sdvo->pixel_clock_min / 1000, | |
2868 | intel_sdvo->pixel_clock_max / 1000, | |
2869 | (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', | |
2870 | (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', | |
342dc382 | 2871 | /* check currently supported outputs */ |
ea5b213a | 2872 | intel_sdvo->caps.output_flags & |
79e53945 | 2873 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
ea5b213a | 2874 | intel_sdvo->caps.output_flags & |
79e53945 | 2875 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
7d57382e | 2876 | return true; |
79e53945 | 2877 | |
d0ddfbd3 JN |
2878 | err_output: |
2879 | intel_sdvo_output_cleanup(intel_sdvo); | |
2880 | ||
f899fc64 | 2881 | err: |
373a3cf7 | 2882 | drm_encoder_cleanup(&intel_encoder->base); |
e957d772 | 2883 | i2c_del_adapter(&intel_sdvo->ddc); |
fbfcc4f3 JN |
2884 | err_i2c_bus: |
2885 | intel_sdvo_unselect_i2c_bus(intel_sdvo); | |
ea5b213a | 2886 | kfree(intel_sdvo); |
79e53945 | 2887 | |
7d57382e | 2888 | return false; |
79e53945 | 2889 | } |