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79e53945 JB |
1 | /* |
2 | * Copyright 2006 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright © 2006-2007 Intel Corporation | |
4 | * Jesse Barnes <jesse.barnes@intel.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | |
7 | * copy of this software and associated documentation files (the "Software"), | |
8 | * to deal in the Software without restriction, including without limitation | |
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
10 | * and/or sell copies of the Software, and to permit persons to whom the | |
11 | * Software is furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the next | |
14 | * paragraph) shall be included in all copies or substantial portions of the | |
15 | * Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
23 | * DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | * Authors: | |
26 | * Eric Anholt <eric@anholt.net> | |
27 | */ | |
28 | #include <linux/i2c.h> | |
5a0e3ad6 | 29 | #include <linux/slab.h> |
79e53945 | 30 | #include <linux/delay.h> |
2d1a8a48 | 31 | #include <linux/export.h> |
760285e7 | 32 | #include <drm/drmP.h> |
c6f95f27 | 33 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
34 | #include <drm/drm_crtc.h> |
35 | #include <drm/drm_edid.h> | |
ea5b213a | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 JB |
38 | #include "i915_drv.h" |
39 | #include "intel_sdvo_regs.h" | |
40 | ||
14571b4c ZW |
41 | #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1) |
42 | #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1) | |
43 | #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1) | |
a0b1c7a5 | 44 | #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0) |
14571b4c ZW |
45 | |
46 | #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\ | |
0206e353 | 47 | SDVO_TV_MASK) |
14571b4c ZW |
48 | |
49 | #define IS_TV(c) (c->output_flag & SDVO_TV_MASK) | |
13946743 | 50 | #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK) |
14571b4c | 51 | #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK) |
32aad86f | 52 | #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK)) |
52220085 | 53 | #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK)) |
14571b4c | 54 | |
79e53945 | 55 | |
2e88e40b | 56 | static const char *tv_format_names[] = { |
ce6feabd ZY |
57 | "NTSC_M" , "NTSC_J" , "NTSC_443", |
58 | "PAL_B" , "PAL_D" , "PAL_G" , | |
59 | "PAL_H" , "PAL_I" , "PAL_M" , | |
60 | "PAL_N" , "PAL_NC" , "PAL_60" , | |
61 | "SECAM_B" , "SECAM_D" , "SECAM_G" , | |
62 | "SECAM_K" , "SECAM_K1", "SECAM_L" , | |
63 | "SECAM_60" | |
64 | }; | |
65 | ||
66 | #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names)) | |
67 | ||
ea5b213a CW |
68 | struct intel_sdvo { |
69 | struct intel_encoder base; | |
70 | ||
f899fc64 | 71 | struct i2c_adapter *i2c; |
f9c10a9b | 72 | u8 slave_addr; |
e2f0ba97 | 73 | |
e957d772 CW |
74 | struct i2c_adapter ddc; |
75 | ||
e2f0ba97 | 76 | /* Register for the SDVO device: SDVOB or SDVOC */ |
eef4eacb | 77 | uint32_t sdvo_reg; |
79e53945 | 78 | |
e2f0ba97 JB |
79 | /* Active outputs controlled by this SDVO output */ |
80 | uint16_t controlled_output; | |
79e53945 | 81 | |
e2f0ba97 JB |
82 | /* |
83 | * Capabilities of the SDVO device returned by | |
19d415a2 | 84 | * intel_sdvo_get_capabilities() |
e2f0ba97 | 85 | */ |
79e53945 | 86 | struct intel_sdvo_caps caps; |
e2f0ba97 JB |
87 | |
88 | /* Pixel clock limitations reported by the SDVO device, in kHz */ | |
79e53945 JB |
89 | int pixel_clock_min, pixel_clock_max; |
90 | ||
fb7a46f3 | 91 | /* |
92 | * For multiple function SDVO device, | |
93 | * this is for current attached outputs. | |
94 | */ | |
95 | uint16_t attached_output; | |
96 | ||
cc68c81a SF |
97 | /* |
98 | * Hotplug activation bits for this device | |
99 | */ | |
5fa7ac9c | 100 | uint16_t hotplug_active; |
cc68c81a | 101 | |
e953fd7b CW |
102 | /** |
103 | * This is used to select the color range of RBG outputs in HDMI mode. | |
104 | * It is only valid when using TMDS encoding and 8 bit per color mode. | |
105 | */ | |
106 | uint32_t color_range; | |
55bc60db | 107 | bool color_range_auto; |
e953fd7b | 108 | |
e2f0ba97 JB |
109 | /** |
110 | * This is set if we're going to treat the device as TV-out. | |
111 | * | |
112 | * While we have these nice friendly flags for output types that ought | |
113 | * to decide this for us, the S-Video output on our HDMI+S-Video card | |
114 | * shows up as RGB1 (VGA). | |
115 | */ | |
116 | bool is_tv; | |
117 | ||
eef4eacb DV |
118 | /* On different gens SDVOB is at different places. */ |
119 | bool is_sdvob; | |
120 | ||
ce6feabd | 121 | /* This is for current tv format name */ |
40039750 | 122 | int tv_format_index; |
ce6feabd | 123 | |
e2f0ba97 JB |
124 | /** |
125 | * This is set if we treat the device as HDMI, instead of DVI. | |
126 | */ | |
127 | bool is_hdmi; | |
da79de97 CW |
128 | bool has_hdmi_monitor; |
129 | bool has_hdmi_audio; | |
abedc077 | 130 | bool rgb_quant_range_selectable; |
12682a97 | 131 | |
7086c87f | 132 | /** |
6c9547ff CW |
133 | * This is set if we detect output of sdvo device as LVDS and |
134 | * have a valid fixed mode to use with the panel. | |
7086c87f ML |
135 | */ |
136 | bool is_lvds; | |
e2f0ba97 | 137 | |
12682a97 | 138 | /** |
139 | * This is sdvo fixed pannel mode pointer | |
140 | */ | |
141 | struct drm_display_mode *sdvo_lvds_fixed_mode; | |
142 | ||
c751ce4f | 143 | /* DDC bus used by this SDVO encoder */ |
e2f0ba97 | 144 | uint8_t ddc_bus; |
e751823d EE |
145 | |
146 | /* | |
147 | * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd | |
148 | */ | |
149 | uint8_t dtd_sdvo_flags; | |
14571b4c ZW |
150 | }; |
151 | ||
152 | struct intel_sdvo_connector { | |
615fb93f CW |
153 | struct intel_connector base; |
154 | ||
14571b4c ZW |
155 | /* Mark the type of connector */ |
156 | uint16_t output_flag; | |
157 | ||
c3e5f67b | 158 | enum hdmi_force_audio force_audio; |
7f36e7ed | 159 | |
14571b4c | 160 | /* This contains all current supported TV format */ |
40039750 | 161 | u8 tv_format_supported[TV_FORMAT_NUM]; |
14571b4c | 162 | int format_supported_num; |
c5521706 | 163 | struct drm_property *tv_format; |
14571b4c | 164 | |
b9219c5e | 165 | /* add the property for the SDVO-TV */ |
c5521706 CW |
166 | struct drm_property *left; |
167 | struct drm_property *right; | |
168 | struct drm_property *top; | |
169 | struct drm_property *bottom; | |
170 | struct drm_property *hpos; | |
171 | struct drm_property *vpos; | |
172 | struct drm_property *contrast; | |
173 | struct drm_property *saturation; | |
174 | struct drm_property *hue; | |
175 | struct drm_property *sharpness; | |
176 | struct drm_property *flicker_filter; | |
177 | struct drm_property *flicker_filter_adaptive; | |
178 | struct drm_property *flicker_filter_2d; | |
179 | struct drm_property *tv_chroma_filter; | |
180 | struct drm_property *tv_luma_filter; | |
e044218a | 181 | struct drm_property *dot_crawl; |
b9219c5e ZY |
182 | |
183 | /* add the property for the SDVO-TV/LVDS */ | |
c5521706 | 184 | struct drm_property *brightness; |
b9219c5e ZY |
185 | |
186 | /* Add variable to record current setting for the above property */ | |
187 | u32 left_margin, right_margin, top_margin, bottom_margin; | |
c5521706 | 188 | |
b9219c5e ZY |
189 | /* this is to get the range of margin.*/ |
190 | u32 max_hscan, max_vscan; | |
191 | u32 max_hpos, cur_hpos; | |
192 | u32 max_vpos, cur_vpos; | |
193 | u32 cur_brightness, max_brightness; | |
194 | u32 cur_contrast, max_contrast; | |
195 | u32 cur_saturation, max_saturation; | |
196 | u32 cur_hue, max_hue; | |
c5521706 CW |
197 | u32 cur_sharpness, max_sharpness; |
198 | u32 cur_flicker_filter, max_flicker_filter; | |
199 | u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive; | |
200 | u32 cur_flicker_filter_2d, max_flicker_filter_2d; | |
201 | u32 cur_tv_chroma_filter, max_tv_chroma_filter; | |
202 | u32 cur_tv_luma_filter, max_tv_luma_filter; | |
e044218a | 203 | u32 cur_dot_crawl, max_dot_crawl; |
79e53945 JB |
204 | }; |
205 | ||
8aca63aa | 206 | static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder) |
ea5b213a | 207 | { |
8aca63aa | 208 | return container_of(encoder, struct intel_sdvo, base); |
ea5b213a CW |
209 | } |
210 | ||
df0e9248 CW |
211 | static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector) |
212 | { | |
8aca63aa | 213 | return to_sdvo(intel_attached_encoder(connector)); |
df0e9248 CW |
214 | } |
215 | ||
615fb93f CW |
216 | static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector) |
217 | { | |
218 | return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base); | |
219 | } | |
220 | ||
fb7a46f3 | 221 | static bool |
ea5b213a | 222 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags); |
32aad86f CW |
223 | static bool |
224 | intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, | |
225 | struct intel_sdvo_connector *intel_sdvo_connector, | |
226 | int type); | |
227 | static bool | |
228 | intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, | |
229 | struct intel_sdvo_connector *intel_sdvo_connector); | |
fb7a46f3 | 230 | |
79e53945 JB |
231 | /** |
232 | * Writes the SDVOB or SDVOC with the given value, but always writes both | |
233 | * SDVOB and SDVOC to work around apparent hardware issues (according to | |
234 | * comments in the BIOS). | |
235 | */ | |
ea5b213a | 236 | static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) |
79e53945 | 237 | { |
4ef69c7a | 238 | struct drm_device *dev = intel_sdvo->base.base.dev; |
79e53945 | 239 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 JB |
240 | u32 bval = val, cval = val; |
241 | int i; | |
242 | ||
ea5b213a CW |
243 | if (intel_sdvo->sdvo_reg == PCH_SDVOB) { |
244 | I915_WRITE(intel_sdvo->sdvo_reg, val); | |
abab6311 | 245 | POSTING_READ(intel_sdvo->sdvo_reg); |
461ed3ca ZY |
246 | return; |
247 | } | |
248 | ||
e2debe91 PZ |
249 | if (intel_sdvo->sdvo_reg == GEN3_SDVOB) |
250 | cval = I915_READ(GEN3_SDVOC); | |
251 | else | |
252 | bval = I915_READ(GEN3_SDVOB); | |
253 | ||
79e53945 JB |
254 | /* |
255 | * Write the registers twice for luck. Sometimes, | |
256 | * writing them only once doesn't appear to 'stick'. | |
257 | * The BIOS does this too. Yay, magic | |
258 | */ | |
259 | for (i = 0; i < 2; i++) | |
260 | { | |
e2debe91 | 261 | I915_WRITE(GEN3_SDVOB, bval); |
abab6311 | 262 | POSTING_READ(GEN3_SDVOB); |
e2debe91 | 263 | I915_WRITE(GEN3_SDVOC, cval); |
abab6311 | 264 | POSTING_READ(GEN3_SDVOC); |
79e53945 JB |
265 | } |
266 | } | |
267 | ||
32aad86f | 268 | static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch) |
79e53945 | 269 | { |
79e53945 JB |
270 | struct i2c_msg msgs[] = { |
271 | { | |
e957d772 | 272 | .addr = intel_sdvo->slave_addr, |
79e53945 JB |
273 | .flags = 0, |
274 | .len = 1, | |
e957d772 | 275 | .buf = &addr, |
79e53945 JB |
276 | }, |
277 | { | |
e957d772 | 278 | .addr = intel_sdvo->slave_addr, |
79e53945 JB |
279 | .flags = I2C_M_RD, |
280 | .len = 1, | |
e957d772 | 281 | .buf = ch, |
79e53945 JB |
282 | } |
283 | }; | |
32aad86f | 284 | int ret; |
79e53945 | 285 | |
f899fc64 | 286 | if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2) |
79e53945 | 287 | return true; |
79e53945 | 288 | |
8a4c47f3 | 289 | DRM_DEBUG_KMS("i2c transfer returned %d\n", ret); |
79e53945 JB |
290 | return false; |
291 | } | |
292 | ||
79e53945 JB |
293 | #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd} |
294 | /** Mapping of command numbers to names, for debug output */ | |
005568be | 295 | static const struct _sdvo_cmd_name { |
e2f0ba97 | 296 | u8 cmd; |
2e88e40b | 297 | const char *name; |
79e53945 | 298 | } sdvo_cmd_names[] = { |
0206e353 AJ |
299 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET), |
300 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS), | |
301 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV), | |
302 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS), | |
303 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS), | |
304 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS), | |
305 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP), | |
306 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP), | |
307 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS), | |
308 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT), | |
309 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG), | |
310 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG), | |
311 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE), | |
312 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT), | |
313 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT), | |
314 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1), | |
315 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2), | |
316 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
317 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2), | |
318 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1), | |
319 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1), | |
320 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2), | |
321 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1), | |
322 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2), | |
323 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING), | |
324 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1), | |
325 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2), | |
326 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE), | |
327 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE), | |
328 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS), | |
329 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT), | |
330 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT), | |
331 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS), | |
332 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT), | |
333 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT), | |
334 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES), | |
335 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE), | |
336 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE), | |
337 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE), | |
338 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH), | |
339 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT), | |
340 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT), | |
341 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS), | |
342 | ||
343 | /* Add the op code for SDVO enhancements */ | |
344 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS), | |
345 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS), | |
346 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS), | |
347 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS), | |
348 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS), | |
349 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS), | |
350 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION), | |
351 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION), | |
352 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION), | |
353 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE), | |
354 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE), | |
355 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE), | |
356 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST), | |
357 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST), | |
358 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST), | |
359 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS), | |
360 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS), | |
361 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS), | |
362 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H), | |
363 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H), | |
364 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H), | |
365 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V), | |
366 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V), | |
367 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V), | |
368 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER), | |
369 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER), | |
370 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER), | |
371 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE), | |
372 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE), | |
373 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE), | |
374 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D), | |
375 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D), | |
376 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D), | |
377 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS), | |
378 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS), | |
379 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS), | |
380 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL), | |
381 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL), | |
382 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER), | |
383 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER), | |
384 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER), | |
385 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER), | |
386 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER), | |
387 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER), | |
388 | ||
389 | /* HDMI op code */ | |
390 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE), | |
391 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE), | |
392 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE), | |
393 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI), | |
394 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI), | |
395 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP), | |
396 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY), | |
397 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY), | |
398 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER), | |
399 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT), | |
400 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT), | |
401 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX), | |
402 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX), | |
403 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO), | |
404 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT), | |
405 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT), | |
406 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE), | |
407 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE), | |
408 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA), | |
409 | SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA), | |
79e53945 JB |
410 | }; |
411 | ||
eef4eacb | 412 | #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC") |
79e53945 | 413 | |
ea5b213a | 414 | static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, |
32aad86f | 415 | const void *args, int args_len) |
79e53945 | 416 | { |
84fcb469 DV |
417 | int i, pos = 0; |
418 | #define BUF_LEN 256 | |
419 | char buffer[BUF_LEN]; | |
420 | ||
421 | #define BUF_PRINT(args...) \ | |
422 | pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) | |
423 | ||
79e53945 | 424 | |
84fcb469 DV |
425 | for (i = 0; i < args_len; i++) { |
426 | BUF_PRINT("%02X ", ((u8 *)args)[i]); | |
427 | } | |
428 | for (; i < 8; i++) { | |
429 | BUF_PRINT(" "); | |
430 | } | |
04ad327f | 431 | for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { |
79e53945 | 432 | if (cmd == sdvo_cmd_names[i].cmd) { |
84fcb469 | 433 | BUF_PRINT("(%s)", sdvo_cmd_names[i].name); |
79e53945 JB |
434 | break; |
435 | } | |
436 | } | |
84fcb469 DV |
437 | if (i == ARRAY_SIZE(sdvo_cmd_names)) { |
438 | BUF_PRINT("(%02X)", cmd); | |
439 | } | |
440 | BUG_ON(pos >= BUF_LEN - 1); | |
441 | #undef BUF_PRINT | |
442 | #undef BUF_LEN | |
443 | ||
444 | DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer); | |
79e53945 | 445 | } |
79e53945 | 446 | |
e957d772 CW |
447 | static const char *cmd_status_names[] = { |
448 | "Power on", | |
449 | "Success", | |
450 | "Not supported", | |
451 | "Invalid arg", | |
452 | "Pending", | |
453 | "Target not specified", | |
454 | "Scaling not supported" | |
455 | }; | |
456 | ||
32aad86f CW |
457 | static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd, |
458 | const void *args, int args_len) | |
79e53945 | 459 | { |
3bf3f452 BW |
460 | u8 *buf, status; |
461 | struct i2c_msg *msgs; | |
462 | int i, ret = true; | |
463 | ||
0274df3e | 464 | /* Would be simpler to allocate both in one go ? */ |
5c67eeb6 | 465 | buf = kzalloc(args_len * 2 + 2, GFP_KERNEL); |
3bf3f452 BW |
466 | if (!buf) |
467 | return false; | |
468 | ||
469 | msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); | |
0274df3e AC |
470 | if (!msgs) { |
471 | kfree(buf); | |
3bf3f452 | 472 | return false; |
0274df3e | 473 | } |
79e53945 | 474 | |
ea5b213a | 475 | intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); |
79e53945 JB |
476 | |
477 | for (i = 0; i < args_len; i++) { | |
e957d772 CW |
478 | msgs[i].addr = intel_sdvo->slave_addr; |
479 | msgs[i].flags = 0; | |
480 | msgs[i].len = 2; | |
481 | msgs[i].buf = buf + 2 *i; | |
482 | buf[2*i + 0] = SDVO_I2C_ARG_0 - i; | |
483 | buf[2*i + 1] = ((u8*)args)[i]; | |
484 | } | |
485 | msgs[i].addr = intel_sdvo->slave_addr; | |
486 | msgs[i].flags = 0; | |
487 | msgs[i].len = 2; | |
488 | msgs[i].buf = buf + 2*i; | |
489 | buf[2*i + 0] = SDVO_I2C_OPCODE; | |
490 | buf[2*i + 1] = cmd; | |
491 | ||
492 | /* the following two are to read the response */ | |
493 | status = SDVO_I2C_CMD_STATUS; | |
494 | msgs[i+1].addr = intel_sdvo->slave_addr; | |
495 | msgs[i+1].flags = 0; | |
496 | msgs[i+1].len = 1; | |
497 | msgs[i+1].buf = &status; | |
498 | ||
499 | msgs[i+2].addr = intel_sdvo->slave_addr; | |
500 | msgs[i+2].flags = I2C_M_RD; | |
501 | msgs[i+2].len = 1; | |
502 | msgs[i+2].buf = &status; | |
503 | ||
504 | ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3); | |
505 | if (ret < 0) { | |
506 | DRM_DEBUG_KMS("I2c transfer returned %d\n", ret); | |
3bf3f452 BW |
507 | ret = false; |
508 | goto out; | |
e957d772 CW |
509 | } |
510 | if (ret != i+3) { | |
511 | /* failure in I2C transfer */ | |
512 | DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3); | |
3bf3f452 | 513 | ret = false; |
e957d772 CW |
514 | } |
515 | ||
3bf3f452 BW |
516 | out: |
517 | kfree(msgs); | |
518 | kfree(buf); | |
519 | return ret; | |
79e53945 JB |
520 | } |
521 | ||
b5c616a7 CW |
522 | static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo, |
523 | void *response, int response_len) | |
79e53945 | 524 | { |
fc37381c | 525 | u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ |
b5c616a7 | 526 | u8 status; |
84fcb469 DV |
527 | int i, pos = 0; |
528 | #define BUF_LEN 256 | |
529 | char buffer[BUF_LEN]; | |
79e53945 | 530 | |
d121a5d2 | 531 | |
b5c616a7 CW |
532 | /* |
533 | * The documentation states that all commands will be | |
534 | * processed within 15µs, and that we need only poll | |
535 | * the status byte a maximum of 3 times in order for the | |
536 | * command to be complete. | |
537 | * | |
538 | * Check 5 times in case the hardware failed to read the docs. | |
fc37381c CW |
539 | * |
540 | * Also beware that the first response by many devices is to | |
541 | * reply PENDING and stall for time. TVs are notorious for | |
542 | * requiring longer than specified to complete their replies. | |
543 | * Originally (in the DDX long ago), the delay was only ever 15ms | |
544 | * with an additional delay of 30ms applied for TVs added later after | |
545 | * many experiments. To accommodate both sets of delays, we do a | |
546 | * sequence of slow checks if the device is falling behind and fails | |
547 | * to reply within 5*15µs. | |
b5c616a7 | 548 | */ |
d121a5d2 CW |
549 | if (!intel_sdvo_read_byte(intel_sdvo, |
550 | SDVO_I2C_CMD_STATUS, | |
551 | &status)) | |
552 | goto log_fail; | |
553 | ||
1ad87e72 | 554 | while ((status == SDVO_CMD_STATUS_PENDING || |
46a3f4a3 | 555 | status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) { |
fc37381c CW |
556 | if (retry < 10) |
557 | msleep(15); | |
558 | else | |
559 | udelay(15); | |
560 | ||
b5c616a7 CW |
561 | if (!intel_sdvo_read_byte(intel_sdvo, |
562 | SDVO_I2C_CMD_STATUS, | |
563 | &status)) | |
d121a5d2 CW |
564 | goto log_fail; |
565 | } | |
b5c616a7 | 566 | |
84fcb469 DV |
567 | #define BUF_PRINT(args...) \ |
568 | pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args) | |
569 | ||
79e53945 | 570 | if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) |
84fcb469 | 571 | BUF_PRINT("(%s)", cmd_status_names[status]); |
79e53945 | 572 | else |
84fcb469 | 573 | BUF_PRINT("(??? %d)", status); |
79e53945 | 574 | |
b5c616a7 CW |
575 | if (status != SDVO_CMD_STATUS_SUCCESS) |
576 | goto log_fail; | |
79e53945 | 577 | |
b5c616a7 CW |
578 | /* Read the command response */ |
579 | for (i = 0; i < response_len; i++) { | |
580 | if (!intel_sdvo_read_byte(intel_sdvo, | |
581 | SDVO_I2C_RETURN_0 + i, | |
582 | &((u8 *)response)[i])) | |
583 | goto log_fail; | |
84fcb469 | 584 | BUF_PRINT(" %02X", ((u8 *)response)[i]); |
b5c616a7 | 585 | } |
84fcb469 DV |
586 | BUG_ON(pos >= BUF_LEN - 1); |
587 | #undef BUF_PRINT | |
588 | #undef BUF_LEN | |
589 | ||
590 | DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer); | |
b5c616a7 | 591 | return true; |
79e53945 | 592 | |
b5c616a7 | 593 | log_fail: |
84fcb469 | 594 | DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo)); |
b5c616a7 | 595 | return false; |
79e53945 JB |
596 | } |
597 | ||
b358d0a6 | 598 | static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode) |
79e53945 JB |
599 | { |
600 | if (mode->clock >= 100000) | |
601 | return 1; | |
602 | else if (mode->clock >= 50000) | |
603 | return 2; | |
604 | else | |
605 | return 4; | |
606 | } | |
607 | ||
e957d772 CW |
608 | static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo, |
609 | u8 ddc_bus) | |
79e53945 | 610 | { |
d121a5d2 | 611 | /* This must be the immediately preceding write before the i2c xfer */ |
e957d772 CW |
612 | return intel_sdvo_write_cmd(intel_sdvo, |
613 | SDVO_CMD_SET_CONTROL_BUS_SWITCH, | |
614 | &ddc_bus, 1); | |
79e53945 JB |
615 | } |
616 | ||
32aad86f | 617 | static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len) |
79e53945 | 618 | { |
d121a5d2 CW |
619 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len)) |
620 | return false; | |
621 | ||
622 | return intel_sdvo_read_response(intel_sdvo, NULL, 0); | |
32aad86f | 623 | } |
79e53945 | 624 | |
32aad86f CW |
625 | static bool |
626 | intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len) | |
627 | { | |
628 | if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0)) | |
629 | return false; | |
79e53945 | 630 | |
32aad86f CW |
631 | return intel_sdvo_read_response(intel_sdvo, value, len); |
632 | } | |
79e53945 | 633 | |
32aad86f CW |
634 | static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) |
635 | { | |
636 | struct intel_sdvo_set_target_input_args targets = {0}; | |
637 | return intel_sdvo_set_value(intel_sdvo, | |
638 | SDVO_CMD_SET_TARGET_INPUT, | |
639 | &targets, sizeof(targets)); | |
79e53945 JB |
640 | } |
641 | ||
642 | /** | |
643 | * Return whether each input is trained. | |
644 | * | |
645 | * This function is making an assumption about the layout of the response, | |
646 | * which should be checked against the docs. | |
647 | */ | |
ea5b213a | 648 | static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2) |
79e53945 JB |
649 | { |
650 | struct intel_sdvo_get_trained_inputs_response response; | |
79e53945 | 651 | |
1a3665c8 | 652 | BUILD_BUG_ON(sizeof(response) != 1); |
32aad86f CW |
653 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS, |
654 | &response, sizeof(response))) | |
79e53945 JB |
655 | return false; |
656 | ||
657 | *input_1 = response.input0_trained; | |
658 | *input_2 = response.input1_trained; | |
659 | return true; | |
660 | } | |
661 | ||
ea5b213a | 662 | static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
663 | u16 outputs) |
664 | { | |
32aad86f CW |
665 | return intel_sdvo_set_value(intel_sdvo, |
666 | SDVO_CMD_SET_ACTIVE_OUTPUTS, | |
667 | &outputs, sizeof(outputs)); | |
79e53945 JB |
668 | } |
669 | ||
4ac41f47 DV |
670 | static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo, |
671 | u16 *outputs) | |
672 | { | |
673 | return intel_sdvo_get_value(intel_sdvo, | |
674 | SDVO_CMD_GET_ACTIVE_OUTPUTS, | |
675 | outputs, sizeof(*outputs)); | |
676 | } | |
677 | ||
ea5b213a | 678 | static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
679 | int mode) |
680 | { | |
32aad86f | 681 | u8 state = SDVO_ENCODER_STATE_ON; |
79e53945 JB |
682 | |
683 | switch (mode) { | |
684 | case DRM_MODE_DPMS_ON: | |
685 | state = SDVO_ENCODER_STATE_ON; | |
686 | break; | |
687 | case DRM_MODE_DPMS_STANDBY: | |
688 | state = SDVO_ENCODER_STATE_STANDBY; | |
689 | break; | |
690 | case DRM_MODE_DPMS_SUSPEND: | |
691 | state = SDVO_ENCODER_STATE_SUSPEND; | |
692 | break; | |
693 | case DRM_MODE_DPMS_OFF: | |
694 | state = SDVO_ENCODER_STATE_OFF; | |
695 | break; | |
696 | } | |
697 | ||
32aad86f CW |
698 | return intel_sdvo_set_value(intel_sdvo, |
699 | SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state)); | |
79e53945 JB |
700 | } |
701 | ||
ea5b213a | 702 | static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
703 | int *clock_min, |
704 | int *clock_max) | |
705 | { | |
706 | struct intel_sdvo_pixel_clock_range clocks; | |
79e53945 | 707 | |
1a3665c8 | 708 | BUILD_BUG_ON(sizeof(clocks) != 4); |
32aad86f CW |
709 | if (!intel_sdvo_get_value(intel_sdvo, |
710 | SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE, | |
711 | &clocks, sizeof(clocks))) | |
79e53945 JB |
712 | return false; |
713 | ||
714 | /* Convert the values from units of 10 kHz to kHz. */ | |
715 | *clock_min = clocks.min * 10; | |
716 | *clock_max = clocks.max * 10; | |
79e53945 JB |
717 | return true; |
718 | } | |
719 | ||
ea5b213a | 720 | static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
721 | u16 outputs) |
722 | { | |
32aad86f CW |
723 | return intel_sdvo_set_value(intel_sdvo, |
724 | SDVO_CMD_SET_TARGET_OUTPUT, | |
725 | &outputs, sizeof(outputs)); | |
79e53945 JB |
726 | } |
727 | ||
ea5b213a | 728 | static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
79e53945 JB |
729 | struct intel_sdvo_dtd *dtd) |
730 | { | |
32aad86f CW |
731 | return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && |
732 | intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); | |
79e53945 JB |
733 | } |
734 | ||
045ac3b5 JB |
735 | static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd, |
736 | struct intel_sdvo_dtd *dtd) | |
737 | { | |
738 | return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) && | |
739 | intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2)); | |
740 | } | |
741 | ||
ea5b213a | 742 | static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
743 | struct intel_sdvo_dtd *dtd) |
744 | { | |
ea5b213a | 745 | return intel_sdvo_set_timing(intel_sdvo, |
79e53945 JB |
746 | SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd); |
747 | } | |
748 | ||
ea5b213a | 749 | static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo, |
79e53945 JB |
750 | struct intel_sdvo_dtd *dtd) |
751 | { | |
ea5b213a | 752 | return intel_sdvo_set_timing(intel_sdvo, |
79e53945 JB |
753 | SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd); |
754 | } | |
755 | ||
045ac3b5 JB |
756 | static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo, |
757 | struct intel_sdvo_dtd *dtd) | |
758 | { | |
759 | return intel_sdvo_get_timing(intel_sdvo, | |
760 | SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd); | |
761 | } | |
762 | ||
e2f0ba97 | 763 | static bool |
ea5b213a | 764 | intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
765 | uint16_t clock, |
766 | uint16_t width, | |
767 | uint16_t height) | |
768 | { | |
769 | struct intel_sdvo_preferred_input_timing_args args; | |
e2f0ba97 | 770 | |
e642c6f1 | 771 | memset(&args, 0, sizeof(args)); |
e2f0ba97 JB |
772 | args.clock = clock; |
773 | args.width = width; | |
774 | args.height = height; | |
e642c6f1 | 775 | args.interlace = 0; |
12682a97 | 776 | |
ea5b213a CW |
777 | if (intel_sdvo->is_lvds && |
778 | (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width || | |
779 | intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height)) | |
12682a97 | 780 | args.scaled = 1; |
781 | ||
32aad86f CW |
782 | return intel_sdvo_set_value(intel_sdvo, |
783 | SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING, | |
784 | &args, sizeof(args)); | |
e2f0ba97 JB |
785 | } |
786 | ||
ea5b213a | 787 | static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
788 | struct intel_sdvo_dtd *dtd) |
789 | { | |
1a3665c8 CW |
790 | BUILD_BUG_ON(sizeof(dtd->part1) != 8); |
791 | BUILD_BUG_ON(sizeof(dtd->part2) != 8); | |
32aad86f CW |
792 | return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1, |
793 | &dtd->part1, sizeof(dtd->part1)) && | |
794 | intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2, | |
795 | &dtd->part2, sizeof(dtd->part2)); | |
e2f0ba97 | 796 | } |
79e53945 | 797 | |
ea5b213a | 798 | static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) |
79e53945 | 799 | { |
32aad86f | 800 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1); |
79e53945 JB |
801 | } |
802 | ||
e2f0ba97 | 803 | static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd, |
32aad86f | 804 | const struct drm_display_mode *mode) |
79e53945 | 805 | { |
e2f0ba97 JB |
806 | uint16_t width, height; |
807 | uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len; | |
808 | uint16_t h_sync_offset, v_sync_offset; | |
6651819b | 809 | int mode_clock; |
79e53945 | 810 | |
1c4a814e DV |
811 | memset(dtd, 0, sizeof(*dtd)); |
812 | ||
c6ebd4c0 DV |
813 | width = mode->hdisplay; |
814 | height = mode->vdisplay; | |
79e53945 JB |
815 | |
816 | /* do some mode translations */ | |
c6ebd4c0 DV |
817 | h_blank_len = mode->htotal - mode->hdisplay; |
818 | h_sync_len = mode->hsync_end - mode->hsync_start; | |
79e53945 | 819 | |
c6ebd4c0 DV |
820 | v_blank_len = mode->vtotal - mode->vdisplay; |
821 | v_sync_len = mode->vsync_end - mode->vsync_start; | |
79e53945 | 822 | |
c6ebd4c0 DV |
823 | h_sync_offset = mode->hsync_start - mode->hdisplay; |
824 | v_sync_offset = mode->vsync_start - mode->vdisplay; | |
79e53945 | 825 | |
6651819b | 826 | mode_clock = mode->clock; |
6651819b DV |
827 | mode_clock /= 10; |
828 | dtd->part1.clock = mode_clock; | |
829 | ||
e2f0ba97 JB |
830 | dtd->part1.h_active = width & 0xff; |
831 | dtd->part1.h_blank = h_blank_len & 0xff; | |
832 | dtd->part1.h_high = (((width >> 8) & 0xf) << 4) | | |
79e53945 | 833 | ((h_blank_len >> 8) & 0xf); |
e2f0ba97 JB |
834 | dtd->part1.v_active = height & 0xff; |
835 | dtd->part1.v_blank = v_blank_len & 0xff; | |
836 | dtd->part1.v_high = (((height >> 8) & 0xf) << 4) | | |
79e53945 JB |
837 | ((v_blank_len >> 8) & 0xf); |
838 | ||
171a9e96 | 839 | dtd->part2.h_sync_off = h_sync_offset & 0xff; |
e2f0ba97 JB |
840 | dtd->part2.h_sync_width = h_sync_len & 0xff; |
841 | dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 | | |
79e53945 | 842 | (v_sync_len & 0xf); |
e2f0ba97 | 843 | dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) | |
79e53945 JB |
844 | ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) | |
845 | ((v_sync_len & 0x30) >> 4); | |
846 | ||
e2f0ba97 | 847 | dtd->part2.dtd_flags = 0x18; |
59d92bfa DV |
848 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
849 | dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE; | |
79e53945 | 850 | if (mode->flags & DRM_MODE_FLAG_PHSYNC) |
59d92bfa | 851 | dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE; |
79e53945 | 852 | if (mode->flags & DRM_MODE_FLAG_PVSYNC) |
59d92bfa | 853 | dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE; |
e2f0ba97 | 854 | |
e2f0ba97 | 855 | dtd->part2.v_sync_off_high = v_sync_offset & 0xc0; |
e2f0ba97 JB |
856 | } |
857 | ||
1c4a814e | 858 | static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode, |
32aad86f | 859 | const struct intel_sdvo_dtd *dtd) |
e2f0ba97 | 860 | { |
1c4a814e DV |
861 | struct drm_display_mode mode = {}; |
862 | ||
863 | mode.hdisplay = dtd->part1.h_active; | |
864 | mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8; | |
865 | mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off; | |
866 | mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2; | |
867 | mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width; | |
868 | mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4; | |
869 | mode.htotal = mode.hdisplay + dtd->part1.h_blank; | |
870 | mode.htotal += (dtd->part1.h_high & 0xf) << 8; | |
871 | ||
872 | mode.vdisplay = dtd->part1.v_active; | |
873 | mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8; | |
874 | mode.vsync_start = mode.vdisplay; | |
875 | mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf; | |
876 | mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2; | |
877 | mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0; | |
878 | mode.vsync_end = mode.vsync_start + | |
e2f0ba97 | 879 | (dtd->part2.v_sync_off_width & 0xf); |
1c4a814e DV |
880 | mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4; |
881 | mode.vtotal = mode.vdisplay + dtd->part1.v_blank; | |
882 | mode.vtotal += (dtd->part1.v_high & 0xf) << 8; | |
e2f0ba97 | 883 | |
1c4a814e | 884 | mode.clock = dtd->part1.clock * 10; |
e2f0ba97 | 885 | |
59d92bfa | 886 | if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE) |
1c4a814e | 887 | mode.flags |= DRM_MODE_FLAG_INTERLACE; |
59d92bfa | 888 | if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) |
1c4a814e | 889 | mode.flags |= DRM_MODE_FLAG_PHSYNC; |
3cea210f | 890 | else |
1c4a814e | 891 | mode.flags |= DRM_MODE_FLAG_NHSYNC; |
59d92bfa | 892 | if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) |
1c4a814e | 893 | mode.flags |= DRM_MODE_FLAG_PVSYNC; |
3cea210f | 894 | else |
1c4a814e DV |
895 | mode.flags |= DRM_MODE_FLAG_NVSYNC; |
896 | ||
897 | drm_mode_set_crtcinfo(&mode, 0); | |
898 | ||
899 | drm_mode_copy(pmode, &mode); | |
e2f0ba97 JB |
900 | } |
901 | ||
e27d8538 | 902 | static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo) |
e2f0ba97 | 903 | { |
e27d8538 | 904 | struct intel_sdvo_encode encode; |
e2f0ba97 | 905 | |
1a3665c8 | 906 | BUILD_BUG_ON(sizeof(encode) != 2); |
e27d8538 CW |
907 | return intel_sdvo_get_value(intel_sdvo, |
908 | SDVO_CMD_GET_SUPP_ENCODE, | |
909 | &encode, sizeof(encode)); | |
e2f0ba97 JB |
910 | } |
911 | ||
ea5b213a | 912 | static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo, |
c751ce4f | 913 | uint8_t mode) |
e2f0ba97 | 914 | { |
32aad86f | 915 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1); |
e2f0ba97 JB |
916 | } |
917 | ||
ea5b213a | 918 | static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo, |
e2f0ba97 JB |
919 | uint8_t mode) |
920 | { | |
32aad86f | 921 | return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1); |
e2f0ba97 JB |
922 | } |
923 | ||
924 | #if 0 | |
ea5b213a | 925 | static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo) |
e2f0ba97 JB |
926 | { |
927 | int i, j; | |
928 | uint8_t set_buf_index[2]; | |
929 | uint8_t av_split; | |
930 | uint8_t buf_size; | |
931 | uint8_t buf[48]; | |
932 | uint8_t *pos; | |
933 | ||
32aad86f | 934 | intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1); |
e2f0ba97 JB |
935 | |
936 | for (i = 0; i <= av_split; i++) { | |
937 | set_buf_index[0] = i; set_buf_index[1] = 0; | |
c751ce4f | 938 | intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX, |
e2f0ba97 | 939 | set_buf_index, 2); |
c751ce4f EA |
940 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0); |
941 | intel_sdvo_read_response(encoder, &buf_size, 1); | |
e2f0ba97 JB |
942 | |
943 | pos = buf; | |
944 | for (j = 0; j <= buf_size; j += 8) { | |
c751ce4f | 945 | intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA, |
e2f0ba97 | 946 | NULL, 0); |
c751ce4f | 947 | intel_sdvo_read_response(encoder, pos, 8); |
e2f0ba97 JB |
948 | pos += 8; |
949 | } | |
950 | } | |
951 | } | |
952 | #endif | |
953 | ||
b6e0e543 DV |
954 | static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo, |
955 | unsigned if_index, uint8_t tx_rate, | |
fff63867 | 956 | const uint8_t *data, unsigned length) |
b6e0e543 DV |
957 | { |
958 | uint8_t set_buf_index[2] = { if_index, 0 }; | |
959 | uint8_t hbuf_size, tmp[8]; | |
960 | int i; | |
961 | ||
962 | if (!intel_sdvo_set_value(intel_sdvo, | |
963 | SDVO_CMD_SET_HBUF_INDEX, | |
964 | set_buf_index, 2)) | |
965 | return false; | |
966 | ||
967 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO, | |
968 | &hbuf_size, 1)) | |
969 | return false; | |
970 | ||
971 | /* Buffer size is 0 based, hooray! */ | |
972 | hbuf_size++; | |
973 | ||
974 | DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n", | |
975 | if_index, length, hbuf_size); | |
976 | ||
977 | for (i = 0; i < hbuf_size; i += 8) { | |
978 | memset(tmp, 0, 8); | |
979 | if (i < length) | |
980 | memcpy(tmp, data + i, min_t(unsigned, 8, length - i)); | |
981 | ||
982 | if (!intel_sdvo_set_value(intel_sdvo, | |
983 | SDVO_CMD_SET_HBUF_DATA, | |
984 | tmp, 8)) | |
985 | return false; | |
986 | } | |
987 | ||
988 | return intel_sdvo_set_value(intel_sdvo, | |
989 | SDVO_CMD_SET_HBUF_TXRATE, | |
990 | &tx_rate, 1); | |
991 | } | |
992 | ||
abedc077 VS |
993 | static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo, |
994 | const struct drm_display_mode *adjusted_mode) | |
e2f0ba97 | 995 | { |
15dcd350 DL |
996 | uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)]; |
997 | struct drm_crtc *crtc = intel_sdvo->base.base.crtc; | |
998 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
999 | union hdmi_infoframe frame; | |
1000 | int ret; | |
1001 | ssize_t len; | |
1002 | ||
1003 | ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, | |
1004 | adjusted_mode); | |
1005 | if (ret < 0) { | |
1006 | DRM_ERROR("couldn't fill AVI infoframe\n"); | |
1007 | return false; | |
1008 | } | |
3c17fe4b | 1009 | |
abedc077 | 1010 | if (intel_sdvo->rgb_quant_range_selectable) { |
6e3c9717 | 1011 | if (intel_crtc->config->limited_color_range) |
15dcd350 DL |
1012 | frame.avi.quantization_range = |
1013 | HDMI_QUANTIZATION_RANGE_LIMITED; | |
abedc077 | 1014 | else |
15dcd350 DL |
1015 | frame.avi.quantization_range = |
1016 | HDMI_QUANTIZATION_RANGE_FULL; | |
abedc077 VS |
1017 | } |
1018 | ||
15dcd350 DL |
1019 | len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data)); |
1020 | if (len < 0) | |
1021 | return false; | |
81014b9d | 1022 | |
b6e0e543 DV |
1023 | return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF, |
1024 | SDVO_HBUF_TX_VSYNC, | |
1025 | sdvo_data, sizeof(sdvo_data)); | |
e2f0ba97 JB |
1026 | } |
1027 | ||
32aad86f | 1028 | static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo) |
7026d4ac | 1029 | { |
ce6feabd | 1030 | struct intel_sdvo_tv_format format; |
40039750 | 1031 | uint32_t format_map; |
ce6feabd | 1032 | |
40039750 | 1033 | format_map = 1 << intel_sdvo->tv_format_index; |
ce6feabd | 1034 | memset(&format, 0, sizeof(format)); |
32aad86f | 1035 | memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map))); |
ce6feabd | 1036 | |
32aad86f CW |
1037 | BUILD_BUG_ON(sizeof(format) != 6); |
1038 | return intel_sdvo_set_value(intel_sdvo, | |
1039 | SDVO_CMD_SET_TV_FORMAT, | |
1040 | &format, sizeof(format)); | |
7026d4ac ZW |
1041 | } |
1042 | ||
32aad86f CW |
1043 | static bool |
1044 | intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo, | |
e811f5ae | 1045 | const struct drm_display_mode *mode) |
e2f0ba97 | 1046 | { |
32aad86f | 1047 | struct intel_sdvo_dtd output_dtd; |
79e53945 | 1048 | |
32aad86f CW |
1049 | if (!intel_sdvo_set_target_output(intel_sdvo, |
1050 | intel_sdvo->attached_output)) | |
1051 | return false; | |
e2f0ba97 | 1052 | |
32aad86f CW |
1053 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); |
1054 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) | |
1055 | return false; | |
e2f0ba97 | 1056 | |
32aad86f CW |
1057 | return true; |
1058 | } | |
1059 | ||
c9a29698 DV |
1060 | /* Asks the sdvo controller for the preferred input mode given the output mode. |
1061 | * Unfortunately we have to set up the full output mode to do that. */ | |
32aad86f | 1062 | static bool |
c9a29698 | 1063 | intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo, |
e811f5ae | 1064 | const struct drm_display_mode *mode, |
c9a29698 | 1065 | struct drm_display_mode *adjusted_mode) |
32aad86f | 1066 | { |
c9a29698 DV |
1067 | struct intel_sdvo_dtd input_dtd; |
1068 | ||
32aad86f CW |
1069 | /* Reset the input timing to the screen. Assume always input 0. */ |
1070 | if (!intel_sdvo_set_target_input(intel_sdvo)) | |
1071 | return false; | |
e2f0ba97 | 1072 | |
32aad86f CW |
1073 | if (!intel_sdvo_create_preferred_input_timing(intel_sdvo, |
1074 | mode->clock / 10, | |
1075 | mode->hdisplay, | |
1076 | mode->vdisplay)) | |
1077 | return false; | |
e2f0ba97 | 1078 | |
32aad86f | 1079 | if (!intel_sdvo_get_preferred_input_timing(intel_sdvo, |
c9a29698 | 1080 | &input_dtd)) |
32aad86f | 1081 | return false; |
e2f0ba97 | 1082 | |
c9a29698 | 1083 | intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd); |
e751823d | 1084 | intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags; |
79e53945 | 1085 | |
32aad86f CW |
1086 | return true; |
1087 | } | |
12682a97 | 1088 | |
5cec258b | 1089 | static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config) |
70484559 | 1090 | { |
3c52f4eb | 1091 | unsigned dotclock = pipe_config->port_clock; |
70484559 DV |
1092 | struct dpll *clock = &pipe_config->dpll; |
1093 | ||
1094 | /* SDVO TV has fixed PLL values depend on its clock range, | |
1095 | this mirrors vbios setting. */ | |
1096 | if (dotclock >= 100000 && dotclock < 140500) { | |
1097 | clock->p1 = 2; | |
1098 | clock->p2 = 10; | |
1099 | clock->n = 3; | |
1100 | clock->m1 = 16; | |
1101 | clock->m2 = 8; | |
1102 | } else if (dotclock >= 140500 && dotclock <= 200000) { | |
1103 | clock->p1 = 1; | |
1104 | clock->p2 = 10; | |
1105 | clock->n = 6; | |
1106 | clock->m1 = 12; | |
1107 | clock->m2 = 8; | |
1108 | } else { | |
1109 | WARN(1, "SDVO TV clock out of range: %i\n", dotclock); | |
1110 | } | |
1111 | ||
1112 | pipe_config->clock_set = true; | |
1113 | } | |
1114 | ||
6cc5f341 | 1115 | static bool intel_sdvo_compute_config(struct intel_encoder *encoder, |
5cec258b | 1116 | struct intel_crtc_state *pipe_config) |
32aad86f | 1117 | { |
8aca63aa | 1118 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
2d112de7 ACO |
1119 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
1120 | struct drm_display_mode *mode = &pipe_config->base.mode; | |
12682a97 | 1121 | |
5d2d38dd DV |
1122 | DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n"); |
1123 | pipe_config->pipe_bpp = 8*3; | |
1124 | ||
5bfe2ac0 DV |
1125 | if (HAS_PCH_SPLIT(encoder->base.dev)) |
1126 | pipe_config->has_pch_encoder = true; | |
1127 | ||
32aad86f CW |
1128 | /* We need to construct preferred input timings based on our |
1129 | * output timings. To do that, we have to set the output | |
1130 | * timings, even though this isn't really the right place in | |
1131 | * the sequence to do it. Oh well. | |
1132 | */ | |
1133 | if (intel_sdvo->is_tv) { | |
1134 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode)) | |
1135 | return false; | |
12682a97 | 1136 | |
c9a29698 DV |
1137 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
1138 | mode, | |
1139 | adjusted_mode); | |
09ede541 | 1140 | pipe_config->sdvo_tv_clock = true; |
ea5b213a | 1141 | } else if (intel_sdvo->is_lvds) { |
32aad86f | 1142 | if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, |
6c9547ff | 1143 | intel_sdvo->sdvo_lvds_fixed_mode)) |
e2f0ba97 | 1144 | return false; |
12682a97 | 1145 | |
c9a29698 DV |
1146 | (void) intel_sdvo_get_preferred_input_mode(intel_sdvo, |
1147 | mode, | |
1148 | adjusted_mode); | |
e2f0ba97 | 1149 | } |
32aad86f CW |
1150 | |
1151 | /* Make the CRTC code factor in the SDVO pixel multiplier. The | |
6c9547ff | 1152 | * SDVO device will factor out the multiplier during mode_set. |
32aad86f | 1153 | */ |
6cc5f341 DV |
1154 | pipe_config->pixel_multiplier = |
1155 | intel_sdvo_get_pixel_multiplier(adjusted_mode); | |
32aad86f | 1156 | |
9f04003e DV |
1157 | pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor; |
1158 | ||
55bc60db VS |
1159 | if (intel_sdvo->color_range_auto) { |
1160 | /* See CEA-861-E - 5.1 Default Encoding Parameters */ | |
4f3a8bc7 PZ |
1161 | /* FIXME: This bit is only valid when using TMDS encoding and 8 |
1162 | * bit per color mode. */ | |
9f04003e | 1163 | if (pipe_config->has_hdmi_sink && |
18316c8c | 1164 | drm_match_cea_mode(adjusted_mode) > 1) |
69f5acc8 DV |
1165 | pipe_config->limited_color_range = true; |
1166 | } else { | |
9f04003e | 1167 | if (pipe_config->has_hdmi_sink && |
69f5acc8 DV |
1168 | intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235) |
1169 | pipe_config->limited_color_range = true; | |
55bc60db VS |
1170 | } |
1171 | ||
70484559 DV |
1172 | /* Clock computation needs to happen after pixel multiplier. */ |
1173 | if (intel_sdvo->is_tv) | |
1174 | i9xx_adjust_sdvo_tv_clock(pipe_config); | |
1175 | ||
e2f0ba97 JB |
1176 | return true; |
1177 | } | |
1178 | ||
192d47a6 | 1179 | static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder) |
e2f0ba97 | 1180 | { |
6cc5f341 | 1181 | struct drm_device *dev = intel_encoder->base.dev; |
e2f0ba97 | 1182 | struct drm_i915_private *dev_priv = dev->dev_private; |
eeb47937 | 1183 | struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc); |
6cc5f341 | 1184 | struct drm_display_mode *adjusted_mode = |
6e3c9717 ACO |
1185 | &crtc->config->base.adjusted_mode; |
1186 | struct drm_display_mode *mode = &crtc->config->base.mode; | |
8aca63aa | 1187 | struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder); |
6c9547ff | 1188 | u32 sdvox; |
e2f0ba97 | 1189 | struct intel_sdvo_in_out_map in_out; |
6651819b | 1190 | struct intel_sdvo_dtd input_dtd, output_dtd; |
6c9547ff | 1191 | int rate; |
e2f0ba97 JB |
1192 | |
1193 | if (!mode) | |
1194 | return; | |
1195 | ||
1196 | /* First, set the input mapping for the first input to our controlled | |
1197 | * output. This is only correct if we're a single-input device, in | |
1198 | * which case the first input is the output from the appropriate SDVO | |
1199 | * channel on the motherboard. In a two-input device, the first input | |
1200 | * will be SDVOB and the second SDVOC. | |
1201 | */ | |
ea5b213a | 1202 | in_out.in0 = intel_sdvo->attached_output; |
e2f0ba97 JB |
1203 | in_out.in1 = 0; |
1204 | ||
c74696b9 PR |
1205 | intel_sdvo_set_value(intel_sdvo, |
1206 | SDVO_CMD_SET_IN_OUT_MAP, | |
1207 | &in_out, sizeof(in_out)); | |
e2f0ba97 | 1208 | |
6c9547ff CW |
1209 | /* Set the output timings to the screen */ |
1210 | if (!intel_sdvo_set_target_output(intel_sdvo, | |
1211 | intel_sdvo->attached_output)) | |
1212 | return; | |
e2f0ba97 | 1213 | |
6651819b DV |
1214 | /* lvds has a special fixed output timing. */ |
1215 | if (intel_sdvo->is_lvds) | |
1216 | intel_sdvo_get_dtd_from_mode(&output_dtd, | |
1217 | intel_sdvo->sdvo_lvds_fixed_mode); | |
1218 | else | |
1219 | intel_sdvo_get_dtd_from_mode(&output_dtd, mode); | |
c8d4bb54 DV |
1220 | if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd)) |
1221 | DRM_INFO("Setting output timings on %s failed\n", | |
1222 | SDVO_NAME(intel_sdvo)); | |
79e53945 JB |
1223 | |
1224 | /* Set the input timing to the screen. Assume always input 0. */ | |
32aad86f CW |
1225 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
1226 | return; | |
79e53945 | 1227 | |
6e3c9717 | 1228 | if (crtc->config->has_hdmi_sink) { |
97aaf910 CW |
1229 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI); |
1230 | intel_sdvo_set_colorimetry(intel_sdvo, | |
1231 | SDVO_COLORIMETRY_RGB256); | |
abedc077 | 1232 | intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode); |
97aaf910 CW |
1233 | } else |
1234 | intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI); | |
7026d4ac | 1235 | |
6c9547ff CW |
1236 | if (intel_sdvo->is_tv && |
1237 | !intel_sdvo_set_tv_format(intel_sdvo)) | |
1238 | return; | |
e2f0ba97 | 1239 | |
6651819b | 1240 | intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode); |
eeb47937 | 1241 | |
e751823d EE |
1242 | if (intel_sdvo->is_tv || intel_sdvo->is_lvds) |
1243 | input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags; | |
c8d4bb54 DV |
1244 | if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd)) |
1245 | DRM_INFO("Setting input timings on %s failed\n", | |
1246 | SDVO_NAME(intel_sdvo)); | |
79e53945 | 1247 | |
6e3c9717 | 1248 | switch (crtc->config->pixel_multiplier) { |
6c9547ff | 1249 | default: |
fd0753cf | 1250 | WARN(1, "unknown pixel multiplier specified\n"); |
32aad86f CW |
1251 | case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break; |
1252 | case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break; | |
1253 | case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break; | |
79e53945 | 1254 | } |
32aad86f CW |
1255 | if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate)) |
1256 | return; | |
79e53945 JB |
1257 | |
1258 | /* Set the SDVO control regs. */ | |
a6c45cf0 | 1259 | if (INTEL_INFO(dev)->gen >= 4) { |
ba68e086 PZ |
1260 | /* The real mode polarity is set by the SDVO commands, using |
1261 | * struct intel_sdvo_dtd. */ | |
1262 | sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH; | |
6e3c9717 | 1263 | if (!HAS_PCH_SPLIT(dev) && crtc->config->limited_color_range) |
69f5acc8 | 1264 | sdvox |= HDMI_COLOR_RANGE_16_235; |
6714afb1 CW |
1265 | if (INTEL_INFO(dev)->gen < 5) |
1266 | sdvox |= SDVO_BORDER_ENABLE; | |
e2f0ba97 | 1267 | } else { |
6c9547ff | 1268 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
ea5b213a | 1269 | switch (intel_sdvo->sdvo_reg) { |
e2debe91 | 1270 | case GEN3_SDVOB: |
e2f0ba97 JB |
1271 | sdvox &= SDVOB_PRESERVE_MASK; |
1272 | break; | |
e2debe91 | 1273 | case GEN3_SDVOC: |
e2f0ba97 JB |
1274 | sdvox &= SDVOC_PRESERVE_MASK; |
1275 | break; | |
1276 | } | |
1277 | sdvox |= (9 << 19) | SDVO_BORDER_ENABLE; | |
1278 | } | |
3573c410 PZ |
1279 | |
1280 | if (INTEL_PCH_TYPE(dev) >= PCH_CPT) | |
eeb47937 | 1281 | sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe); |
3573c410 | 1282 | else |
eeb47937 | 1283 | sdvox |= SDVO_PIPE_SEL(crtc->pipe); |
3573c410 | 1284 | |
da79de97 | 1285 | if (intel_sdvo->has_hdmi_audio) |
6c9547ff | 1286 | sdvox |= SDVO_AUDIO_ENABLE; |
79e53945 | 1287 | |
a6c45cf0 | 1288 | if (INTEL_INFO(dev)->gen >= 4) { |
e2f0ba97 JB |
1289 | /* done in crtc_mode_set as the dpll_md reg must be written early */ |
1290 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { | |
1291 | /* done in crtc_mode_set as it lives inside the dpll register */ | |
79e53945 | 1292 | } else { |
6e3c9717 | 1293 | sdvox |= (crtc->config->pixel_multiplier - 1) |
6cc5f341 | 1294 | << SDVO_PORT_MULTIPLY_SHIFT; |
79e53945 JB |
1295 | } |
1296 | ||
6714afb1 CW |
1297 | if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL && |
1298 | INTEL_INFO(dev)->gen < 5) | |
12682a97 | 1299 | sdvox |= SDVO_STALL_SELECT; |
ea5b213a | 1300 | intel_sdvo_write_sdvox(intel_sdvo, sdvox); |
79e53945 JB |
1301 | } |
1302 | ||
4ac41f47 | 1303 | static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector) |
79e53945 | 1304 | { |
4ac41f47 DV |
1305 | struct intel_sdvo_connector *intel_sdvo_connector = |
1306 | to_intel_sdvo_connector(&connector->base); | |
1307 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base); | |
2f28c50b | 1308 | u16 active_outputs = 0; |
4ac41f47 DV |
1309 | |
1310 | intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); | |
1311 | ||
1312 | if (active_outputs & intel_sdvo_connector->output_flag) | |
1313 | return true; | |
1314 | else | |
1315 | return false; | |
1316 | } | |
1317 | ||
1318 | static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder, | |
1319 | enum pipe *pipe) | |
1320 | { | |
1321 | struct drm_device *dev = encoder->base.dev; | |
79e53945 | 1322 | struct drm_i915_private *dev_priv = dev->dev_private; |
8aca63aa | 1323 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
2f28c50b | 1324 | u16 active_outputs = 0; |
4ac41f47 DV |
1325 | u32 tmp; |
1326 | ||
1327 | tmp = I915_READ(intel_sdvo->sdvo_reg); | |
7a7d1fb7 | 1328 | intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs); |
4ac41f47 | 1329 | |
7a7d1fb7 | 1330 | if (!(tmp & SDVO_ENABLE) && (active_outputs == 0)) |
4ac41f47 DV |
1331 | return false; |
1332 | ||
1333 | if (HAS_PCH_CPT(dev)) | |
1334 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
1335 | else | |
1336 | *pipe = PORT_TO_PIPE(tmp); | |
1337 | ||
1338 | return true; | |
1339 | } | |
1340 | ||
045ac3b5 | 1341 | static void intel_sdvo_get_config(struct intel_encoder *encoder, |
5cec258b | 1342 | struct intel_crtc_state *pipe_config) |
045ac3b5 | 1343 | { |
6c49f241 DV |
1344 | struct drm_device *dev = encoder->base.dev; |
1345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8aca63aa | 1346 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
045ac3b5 | 1347 | struct intel_sdvo_dtd dtd; |
6c49f241 | 1348 | int encoder_pixel_multiplier = 0; |
18442d08 | 1349 | int dotclock; |
6c49f241 DV |
1350 | u32 flags = 0, sdvox; |
1351 | u8 val; | |
045ac3b5 JB |
1352 | bool ret; |
1353 | ||
b5a9fa09 DV |
1354 | sdvox = I915_READ(intel_sdvo->sdvo_reg); |
1355 | ||
045ac3b5 JB |
1356 | ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd); |
1357 | if (!ret) { | |
bb760063 DV |
1358 | /* Some sdvo encoders are not spec compliant and don't |
1359 | * implement the mandatory get_timings function. */ | |
045ac3b5 | 1360 | DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n"); |
bb760063 DV |
1361 | pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS; |
1362 | } else { | |
1363 | if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE) | |
1364 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1365 | else | |
1366 | flags |= DRM_MODE_FLAG_NHSYNC; | |
045ac3b5 | 1367 | |
bb760063 DV |
1368 | if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE) |
1369 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1370 | else | |
1371 | flags |= DRM_MODE_FLAG_NVSYNC; | |
045ac3b5 JB |
1372 | } |
1373 | ||
2d112de7 | 1374 | pipe_config->base.adjusted_mode.flags |= flags; |
045ac3b5 | 1375 | |
fdafa9e2 DV |
1376 | /* |
1377 | * pixel multiplier readout is tricky: Only on i915g/gm it is stored in | |
1378 | * the sdvo port register, on all other platforms it is part of the dpll | |
1379 | * state. Since the general pipe state readout happens before the | |
1380 | * encoder->get_config we so already have a valid pixel multplier on all | |
1381 | * other platfroms. | |
1382 | */ | |
6c49f241 | 1383 | if (IS_I915G(dev) || IS_I915GM(dev)) { |
6c49f241 DV |
1384 | pipe_config->pixel_multiplier = |
1385 | ((sdvox & SDVO_PORT_MULTIPLY_MASK) | |
1386 | >> SDVO_PORT_MULTIPLY_SHIFT) + 1; | |
1387 | } | |
045ac3b5 | 1388 | |
2b85886a VS |
1389 | dotclock = pipe_config->port_clock; |
1390 | if (pipe_config->pixel_multiplier) | |
1391 | dotclock /= pipe_config->pixel_multiplier; | |
18442d08 VS |
1392 | |
1393 | if (HAS_PCH_SPLIT(dev)) | |
1394 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
1395 | ||
2d112de7 | 1396 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
18442d08 | 1397 | |
6c49f241 | 1398 | /* Cross check the port pixel multiplier with the sdvo encoder state. */ |
53b91408 DL |
1399 | if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT, |
1400 | &val, 1)) { | |
1401 | switch (val) { | |
1402 | case SDVO_CLOCK_RATE_MULT_1X: | |
1403 | encoder_pixel_multiplier = 1; | |
1404 | break; | |
1405 | case SDVO_CLOCK_RATE_MULT_2X: | |
1406 | encoder_pixel_multiplier = 2; | |
1407 | break; | |
1408 | case SDVO_CLOCK_RATE_MULT_4X: | |
1409 | encoder_pixel_multiplier = 4; | |
1410 | break; | |
1411 | } | |
6c49f241 | 1412 | } |
fdafa9e2 | 1413 | |
b5a9fa09 DV |
1414 | if (sdvox & HDMI_COLOR_RANGE_16_235) |
1415 | pipe_config->limited_color_range = true; | |
1416 | ||
9f04003e DV |
1417 | if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE, |
1418 | &val, 1)) { | |
1419 | if (val == SDVO_ENCODE_HDMI) | |
1420 | pipe_config->has_hdmi_sink = true; | |
1421 | } | |
1422 | ||
6c49f241 DV |
1423 | WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier, |
1424 | "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n", | |
1425 | pipe_config->pixel_multiplier, encoder_pixel_multiplier); | |
045ac3b5 JB |
1426 | } |
1427 | ||
ce22c320 DV |
1428 | static void intel_disable_sdvo(struct intel_encoder *encoder) |
1429 | { | |
1430 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
8aca63aa | 1431 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
ce22c320 DV |
1432 | u32 temp; |
1433 | ||
1434 | intel_sdvo_set_active_outputs(intel_sdvo, 0); | |
1435 | if (0) | |
1436 | intel_sdvo_set_encoder_power_state(intel_sdvo, | |
1437 | DRM_MODE_DPMS_OFF); | |
1438 | ||
1439 | temp = I915_READ(intel_sdvo->sdvo_reg); | |
1440 | if ((temp & SDVO_ENABLE) != 0) { | |
776ca7cf CW |
1441 | /* HW workaround for IBX, we need to move the port to |
1442 | * transcoder A before disabling it. */ | |
1443 | if (HAS_PCH_IBX(encoder->base.dev)) { | |
1444 | struct drm_crtc *crtc = encoder->base.crtc; | |
1445 | int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1; | |
1446 | ||
1447 | if (temp & SDVO_PIPE_B_SELECT) { | |
1448 | temp &= ~SDVO_PIPE_B_SELECT; | |
1449 | I915_WRITE(intel_sdvo->sdvo_reg, temp); | |
1450 | POSTING_READ(intel_sdvo->sdvo_reg); | |
1451 | ||
1452 | /* Again we need to write this twice. */ | |
1453 | I915_WRITE(intel_sdvo->sdvo_reg, temp); | |
1454 | POSTING_READ(intel_sdvo->sdvo_reg); | |
1455 | ||
1456 | /* Transcoder selection bits only update | |
1457 | * effectively on vblank. */ | |
1458 | if (crtc) | |
1459 | intel_wait_for_vblank(encoder->base.dev, pipe); | |
1460 | else | |
1461 | msleep(50); | |
1462 | } | |
1463 | } | |
1464 | ||
ce22c320 DV |
1465 | intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE); |
1466 | } | |
1467 | } | |
1468 | ||
1469 | static void intel_enable_sdvo(struct intel_encoder *encoder) | |
1470 | { | |
1471 | struct drm_device *dev = encoder->base.dev; | |
1472 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8aca63aa | 1473 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
ce22c320 | 1474 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
79e53945 | 1475 | u32 temp; |
ce22c320 DV |
1476 | bool input1, input2; |
1477 | int i; | |
d0a7b6de | 1478 | bool success; |
ce22c320 DV |
1479 | |
1480 | temp = I915_READ(intel_sdvo->sdvo_reg); | |
776ca7cf CW |
1481 | if ((temp & SDVO_ENABLE) == 0) { |
1482 | /* HW workaround for IBX, we need to move the port | |
dc0fa718 PZ |
1483 | * to transcoder A before disabling it, so restore it here. */ |
1484 | if (HAS_PCH_IBX(dev)) | |
1485 | temp |= SDVO_PIPE_SEL(intel_crtc->pipe); | |
776ca7cf | 1486 | |
ce22c320 | 1487 | intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE); |
776ca7cf | 1488 | } |
ce22c320 DV |
1489 | for (i = 0; i < 2; i++) |
1490 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
1491 | ||
d0a7b6de | 1492 | success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2); |
ce22c320 DV |
1493 | /* Warn if the device reported failure to sync. |
1494 | * A lot of SDVO devices fail to notify of sync, but it's | |
1495 | * a given it the status is a success, we succeeded. | |
1496 | */ | |
d0a7b6de | 1497 | if (success && !input1) { |
ce22c320 DV |
1498 | DRM_DEBUG_KMS("First %s output reported failure to " |
1499 | "sync\n", SDVO_NAME(intel_sdvo)); | |
1500 | } | |
1501 | ||
1502 | if (0) | |
1503 | intel_sdvo_set_encoder_power_state(intel_sdvo, | |
1504 | DRM_MODE_DPMS_ON); | |
1505 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); | |
1506 | } | |
1507 | ||
6b1c087b | 1508 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
b2cabb0e | 1509 | static void intel_sdvo_dpms(struct drm_connector *connector, int mode) |
79e53945 | 1510 | { |
b2cabb0e DV |
1511 | struct drm_crtc *crtc; |
1512 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); | |
1513 | ||
1514 | /* dvo supports only 2 dpms states. */ | |
1515 | if (mode != DRM_MODE_DPMS_ON) | |
1516 | mode = DRM_MODE_DPMS_OFF; | |
1517 | ||
1518 | if (mode == connector->dpms) | |
1519 | return; | |
1520 | ||
1521 | connector->dpms = mode; | |
1522 | ||
1523 | /* Only need to change hw state when actually enabled */ | |
1524 | crtc = intel_sdvo->base.base.crtc; | |
1525 | if (!crtc) { | |
1526 | intel_sdvo->base.connectors_active = false; | |
1527 | return; | |
1528 | } | |
79e53945 | 1529 | |
6b1c087b JN |
1530 | /* We set active outputs manually below in case pipe dpms doesn't change |
1531 | * due to cloning. */ | |
79e53945 | 1532 | if (mode != DRM_MODE_DPMS_ON) { |
ea5b213a | 1533 | intel_sdvo_set_active_outputs(intel_sdvo, 0); |
79e53945 | 1534 | if (0) |
ea5b213a | 1535 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
79e53945 | 1536 | |
b2cabb0e DV |
1537 | intel_sdvo->base.connectors_active = false; |
1538 | ||
1539 | intel_crtc_update_dpms(crtc); | |
79e53945 | 1540 | } else { |
b2cabb0e DV |
1541 | intel_sdvo->base.connectors_active = true; |
1542 | ||
1543 | intel_crtc_update_dpms(crtc); | |
79e53945 JB |
1544 | |
1545 | if (0) | |
ea5b213a CW |
1546 | intel_sdvo_set_encoder_power_state(intel_sdvo, mode); |
1547 | intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output); | |
79e53945 | 1548 | } |
0a91ca29 | 1549 | |
b980514c | 1550 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
1551 | } |
1552 | ||
c19de8eb DL |
1553 | static enum drm_mode_status |
1554 | intel_sdvo_mode_valid(struct drm_connector *connector, | |
1555 | struct drm_display_mode *mode) | |
79e53945 | 1556 | { |
df0e9248 | 1557 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
79e53945 JB |
1558 | |
1559 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) | |
1560 | return MODE_NO_DBLESCAN; | |
1561 | ||
ea5b213a | 1562 | if (intel_sdvo->pixel_clock_min > mode->clock) |
79e53945 JB |
1563 | return MODE_CLOCK_LOW; |
1564 | ||
ea5b213a | 1565 | if (intel_sdvo->pixel_clock_max < mode->clock) |
79e53945 JB |
1566 | return MODE_CLOCK_HIGH; |
1567 | ||
8545423a | 1568 | if (intel_sdvo->is_lvds) { |
ea5b213a | 1569 | if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay) |
12682a97 | 1570 | return MODE_PANEL; |
1571 | ||
ea5b213a | 1572 | if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay) |
12682a97 | 1573 | return MODE_PANEL; |
1574 | } | |
1575 | ||
79e53945 JB |
1576 | return MODE_OK; |
1577 | } | |
1578 | ||
ea5b213a | 1579 | static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps) |
79e53945 | 1580 | { |
1a3665c8 | 1581 | BUILD_BUG_ON(sizeof(*caps) != 8); |
e957d772 CW |
1582 | if (!intel_sdvo_get_value(intel_sdvo, |
1583 | SDVO_CMD_GET_DEVICE_CAPS, | |
1584 | caps, sizeof(*caps))) | |
1585 | return false; | |
1586 | ||
1587 | DRM_DEBUG_KMS("SDVO capabilities:\n" | |
1588 | " vendor_id: %d\n" | |
1589 | " device_id: %d\n" | |
1590 | " device_rev_id: %d\n" | |
1591 | " sdvo_version_major: %d\n" | |
1592 | " sdvo_version_minor: %d\n" | |
1593 | " sdvo_inputs_mask: %d\n" | |
1594 | " smooth_scaling: %d\n" | |
1595 | " sharp_scaling: %d\n" | |
1596 | " up_scaling: %d\n" | |
1597 | " down_scaling: %d\n" | |
1598 | " stall_support: %d\n" | |
1599 | " output_flags: %d\n", | |
1600 | caps->vendor_id, | |
1601 | caps->device_id, | |
1602 | caps->device_rev_id, | |
1603 | caps->sdvo_version_major, | |
1604 | caps->sdvo_version_minor, | |
1605 | caps->sdvo_inputs_mask, | |
1606 | caps->smooth_scaling, | |
1607 | caps->sharp_scaling, | |
1608 | caps->up_scaling, | |
1609 | caps->down_scaling, | |
1610 | caps->stall_support, | |
1611 | caps->output_flags); | |
1612 | ||
1613 | return true; | |
79e53945 JB |
1614 | } |
1615 | ||
5fa7ac9c | 1616 | static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo) |
79e53945 | 1617 | { |
768b107e | 1618 | struct drm_device *dev = intel_sdvo->base.base.dev; |
5fa7ac9c | 1619 | uint16_t hotplug; |
79e53945 | 1620 | |
1d83d957 VS |
1621 | if (!I915_HAS_HOTPLUG(dev)) |
1622 | return 0; | |
1623 | ||
768b107e DV |
1624 | /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise |
1625 | * on the line. */ | |
1626 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
5fa7ac9c | 1627 | return 0; |
768b107e | 1628 | |
5fa7ac9c JN |
1629 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, |
1630 | &hotplug, sizeof(hotplug))) | |
1631 | return 0; | |
768b107e | 1632 | |
5fa7ac9c | 1633 | return hotplug; |
79e53945 JB |
1634 | } |
1635 | ||
cc68c81a | 1636 | static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder) |
79e53945 | 1637 | { |
8aca63aa | 1638 | struct intel_sdvo *intel_sdvo = to_sdvo(encoder); |
79e53945 | 1639 | |
5fa7ac9c JN |
1640 | intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, |
1641 | &intel_sdvo->hotplug_active, 2); | |
79e53945 JB |
1642 | } |
1643 | ||
fb7a46f3 | 1644 | static bool |
ea5b213a | 1645 | intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo) |
fb7a46f3 | 1646 | { |
bc65212c | 1647 | /* Is there more than one type of output? */ |
2294488d | 1648 | return hweight16(intel_sdvo->caps.output_flags) > 1; |
fb7a46f3 | 1649 | } |
1650 | ||
f899fc64 | 1651 | static struct edid * |
e957d772 | 1652 | intel_sdvo_get_edid(struct drm_connector *connector) |
f899fc64 | 1653 | { |
e957d772 CW |
1654 | struct intel_sdvo *sdvo = intel_attached_sdvo(connector); |
1655 | return drm_get_edid(connector, &sdvo->ddc); | |
f899fc64 CW |
1656 | } |
1657 | ||
ff482d83 CW |
1658 | /* Mac mini hack -- use the same DDC as the analog connector */ |
1659 | static struct edid * | |
1660 | intel_sdvo_get_analog_edid(struct drm_connector *connector) | |
1661 | { | |
f899fc64 | 1662 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
ff482d83 | 1663 | |
0c1dab89 | 1664 | return drm_get_edid(connector, |
3bd7d909 | 1665 | intel_gmbus_get_adapter(dev_priv, |
41aa3448 | 1666 | dev_priv->vbt.crt_ddc_pin)); |
ff482d83 CW |
1667 | } |
1668 | ||
c43b5634 | 1669 | static enum drm_connector_status |
8bf38485 | 1670 | intel_sdvo_tmds_sink_detect(struct drm_connector *connector) |
9dff6af8 | 1671 | { |
df0e9248 | 1672 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
9d1a903d CW |
1673 | enum drm_connector_status status; |
1674 | struct edid *edid; | |
9dff6af8 | 1675 | |
e957d772 | 1676 | edid = intel_sdvo_get_edid(connector); |
57cdaf90 | 1677 | |
ea5b213a | 1678 | if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) { |
e957d772 | 1679 | u8 ddc, saved_ddc = intel_sdvo->ddc_bus; |
9d1a903d | 1680 | |
7c3f0a27 ZY |
1681 | /* |
1682 | * Don't use the 1 as the argument of DDC bus switch to get | |
1683 | * the EDID. It is used for SDVO SPD ROM. | |
1684 | */ | |
9d1a903d | 1685 | for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) { |
e957d772 CW |
1686 | intel_sdvo->ddc_bus = ddc; |
1687 | edid = intel_sdvo_get_edid(connector); | |
1688 | if (edid) | |
7c3f0a27 | 1689 | break; |
7c3f0a27 | 1690 | } |
e957d772 CW |
1691 | /* |
1692 | * If we found the EDID on the other bus, | |
1693 | * assume that is the correct DDC bus. | |
1694 | */ | |
1695 | if (edid == NULL) | |
1696 | intel_sdvo->ddc_bus = saved_ddc; | |
7c3f0a27 | 1697 | } |
9d1a903d CW |
1698 | |
1699 | /* | |
1700 | * When there is no edid and no monitor is connected with VGA | |
1701 | * port, try to use the CRT ddc to read the EDID for DVI-connector. | |
57cdaf90 | 1702 | */ |
ff482d83 CW |
1703 | if (edid == NULL) |
1704 | edid = intel_sdvo_get_analog_edid(connector); | |
149c36a3 | 1705 | |
2f551c84 | 1706 | status = connector_status_unknown; |
9dff6af8 | 1707 | if (edid != NULL) { |
149c36a3 | 1708 | /* DDC bus is shared, match EDID to connector type */ |
9d1a903d CW |
1709 | if (edid->input & DRM_EDID_INPUT_DIGITAL) { |
1710 | status = connector_status_connected; | |
da79de97 CW |
1711 | if (intel_sdvo->is_hdmi) { |
1712 | intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid); | |
1713 | intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid); | |
abedc077 VS |
1714 | intel_sdvo->rgb_quant_range_selectable = |
1715 | drm_rgb_quant_range_selectable(edid); | |
da79de97 | 1716 | } |
13946743 CW |
1717 | } else |
1718 | status = connector_status_disconnected; | |
9d1a903d CW |
1719 | kfree(edid); |
1720 | } | |
7f36e7ed CW |
1721 | |
1722 | if (status == connector_status_connected) { | |
1723 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); | |
c3e5f67b DV |
1724 | if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO) |
1725 | intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON); | |
7f36e7ed CW |
1726 | } |
1727 | ||
2b8d33f7 | 1728 | return status; |
9dff6af8 ML |
1729 | } |
1730 | ||
52220085 CW |
1731 | static bool |
1732 | intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo, | |
1733 | struct edid *edid) | |
1734 | { | |
1735 | bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL); | |
1736 | bool connector_is_digital = !!IS_DIGITAL(sdvo); | |
1737 | ||
1738 | DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n", | |
1739 | connector_is_digital, monitor_is_digital); | |
1740 | return connector_is_digital == monitor_is_digital; | |
1741 | } | |
1742 | ||
7b334fcb | 1743 | static enum drm_connector_status |
930a9e28 | 1744 | intel_sdvo_detect(struct drm_connector *connector, bool force) |
79e53945 | 1745 | { |
fb7a46f3 | 1746 | uint16_t response; |
df0e9248 | 1747 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
615fb93f | 1748 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
14571b4c | 1749 | enum drm_connector_status ret; |
79e53945 | 1750 | |
164c8598 | 1751 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 1752 | connector->base.id, connector->name); |
164c8598 | 1753 | |
fc37381c CW |
1754 | if (!intel_sdvo_get_value(intel_sdvo, |
1755 | SDVO_CMD_GET_ATTACHED_DISPLAYS, | |
1756 | &response, 2)) | |
32aad86f | 1757 | return connector_status_unknown; |
79e53945 | 1758 | |
e957d772 CW |
1759 | DRM_DEBUG_KMS("SDVO response %d %d [%x]\n", |
1760 | response & 0xff, response >> 8, | |
1761 | intel_sdvo_connector->output_flag); | |
e2f0ba97 | 1762 | |
fb7a46f3 | 1763 | if (response == 0) |
79e53945 | 1764 | return connector_status_disconnected; |
fb7a46f3 | 1765 | |
ea5b213a | 1766 | intel_sdvo->attached_output = response; |
14571b4c | 1767 | |
97aaf910 CW |
1768 | intel_sdvo->has_hdmi_monitor = false; |
1769 | intel_sdvo->has_hdmi_audio = false; | |
abedc077 | 1770 | intel_sdvo->rgb_quant_range_selectable = false; |
97aaf910 | 1771 | |
615fb93f | 1772 | if ((intel_sdvo_connector->output_flag & response) == 0) |
14571b4c | 1773 | ret = connector_status_disconnected; |
13946743 | 1774 | else if (IS_TMDS(intel_sdvo_connector)) |
8bf38485 | 1775 | ret = intel_sdvo_tmds_sink_detect(connector); |
13946743 CW |
1776 | else { |
1777 | struct edid *edid; | |
1778 | ||
1779 | /* if we have an edid check it matches the connection */ | |
1780 | edid = intel_sdvo_get_edid(connector); | |
1781 | if (edid == NULL) | |
1782 | edid = intel_sdvo_get_analog_edid(connector); | |
1783 | if (edid != NULL) { | |
52220085 CW |
1784 | if (intel_sdvo_connector_matches_edid(intel_sdvo_connector, |
1785 | edid)) | |
13946743 | 1786 | ret = connector_status_connected; |
52220085 CW |
1787 | else |
1788 | ret = connector_status_disconnected; | |
1789 | ||
13946743 CW |
1790 | kfree(edid); |
1791 | } else | |
1792 | ret = connector_status_connected; | |
1793 | } | |
14571b4c ZW |
1794 | |
1795 | /* May update encoder flag for like clock for SDVO TV, etc.*/ | |
1796 | if (ret == connector_status_connected) { | |
ea5b213a CW |
1797 | intel_sdvo->is_tv = false; |
1798 | intel_sdvo->is_lvds = false; | |
14571b4c | 1799 | |
09ede541 | 1800 | if (response & SDVO_TV_MASK) |
ea5b213a | 1801 | intel_sdvo->is_tv = true; |
14571b4c | 1802 | if (response & SDVO_LVDS_MASK) |
8545423a | 1803 | intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL; |
fb7a46f3 | 1804 | } |
14571b4c ZW |
1805 | |
1806 | return ret; | |
79e53945 JB |
1807 | } |
1808 | ||
e2f0ba97 | 1809 | static void intel_sdvo_get_ddc_modes(struct drm_connector *connector) |
79e53945 | 1810 | { |
ff482d83 | 1811 | struct edid *edid; |
79e53945 | 1812 | |
46a3f4a3 | 1813 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 1814 | connector->base.id, connector->name); |
46a3f4a3 | 1815 | |
79e53945 | 1816 | /* set the bus switch and get the modes */ |
e957d772 | 1817 | edid = intel_sdvo_get_edid(connector); |
79e53945 | 1818 | |
57cdaf90 KP |
1819 | /* |
1820 | * Mac mini hack. On this device, the DVI-I connector shares one DDC | |
1821 | * link between analog and digital outputs. So, if the regular SDVO | |
1822 | * DDC fails, check to see if the analog output is disconnected, in | |
1823 | * which case we'll look there for the digital DDC data. | |
e2f0ba97 | 1824 | */ |
f899fc64 CW |
1825 | if (edid == NULL) |
1826 | edid = intel_sdvo_get_analog_edid(connector); | |
1827 | ||
ff482d83 | 1828 | if (edid != NULL) { |
52220085 CW |
1829 | if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector), |
1830 | edid)) { | |
0c1dab89 CW |
1831 | drm_mode_connector_update_edid_property(connector, edid); |
1832 | drm_add_edid_modes(connector, edid); | |
1833 | } | |
13946743 | 1834 | |
ff482d83 | 1835 | kfree(edid); |
e2f0ba97 | 1836 | } |
e2f0ba97 JB |
1837 | } |
1838 | ||
1839 | /* | |
1840 | * Set of SDVO TV modes. | |
1841 | * Note! This is in reply order (see loop in get_tv_modes). | |
1842 | * XXX: all 60Hz refresh? | |
1843 | */ | |
b1f559ec | 1844 | static const struct drm_display_mode sdvo_tv_modes[] = { |
7026d4ac ZW |
1845 | { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384, |
1846 | 416, 0, 200, 201, 232, 233, 0, | |
e2f0ba97 | 1847 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1848 | { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384, |
1849 | 416, 0, 240, 241, 272, 273, 0, | |
e2f0ba97 | 1850 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1851 | { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464, |
1852 | 496, 0, 300, 301, 332, 333, 0, | |
e2f0ba97 | 1853 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1854 | { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704, |
1855 | 736, 0, 350, 351, 382, 383, 0, | |
e2f0ba97 | 1856 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1857 | { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704, |
1858 | 736, 0, 400, 401, 432, 433, 0, | |
e2f0ba97 | 1859 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1860 | { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704, |
1861 | 736, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1862 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1863 | { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768, |
1864 | 800, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1865 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1866 | { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768, |
1867 | 800, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1868 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1869 | { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784, |
1870 | 816, 0, 350, 351, 382, 383, 0, | |
e2f0ba97 | 1871 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1872 | { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784, |
1873 | 816, 0, 400, 401, 432, 433, 0, | |
e2f0ba97 | 1874 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1875 | { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784, |
1876 | 816, 0, 480, 481, 512, 513, 0, | |
e2f0ba97 | 1877 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1878 | { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784, |
1879 | 816, 0, 540, 541, 572, 573, 0, | |
e2f0ba97 | 1880 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1881 | { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784, |
1882 | 816, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1883 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1884 | { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832, |
1885 | 864, 0, 576, 577, 608, 609, 0, | |
e2f0ba97 | 1886 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1887 | { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864, |
1888 | 896, 0, 600, 601, 632, 633, 0, | |
e2f0ba97 | 1889 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1890 | { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896, |
1891 | 928, 0, 624, 625, 656, 657, 0, | |
e2f0ba97 | 1892 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1893 | { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984, |
1894 | 1016, 0, 766, 767, 798, 799, 0, | |
e2f0ba97 | 1895 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1896 | { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088, |
1897 | 1120, 0, 768, 769, 800, 801, 0, | |
e2f0ba97 | 1898 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
7026d4ac ZW |
1899 | { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344, |
1900 | 1376, 0, 1024, 1025, 1056, 1057, 0, | |
e2f0ba97 JB |
1901 | DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, |
1902 | }; | |
1903 | ||
1904 | static void intel_sdvo_get_tv_modes(struct drm_connector *connector) | |
1905 | { | |
df0e9248 | 1906 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
7026d4ac | 1907 | struct intel_sdvo_sdtv_resolution_request tv_res; |
ce6feabd ZY |
1908 | uint32_t reply = 0, format_map = 0; |
1909 | int i; | |
e2f0ba97 | 1910 | |
46a3f4a3 | 1911 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 1912 | connector->base.id, connector->name); |
46a3f4a3 | 1913 | |
e2f0ba97 JB |
1914 | /* Read the list of supported input resolutions for the selected TV |
1915 | * format. | |
1916 | */ | |
40039750 | 1917 | format_map = 1 << intel_sdvo->tv_format_index; |
ce6feabd | 1918 | memcpy(&tv_res, &format_map, |
32aad86f | 1919 | min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request))); |
ce6feabd | 1920 | |
32aad86f CW |
1921 | if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output)) |
1922 | return; | |
ce6feabd | 1923 | |
32aad86f | 1924 | BUILD_BUG_ON(sizeof(tv_res) != 3); |
e957d772 CW |
1925 | if (!intel_sdvo_write_cmd(intel_sdvo, |
1926 | SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT, | |
32aad86f CW |
1927 | &tv_res, sizeof(tv_res))) |
1928 | return; | |
1929 | if (!intel_sdvo_read_response(intel_sdvo, &reply, 3)) | |
e2f0ba97 JB |
1930 | return; |
1931 | ||
1932 | for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++) | |
7026d4ac ZW |
1933 | if (reply & (1 << i)) { |
1934 | struct drm_display_mode *nmode; | |
1935 | nmode = drm_mode_duplicate(connector->dev, | |
32aad86f | 1936 | &sdvo_tv_modes[i]); |
7026d4ac ZW |
1937 | if (nmode) |
1938 | drm_mode_probed_add(connector, nmode); | |
1939 | } | |
e2f0ba97 JB |
1940 | } |
1941 | ||
7086c87f ML |
1942 | static void intel_sdvo_get_lvds_modes(struct drm_connector *connector) |
1943 | { | |
df0e9248 | 1944 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
7086c87f | 1945 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
12682a97 | 1946 | struct drm_display_mode *newmode; |
7086c87f | 1947 | |
46a3f4a3 | 1948 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 1949 | connector->base.id, connector->name); |
46a3f4a3 | 1950 | |
7086c87f | 1951 | /* |
c3456fb3 | 1952 | * Fetch modes from VBT. For SDVO prefer the VBT mode since some |
4300a0f8 | 1953 | * SDVO->LVDS transcoders can't cope with the EDID mode. |
7086c87f | 1954 | */ |
41aa3448 | 1955 | if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) { |
7086c87f | 1956 | newmode = drm_mode_duplicate(connector->dev, |
41aa3448 | 1957 | dev_priv->vbt.sdvo_lvds_vbt_mode); |
7086c87f ML |
1958 | if (newmode != NULL) { |
1959 | /* Guarantee the mode is preferred */ | |
1960 | newmode->type = (DRM_MODE_TYPE_PREFERRED | | |
1961 | DRM_MODE_TYPE_DRIVER); | |
1962 | drm_mode_probed_add(connector, newmode); | |
1963 | } | |
1964 | } | |
12682a97 | 1965 | |
4300a0f8 DA |
1966 | /* |
1967 | * Attempt to get the mode list from DDC. | |
1968 | * Assume that the preferred modes are | |
1969 | * arranged in priority order. | |
1970 | */ | |
1971 | intel_ddc_get_modes(connector, &intel_sdvo->ddc); | |
1972 | ||
12682a97 | 1973 | list_for_each_entry(newmode, &connector->probed_modes, head) { |
1974 | if (newmode->type & DRM_MODE_TYPE_PREFERRED) { | |
ea5b213a | 1975 | intel_sdvo->sdvo_lvds_fixed_mode = |
12682a97 | 1976 | drm_mode_duplicate(connector->dev, newmode); |
6c9547ff | 1977 | |
8545423a | 1978 | intel_sdvo->is_lvds = true; |
12682a97 | 1979 | break; |
1980 | } | |
1981 | } | |
7086c87f ML |
1982 | } |
1983 | ||
e2f0ba97 JB |
1984 | static int intel_sdvo_get_modes(struct drm_connector *connector) |
1985 | { | |
615fb93f | 1986 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
e2f0ba97 | 1987 | |
615fb93f | 1988 | if (IS_TV(intel_sdvo_connector)) |
e2f0ba97 | 1989 | intel_sdvo_get_tv_modes(connector); |
615fb93f | 1990 | else if (IS_LVDS(intel_sdvo_connector)) |
7086c87f | 1991 | intel_sdvo_get_lvds_modes(connector); |
e2f0ba97 JB |
1992 | else |
1993 | intel_sdvo_get_ddc_modes(connector); | |
1994 | ||
32aad86f | 1995 | return !list_empty(&connector->probed_modes); |
79e53945 JB |
1996 | } |
1997 | ||
1998 | static void intel_sdvo_destroy(struct drm_connector *connector) | |
1999 | { | |
615fb93f | 2000 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
79e53945 | 2001 | |
79e53945 | 2002 | drm_connector_cleanup(connector); |
4b745b1e | 2003 | kfree(intel_sdvo_connector); |
79e53945 JB |
2004 | } |
2005 | ||
1aad7ac0 CW |
2006 | static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector) |
2007 | { | |
2008 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); | |
2009 | struct edid *edid; | |
2010 | bool has_audio = false; | |
2011 | ||
2012 | if (!intel_sdvo->is_hdmi) | |
2013 | return false; | |
2014 | ||
2015 | edid = intel_sdvo_get_edid(connector); | |
2016 | if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL) | |
2017 | has_audio = drm_detect_monitor_audio(edid); | |
38ab8a20 | 2018 | kfree(edid); |
1aad7ac0 CW |
2019 | |
2020 | return has_audio; | |
2021 | } | |
2022 | ||
ce6feabd ZY |
2023 | static int |
2024 | intel_sdvo_set_property(struct drm_connector *connector, | |
2025 | struct drm_property *property, | |
2026 | uint64_t val) | |
2027 | { | |
df0e9248 | 2028 | struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); |
615fb93f | 2029 | struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector); |
e953fd7b | 2030 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
b9219c5e | 2031 | uint16_t temp_value; |
32aad86f CW |
2032 | uint8_t cmd; |
2033 | int ret; | |
ce6feabd | 2034 | |
662595df | 2035 | ret = drm_object_property_set_value(&connector->base, property, val); |
32aad86f CW |
2036 | if (ret) |
2037 | return ret; | |
ce6feabd | 2038 | |
3f43c48d | 2039 | if (property == dev_priv->force_audio_property) { |
1aad7ac0 CW |
2040 | int i = val; |
2041 | bool has_audio; | |
2042 | ||
2043 | if (i == intel_sdvo_connector->force_audio) | |
7f36e7ed CW |
2044 | return 0; |
2045 | ||
1aad7ac0 | 2046 | intel_sdvo_connector->force_audio = i; |
7f36e7ed | 2047 | |
c3e5f67b | 2048 | if (i == HDMI_AUDIO_AUTO) |
1aad7ac0 CW |
2049 | has_audio = intel_sdvo_detect_hdmi_audio(connector); |
2050 | else | |
c3e5f67b | 2051 | has_audio = (i == HDMI_AUDIO_ON); |
7f36e7ed | 2052 | |
1aad7ac0 | 2053 | if (has_audio == intel_sdvo->has_hdmi_audio) |
7f36e7ed | 2054 | return 0; |
7f36e7ed | 2055 | |
1aad7ac0 | 2056 | intel_sdvo->has_hdmi_audio = has_audio; |
7f36e7ed CW |
2057 | goto done; |
2058 | } | |
2059 | ||
e953fd7b | 2060 | if (property == dev_priv->broadcast_rgb_property) { |
ae4edb80 DV |
2061 | bool old_auto = intel_sdvo->color_range_auto; |
2062 | uint32_t old_range = intel_sdvo->color_range; | |
2063 | ||
55bc60db VS |
2064 | switch (val) { |
2065 | case INTEL_BROADCAST_RGB_AUTO: | |
2066 | intel_sdvo->color_range_auto = true; | |
2067 | break; | |
2068 | case INTEL_BROADCAST_RGB_FULL: | |
2069 | intel_sdvo->color_range_auto = false; | |
2070 | intel_sdvo->color_range = 0; | |
2071 | break; | |
2072 | case INTEL_BROADCAST_RGB_LIMITED: | |
2073 | intel_sdvo->color_range_auto = false; | |
4f3a8bc7 PZ |
2074 | /* FIXME: this bit is only valid when using TMDS |
2075 | * encoding and 8 bit per color mode. */ | |
2076 | intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235; | |
55bc60db VS |
2077 | break; |
2078 | default: | |
2079 | return -EINVAL; | |
2080 | } | |
ae4edb80 DV |
2081 | |
2082 | if (old_auto == intel_sdvo->color_range_auto && | |
2083 | old_range == intel_sdvo->color_range) | |
2084 | return 0; | |
2085 | ||
7f36e7ed CW |
2086 | goto done; |
2087 | } | |
2088 | ||
c5521706 CW |
2089 | #define CHECK_PROPERTY(name, NAME) \ |
2090 | if (intel_sdvo_connector->name == property) { \ | |
2091 | if (intel_sdvo_connector->cur_##name == temp_value) return 0; \ | |
2092 | if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \ | |
2093 | cmd = SDVO_CMD_SET_##NAME; \ | |
2094 | intel_sdvo_connector->cur_##name = temp_value; \ | |
2095 | goto set_value; \ | |
2096 | } | |
2097 | ||
2098 | if (property == intel_sdvo_connector->tv_format) { | |
32aad86f CW |
2099 | if (val >= TV_FORMAT_NUM) |
2100 | return -EINVAL; | |
2101 | ||
40039750 | 2102 | if (intel_sdvo->tv_format_index == |
615fb93f | 2103 | intel_sdvo_connector->tv_format_supported[val]) |
32aad86f | 2104 | return 0; |
ce6feabd | 2105 | |
40039750 | 2106 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val]; |
c5521706 | 2107 | goto done; |
32aad86f | 2108 | } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) { |
b9219c5e | 2109 | temp_value = val; |
c5521706 | 2110 | if (intel_sdvo_connector->left == property) { |
662595df | 2111 | drm_object_property_set_value(&connector->base, |
c5521706 | 2112 | intel_sdvo_connector->right, val); |
615fb93f | 2113 | if (intel_sdvo_connector->left_margin == temp_value) |
32aad86f | 2114 | return 0; |
b9219c5e | 2115 | |
615fb93f CW |
2116 | intel_sdvo_connector->left_margin = temp_value; |
2117 | intel_sdvo_connector->right_margin = temp_value; | |
2118 | temp_value = intel_sdvo_connector->max_hscan - | |
c5521706 | 2119 | intel_sdvo_connector->left_margin; |
b9219c5e | 2120 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
c5521706 CW |
2121 | goto set_value; |
2122 | } else if (intel_sdvo_connector->right == property) { | |
662595df | 2123 | drm_object_property_set_value(&connector->base, |
c5521706 | 2124 | intel_sdvo_connector->left, val); |
615fb93f | 2125 | if (intel_sdvo_connector->right_margin == temp_value) |
32aad86f | 2126 | return 0; |
b9219c5e | 2127 | |
615fb93f CW |
2128 | intel_sdvo_connector->left_margin = temp_value; |
2129 | intel_sdvo_connector->right_margin = temp_value; | |
2130 | temp_value = intel_sdvo_connector->max_hscan - | |
2131 | intel_sdvo_connector->left_margin; | |
b9219c5e | 2132 | cmd = SDVO_CMD_SET_OVERSCAN_H; |
c5521706 CW |
2133 | goto set_value; |
2134 | } else if (intel_sdvo_connector->top == property) { | |
662595df | 2135 | drm_object_property_set_value(&connector->base, |
c5521706 | 2136 | intel_sdvo_connector->bottom, val); |
615fb93f | 2137 | if (intel_sdvo_connector->top_margin == temp_value) |
32aad86f | 2138 | return 0; |
b9219c5e | 2139 | |
615fb93f CW |
2140 | intel_sdvo_connector->top_margin = temp_value; |
2141 | intel_sdvo_connector->bottom_margin = temp_value; | |
2142 | temp_value = intel_sdvo_connector->max_vscan - | |
c5521706 | 2143 | intel_sdvo_connector->top_margin; |
b9219c5e | 2144 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
c5521706 CW |
2145 | goto set_value; |
2146 | } else if (intel_sdvo_connector->bottom == property) { | |
662595df | 2147 | drm_object_property_set_value(&connector->base, |
c5521706 | 2148 | intel_sdvo_connector->top, val); |
615fb93f | 2149 | if (intel_sdvo_connector->bottom_margin == temp_value) |
32aad86f CW |
2150 | return 0; |
2151 | ||
615fb93f CW |
2152 | intel_sdvo_connector->top_margin = temp_value; |
2153 | intel_sdvo_connector->bottom_margin = temp_value; | |
2154 | temp_value = intel_sdvo_connector->max_vscan - | |
c5521706 | 2155 | intel_sdvo_connector->top_margin; |
b9219c5e | 2156 | cmd = SDVO_CMD_SET_OVERSCAN_V; |
c5521706 CW |
2157 | goto set_value; |
2158 | } | |
2159 | CHECK_PROPERTY(hpos, HPOS) | |
2160 | CHECK_PROPERTY(vpos, VPOS) | |
2161 | CHECK_PROPERTY(saturation, SATURATION) | |
2162 | CHECK_PROPERTY(contrast, CONTRAST) | |
2163 | CHECK_PROPERTY(hue, HUE) | |
2164 | CHECK_PROPERTY(brightness, BRIGHTNESS) | |
2165 | CHECK_PROPERTY(sharpness, SHARPNESS) | |
2166 | CHECK_PROPERTY(flicker_filter, FLICKER_FILTER) | |
2167 | CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D) | |
2168 | CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE) | |
2169 | CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER) | |
2170 | CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER) | |
e044218a | 2171 | CHECK_PROPERTY(dot_crawl, DOT_CRAWL) |
c5521706 | 2172 | } |
b9219c5e | 2173 | |
c5521706 | 2174 | return -EINVAL; /* unknown property */ |
b9219c5e | 2175 | |
c5521706 CW |
2176 | set_value: |
2177 | if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2)) | |
2178 | return -EIO; | |
b9219c5e | 2179 | |
b9219c5e | 2180 | |
c5521706 | 2181 | done: |
c0c36b94 CW |
2182 | if (intel_sdvo->base.base.crtc) |
2183 | intel_crtc_restore_mode(intel_sdvo->base.base.crtc); | |
c5521706 | 2184 | |
32aad86f | 2185 | return 0; |
c5521706 | 2186 | #undef CHECK_PROPERTY |
ce6feabd ZY |
2187 | } |
2188 | ||
79e53945 | 2189 | static const struct drm_connector_funcs intel_sdvo_connector_funcs = { |
b2cabb0e | 2190 | .dpms = intel_sdvo_dpms, |
79e53945 JB |
2191 | .detect = intel_sdvo_detect, |
2192 | .fill_modes = drm_helper_probe_single_connector_modes, | |
ce6feabd | 2193 | .set_property = intel_sdvo_set_property, |
2545e4a6 | 2194 | .atomic_get_property = intel_connector_atomic_get_property, |
79e53945 | 2195 | .destroy = intel_sdvo_destroy, |
c6f95f27 | 2196 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 2197 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
79e53945 JB |
2198 | }; |
2199 | ||
2200 | static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = { | |
2201 | .get_modes = intel_sdvo_get_modes, | |
2202 | .mode_valid = intel_sdvo_mode_valid, | |
df0e9248 | 2203 | .best_encoder = intel_best_encoder, |
79e53945 JB |
2204 | }; |
2205 | ||
b358d0a6 | 2206 | static void intel_sdvo_enc_destroy(struct drm_encoder *encoder) |
79e53945 | 2207 | { |
8aca63aa | 2208 | struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder)); |
d2a82a6f | 2209 | |
ea5b213a | 2210 | if (intel_sdvo->sdvo_lvds_fixed_mode != NULL) |
d2a82a6f | 2211 | drm_mode_destroy(encoder->dev, |
ea5b213a | 2212 | intel_sdvo->sdvo_lvds_fixed_mode); |
d2a82a6f | 2213 | |
e957d772 | 2214 | i2c_del_adapter(&intel_sdvo->ddc); |
ea5b213a | 2215 | intel_encoder_destroy(encoder); |
79e53945 JB |
2216 | } |
2217 | ||
2218 | static const struct drm_encoder_funcs intel_sdvo_enc_funcs = { | |
2219 | .destroy = intel_sdvo_enc_destroy, | |
2220 | }; | |
2221 | ||
b66d8424 CW |
2222 | static void |
2223 | intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo) | |
2224 | { | |
2225 | uint16_t mask = 0; | |
2226 | unsigned int num_bits; | |
2227 | ||
2228 | /* Make a mask of outputs less than or equal to our own priority in the | |
2229 | * list. | |
2230 | */ | |
2231 | switch (sdvo->controlled_output) { | |
2232 | case SDVO_OUTPUT_LVDS1: | |
2233 | mask |= SDVO_OUTPUT_LVDS1; | |
2234 | case SDVO_OUTPUT_LVDS0: | |
2235 | mask |= SDVO_OUTPUT_LVDS0; | |
2236 | case SDVO_OUTPUT_TMDS1: | |
2237 | mask |= SDVO_OUTPUT_TMDS1; | |
2238 | case SDVO_OUTPUT_TMDS0: | |
2239 | mask |= SDVO_OUTPUT_TMDS0; | |
2240 | case SDVO_OUTPUT_RGB1: | |
2241 | mask |= SDVO_OUTPUT_RGB1; | |
2242 | case SDVO_OUTPUT_RGB0: | |
2243 | mask |= SDVO_OUTPUT_RGB0; | |
2244 | break; | |
2245 | } | |
2246 | ||
2247 | /* Count bits to find what number we are in the priority list. */ | |
2248 | mask &= sdvo->caps.output_flags; | |
2249 | num_bits = hweight16(mask); | |
2250 | /* If more than 3 outputs, default to DDC bus 3 for now. */ | |
2251 | if (num_bits > 3) | |
2252 | num_bits = 3; | |
2253 | ||
2254 | /* Corresponds to SDVO_CONTROL_BUS_DDCx */ | |
2255 | sdvo->ddc_bus = 1 << num_bits; | |
2256 | } | |
79e53945 | 2257 | |
e2f0ba97 JB |
2258 | /** |
2259 | * Choose the appropriate DDC bus for control bus switch command for this | |
2260 | * SDVO output based on the controlled output. | |
2261 | * | |
2262 | * DDC bus number assignment is in a priority order of RGB outputs, then TMDS | |
2263 | * outputs, then LVDS outputs. | |
2264 | */ | |
2265 | static void | |
b1083333 | 2266 | intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv, |
ea5b213a | 2267 | struct intel_sdvo *sdvo, u32 reg) |
e2f0ba97 | 2268 | { |
b1083333 | 2269 | struct sdvo_device_mapping *mapping; |
e2f0ba97 | 2270 | |
eef4eacb | 2271 | if (sdvo->is_sdvob) |
b1083333 AJ |
2272 | mapping = &(dev_priv->sdvo_mappings[0]); |
2273 | else | |
2274 | mapping = &(dev_priv->sdvo_mappings[1]); | |
e2f0ba97 | 2275 | |
b66d8424 CW |
2276 | if (mapping->initialized) |
2277 | sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4); | |
2278 | else | |
2279 | intel_sdvo_guess_ddc_bus(sdvo); | |
e2f0ba97 JB |
2280 | } |
2281 | ||
e957d772 CW |
2282 | static void |
2283 | intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv, | |
2284 | struct intel_sdvo *sdvo, u32 reg) | |
2285 | { | |
2286 | struct sdvo_device_mapping *mapping; | |
46eb3036 | 2287 | u8 pin; |
e957d772 | 2288 | |
eef4eacb | 2289 | if (sdvo->is_sdvob) |
e957d772 CW |
2290 | mapping = &dev_priv->sdvo_mappings[0]; |
2291 | else | |
2292 | mapping = &dev_priv->sdvo_mappings[1]; | |
2293 | ||
88ac7939 JN |
2294 | if (mapping->initialized && |
2295 | intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin)) | |
e957d772 | 2296 | pin = mapping->i2c_pin; |
6cb1612a | 2297 | else |
988c7015 | 2298 | pin = GMBUS_PIN_DPB; |
e957d772 | 2299 | |
6cb1612a JN |
2300 | sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin); |
2301 | ||
2302 | /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow | |
2303 | * our code totally fails once we start using gmbus. Hence fall back to | |
2304 | * bit banging for now. */ | |
2305 | intel_gmbus_force_bit(sdvo->i2c, true); | |
e957d772 CW |
2306 | } |
2307 | ||
fbfcc4f3 JN |
2308 | /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */ |
2309 | static void | |
2310 | intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo) | |
2311 | { | |
2312 | intel_gmbus_force_bit(sdvo->i2c, false); | |
e957d772 CW |
2313 | } |
2314 | ||
e2f0ba97 | 2315 | static bool |
e27d8538 | 2316 | intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device) |
e2f0ba97 | 2317 | { |
97aaf910 | 2318 | return intel_sdvo_check_supp_encode(intel_sdvo); |
e2f0ba97 JB |
2319 | } |
2320 | ||
714605e4 | 2321 | static u8 |
eef4eacb | 2322 | intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo) |
714605e4 | 2323 | { |
2324 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2325 | struct sdvo_device_mapping *my_mapping, *other_mapping; | |
2326 | ||
eef4eacb | 2327 | if (sdvo->is_sdvob) { |
714605e4 | 2328 | my_mapping = &dev_priv->sdvo_mappings[0]; |
2329 | other_mapping = &dev_priv->sdvo_mappings[1]; | |
2330 | } else { | |
2331 | my_mapping = &dev_priv->sdvo_mappings[1]; | |
2332 | other_mapping = &dev_priv->sdvo_mappings[0]; | |
2333 | } | |
2334 | ||
2335 | /* If the BIOS described our SDVO device, take advantage of it. */ | |
2336 | if (my_mapping->slave_addr) | |
2337 | return my_mapping->slave_addr; | |
2338 | ||
2339 | /* If the BIOS only described a different SDVO device, use the | |
2340 | * address that it isn't using. | |
2341 | */ | |
2342 | if (other_mapping->slave_addr) { | |
2343 | if (other_mapping->slave_addr == 0x70) | |
2344 | return 0x72; | |
2345 | else | |
2346 | return 0x70; | |
2347 | } | |
2348 | ||
2349 | /* No SDVO device info is found for another DVO port, | |
2350 | * so use mapping assumption we had before BIOS parsing. | |
2351 | */ | |
eef4eacb | 2352 | if (sdvo->is_sdvob) |
714605e4 | 2353 | return 0x70; |
2354 | else | |
2355 | return 0x72; | |
2356 | } | |
2357 | ||
931c1c26 ID |
2358 | static void |
2359 | intel_sdvo_connector_unregister(struct intel_connector *intel_connector) | |
2360 | { | |
2361 | struct drm_connector *drm_connector; | |
2362 | struct intel_sdvo *sdvo_encoder; | |
2363 | ||
2364 | drm_connector = &intel_connector->base; | |
2365 | sdvo_encoder = intel_attached_sdvo(&intel_connector->base); | |
2366 | ||
2367 | sysfs_remove_link(&drm_connector->kdev->kobj, | |
2368 | sdvo_encoder->ddc.dev.kobj.name); | |
2369 | intel_connector_unregister(intel_connector); | |
2370 | } | |
2371 | ||
c393454d | 2372 | static int |
df0e9248 CW |
2373 | intel_sdvo_connector_init(struct intel_sdvo_connector *connector, |
2374 | struct intel_sdvo *encoder) | |
14571b4c | 2375 | { |
c393454d ID |
2376 | struct drm_connector *drm_connector; |
2377 | int ret; | |
2378 | ||
2379 | drm_connector = &connector->base.base; | |
2380 | ret = drm_connector_init(encoder->base.base.dev, | |
2381 | drm_connector, | |
df0e9248 CW |
2382 | &intel_sdvo_connector_funcs, |
2383 | connector->base.base.connector_type); | |
c393454d ID |
2384 | if (ret < 0) |
2385 | return ret; | |
6070a4a9 | 2386 | |
c393454d | 2387 | drm_connector_helper_add(drm_connector, |
df0e9248 | 2388 | &intel_sdvo_connector_helper_funcs); |
14571b4c | 2389 | |
8f4839e2 | 2390 | connector->base.base.interlace_allowed = 1; |
df0e9248 CW |
2391 | connector->base.base.doublescan_allowed = 0; |
2392 | connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB; | |
4ac41f47 | 2393 | connector->base.get_hw_state = intel_sdvo_connector_get_hw_state; |
931c1c26 | 2394 | connector->base.unregister = intel_sdvo_connector_unregister; |
14571b4c | 2395 | |
df0e9248 | 2396 | intel_connector_attach_encoder(&connector->base, &encoder->base); |
34ea3d38 | 2397 | ret = drm_connector_register(drm_connector); |
c393454d ID |
2398 | if (ret < 0) |
2399 | goto err1; | |
2400 | ||
4d43e9bd EE |
2401 | ret = sysfs_create_link(&drm_connector->kdev->kobj, |
2402 | &encoder->ddc.dev.kobj, | |
931c1c26 ID |
2403 | encoder->ddc.dev.kobj.name); |
2404 | if (ret < 0) | |
2405 | goto err2; | |
2406 | ||
c393454d ID |
2407 | return 0; |
2408 | ||
931c1c26 | 2409 | err2: |
34ea3d38 | 2410 | drm_connector_unregister(drm_connector); |
c393454d ID |
2411 | err1: |
2412 | drm_connector_cleanup(drm_connector); | |
2413 | ||
2414 | return ret; | |
14571b4c | 2415 | } |
6070a4a9 | 2416 | |
7f36e7ed | 2417 | static void |
55bc60db VS |
2418 | intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo, |
2419 | struct intel_sdvo_connector *connector) | |
7f36e7ed CW |
2420 | { |
2421 | struct drm_device *dev = connector->base.base.dev; | |
2422 | ||
3f43c48d | 2423 | intel_attach_force_audio_property(&connector->base.base); |
55bc60db | 2424 | if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) { |
e953fd7b | 2425 | intel_attach_broadcast_rgb_property(&connector->base.base); |
55bc60db VS |
2426 | intel_sdvo->color_range_auto = true; |
2427 | } | |
7f36e7ed CW |
2428 | } |
2429 | ||
9bdbd0b9 ACO |
2430 | static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void) |
2431 | { | |
2432 | struct intel_sdvo_connector *sdvo_connector; | |
2433 | ||
2434 | sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL); | |
2435 | if (!sdvo_connector) | |
2436 | return NULL; | |
2437 | ||
2438 | if (intel_connector_init(&sdvo_connector->base) < 0) { | |
2439 | kfree(sdvo_connector); | |
2440 | return NULL; | |
2441 | } | |
2442 | ||
2443 | return sdvo_connector; | |
2444 | } | |
2445 | ||
fb7a46f3 | 2446 | static bool |
ea5b213a | 2447 | intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device) |
fb7a46f3 | 2448 | { |
4ef69c7a | 2449 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
14571b4c | 2450 | struct drm_connector *connector; |
cc68c81a | 2451 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
14571b4c | 2452 | struct intel_connector *intel_connector; |
615fb93f | 2453 | struct intel_sdvo_connector *intel_sdvo_connector; |
14571b4c | 2454 | |
46a3f4a3 CW |
2455 | DRM_DEBUG_KMS("initialising DVI device %d\n", device); |
2456 | ||
9bdbd0b9 | 2457 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
615fb93f | 2458 | if (!intel_sdvo_connector) |
14571b4c ZW |
2459 | return false; |
2460 | ||
14571b4c | 2461 | if (device == 0) { |
ea5b213a | 2462 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0; |
615fb93f | 2463 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0; |
14571b4c | 2464 | } else if (device == 1) { |
ea5b213a | 2465 | intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1; |
615fb93f | 2466 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1; |
14571b4c ZW |
2467 | } |
2468 | ||
615fb93f | 2469 | intel_connector = &intel_sdvo_connector->base; |
14571b4c | 2470 | connector = &intel_connector->base; |
5fa7ac9c JN |
2471 | if (intel_sdvo_get_hotplug_support(intel_sdvo) & |
2472 | intel_sdvo_connector->output_flag) { | |
5fa7ac9c | 2473 | intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag; |
cc68c81a SF |
2474 | /* Some SDVO devices have one-shot hotplug interrupts. |
2475 | * Ensure that they get re-enabled when an interrupt happens. | |
2476 | */ | |
2477 | intel_encoder->hot_plug = intel_sdvo_enable_hotplug; | |
2478 | intel_sdvo_enable_hotplug(intel_encoder); | |
5fa7ac9c | 2479 | } else { |
821450c6 | 2480 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT; |
5fa7ac9c | 2481 | } |
14571b4c ZW |
2482 | encoder->encoder_type = DRM_MODE_ENCODER_TMDS; |
2483 | connector->connector_type = DRM_MODE_CONNECTOR_DVID; | |
2484 | ||
e27d8538 | 2485 | if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) { |
14571b4c | 2486 | connector->connector_type = DRM_MODE_CONNECTOR_HDMIA; |
e27d8538 | 2487 | intel_sdvo->is_hdmi = true; |
14571b4c | 2488 | } |
14571b4c | 2489 | |
c393454d ID |
2490 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
2491 | kfree(intel_sdvo_connector); | |
2492 | return false; | |
2493 | } | |
2494 | ||
f797d221 | 2495 | if (intel_sdvo->is_hdmi) |
55bc60db | 2496 | intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector); |
14571b4c ZW |
2497 | |
2498 | return true; | |
2499 | } | |
2500 | ||
2501 | static bool | |
ea5b213a | 2502 | intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type) |
14571b4c | 2503 | { |
4ef69c7a CW |
2504 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2505 | struct drm_connector *connector; | |
2506 | struct intel_connector *intel_connector; | |
2507 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2508 | |
46a3f4a3 CW |
2509 | DRM_DEBUG_KMS("initialising TV type %d\n", type); |
2510 | ||
9bdbd0b9 | 2511 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
615fb93f CW |
2512 | if (!intel_sdvo_connector) |
2513 | return false; | |
14571b4c | 2514 | |
615fb93f | 2515 | intel_connector = &intel_sdvo_connector->base; |
4ef69c7a CW |
2516 | connector = &intel_connector->base; |
2517 | encoder->encoder_type = DRM_MODE_ENCODER_TVDAC; | |
2518 | connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO; | |
14571b4c | 2519 | |
4ef69c7a CW |
2520 | intel_sdvo->controlled_output |= type; |
2521 | intel_sdvo_connector->output_flag = type; | |
14571b4c | 2522 | |
4ef69c7a | 2523 | intel_sdvo->is_tv = true; |
14571b4c | 2524 | |
c393454d ID |
2525 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
2526 | kfree(intel_sdvo_connector); | |
2527 | return false; | |
2528 | } | |
14571b4c | 2529 | |
4ef69c7a | 2530 | if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type)) |
32aad86f | 2531 | goto err; |
14571b4c | 2532 | |
4ef69c7a | 2533 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
32aad86f | 2534 | goto err; |
14571b4c | 2535 | |
4ef69c7a | 2536 | return true; |
32aad86f CW |
2537 | |
2538 | err: | |
34ea3d38 | 2539 | drm_connector_unregister(connector); |
123d5c01 | 2540 | intel_sdvo_destroy(connector); |
32aad86f | 2541 | return false; |
14571b4c ZW |
2542 | } |
2543 | ||
2544 | static bool | |
ea5b213a | 2545 | intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device) |
14571b4c | 2546 | { |
4ef69c7a CW |
2547 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2548 | struct drm_connector *connector; | |
2549 | struct intel_connector *intel_connector; | |
2550 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2551 | |
46a3f4a3 CW |
2552 | DRM_DEBUG_KMS("initialising analog device %d\n", device); |
2553 | ||
b14c5679 | 2554 | intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL); |
615fb93f CW |
2555 | if (!intel_sdvo_connector) |
2556 | return false; | |
14571b4c | 2557 | |
615fb93f | 2558 | intel_connector = &intel_sdvo_connector->base; |
4ef69c7a | 2559 | connector = &intel_connector->base; |
821450c6 | 2560 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; |
4ef69c7a CW |
2561 | encoder->encoder_type = DRM_MODE_ENCODER_DAC; |
2562 | connector->connector_type = DRM_MODE_CONNECTOR_VGA; | |
2563 | ||
2564 | if (device == 0) { | |
2565 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0; | |
2566 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0; | |
2567 | } else if (device == 1) { | |
2568 | intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1; | |
2569 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1; | |
2570 | } | |
2571 | ||
c393454d ID |
2572 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
2573 | kfree(intel_sdvo_connector); | |
2574 | return false; | |
2575 | } | |
2576 | ||
4ef69c7a | 2577 | return true; |
14571b4c ZW |
2578 | } |
2579 | ||
2580 | static bool | |
ea5b213a | 2581 | intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device) |
14571b4c | 2582 | { |
4ef69c7a CW |
2583 | struct drm_encoder *encoder = &intel_sdvo->base.base; |
2584 | struct drm_connector *connector; | |
2585 | struct intel_connector *intel_connector; | |
2586 | struct intel_sdvo_connector *intel_sdvo_connector; | |
14571b4c | 2587 | |
46a3f4a3 CW |
2588 | DRM_DEBUG_KMS("initialising LVDS device %d\n", device); |
2589 | ||
9bdbd0b9 | 2590 | intel_sdvo_connector = intel_sdvo_connector_alloc(); |
615fb93f CW |
2591 | if (!intel_sdvo_connector) |
2592 | return false; | |
14571b4c | 2593 | |
615fb93f CW |
2594 | intel_connector = &intel_sdvo_connector->base; |
2595 | connector = &intel_connector->base; | |
4ef69c7a CW |
2596 | encoder->encoder_type = DRM_MODE_ENCODER_LVDS; |
2597 | connector->connector_type = DRM_MODE_CONNECTOR_LVDS; | |
2598 | ||
2599 | if (device == 0) { | |
2600 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0; | |
2601 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0; | |
2602 | } else if (device == 1) { | |
2603 | intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1; | |
2604 | intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1; | |
2605 | } | |
2606 | ||
c393454d ID |
2607 | if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) { |
2608 | kfree(intel_sdvo_connector); | |
2609 | return false; | |
2610 | } | |
2611 | ||
4ef69c7a | 2612 | if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector)) |
32aad86f CW |
2613 | goto err; |
2614 | ||
2615 | return true; | |
2616 | ||
2617 | err: | |
34ea3d38 | 2618 | drm_connector_unregister(connector); |
123d5c01 | 2619 | intel_sdvo_destroy(connector); |
32aad86f | 2620 | return false; |
14571b4c ZW |
2621 | } |
2622 | ||
2623 | static bool | |
ea5b213a | 2624 | intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags) |
14571b4c | 2625 | { |
ea5b213a | 2626 | intel_sdvo->is_tv = false; |
ea5b213a | 2627 | intel_sdvo->is_lvds = false; |
fb7a46f3 | 2628 | |
14571b4c | 2629 | /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/ |
fb7a46f3 | 2630 | |
14571b4c | 2631 | if (flags & SDVO_OUTPUT_TMDS0) |
ea5b213a | 2632 | if (!intel_sdvo_dvi_init(intel_sdvo, 0)) |
14571b4c ZW |
2633 | return false; |
2634 | ||
2635 | if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK) | |
ea5b213a | 2636 | if (!intel_sdvo_dvi_init(intel_sdvo, 1)) |
14571b4c ZW |
2637 | return false; |
2638 | ||
2639 | /* TV has no XXX1 function block */ | |
a1f4b7ff | 2640 | if (flags & SDVO_OUTPUT_SVID0) |
ea5b213a | 2641 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0)) |
14571b4c ZW |
2642 | return false; |
2643 | ||
2644 | if (flags & SDVO_OUTPUT_CVBS0) | |
ea5b213a | 2645 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0)) |
14571b4c | 2646 | return false; |
fb7a46f3 | 2647 | |
a0b1c7a5 CW |
2648 | if (flags & SDVO_OUTPUT_YPRPB0) |
2649 | if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0)) | |
2650 | return false; | |
2651 | ||
14571b4c | 2652 | if (flags & SDVO_OUTPUT_RGB0) |
ea5b213a | 2653 | if (!intel_sdvo_analog_init(intel_sdvo, 0)) |
14571b4c ZW |
2654 | return false; |
2655 | ||
2656 | if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK) | |
ea5b213a | 2657 | if (!intel_sdvo_analog_init(intel_sdvo, 1)) |
14571b4c ZW |
2658 | return false; |
2659 | ||
2660 | if (flags & SDVO_OUTPUT_LVDS0) | |
ea5b213a | 2661 | if (!intel_sdvo_lvds_init(intel_sdvo, 0)) |
14571b4c ZW |
2662 | return false; |
2663 | ||
2664 | if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK) | |
ea5b213a | 2665 | if (!intel_sdvo_lvds_init(intel_sdvo, 1)) |
14571b4c | 2666 | return false; |
fb7a46f3 | 2667 | |
14571b4c | 2668 | if ((flags & SDVO_OUTPUT_MASK) == 0) { |
fb7a46f3 | 2669 | unsigned char bytes[2]; |
2670 | ||
ea5b213a CW |
2671 | intel_sdvo->controlled_output = 0; |
2672 | memcpy(bytes, &intel_sdvo->caps.output_flags, 2); | |
51c8b407 | 2673 | DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n", |
ea5b213a | 2674 | SDVO_NAME(intel_sdvo), |
51c8b407 | 2675 | bytes[0], bytes[1]); |
14571b4c | 2676 | return false; |
fb7a46f3 | 2677 | } |
27f8227b | 2678 | intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
fb7a46f3 | 2679 | |
14571b4c | 2680 | return true; |
fb7a46f3 | 2681 | } |
2682 | ||
d0ddfbd3 JN |
2683 | static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo) |
2684 | { | |
2685 | struct drm_device *dev = intel_sdvo->base.base.dev; | |
2686 | struct drm_connector *connector, *tmp; | |
2687 | ||
2688 | list_for_each_entry_safe(connector, tmp, | |
2689 | &dev->mode_config.connector_list, head) { | |
d9255d57 | 2690 | if (intel_attached_encoder(connector) == &intel_sdvo->base) { |
34ea3d38 | 2691 | drm_connector_unregister(connector); |
d0ddfbd3 | 2692 | intel_sdvo_destroy(connector); |
d9255d57 | 2693 | } |
d0ddfbd3 JN |
2694 | } |
2695 | } | |
2696 | ||
32aad86f CW |
2697 | static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo, |
2698 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2699 | int type) | |
ce6feabd | 2700 | { |
4ef69c7a | 2701 | struct drm_device *dev = intel_sdvo->base.base.dev; |
ce6feabd ZY |
2702 | struct intel_sdvo_tv_format format; |
2703 | uint32_t format_map, i; | |
ce6feabd | 2704 | |
32aad86f CW |
2705 | if (!intel_sdvo_set_target_output(intel_sdvo, type)) |
2706 | return false; | |
ce6feabd | 2707 | |
1a3665c8 | 2708 | BUILD_BUG_ON(sizeof(format) != 6); |
32aad86f CW |
2709 | if (!intel_sdvo_get_value(intel_sdvo, |
2710 | SDVO_CMD_GET_SUPPORTED_TV_FORMATS, | |
2711 | &format, sizeof(format))) | |
2712 | return false; | |
ce6feabd | 2713 | |
32aad86f | 2714 | memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format))); |
ce6feabd ZY |
2715 | |
2716 | if (format_map == 0) | |
32aad86f | 2717 | return false; |
ce6feabd | 2718 | |
615fb93f | 2719 | intel_sdvo_connector->format_supported_num = 0; |
ce6feabd | 2720 | for (i = 0 ; i < TV_FORMAT_NUM; i++) |
40039750 CW |
2721 | if (format_map & (1 << i)) |
2722 | intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i; | |
ce6feabd ZY |
2723 | |
2724 | ||
c5521706 | 2725 | intel_sdvo_connector->tv_format = |
32aad86f CW |
2726 | drm_property_create(dev, DRM_MODE_PROP_ENUM, |
2727 | "mode", intel_sdvo_connector->format_supported_num); | |
c5521706 | 2728 | if (!intel_sdvo_connector->tv_format) |
fcc8d672 | 2729 | return false; |
ce6feabd | 2730 | |
615fb93f | 2731 | for (i = 0; i < intel_sdvo_connector->format_supported_num; i++) |
ce6feabd | 2732 | drm_property_add_enum( |
c5521706 | 2733 | intel_sdvo_connector->tv_format, i, |
40039750 | 2734 | i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]); |
ce6feabd | 2735 | |
40039750 | 2736 | intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0]; |
662595df | 2737 | drm_object_attach_property(&intel_sdvo_connector->base.base.base, |
c5521706 | 2738 | intel_sdvo_connector->tv_format, 0); |
32aad86f | 2739 | return true; |
ce6feabd ZY |
2740 | |
2741 | } | |
2742 | ||
c5521706 CW |
2743 | #define ENHANCEMENT(name, NAME) do { \ |
2744 | if (enhancements.name) { \ | |
2745 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \ | |
2746 | !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \ | |
2747 | return false; \ | |
2748 | intel_sdvo_connector->max_##name = data_value[0]; \ | |
2749 | intel_sdvo_connector->cur_##name = response; \ | |
2750 | intel_sdvo_connector->name = \ | |
d9bc3c02 | 2751 | drm_property_create_range(dev, 0, #name, 0, data_value[0]); \ |
c5521706 | 2752 | if (!intel_sdvo_connector->name) return false; \ |
662595df | 2753 | drm_object_attach_property(&connector->base, \ |
c5521706 CW |
2754 | intel_sdvo_connector->name, \ |
2755 | intel_sdvo_connector->cur_##name); \ | |
2756 | DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \ | |
2757 | data_value[0], data_value[1], response); \ | |
2758 | } \ | |
0206e353 | 2759 | } while (0) |
c5521706 CW |
2760 | |
2761 | static bool | |
2762 | intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo, | |
2763 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2764 | struct intel_sdvo_enhancements_reply enhancements) | |
b9219c5e | 2765 | { |
4ef69c7a | 2766 | struct drm_device *dev = intel_sdvo->base.base.dev; |
32aad86f | 2767 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
b9219c5e ZY |
2768 | uint16_t response, data_value[2]; |
2769 | ||
c5521706 CW |
2770 | /* when horizontal overscan is supported, Add the left/right property */ |
2771 | if (enhancements.overscan_h) { | |
2772 | if (!intel_sdvo_get_value(intel_sdvo, | |
2773 | SDVO_CMD_GET_MAX_OVERSCAN_H, | |
2774 | &data_value, 4)) | |
2775 | return false; | |
32aad86f | 2776 | |
c5521706 CW |
2777 | if (!intel_sdvo_get_value(intel_sdvo, |
2778 | SDVO_CMD_GET_OVERSCAN_H, | |
2779 | &response, 2)) | |
2780 | return false; | |
fcc8d672 | 2781 | |
c5521706 CW |
2782 | intel_sdvo_connector->max_hscan = data_value[0]; |
2783 | intel_sdvo_connector->left_margin = data_value[0] - response; | |
2784 | intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin; | |
2785 | intel_sdvo_connector->left = | |
d9bc3c02 | 2786 | drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]); |
c5521706 CW |
2787 | if (!intel_sdvo_connector->left) |
2788 | return false; | |
fcc8d672 | 2789 | |
662595df | 2790 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2791 | intel_sdvo_connector->left, |
2792 | intel_sdvo_connector->left_margin); | |
fcc8d672 | 2793 | |
c5521706 | 2794 | intel_sdvo_connector->right = |
d9bc3c02 | 2795 | drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]); |
c5521706 CW |
2796 | if (!intel_sdvo_connector->right) |
2797 | return false; | |
32aad86f | 2798 | |
662595df | 2799 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2800 | intel_sdvo_connector->right, |
2801 | intel_sdvo_connector->right_margin); | |
2802 | DRM_DEBUG_KMS("h_overscan: max %d, " | |
2803 | "default %d, current %d\n", | |
2804 | data_value[0], data_value[1], response); | |
2805 | } | |
32aad86f | 2806 | |
c5521706 CW |
2807 | if (enhancements.overscan_v) { |
2808 | if (!intel_sdvo_get_value(intel_sdvo, | |
2809 | SDVO_CMD_GET_MAX_OVERSCAN_V, | |
2810 | &data_value, 4)) | |
2811 | return false; | |
fcc8d672 | 2812 | |
c5521706 CW |
2813 | if (!intel_sdvo_get_value(intel_sdvo, |
2814 | SDVO_CMD_GET_OVERSCAN_V, | |
2815 | &response, 2)) | |
2816 | return false; | |
32aad86f | 2817 | |
c5521706 CW |
2818 | intel_sdvo_connector->max_vscan = data_value[0]; |
2819 | intel_sdvo_connector->top_margin = data_value[0] - response; | |
2820 | intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin; | |
2821 | intel_sdvo_connector->top = | |
d9bc3c02 SH |
2822 | drm_property_create_range(dev, 0, |
2823 | "top_margin", 0, data_value[0]); | |
c5521706 CW |
2824 | if (!intel_sdvo_connector->top) |
2825 | return false; | |
32aad86f | 2826 | |
662595df | 2827 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2828 | intel_sdvo_connector->top, |
2829 | intel_sdvo_connector->top_margin); | |
fcc8d672 | 2830 | |
c5521706 | 2831 | intel_sdvo_connector->bottom = |
d9bc3c02 SH |
2832 | drm_property_create_range(dev, 0, |
2833 | "bottom_margin", 0, data_value[0]); | |
c5521706 CW |
2834 | if (!intel_sdvo_connector->bottom) |
2835 | return false; | |
32aad86f | 2836 | |
662595df | 2837 | drm_object_attach_property(&connector->base, |
c5521706 CW |
2838 | intel_sdvo_connector->bottom, |
2839 | intel_sdvo_connector->bottom_margin); | |
2840 | DRM_DEBUG_KMS("v_overscan: max %d, " | |
2841 | "default %d, current %d\n", | |
2842 | data_value[0], data_value[1], response); | |
2843 | } | |
32aad86f | 2844 | |
c5521706 CW |
2845 | ENHANCEMENT(hpos, HPOS); |
2846 | ENHANCEMENT(vpos, VPOS); | |
2847 | ENHANCEMENT(saturation, SATURATION); | |
2848 | ENHANCEMENT(contrast, CONTRAST); | |
2849 | ENHANCEMENT(hue, HUE); | |
2850 | ENHANCEMENT(sharpness, SHARPNESS); | |
2851 | ENHANCEMENT(brightness, BRIGHTNESS); | |
2852 | ENHANCEMENT(flicker_filter, FLICKER_FILTER); | |
2853 | ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE); | |
2854 | ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D); | |
2855 | ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER); | |
2856 | ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER); | |
fcc8d672 | 2857 | |
e044218a CW |
2858 | if (enhancements.dot_crawl) { |
2859 | if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2)) | |
2860 | return false; | |
2861 | ||
2862 | intel_sdvo_connector->max_dot_crawl = 1; | |
2863 | intel_sdvo_connector->cur_dot_crawl = response & 0x1; | |
2864 | intel_sdvo_connector->dot_crawl = | |
d9bc3c02 | 2865 | drm_property_create_range(dev, 0, "dot_crawl", 0, 1); |
e044218a CW |
2866 | if (!intel_sdvo_connector->dot_crawl) |
2867 | return false; | |
2868 | ||
662595df | 2869 | drm_object_attach_property(&connector->base, |
e044218a CW |
2870 | intel_sdvo_connector->dot_crawl, |
2871 | intel_sdvo_connector->cur_dot_crawl); | |
2872 | DRM_DEBUG_KMS("dot crawl: current %d\n", response); | |
2873 | } | |
2874 | ||
c5521706 CW |
2875 | return true; |
2876 | } | |
32aad86f | 2877 | |
c5521706 CW |
2878 | static bool |
2879 | intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo, | |
2880 | struct intel_sdvo_connector *intel_sdvo_connector, | |
2881 | struct intel_sdvo_enhancements_reply enhancements) | |
2882 | { | |
4ef69c7a | 2883 | struct drm_device *dev = intel_sdvo->base.base.dev; |
c5521706 CW |
2884 | struct drm_connector *connector = &intel_sdvo_connector->base.base; |
2885 | uint16_t response, data_value[2]; | |
32aad86f | 2886 | |
c5521706 | 2887 | ENHANCEMENT(brightness, BRIGHTNESS); |
fcc8d672 | 2888 | |
c5521706 CW |
2889 | return true; |
2890 | } | |
2891 | #undef ENHANCEMENT | |
32aad86f | 2892 | |
c5521706 CW |
2893 | static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo, |
2894 | struct intel_sdvo_connector *intel_sdvo_connector) | |
2895 | { | |
2896 | union { | |
2897 | struct intel_sdvo_enhancements_reply reply; | |
2898 | uint16_t response; | |
2899 | } enhancements; | |
32aad86f | 2900 | |
1a3665c8 CW |
2901 | BUILD_BUG_ON(sizeof(enhancements) != 2); |
2902 | ||
cf9a2f3a CW |
2903 | enhancements.response = 0; |
2904 | intel_sdvo_get_value(intel_sdvo, | |
2905 | SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS, | |
2906 | &enhancements, sizeof(enhancements)); | |
c5521706 CW |
2907 | if (enhancements.response == 0) { |
2908 | DRM_DEBUG_KMS("No enhancement is supported\n"); | |
2909 | return true; | |
b9219c5e | 2910 | } |
32aad86f | 2911 | |
c5521706 CW |
2912 | if (IS_TV(intel_sdvo_connector)) |
2913 | return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply); | |
0206e353 | 2914 | else if (IS_LVDS(intel_sdvo_connector)) |
c5521706 CW |
2915 | return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply); |
2916 | else | |
2917 | return true; | |
e957d772 CW |
2918 | } |
2919 | ||
2920 | static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter, | |
2921 | struct i2c_msg *msgs, | |
2922 | int num) | |
2923 | { | |
2924 | struct intel_sdvo *sdvo = adapter->algo_data; | |
fcc8d672 | 2925 | |
e957d772 CW |
2926 | if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus)) |
2927 | return -EIO; | |
2928 | ||
2929 | return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num); | |
2930 | } | |
2931 | ||
2932 | static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter) | |
2933 | { | |
2934 | struct intel_sdvo *sdvo = adapter->algo_data; | |
2935 | return sdvo->i2c->algo->functionality(sdvo->i2c); | |
2936 | } | |
2937 | ||
2938 | static const struct i2c_algorithm intel_sdvo_ddc_proxy = { | |
2939 | .master_xfer = intel_sdvo_ddc_proxy_xfer, | |
2940 | .functionality = intel_sdvo_ddc_proxy_func | |
2941 | }; | |
2942 | ||
2943 | static bool | |
2944 | intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo, | |
2945 | struct drm_device *dev) | |
2946 | { | |
2947 | sdvo->ddc.owner = THIS_MODULE; | |
2948 | sdvo->ddc.class = I2C_CLASS_DDC; | |
2949 | snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy"); | |
2950 | sdvo->ddc.dev.parent = &dev->pdev->dev; | |
2951 | sdvo->ddc.algo_data = sdvo; | |
2952 | sdvo->ddc.algo = &intel_sdvo_ddc_proxy; | |
2953 | ||
2954 | return i2c_add_adapter(&sdvo->ddc) == 0; | |
b9219c5e ZY |
2955 | } |
2956 | ||
eef4eacb | 2957 | bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob) |
79e53945 | 2958 | { |
b01f2c3a | 2959 | struct drm_i915_private *dev_priv = dev->dev_private; |
21d40d37 | 2960 | struct intel_encoder *intel_encoder; |
ea5b213a | 2961 | struct intel_sdvo *intel_sdvo; |
79e53945 | 2962 | int i; |
b14c5679 | 2963 | intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL); |
ea5b213a | 2964 | if (!intel_sdvo) |
7d57382e | 2965 | return false; |
79e53945 | 2966 | |
56184e3d | 2967 | intel_sdvo->sdvo_reg = sdvo_reg; |
eef4eacb DV |
2968 | intel_sdvo->is_sdvob = is_sdvob; |
2969 | intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1; | |
56184e3d | 2970 | intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg); |
fbfcc4f3 JN |
2971 | if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) |
2972 | goto err_i2c_bus; | |
e957d772 | 2973 | |
56184e3d | 2974 | /* encoder type will be decided later */ |
ea5b213a | 2975 | intel_encoder = &intel_sdvo->base; |
21d40d37 | 2976 | intel_encoder->type = INTEL_OUTPUT_SDVO; |
373a3cf7 | 2977 | drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0); |
79e53945 | 2978 | |
79e53945 JB |
2979 | /* Read the regs to test if we can talk to the device */ |
2980 | for (i = 0; i < 0x40; i++) { | |
f899fc64 CW |
2981 | u8 byte; |
2982 | ||
2983 | if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) { | |
eef4eacb DV |
2984 | DRM_DEBUG_KMS("No SDVO device found on %s\n", |
2985 | SDVO_NAME(intel_sdvo)); | |
f899fc64 | 2986 | goto err; |
79e53945 JB |
2987 | } |
2988 | } | |
2989 | ||
6cc5f341 | 2990 | intel_encoder->compute_config = intel_sdvo_compute_config; |
ce22c320 | 2991 | intel_encoder->disable = intel_disable_sdvo; |
192d47a6 | 2992 | intel_encoder->pre_enable = intel_sdvo_pre_enable; |
ce22c320 | 2993 | intel_encoder->enable = intel_enable_sdvo; |
4ac41f47 | 2994 | intel_encoder->get_hw_state = intel_sdvo_get_hw_state; |
045ac3b5 | 2995 | intel_encoder->get_config = intel_sdvo_get_config; |
ce22c320 | 2996 | |
af901ca1 | 2997 | /* In default case sdvo lvds is false */ |
32aad86f | 2998 | if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps)) |
f899fc64 | 2999 | goto err; |
79e53945 | 3000 | |
ea5b213a CW |
3001 | if (intel_sdvo_output_setup(intel_sdvo, |
3002 | intel_sdvo->caps.output_flags) != true) { | |
eef4eacb DV |
3003 | DRM_DEBUG_KMS("SDVO output failed to setup on %s\n", |
3004 | SDVO_NAME(intel_sdvo)); | |
d0ddfbd3 JN |
3005 | /* Output_setup can leave behind connectors! */ |
3006 | goto err_output; | |
79e53945 JB |
3007 | } |
3008 | ||
7ba220ce CW |
3009 | /* Only enable the hotplug irq if we need it, to work around noisy |
3010 | * hotplug lines. | |
3011 | */ | |
3012 | if (intel_sdvo->hotplug_active) { | |
3013 | intel_encoder->hpd_pin = | |
3014 | intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C; | |
3015 | } | |
3016 | ||
e506d6fd DV |
3017 | /* |
3018 | * Cloning SDVO with anything is often impossible, since the SDVO | |
3019 | * encoder can request a special input timing mode. And even if that's | |
3020 | * not the case we have evidence that cloning a plain unscaled mode with | |
3021 | * VGA doesn't really work. Furthermore the cloning flags are way too | |
3022 | * simplistic anyway to express such constraints, so just give up on | |
3023 | * cloning for SDVO encoders. | |
3024 | */ | |
bc079e8b | 3025 | intel_sdvo->base.cloneable = 0; |
e506d6fd | 3026 | |
ea5b213a | 3027 | intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg); |
e2f0ba97 | 3028 | |
79e53945 | 3029 | /* Set the input timing to the screen. Assume always input 0. */ |
32aad86f | 3030 | if (!intel_sdvo_set_target_input(intel_sdvo)) |
d0ddfbd3 | 3031 | goto err_output; |
79e53945 | 3032 | |
32aad86f CW |
3033 | if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo, |
3034 | &intel_sdvo->pixel_clock_min, | |
3035 | &intel_sdvo->pixel_clock_max)) | |
d0ddfbd3 | 3036 | goto err_output; |
79e53945 | 3037 | |
8a4c47f3 | 3038 | DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, " |
342dc382 | 3039 | "clock range %dMHz - %dMHz, " |
3040 | "input 1: %c, input 2: %c, " | |
3041 | "output 1: %c, output 2: %c\n", | |
ea5b213a CW |
3042 | SDVO_NAME(intel_sdvo), |
3043 | intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id, | |
3044 | intel_sdvo->caps.device_rev_id, | |
3045 | intel_sdvo->pixel_clock_min / 1000, | |
3046 | intel_sdvo->pixel_clock_max / 1000, | |
3047 | (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N', | |
3048 | (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N', | |
342dc382 | 3049 | /* check currently supported outputs */ |
ea5b213a | 3050 | intel_sdvo->caps.output_flags & |
79e53945 | 3051 | (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N', |
ea5b213a | 3052 | intel_sdvo->caps.output_flags & |
79e53945 | 3053 | (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N'); |
7d57382e | 3054 | return true; |
79e53945 | 3055 | |
d0ddfbd3 JN |
3056 | err_output: |
3057 | intel_sdvo_output_cleanup(intel_sdvo); | |
3058 | ||
f899fc64 | 3059 | err: |
373a3cf7 | 3060 | drm_encoder_cleanup(&intel_encoder->base); |
e957d772 | 3061 | i2c_del_adapter(&intel_sdvo->ddc); |
fbfcc4f3 JN |
3062 | err_i2c_bus: |
3063 | intel_sdvo_unselect_i2c_bus(intel_sdvo); | |
ea5b213a | 3064 | kfree(intel_sdvo); |
79e53945 | 3065 | |
7d57382e | 3066 | return false; |
79e53945 | 3067 | } |