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drm/i915: fix sparse warnings: make symbols static
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
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79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
29#include <linux/delay.h>
30#include "drmP.h"
31#include "drm.h"
32#include "drm_crtc.h"
33#include "intel_drv.h"
34#include "i915_drm.h"
35#include "i915_drv.h"
36#include "intel_sdvo_regs.h"
37
38#undef SDVO_DEBUG
39
40struct intel_sdvo_priv {
41 struct intel_i2c_chan *i2c_bus;
42 int slaveaddr;
43 int output_device;
44
45 u16 active_outputs;
46
47 struct intel_sdvo_caps caps;
48 int pixel_clock_min, pixel_clock_max;
49
50 int save_sdvo_mult;
51 u16 save_active_outputs;
52 struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
53 struct intel_sdvo_dtd save_output_dtd[16];
54 u32 save_SDVOX;
55};
56
57/**
58 * Writes the SDVOB or SDVOC with the given value, but always writes both
59 * SDVOB and SDVOC to work around apparent hardware issues (according to
60 * comments in the BIOS).
61 */
b358d0a6 62static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
79e53945
JB		 63{
64 struct drm_device *dev = intel_output->base.dev;
65 struct drm_i915_private *dev_priv = dev->dev_private;
66 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
67 u32 bval = val, cval = val;
68 int i;
69
70 if (sdvo_priv->output_device == SDVOB) {
71 cval = I915_READ(SDVOC);
72 } else {
73 bval = I915_READ(SDVOB);
74 }
75 /*
76 * Write the registers twice for luck. Sometimes,
77 * writing them only once doesn't appear to 'stick'.
78 * The BIOS does this too. Yay, magic
79 */
80 for (i = 0; i < 2; i++)
81 {
82 I915_WRITE(SDVOB, bval);
83 I915_READ(SDVOB);
84 I915_WRITE(SDVOC, cval);
85 I915_READ(SDVOC);
86 }
87}
88
89static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
90 u8 *ch)
91{
92 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
93 u8 out_buf[2];
94 u8 buf[2];
95 int ret;
96
97 struct i2c_msg msgs[] = {
98 {
99 .addr = sdvo_priv->i2c_bus->slave_addr,
100 .flags = 0,
101 .len = 1,
102 .buf = out_buf,
103 },
104 {
105 .addr = sdvo_priv->i2c_bus->slave_addr,
106 .flags = I2C_M_RD,
107 .len = 1,
108 .buf = buf,
109 }
110 };
111
112 out_buf[0] = addr;
113 out_buf[1] = 0;
114
115 if ((ret = i2c_transfer(&sdvo_priv->i2c_bus->adapter, msgs, 2)) == 2)
116 {
117 *ch = buf[0];
118 return true;
119 }
120
121 DRM_DEBUG("i2c transfer returned %d\n", ret);
122 return false;
123}
124
125static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
126 u8 ch)
127{
128 u8 out_buf[2];
129 struct i2c_msg msgs[] = {
130 {
131 .addr = intel_output->i2c_bus->slave_addr,
132 .flags = 0,
133 .len = 2,
134 .buf = out_buf,
135 }
136 };
137
138 out_buf[0] = addr;
139 out_buf[1] = ch;
140
141 if (i2c_transfer(&intel_output->i2c_bus->adapter, msgs, 1) == 1)
142 {
143 return true;
144 }
145 return false;
146}
147
148#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
149/** Mapping of command numbers to names, for debug output */
150const static struct _sdvo_cmd_name {
151 u8 cmd;
152 char *name;
153} sdvo_cmd_names[] = {
154 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
155 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
156 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
157 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
158 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
159 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
160 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
161 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
162 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
163 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
164 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
165 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
166 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
167 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
168 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
169 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
170 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
171 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
172 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
173 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
174 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
175 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
176 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
177 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
178 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
179 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
180 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
181 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
182 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
183 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
184 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
185 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
186 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
187 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
188 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
189 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_RESOLUTION_SUPPORT),
190 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
191};
192
193#define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
194#define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)
195
196#ifdef SDVO_DEBUG
197static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
198 void *args, int args_len)
199{
200 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
201 int i;
202
203 DRM_DEBUG("%s: W: %02X ", SDVO_NAME(sdvo_priv), cmd);
204 for (i = 0; i < args_len; i++)
205 printk("%02X ", ((u8 *)args)[i]);
206 for (; i < 8; i++)
207 printk(" ");
208 for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
209 if (cmd == sdvo_cmd_names[i].cmd) {
210 printk("(%s)", sdvo_cmd_names[i].name);
211 break;
212 }
213 }
214 if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
215 printk("(%02X)",cmd);
216 printk("\n");
217}
218#else
219#define intel_sdvo_debug_write(o, c, a, l)
220#endif
221
222static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
223 void *args, int args_len)
224{
225 int i;
226
227 intel_sdvo_debug_write(intel_output, cmd, args, args_len);
228
229 for (i = 0; i < args_len; i++) {
230 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i,
231 ((u8*)args)[i]);
232 }
233
234 intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
235}
236
237#ifdef SDVO_DEBUG
238static const char *cmd_status_names[] = {
239 "Power on",
240 "Success",
241 "Not supported",
242 "Invalid arg",
243 "Pending",
244 "Target not specified",
245 "Scaling not supported"
246};
247
248static void intel_sdvo_debug_response(struct intel_output *intel_output,
249 void *response, int response_len,
250 u8 status)
251{
252 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
253
254 DRM_DEBUG("%s: R: ", SDVO_NAME(sdvo_priv));
255 for (i = 0; i < response_len; i++)
256 printk("%02X ", ((u8 *)response)[i]);
257 for (; i < 8; i++)
258 printk(" ");
259 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
260 printk("(%s)", cmd_status_names[status]);
261 else
262 printk("(??? %d)", status);
263 printk("\n");
264}
265#else
266#define intel_sdvo_debug_response(o, r, l, s)
267#endif
268
269static u8 intel_sdvo_read_response(struct intel_output *intel_output,
270 void *response, int response_len)
271{
272 int i;
273 u8 status;
274 u8 retry = 50;
275
276 while (retry--) {
277 /* Read the command response */
278 for (i = 0; i < response_len; i++) {
279 intel_sdvo_read_byte(intel_output,
280 SDVO_I2C_RETURN_0 + i,
281 &((u8 *)response)[i]);
282 }
283
284 /* read the return status */
285 intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS,
286 &status);
287
288 intel_sdvo_debug_response(intel_output, response, response_len,
289 status);
290 if (status != SDVO_CMD_STATUS_PENDING)
291 return status;
292
293 mdelay(50);
294 }
295
296 return status;
297}
298
b358d0a6 299static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 300{
301 if (mode->clock >= 100000)
302 return 1;
303 else if (mode->clock >= 50000)
304 return 2;
305 else
306 return 4;
307}
308
309/**
310 * Don't check status code from this as it switches the bus back to the
311 * SDVO chips which defeats the purpose of doing a bus switch in the first
312 * place.
313 */
b358d0a6
HE		 314static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
315 u8 target)
79e53945
JB		 316{
317 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH, &target, 1);
318}
319
320static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
321{
322 struct intel_sdvo_set_target_input_args targets = {0};
323 u8 status;
324
325 if (target_0 && target_1)
326 return SDVO_CMD_STATUS_NOTSUPP;
327
328 if (target_1)
329 targets.target_1 = 1;
330
331 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
332 sizeof(targets));
333
334 status = intel_sdvo_read_response(intel_output, NULL, 0);
335
336 return (status == SDVO_CMD_STATUS_SUCCESS);
337}
338
339/**
340 * Return whether each input is trained.
341 *
342 * This function is making an assumption about the layout of the response,
343 * which should be checked against the docs.
344 */
345static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
346{
347 struct intel_sdvo_get_trained_inputs_response response;
348 u8 status;
349
350 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
351 status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
352 if (status != SDVO_CMD_STATUS_SUCCESS)
353 return false;
354
355 *input_1 = response.input0_trained;
356 *input_2 = response.input1_trained;
357 return true;
358}
359
360static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
361 u16 *outputs)
362{
363 u8 status;
364
365 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
366 status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
367
368 return (status == SDVO_CMD_STATUS_SUCCESS);
369}
370
371static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
372 u16 outputs)
373{
374 u8 status;
375
376 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
377 sizeof(outputs));
378 status = intel_sdvo_read_response(intel_output, NULL, 0);
379 return (status == SDVO_CMD_STATUS_SUCCESS);
380}
381
382static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
383 int mode)
384{
385 u8 status, state = SDVO_ENCODER_STATE_ON;
386
387 switch (mode) {
388 case DRM_MODE_DPMS_ON:
389 state = SDVO_ENCODER_STATE_ON;
390 break;
391 case DRM_MODE_DPMS_STANDBY:
392 state = SDVO_ENCODER_STATE_STANDBY;
393 break;
394 case DRM_MODE_DPMS_SUSPEND:
395 state = SDVO_ENCODER_STATE_SUSPEND;
396 break;
397 case DRM_MODE_DPMS_OFF:
398 state = SDVO_ENCODER_STATE_OFF;
399 break;
400 }
401
402 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
403 sizeof(state));
404 status = intel_sdvo_read_response(intel_output, NULL, 0);
405
406 return (status == SDVO_CMD_STATUS_SUCCESS);
407}
408
409static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
410 int *clock_min,
411 int *clock_max)
412{
413 struct intel_sdvo_pixel_clock_range clocks;
414 u8 status;
415
416 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
417 NULL, 0);
418
419 status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
420
421 if (status != SDVO_CMD_STATUS_SUCCESS)
422 return false;
423
424 /* Convert the values from units of 10 kHz to kHz. */
425 *clock_min = clocks.min * 10;
426 *clock_max = clocks.max * 10;
427
428 return true;
429}
430
431static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
432 u16 outputs)
433{
434 u8 status;
435
436 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
437 sizeof(outputs));
438
439 status = intel_sdvo_read_response(intel_output, NULL, 0);
440 return (status == SDVO_CMD_STATUS_SUCCESS);
441}
442
443static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
444 struct intel_sdvo_dtd *dtd)
445{
446 u8 status;
447
448 intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
449 status = intel_sdvo_read_response(intel_output, &dtd->part1,
450 sizeof(dtd->part1));
451 if (status != SDVO_CMD_STATUS_SUCCESS)
452 return false;
453
454 intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
455 status = intel_sdvo_read_response(intel_output, &dtd->part2,
456 sizeof(dtd->part2));
457 if (status != SDVO_CMD_STATUS_SUCCESS)
458 return false;
459
460 return true;
461}
462
463static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
464 struct intel_sdvo_dtd *dtd)
465{
466 return intel_sdvo_get_timing(intel_output,
467 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
468}
469
470static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
471 struct intel_sdvo_dtd *dtd)
472{
473 return intel_sdvo_get_timing(intel_output,
474 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
475}
476
477static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
478 struct intel_sdvo_dtd *dtd)
479{
480 u8 status;
481
482 intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
483 status = intel_sdvo_read_response(intel_output, NULL, 0);
484 if (status != SDVO_CMD_STATUS_SUCCESS)
485 return false;
486
487 intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
488 status = intel_sdvo_read_response(intel_output, NULL, 0);
489 if (status != SDVO_CMD_STATUS_SUCCESS)
490 return false;
491
492 return true;
493}
494
495static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
496 struct intel_sdvo_dtd *dtd)
497{
498 return intel_sdvo_set_timing(intel_output,
499 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
500}
501
502static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
503 struct intel_sdvo_dtd *dtd)
504{
505 return intel_sdvo_set_timing(intel_output,
506 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
507}
508
509
510static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
511{
512 u8 response, status;
513
514 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
515 status = intel_sdvo_read_response(intel_output, &response, 1);
516
517 if (status != SDVO_CMD_STATUS_SUCCESS) {
518 DRM_DEBUG("Couldn't get SDVO clock rate multiplier\n");
519 return SDVO_CLOCK_RATE_MULT_1X;
520 } else {
521 DRM_DEBUG("Current clock rate multiplier: %d\n", response);
522 }
523
524 return response;
525}
526
527static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
528{
529 u8 status;
530
531 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
532 status = intel_sdvo_read_response(intel_output, NULL, 0);
533 if (status != SDVO_CMD_STATUS_SUCCESS)
534 return false;
535
536 return true;
537}
538
539static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
540 struct drm_display_mode *mode,
541 struct drm_display_mode *adjusted_mode)
542{
543 /* Make the CRTC code factor in the SDVO pixel multiplier. The SDVO
544 * device will be told of the multiplier during mode_set.
545 */
546 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
547 return true;
548}
549
550static void intel_sdvo_mode_set(struct drm_encoder *encoder,
551 struct drm_display_mode *mode,
552 struct drm_display_mode *adjusted_mode)
553{
554 struct drm_device *dev = encoder->dev;
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 struct drm_crtc *crtc = encoder->crtc;
557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
558 struct intel_output *intel_output = enc_to_intel_output(encoder);
559 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
560 u16 width, height;
561 u16 h_blank_len, h_sync_len, v_blank_len, v_sync_len;
562 u16 h_sync_offset, v_sync_offset;
563 u32 sdvox;
564 struct intel_sdvo_dtd output_dtd;
565 int sdvo_pixel_multiply;
566
567 if (!mode)
568 return;
569
570 width = mode->crtc_hdisplay;
571 height = mode->crtc_vdisplay;
572
573 /* do some mode translations */
574 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
575 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
576
577 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
578 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
579
580 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
581 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
582
583 output_dtd.part1.clock = mode->clock / 10;
584 output_dtd.part1.h_active = width & 0xff;
585 output_dtd.part1.h_blank = h_blank_len & 0xff;
586 output_dtd.part1.h_high = (((width >> 8) & 0xf) << 4) |
587 ((h_blank_len >> 8) & 0xf);
588 output_dtd.part1.v_active = height & 0xff;
589 output_dtd.part1.v_blank = v_blank_len & 0xff;
590 output_dtd.part1.v_high = (((height >> 8) & 0xf) << 4) |
591 ((v_blank_len >> 8) & 0xf);
592
593 output_dtd.part2.h_sync_off = h_sync_offset;
594 output_dtd.part2.h_sync_width = h_sync_len & 0xff;
595 output_dtd.part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
596 (v_sync_len & 0xf);
597 output_dtd.part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
598 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
599 ((v_sync_len & 0x30) >> 4);
600
601 output_dtd.part2.dtd_flags = 0x18;
602 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
603 output_dtd.part2.dtd_flags |= 0x2;
604 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
605 output_dtd.part2.dtd_flags |= 0x4;
606
607 output_dtd.part2.sdvo_flags = 0;
608 output_dtd.part2.v_sync_off_high = v_sync_offset & 0xc0;
609 output_dtd.part2.reserved = 0;
610
611 /* Set the output timing to the screen */
612 intel_sdvo_set_target_output(intel_output, sdvo_priv->active_outputs);
613 intel_sdvo_set_output_timing(intel_output, &output_dtd);
614
615 /* Set the input timing to the screen. Assume always input 0. */
616 intel_sdvo_set_target_input(intel_output, true, false);
617
618 /* We would like to use i830_sdvo_create_preferred_input_timing() to
619 * provide the device with a timing it can support, if it supports that
620 * feature. However, presumably we would need to adjust the CRTC to
621 * output the preferred timing, and we don't support that currently.
622 */
623 intel_sdvo_set_input_timing(intel_output, &output_dtd);
624
625 switch (intel_sdvo_get_pixel_multiplier(mode)) {
626 case 1:
627 intel_sdvo_set_clock_rate_mult(intel_output,
628 SDVO_CLOCK_RATE_MULT_1X);
629 break;
630 case 2:
631 intel_sdvo_set_clock_rate_mult(intel_output,
632 SDVO_CLOCK_RATE_MULT_2X);
633 break;
634 case 4:
635 intel_sdvo_set_clock_rate_mult(intel_output,
636 SDVO_CLOCK_RATE_MULT_4X);
637 break;
638 }
639
640 /* Set the SDVO control regs. */
641 if (0/*IS_I965GM(dev)*/) {
642 sdvox = SDVO_BORDER_ENABLE;
643 } else {
644 sdvox = I915_READ(sdvo_priv->output_device);
645 switch (sdvo_priv->output_device) {
646 case SDVOB:
647 sdvox &= SDVOB_PRESERVE_MASK;
648 break;
649 case SDVOC:
650 sdvox &= SDVOC_PRESERVE_MASK;
651 break;
652 }
653 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
654 }
655 if (intel_crtc->pipe == 1)
656 sdvox |= SDVO_PIPE_B_SELECT;
657
658 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
659 if (IS_I965G(dev)) {
660 /* done in crtc_mode_set as the dpll_md reg must be written
661 early */
662 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
663 /* done in crtc_mode_set as it lives inside the
664 dpll register */
665 } else {
666 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
667 }
668
669 intel_sdvo_write_sdvox(intel_output, sdvox);
670}
671
672static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
673{
674 struct drm_device *dev = encoder->dev;
675 struct drm_i915_private *dev_priv = dev->dev_private;
676 struct intel_output *intel_output = enc_to_intel_output(encoder);
677 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
678 u32 temp;
679
680 if (mode != DRM_MODE_DPMS_ON) {
681 intel_sdvo_set_active_outputs(intel_output, 0);
682 if (0)
683 intel_sdvo_set_encoder_power_state(intel_output, mode);
684
685 if (mode == DRM_MODE_DPMS_OFF) {
686 temp = I915_READ(sdvo_priv->output_device);
687 if ((temp & SDVO_ENABLE) != 0) {
688 intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
689 }
690 }
691 } else {
692 bool input1, input2;
693 int i;
694 u8 status;
695
696 temp = I915_READ(sdvo_priv->output_device);
697 if ((temp & SDVO_ENABLE) == 0)
698 intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
699 for (i = 0; i < 2; i++)
700 intel_wait_for_vblank(dev);
701
702 status = intel_sdvo_get_trained_inputs(intel_output, &input1,
703 &input2);
704
705
706 /* Warn if the device reported failure to sync.
707 * A lot of SDVO devices fail to notify of sync, but it's
708 * a given it the status is a success, we succeeded.
709 */
710 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
711 DRM_DEBUG("First %s output reported failure to sync\n",
712 SDVO_NAME(sdvo_priv));
713 }
714
715 if (0)
716 intel_sdvo_set_encoder_power_state(intel_output, mode);
717 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->active_outputs);
718 }
719 return;
720}
721
722static void intel_sdvo_save(struct drm_connector *connector)
723{
724 struct drm_device *dev = connector->dev;
725 struct drm_i915_private *dev_priv = dev->dev_private;
726 struct intel_output *intel_output = to_intel_output(connector);
727 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
728 int o;
729
730 sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
731 intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
732
733 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
734 intel_sdvo_set_target_input(intel_output, true, false);
735 intel_sdvo_get_input_timing(intel_output,
736 &sdvo_priv->save_input_dtd_1);
737 }
738
739 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
740 intel_sdvo_set_target_input(intel_output, false, true);
741 intel_sdvo_get_input_timing(intel_output,
742 &sdvo_priv->save_input_dtd_2);
743 }
744
745 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
746 {
747 u16 this_output = (1 << o);
748 if (sdvo_priv->caps.output_flags & this_output)
749 {
750 intel_sdvo_set_target_output(intel_output, this_output);
751 intel_sdvo_get_output_timing(intel_output,
752 &sdvo_priv->save_output_dtd[o]);
753 }
754 }
755
756 sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
757}
758
759static void intel_sdvo_restore(struct drm_connector *connector)
760{
761 struct drm_device *dev = connector->dev;
762 struct drm_i915_private *dev_priv = dev->dev_private;
763 struct intel_output *intel_output = to_intel_output(connector);
764 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
765 int o;
766 int i;
767 bool input1, input2;
768 u8 status;
769
770 intel_sdvo_set_active_outputs(intel_output, 0);
771
772 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
773 {
774 u16 this_output = (1 << o);
775 if (sdvo_priv->caps.output_flags & this_output) {
776 intel_sdvo_set_target_output(intel_output, this_output);
777 intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
778 }
779 }
780
781 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
782 intel_sdvo_set_target_input(intel_output, true, false);
783 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
784 }
785
786 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
787 intel_sdvo_set_target_input(intel_output, false, true);
788 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
789 }
790
791 intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
792
793 I915_WRITE(sdvo_priv->output_device, sdvo_priv->save_SDVOX);
794
795 if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
796 {
797 for (i = 0; i < 2; i++)
798 intel_wait_for_vblank(dev);
799 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
800 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
801 DRM_DEBUG("First %s output reported failure to sync\n",
802 SDVO_NAME(sdvo_priv));
803 }
804
805 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
806}
807
808static int intel_sdvo_mode_valid(struct drm_connector *connector,
809 struct drm_display_mode *mode)
810{
811 struct intel_output *intel_output = to_intel_output(connector);
812 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
813
814 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
815 return MODE_NO_DBLESCAN;
816
817 if (sdvo_priv->pixel_clock_min > mode->clock)
818 return MODE_CLOCK_LOW;
819
820 if (sdvo_priv->pixel_clock_max < mode->clock)
821 return MODE_CLOCK_HIGH;
822
823 return MODE_OK;
824}
825
826static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
827{
828 u8 status;
829
830 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
831 status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
832 if (status != SDVO_CMD_STATUS_SUCCESS)
833 return false;
834
835 return true;
836}
837
838struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
839{
840 struct drm_connector *connector = NULL;
841 struct intel_output *iout = NULL;
842 struct intel_sdvo_priv *sdvo;
843
844 /* find the sdvo connector */
845 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
846 iout = to_intel_output(connector);
847
848 if (iout->type != INTEL_OUTPUT_SDVO)
849 continue;
850
851 sdvo = iout->dev_priv;
852
853 if (sdvo->output_device == SDVOB && sdvoB)
854 return connector;
855
856 if (sdvo->output_device == SDVOC && !sdvoB)
857 return connector;
858
859 }
860
861 return NULL;
862}
863
864int intel_sdvo_supports_hotplug(struct drm_connector *connector)
865{
866 u8 response[2];
867 u8 status;
868 struct intel_output *intel_output;
869 DRM_DEBUG("\n");
870
871 if (!connector)
872 return 0;
873
874 intel_output = to_intel_output(connector);
875
876 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
877 status = intel_sdvo_read_response(intel_output, &response, 2);
878
879 if (response[0] !=0)
880 return 1;
881
882 return 0;
883}
884
885void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
886{
887 u8 response[2];
888 u8 status;
889 struct intel_output *intel_output = to_intel_output(connector);
890
891 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
892 intel_sdvo_read_response(intel_output, &response, 2);
893
894 if (on) {
895 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
896 status = intel_sdvo_read_response(intel_output, &response, 2);
897
898 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
899 } else {
900 response[0] = 0;
901 response[1] = 0;
902 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
903 }
904
905 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
906 intel_sdvo_read_response(intel_output, &response, 2);
907}
908
909static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
910{
911 u8 response[2];
912 u8 status;
913 struct intel_output *intel_output = to_intel_output(connector);
914
915 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
916 status = intel_sdvo_read_response(intel_output, &response, 2);
917
918 DRM_DEBUG("SDVO response %d %d\n", response[0], response[1]);
919 if ((response[0] != 0) || (response[1] != 0))
920 return connector_status_connected;
921 else
922 return connector_status_disconnected;
923}
924
925static int intel_sdvo_get_modes(struct drm_connector *connector)
926{
927 struct intel_output *intel_output = to_intel_output(connector);
928
929 /* set the bus switch and get the modes */
930 intel_sdvo_set_control_bus_switch(intel_output, SDVO_CONTROL_BUS_DDC2);
931 intel_ddc_get_modes(intel_output);
932
933 if (list_empty(&connector->probed_modes))
934 return 0;
935 return 1;
936}
937
938static void intel_sdvo_destroy(struct drm_connector *connector)
939{
940 struct intel_output *intel_output = to_intel_output(connector);
941
942 if (intel_output->i2c_bus)
943 intel_i2c_destroy(intel_output->i2c_bus);
944 drm_sysfs_connector_remove(connector);
945 drm_connector_cleanup(connector);
946 kfree(intel_output);
947}
948
949static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
950 .dpms = intel_sdvo_dpms,
951 .mode_fixup = intel_sdvo_mode_fixup,
952 .prepare = intel_encoder_prepare,
953 .mode_set = intel_sdvo_mode_set,
954 .commit = intel_encoder_commit,
955};
956
957static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
958 .save = intel_sdvo_save,
959 .restore = intel_sdvo_restore,
960 .detect = intel_sdvo_detect,
961 .fill_modes = drm_helper_probe_single_connector_modes,
962 .destroy = intel_sdvo_destroy,
963};
964
965static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
966 .get_modes = intel_sdvo_get_modes,
967 .mode_valid = intel_sdvo_mode_valid,
968 .best_encoder = intel_best_encoder,
969};
970
b358d0a6 971static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945
JB		 972{
973 drm_encoder_cleanup(encoder);
974}
975
976static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
977 .destroy = intel_sdvo_enc_destroy,
978};
979
980
981void intel_sdvo_init(struct drm_device *dev, int output_device)
982{
983 struct drm_connector *connector;
984 struct intel_output *intel_output;
985 struct intel_sdvo_priv *sdvo_priv;
986 struct intel_i2c_chan *i2cbus = NULL;
987 int connector_type;
988 u8 ch[0x40];
989 int i;
990 int encoder_type, output_id;
991
992 intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
993 if (!intel_output) {
994 return;
995 }
996
997 connector = &intel_output->base;
998
999 drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
1000 DRM_MODE_CONNECTOR_Unknown);
1001 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
1002 sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
1003 intel_output->type = INTEL_OUTPUT_SDVO;
1004
1005 connector->interlace_allowed = 0;
1006 connector->doublescan_allowed = 0;
1007
1008 /* setup the DDC bus. */
1009 if (output_device == SDVOB)
1010 i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
1011 else
1012 i2cbus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
1013
1014 if (!i2cbus)
1015 goto err_connector;
1016
1017 sdvo_priv->i2c_bus = i2cbus;
1018
1019 if (output_device == SDVOB) {
1020 output_id = 1;
1021 sdvo_priv->i2c_bus->slave_addr = 0x38;
1022 } else {
1023 output_id = 2;
1024 sdvo_priv->i2c_bus->slave_addr = 0x39;
1025 }
1026
1027 sdvo_priv->output_device = output_device;
1028 intel_output->i2c_bus = i2cbus;
1029 intel_output->dev_priv = sdvo_priv;
1030
1031
1032 /* Read the regs to test if we can talk to the device */
1033 for (i = 0; i < 0x40; i++) {
1034 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
1035 DRM_DEBUG("No SDVO device found on SDVO%c\n",
1036 output_device == SDVOB ? 'B' : 'C');
1037 goto err_i2c;
1038 }
1039 }
1040
1041 intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
1042
1043 memset(&sdvo_priv->active_outputs, 0, sizeof(sdvo_priv->active_outputs));
1044
1045 /* TODO, CVBS, SVID, YPRPB & SCART outputs. */
1046 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB0)
1047 {
1048 sdvo_priv->active_outputs = SDVO_OUTPUT_RGB0;
1049 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1050 encoder_type = DRM_MODE_ENCODER_DAC;
1051 connector_type = DRM_MODE_CONNECTOR_VGA;
1052 }
1053 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_RGB1)
1054 {
1055 sdvo_priv->active_outputs = SDVO_OUTPUT_RGB1;
1056 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1057 encoder_type = DRM_MODE_ENCODER_DAC;
1058 connector_type = DRM_MODE_CONNECTOR_VGA;
1059 }
1060 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
1061 {
1062 sdvo_priv->active_outputs = SDVO_OUTPUT_TMDS0;
1063 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1064 encoder_type = DRM_MODE_ENCODER_TMDS;
1065 connector_type = DRM_MODE_CONNECTOR_DVID;
1066 }
1067 else if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS1)
1068 {
1069 sdvo_priv->active_outputs = SDVO_OUTPUT_TMDS1;
1070 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1071 encoder_type = DRM_MODE_ENCODER_TMDS;
1072 connector_type = DRM_MODE_CONNECTOR_DVID;
1073 }
1074 else
1075 {
1076 unsigned char bytes[2];
1077
1078 memcpy (bytes, &sdvo_priv->caps.output_flags, 2);
1079 DRM_DEBUG("%s: No active RGB or TMDS outputs (0x%02x%02x)\n",
1080 SDVO_NAME(sdvo_priv),
1081 bytes[0], bytes[1]);
1082 goto err_i2c;
1083 }
1084
1085 drm_encoder_init(dev, &intel_output->enc, &intel_sdvo_enc_funcs, encoder_type);
1086 drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
1087 connector->connector_type = connector_type;
1088
1089 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
1090 drm_sysfs_connector_add(connector);
1091
1092 /* Set the input timing to the screen. Assume always input 0. */
1093 intel_sdvo_set_target_input(intel_output, true, false);
1094
1095 intel_sdvo_get_input_pixel_clock_range(intel_output,
1096 &sdvo_priv->pixel_clock_min,
1097 &sdvo_priv->pixel_clock_max);
1098
1099
1100 DRM_DEBUG("%s device VID/DID: %02X:%02X.%02X, "
1101 "clock range %dMHz - %dMHz, "
1102 "input 1: %c, input 2: %c, "
1103 "output 1: %c, output 2: %c\n",
1104 SDVO_NAME(sdvo_priv),
1105 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
1106 sdvo_priv->caps.device_rev_id,
1107 sdvo_priv->pixel_clock_min / 1000,
1108 sdvo_priv->pixel_clock_max / 1000,
1109 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
1110 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
1111 /* check currently supported outputs */
1112 sdvo_priv->caps.output_flags &
1113 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
1114 sdvo_priv->caps.output_flags &
1115 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
1116
1117 intel_output->ddc_bus = i2cbus;
1118
1119 return;
1120
1121err_i2c:
1122 intel_i2c_destroy(intel_output->i2c_bus);
1123err_connector:
1124 drm_connector_cleanup(connector);
1125 kfree(intel_output);
1126
1127 return;
1128}
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