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drm/i915: state readout and cross checking for limited_color_range
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
ea5b213a 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
79e53945
JB		 37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 46 SDVO_TV_MASK)
14571b4c
ZW		 47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 50#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 51#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 52#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 53
79e53945 54
2e88e40b 55static const char *tv_format_names[] = {
ce6feabd
ZY		 56 "NTSC_M" , "NTSC_J" , "NTSC_443",
57 "PAL_B" , "PAL_D" , "PAL_G" ,
58 "PAL_H" , "PAL_I" , "PAL_M" ,
59 "PAL_N" , "PAL_NC" , "PAL_60" ,
60 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
61 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
62 "SECAM_60"
63};
64
65#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
66
ea5b213a
CW		 67struct intel_sdvo {
68 struct intel_encoder base;
69
f899fc64 70 struct i2c_adapter *i2c;
f9c10a9b 71 u8 slave_addr;
e2f0ba97 72
e957d772
CW		 73 struct i2c_adapter ddc;
74
e2f0ba97 75 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 76 uint32_t sdvo_reg;
79e53945 77
e2f0ba97
JB		 78 /* Active outputs controlled by this SDVO output */
79 uint16_t controlled_output;
79e53945 80
e2f0ba97
JB		 81 /*
82 * Capabilities of the SDVO device returned by
19d415a2 83 * intel_sdvo_get_capabilities()
e2f0ba97 84 */
79e53945 85 struct intel_sdvo_caps caps;
e2f0ba97
JB		 86
87 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 88 int pixel_clock_min, pixel_clock_max;
89
fb7a46f3 90 /*
91 * For multiple function SDVO device,
92 * this is for current attached outputs.
93 */
94 uint16_t attached_output;
95
cc68c81a
SF		 96 /*
97 * Hotplug activation bits for this device
98 */
5fa7ac9c 99 uint16_t hotplug_active;
cc68c81a 100
e953fd7b
CW		 101 /**
102 * This is used to select the color range of RBG outputs in HDMI mode.
103 * It is only valid when using TMDS encoding and 8 bit per color mode.
104 */
105 uint32_t color_range;
55bc60db 106 bool color_range_auto;
e953fd7b 107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
eef4eacb
DV		 117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
ce6feabd 120 /* This is for current tv format name */
40039750 121 int tv_format_index;
ce6feabd 122
e2f0ba97
JB		 123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
da79de97
CW		 127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
abedc077 129 bool rgb_quant_range_selectable;
12682a97 130
7086c87f 131 /**
6c9547ff
CW		 132 * This is set if we detect output of sdvo device as LVDS and
133 * have a valid fixed mode to use with the panel.
7086c87f
ML		 134 */
135 bool is_lvds;
e2f0ba97 136
12682a97 137 /**
138 * This is sdvo fixed pannel mode pointer
139 */
140 struct drm_display_mode *sdvo_lvds_fixed_mode;
141
c751ce4f 142 /* DDC bus used by this SDVO encoder */
e2f0ba97 143 uint8_t ddc_bus;
e751823d
EE		 144
145 /*
146 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
147 */
148 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 149};
150
151struct intel_sdvo_connector {
615fb93f
CW		 152 struct intel_connector base;
153
14571b4c
ZW		 154 /* Mark the type of connector */
155 uint16_t output_flag;
156
c3e5f67b 157 enum hdmi_force_audio force_audio;
7f36e7ed 158
14571b4c 159 /* This contains all current supported TV format */
40039750 160 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 161 int format_supported_num;
c5521706 162 struct drm_property *tv_format;
14571b4c 163
b9219c5e 164 /* add the property for the SDVO-TV */
c5521706
CW		 165 struct drm_property *left;
166 struct drm_property *right;
167 struct drm_property *top;
168 struct drm_property *bottom;
169 struct drm_property *hpos;
170 struct drm_property *vpos;
171 struct drm_property *contrast;
172 struct drm_property *saturation;
173 struct drm_property *hue;
174 struct drm_property *sharpness;
175 struct drm_property *flicker_filter;
176 struct drm_property *flicker_filter_adaptive;
177 struct drm_property *flicker_filter_2d;
178 struct drm_property *tv_chroma_filter;
179 struct drm_property *tv_luma_filter;
e044218a 180 struct drm_property *dot_crawl;
b9219c5e
ZY		 181
182 /* add the property for the SDVO-TV/LVDS */
c5521706 183 struct drm_property *brightness;
b9219c5e
ZY		 184
185 /* Add variable to record current setting for the above property */
186 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 187
b9219c5e
ZY		 188 /* this is to get the range of margin.*/
189 u32 max_hscan, max_vscan;
190 u32 max_hpos, cur_hpos;
191 u32 max_vpos, cur_vpos;
192 u32 cur_brightness, max_brightness;
193 u32 cur_contrast, max_contrast;
194 u32 cur_saturation, max_saturation;
195 u32 cur_hue, max_hue;
c5521706
CW		 196 u32 cur_sharpness, max_sharpness;
197 u32 cur_flicker_filter, max_flicker_filter;
198 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
199 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
200 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
201 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 202 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 203};
204
8aca63aa 205static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
ea5b213a 206{
8aca63aa 207 return container_of(encoder, struct intel_sdvo, base);
ea5b213a
CW		 208}
209
df0e9248
CW		 210static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
211{
8aca63aa 212 return to_sdvo(intel_attached_encoder(connector));
df0e9248
CW		 213}
214
615fb93f
CW		 215static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
216{
217 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
218}
219
fb7a46f3 220static bool
ea5b213a 221intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 222static bool
223intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
224 struct intel_sdvo_connector *intel_sdvo_connector,
225 int type);
226static bool
227intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
228 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 229
79e53945
JB		 230/**
231 * Writes the SDVOB or SDVOC with the given value, but always writes both
232 * SDVOB and SDVOC to work around apparent hardware issues (according to
233 * comments in the BIOS).
234 */
ea5b213a 235static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 236{
4ef69c7a 237 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 238 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 239 u32 bval = val, cval = val;
240 int i;
241
ea5b213a
CW		 242 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
243 I915_WRITE(intel_sdvo->sdvo_reg, val);
244 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 245 return;
246 }
247
e2debe91
PZ		 248 if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
249 cval = I915_READ(GEN3_SDVOC);
250 else
251 bval = I915_READ(GEN3_SDVOB);
252
79e53945
JB		 253 /*
254 * Write the registers twice for luck. Sometimes,
255 * writing them only once doesn't appear to 'stick'.
256 * The BIOS does this too. Yay, magic
257 */
258 for (i = 0; i < 2; i++)
259 {
e2debe91
PZ		 260 I915_WRITE(GEN3_SDVOB, bval);
261 I915_READ(GEN3_SDVOB);
262 I915_WRITE(GEN3_SDVOC, cval);
263 I915_READ(GEN3_SDVOC);
79e53945
JB		 264 }
265}
266
32aad86f 267static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 268{
79e53945
JB		 269 struct i2c_msg msgs[] = {
270 {
e957d772 271 .addr = intel_sdvo->slave_addr,
79e53945
JB		 272 .flags = 0,
273 .len = 1,
e957d772 274 .buf = &addr,
79e53945
JB		 275 },
276 {
e957d772 277 .addr = intel_sdvo->slave_addr,
79e53945
JB		 278 .flags = I2C_M_RD,
279 .len = 1,
e957d772 280 .buf = ch,
79e53945
JB		 281 }
282 };
32aad86f 283 int ret;
79e53945 284
f899fc64 285 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 286 return true;
79e53945 287
8a4c47f3 288 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 289 return false;
290}
291
79e53945
JB		 292#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
293/** Mapping of command numbers to names, for debug output */
005568be 294static const struct _sdvo_cmd_name {
e2f0ba97 295 u8 cmd;
2e88e40b 296 const char *name;
79e53945 297} sdvo_cmd_names[] = {
0206e353
AJ		 298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
341
342 /* Add the op code for SDVO enhancements */
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
387
388 /* HDMI op code */
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 409};
410
eef4eacb 411#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 412
ea5b213a 413static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 414 const void *args, int args_len)
79e53945 415{
84fcb469
DV		 416 int i, pos = 0;
417#define BUF_LEN 256
418 char buffer[BUF_LEN];
419
420#define BUF_PRINT(args...) \
421 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
422
79e53945 423
84fcb469
DV		 424 for (i = 0; i < args_len; i++) {
425 BUF_PRINT("%02X ", ((u8 *)args)[i]);
426 }
427 for (; i < 8; i++) {
428 BUF_PRINT(" ");
429 }
04ad327f 430 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 431 if (cmd == sdvo_cmd_names[i].cmd) {
84fcb469 432 BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 433 break;
434 }
435 }
84fcb469
DV		 436 if (i == ARRAY_SIZE(sdvo_cmd_names)) {
437 BUF_PRINT("(%02X)", cmd);
438 }
439 BUG_ON(pos >= BUF_LEN - 1);
440#undef BUF_PRINT
441#undef BUF_LEN
442
443 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
79e53945 444}
79e53945 445
e957d772
CW		 446static const char *cmd_status_names[] = {
447 "Power on",
448 "Success",
449 "Not supported",
450 "Invalid arg",
451 "Pending",
452 "Target not specified",
453 "Scaling not supported"
454};
455
32aad86f
CW		 456static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
457 const void *args, int args_len)
79e53945 458{
3bf3f452
BW		 459 u8 *buf, status;
460 struct i2c_msg *msgs;
461 int i, ret = true;
462
0274df3e 463 /* Would be simpler to allocate both in one go ? */
5c67eeb6 464 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3bf3f452
BW		 465 if (!buf)
466 return false;
467
468 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e
AC		 469 if (!msgs) {
470 kfree(buf);
3bf3f452 471 return false;
0274df3e 472 }
79e53945 473
ea5b213a 474 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 475
476 for (i = 0; i < args_len; i++) {
e957d772
CW		 477 msgs[i].addr = intel_sdvo->slave_addr;
478 msgs[i].flags = 0;
479 msgs[i].len = 2;
480 msgs[i].buf = buf + 2 *i;
481 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
482 buf[2*i + 1] = ((u8*)args)[i];
483 }
484 msgs[i].addr = intel_sdvo->slave_addr;
485 msgs[i].flags = 0;
486 msgs[i].len = 2;
487 msgs[i].buf = buf + 2*i;
488 buf[2*i + 0] = SDVO_I2C_OPCODE;
489 buf[2*i + 1] = cmd;
490
491 /* the following two are to read the response */
492 status = SDVO_I2C_CMD_STATUS;
493 msgs[i+1].addr = intel_sdvo->slave_addr;
494 msgs[i+1].flags = 0;
495 msgs[i+1].len = 1;
496 msgs[i+1].buf = &status;
497
498 msgs[i+2].addr = intel_sdvo->slave_addr;
499 msgs[i+2].flags = I2C_M_RD;
500 msgs[i+2].len = 1;
501 msgs[i+2].buf = &status;
502
503 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
504 if (ret < 0) {
505 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 506 ret = false;
507 goto out;
e957d772
CW		 508 }
509 if (ret != i+3) {
510 /* failure in I2C transfer */
511 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 512 ret = false;
e957d772
CW		 513 }
514
3bf3f452
BW		 515out:
516 kfree(msgs);
517 kfree(buf);
518 return ret;
79e53945
JB		 519}
520
b5c616a7
CW		 521static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
522 void *response, int response_len)
79e53945 523{
fc37381c 524 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 525 u8 status;
84fcb469
DV		 526 int i, pos = 0;
527#define BUF_LEN 256
528 char buffer[BUF_LEN];
79e53945 529
d121a5d2 530
b5c616a7
CW		 531 /*
532 * The documentation states that all commands will be
533 * processed within 15µs, and that we need only poll
534 * the status byte a maximum of 3 times in order for the
535 * command to be complete.
536 *
537 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 538 *
539 * Also beware that the first response by many devices is to
540 * reply PENDING and stall for time. TVs are notorious for
541 * requiring longer than specified to complete their replies.
542 * Originally (in the DDX long ago), the delay was only ever 15ms
543 * with an additional delay of 30ms applied for TVs added later after
544 * many experiments. To accommodate both sets of delays, we do a
545 * sequence of slow checks if the device is falling behind and fails
546 * to reply within 5*15µs.
b5c616a7 547 */
d121a5d2
CW		 548 if (!intel_sdvo_read_byte(intel_sdvo,
549 SDVO_I2C_CMD_STATUS,
550 &status))
551 goto log_fail;
552
1ad87e72 553 while ((status == SDVO_CMD_STATUS_PENDING ||
46a3f4a3 554 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
fc37381c
CW		 555 if (retry < 10)
556 msleep(15);
557 else
558 udelay(15);
559
b5c616a7
CW		 560 if (!intel_sdvo_read_byte(intel_sdvo,
561 SDVO_I2C_CMD_STATUS,
562 &status))
d121a5d2
CW		 563 goto log_fail;
564 }
b5c616a7 565
84fcb469
DV		 566#define BUF_PRINT(args...) \
567 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
568
79e53945 569 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
84fcb469 570 BUF_PRINT("(%s)", cmd_status_names[status]);
79e53945 571 else
84fcb469 572 BUF_PRINT("(??? %d)", status);
79e53945 573
b5c616a7
CW		 574 if (status != SDVO_CMD_STATUS_SUCCESS)
575 goto log_fail;
79e53945 576
b5c616a7
CW		 577 /* Read the command response */
578 for (i = 0; i < response_len; i++) {
579 if (!intel_sdvo_read_byte(intel_sdvo,
580 SDVO_I2C_RETURN_0 + i,
581 &((u8 *)response)[i]))
582 goto log_fail;
84fcb469 583 BUF_PRINT(" %02X", ((u8 *)response)[i]);
b5c616a7 584 }
84fcb469
DV		 585 BUG_ON(pos >= BUF_LEN - 1);
586#undef BUF_PRINT
587#undef BUF_LEN
588
589 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
b5c616a7 590 return true;
79e53945 591
b5c616a7 592log_fail:
84fcb469 593 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
b5c616a7 594 return false;
79e53945
JB		 595}
596
b358d0a6 597static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 598{
599 if (mode->clock >= 100000)
600 return 1;
601 else if (mode->clock >= 50000)
602 return 2;
603 else
604 return 4;
605}
606
e957d772
CW		 607static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
608 u8 ddc_bus)
79e53945 609{
d121a5d2 610 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 611 return intel_sdvo_write_cmd(intel_sdvo,
612 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
613 &ddc_bus, 1);
79e53945
JB		 614}
615
32aad86f 616static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 617{
d121a5d2
CW		 618 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
619 return false;
620
621 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 622}
79e53945 623
32aad86f
CW		 624static bool
625intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
626{
627 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
628 return false;
79e53945 629
32aad86f
CW		 630 return intel_sdvo_read_response(intel_sdvo, value, len);
631}
79e53945 632
32aad86f
CW		 633static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
634{
635 struct intel_sdvo_set_target_input_args targets = {0};
636 return intel_sdvo_set_value(intel_sdvo,
637 SDVO_CMD_SET_TARGET_INPUT,
638 &targets, sizeof(targets));
79e53945
JB		 639}
640
641/**
642 * Return whether each input is trained.
643 *
644 * This function is making an assumption about the layout of the response,
645 * which should be checked against the docs.
646 */
ea5b213a 647static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 648{
649 struct intel_sdvo_get_trained_inputs_response response;
79e53945 650
1a3665c8 651 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 652 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
653 &response, sizeof(response)))
79e53945
JB		 654 return false;
655
656 *input_1 = response.input0_trained;
657 *input_2 = response.input1_trained;
658 return true;
659}
660
ea5b213a 661static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 662 u16 outputs)
663{
32aad86f
CW		 664 return intel_sdvo_set_value(intel_sdvo,
665 SDVO_CMD_SET_ACTIVE_OUTPUTS,
666 &outputs, sizeof(outputs));
79e53945
JB		 667}
668
4ac41f47
DV		 669static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
670 u16 *outputs)
671{
672 return intel_sdvo_get_value(intel_sdvo,
673 SDVO_CMD_GET_ACTIVE_OUTPUTS,
674 outputs, sizeof(*outputs));
675}
676
ea5b213a 677static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 678 int mode)
679{
32aad86f 680 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 681
682 switch (mode) {
683 case DRM_MODE_DPMS_ON:
684 state = SDVO_ENCODER_STATE_ON;
685 break;
686 case DRM_MODE_DPMS_STANDBY:
687 state = SDVO_ENCODER_STATE_STANDBY;
688 break;
689 case DRM_MODE_DPMS_SUSPEND:
690 state = SDVO_ENCODER_STATE_SUSPEND;
691 break;
692 case DRM_MODE_DPMS_OFF:
693 state = SDVO_ENCODER_STATE_OFF;
694 break;
695 }
696
32aad86f
CW		 697 return intel_sdvo_set_value(intel_sdvo,
698 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 699}
700
ea5b213a 701static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 702 int *clock_min,
703 int *clock_max)
704{
705 struct intel_sdvo_pixel_clock_range clocks;
79e53945 706
1a3665c8 707 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 708 if (!intel_sdvo_get_value(intel_sdvo,
709 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
710 &clocks, sizeof(clocks)))
79e53945
JB		 711 return false;
712
713 /* Convert the values from units of 10 kHz to kHz. */
714 *clock_min = clocks.min * 10;
715 *clock_max = clocks.max * 10;
79e53945
JB		 716 return true;
717}
718
ea5b213a 719static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 720 u16 outputs)
721{
32aad86f
CW		 722 return intel_sdvo_set_value(intel_sdvo,
723 SDVO_CMD_SET_TARGET_OUTPUT,
724 &outputs, sizeof(outputs));
79e53945
JB		 725}
726
ea5b213a 727static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 728 struct intel_sdvo_dtd *dtd)
729{
32aad86f
CW		 730 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
731 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 732}
733
045ac3b5
JB		 734static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
735 struct intel_sdvo_dtd *dtd)
736{
737 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
738 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
739}
740
ea5b213a 741static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 742 struct intel_sdvo_dtd *dtd)
743{
ea5b213a 744 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 745 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
746}
747
ea5b213a 748static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 749 struct intel_sdvo_dtd *dtd)
750{
ea5b213a 751 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 752 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
753}
754
045ac3b5
JB		 755static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
756 struct intel_sdvo_dtd *dtd)
757{
758 return intel_sdvo_get_timing(intel_sdvo,
759 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
760}
761
e2f0ba97 762static bool
ea5b213a 763intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 764 uint16_t clock,
765 uint16_t width,
766 uint16_t height)
767{
768 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 769
e642c6f1 770 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 771 args.clock = clock;
772 args.width = width;
773 args.height = height;
e642c6f1 774 args.interlace = 0;
12682a97 775
ea5b213a
CW		 776 if (intel_sdvo->is_lvds &&
777 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
778 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 779 args.scaled = 1;
780
32aad86f
CW		 781 return intel_sdvo_set_value(intel_sdvo,
782 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
783 &args, sizeof(args));
e2f0ba97
JB		 784}
785
ea5b213a 786static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 787 struct intel_sdvo_dtd *dtd)
788{
1a3665c8
CW		 789 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
790 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 791 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
792 &dtd->part1, sizeof(dtd->part1)) &&
793 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
794 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 795}
79e53945 796
ea5b213a 797static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 798{
32aad86f 799 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 800}
801
e2f0ba97 802static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 803 const struct drm_display_mode *mode)
79e53945 804{
e2f0ba97
JB		 805 uint16_t width, height;
806 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
807 uint16_t h_sync_offset, v_sync_offset;
6651819b 808 int mode_clock;
79e53945 809
1c4a814e
DV		 810 memset(dtd, 0, sizeof(*dtd));
811
c6ebd4c0
DV		 812 width = mode->hdisplay;
813 height = mode->vdisplay;
79e53945
JB		 814
815 /* do some mode translations */
c6ebd4c0
DV		 816 h_blank_len = mode->htotal - mode->hdisplay;
817 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 818
c6ebd4c0
DV		 819 v_blank_len = mode->vtotal - mode->vdisplay;
820 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 821
c6ebd4c0
DV		 822 h_sync_offset = mode->hsync_start - mode->hdisplay;
823 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 824
6651819b 825 mode_clock = mode->clock;
6651819b
DV		 826 mode_clock /= 10;
827 dtd->part1.clock = mode_clock;
828
e2f0ba97
JB		 829 dtd->part1.h_active = width & 0xff;
830 dtd->part1.h_blank = h_blank_len & 0xff;
831 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 832 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 833 dtd->part1.v_active = height & 0xff;
834 dtd->part1.v_blank = v_blank_len & 0xff;
835 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 836 ((v_blank_len >> 8) & 0xf);
837
171a9e96 838 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 839 dtd->part2.h_sync_width = h_sync_len & 0xff;
840 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 841 (v_sync_len & 0xf);
e2f0ba97 842 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 843 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
844 ((v_sync_len & 0x30) >> 4);
845
e2f0ba97 846 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 847 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
848 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 849 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 850 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 851 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 852 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97 853
e2f0ba97 854 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
e2f0ba97
JB		 855}
856
1c4a814e 857static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
32aad86f 858 const struct intel_sdvo_dtd *dtd)
e2f0ba97 859{
1c4a814e
DV		 860 struct drm_display_mode mode = {};
861
862 mode.hdisplay = dtd->part1.h_active;
863 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
864 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
865 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
866 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
867 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
868 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
869 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
870
871 mode.vdisplay = dtd->part1.v_active;
872 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
873 mode.vsync_start = mode.vdisplay;
874 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
875 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
876 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
877 mode.vsync_end = mode.vsync_start +
e2f0ba97 878 (dtd->part2.v_sync_off_width & 0xf);
1c4a814e
DV		 879 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
880 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
881 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
e2f0ba97 882
1c4a814e 883 mode.clock = dtd->part1.clock * 10;
e2f0ba97 884
59d92bfa 885 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
1c4a814e 886 mode.flags |= DRM_MODE_FLAG_INTERLACE;
59d92bfa 887 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1c4a814e 888 mode.flags |= DRM_MODE_FLAG_PHSYNC;
3cea210f 889 else
1c4a814e 890 mode.flags |= DRM_MODE_FLAG_NHSYNC;
59d92bfa 891 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1c4a814e 892 mode.flags |= DRM_MODE_FLAG_PVSYNC;
3cea210f 893 else
1c4a814e
DV		 894 mode.flags |= DRM_MODE_FLAG_NVSYNC;
895
896 drm_mode_set_crtcinfo(&mode, 0);
897
898 drm_mode_copy(pmode, &mode);
e2f0ba97
JB		 899}
900
e27d8538 901static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 902{
e27d8538 903 struct intel_sdvo_encode encode;
e2f0ba97 904
1a3665c8 905 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 906 return intel_sdvo_get_value(intel_sdvo,
907 SDVO_CMD_GET_SUPP_ENCODE,
908 &encode, sizeof(encode));
e2f0ba97
JB		 909}
910
ea5b213a 911static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 912 uint8_t mode)
e2f0ba97 913{
32aad86f 914 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 915}
916
ea5b213a 917static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 918 uint8_t mode)
919{
32aad86f 920 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 921}
922
923#if 0
ea5b213a 924static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 925{
926 int i, j;
927 uint8_t set_buf_index[2];
928 uint8_t av_split;
929 uint8_t buf_size;
930 uint8_t buf[48];
931 uint8_t *pos;
932
32aad86f 933 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 934
935 for (i = 0; i <= av_split; i++) {
936 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 937 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 938 set_buf_index, 2);
c751ce4f
EA		 939 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
940 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 941
942 pos = buf;
943 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 944 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 945 NULL, 0);
c751ce4f 946 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 947 pos += 8;
948 }
949 }
950}
951#endif
952
b6e0e543
DV		 953static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
954 unsigned if_index, uint8_t tx_rate,
fff63867 955 const uint8_t *data, unsigned length)
b6e0e543
DV		 956{
957 uint8_t set_buf_index[2] = { if_index, 0 };
958 uint8_t hbuf_size, tmp[8];
959 int i;
960
961 if (!intel_sdvo_set_value(intel_sdvo,
962 SDVO_CMD_SET_HBUF_INDEX,
963 set_buf_index, 2))
964 return false;
965
966 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
967 &hbuf_size, 1))
968 return false;
969
970 /* Buffer size is 0 based, hooray! */
971 hbuf_size++;
972
973 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
974 if_index, length, hbuf_size);
975
976 for (i = 0; i < hbuf_size; i += 8) {
977 memset(tmp, 0, 8);
978 if (i < length)
979 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
980
981 if (!intel_sdvo_set_value(intel_sdvo,
982 SDVO_CMD_SET_HBUF_DATA,
983 tmp, 8))
984 return false;
985 }
986
987 return intel_sdvo_set_value(intel_sdvo,
988 SDVO_CMD_SET_HBUF_TXRATE,
989 &tx_rate, 1);
990}
991
abedc077
VS		 992static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
993 const struct drm_display_mode *adjusted_mode)
e2f0ba97 994{
15dcd350
DL		 995 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
996 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
998 union hdmi_infoframe frame;
999 int ret;
1000 ssize_t len;
1001
1002 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
1003 adjusted_mode);
1004 if (ret < 0) {
1005 DRM_ERROR("couldn't fill AVI infoframe\n");
1006 return false;
1007 }
3c17fe4b 1008
abedc077 1009 if (intel_sdvo->rgb_quant_range_selectable) {
50f3b016 1010 if (intel_crtc->config.limited_color_range)
15dcd350
DL		 1011 frame.avi.quantization_range =
1012 HDMI_QUANTIZATION_RANGE_LIMITED;
abedc077 1013 else
15dcd350
DL		 1014 frame.avi.quantization_range =
1015 HDMI_QUANTIZATION_RANGE_FULL;
abedc077
VS		 1016 }
1017
15dcd350
DL		 1018 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
1019 if (len < 0)
1020 return false;
81014b9d 1021
b6e0e543
DV		 1022 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1023 SDVO_HBUF_TX_VSYNC,
1024 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 1025}
1026
32aad86f 1027static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 1028{
ce6feabd 1029 struct intel_sdvo_tv_format format;
40039750 1030 uint32_t format_map;
ce6feabd 1031
40039750 1032 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1033 memset(&format, 0, sizeof(format));
32aad86f 1034 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1035
32aad86f
CW		 1036 BUILD_BUG_ON(sizeof(format) != 6);
1037 return intel_sdvo_set_value(intel_sdvo,
1038 SDVO_CMD_SET_TV_FORMAT,
1039 &format, sizeof(format));
7026d4ac
ZW		 1040}
1041
32aad86f
CW		 1042static bool
1043intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1044 const struct drm_display_mode *mode)
e2f0ba97 1045{
32aad86f 1046 struct intel_sdvo_dtd output_dtd;
79e53945 1047
32aad86f
CW		 1048 if (!intel_sdvo_set_target_output(intel_sdvo,
1049 intel_sdvo->attached_output))
1050 return false;
e2f0ba97 1051
32aad86f
CW		 1052 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1053 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1054 return false;
e2f0ba97 1055
32aad86f
CW		 1056 return true;
1057}
1058
c9a29698
DV		 1059/* Asks the sdvo controller for the preferred input mode given the output mode.
1060 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 1061static bool
c9a29698 1062intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1063 const struct drm_display_mode *mode,
c9a29698 1064 struct drm_display_mode *adjusted_mode)
32aad86f 1065{
c9a29698
DV		 1066 struct intel_sdvo_dtd input_dtd;
1067
32aad86f
CW		 1068 /* Reset the input timing to the screen. Assume always input 0. */
1069 if (!intel_sdvo_set_target_input(intel_sdvo))
1070 return false;
e2f0ba97 1071
32aad86f
CW		 1072 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1073 mode->clock / 10,
1074 mode->hdisplay,
1075 mode->vdisplay))
1076 return false;
e2f0ba97 1077
32aad86f 1078 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1079 &input_dtd))
32aad86f 1080 return false;
e2f0ba97 1081
c9a29698 1082 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1083 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1084
32aad86f
CW		 1085 return true;
1086}
12682a97 1087
70484559
DV		 1088static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
1089{
3c52f4eb 1090 unsigned dotclock = pipe_config->port_clock;
70484559
DV		 1091 struct dpll *clock = &pipe_config->dpll;
1092
1093 /* SDVO TV has fixed PLL values depend on its clock range,
1094 this mirrors vbios setting. */
1095 if (dotclock >= 100000 && dotclock < 140500) {
1096 clock->p1 = 2;
1097 clock->p2 = 10;
1098 clock->n = 3;
1099 clock->m1 = 16;
1100 clock->m2 = 8;
1101 } else if (dotclock >= 140500 && dotclock <= 200000) {
1102 clock->p1 = 1;
1103 clock->p2 = 10;
1104 clock->n = 6;
1105 clock->m1 = 12;
1106 clock->m2 = 8;
1107 } else {
1108 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1109 }
1110
1111 pipe_config->clock_set = true;
1112}
1113
6cc5f341
DV		 1114static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1115 struct intel_crtc_config *pipe_config)
32aad86f 1116{
8aca63aa 1117 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
6cc5f341
DV		 1118 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1119 struct drm_display_mode *mode = &pipe_config->requested_mode;
12682a97 1120
5d2d38dd
DV		 1121 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1122 pipe_config->pipe_bpp = 8*3;
1123
5bfe2ac0
DV		 1124 if (HAS_PCH_SPLIT(encoder->base.dev))
1125 pipe_config->has_pch_encoder = true;
1126
32aad86f
CW		 1127 /* We need to construct preferred input timings based on our
1128 * output timings. To do that, we have to set the output
1129 * timings, even though this isn't really the right place in
1130 * the sequence to do it. Oh well.
1131 */
1132 if (intel_sdvo->is_tv) {
1133 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1134 return false;
12682a97 1135
c9a29698
DV		 1136 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1137 mode,
1138 adjusted_mode);
09ede541 1139 pipe_config->sdvo_tv_clock = true;
ea5b213a 1140 } else if (intel_sdvo->is_lvds) {
32aad86f 1141 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1142 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1143 return false;
12682a97 1144
c9a29698
DV		 1145 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1146 mode,
1147 adjusted_mode);
e2f0ba97 1148 }
32aad86f
CW		 1149
1150 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1151 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1152 */
6cc5f341
DV		 1153 pipe_config->pixel_multiplier =
1154 intel_sdvo_get_pixel_multiplier(adjusted_mode);
32aad86f 1155
55bc60db
VS		 1156 if (intel_sdvo->color_range_auto) {
1157 /* See CEA-861-E - 5.1 Default Encoding Parameters */
4f3a8bc7
PZ		 1158 /* FIXME: This bit is only valid when using TMDS encoding and 8
1159 * bit per color mode. */
55bc60db 1160 if (intel_sdvo->has_hdmi_monitor &&
18316c8c 1161 drm_match_cea_mode(adjusted_mode) > 1)
69f5acc8
DV		 1162 pipe_config->limited_color_range = true;
1163 } else {
1164 if (intel_sdvo->has_hdmi_monitor &&
1165 intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235)
1166 pipe_config->limited_color_range = true;
55bc60db
VS		 1167 }
1168
70484559
DV		 1169 /* Clock computation needs to happen after pixel multiplier. */
1170 if (intel_sdvo->is_tv)
1171 i9xx_adjust_sdvo_tv_clock(pipe_config);
1172
e2f0ba97
JB		 1173 return true;
1174}
1175
192d47a6 1176static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder)
e2f0ba97 1177{
6cc5f341 1178 struct drm_device *dev = intel_encoder->base.dev;
e2f0ba97 1179 struct drm_i915_private *dev_priv = dev->dev_private;
eeb47937 1180 struct intel_crtc *crtc = to_intel_crtc(intel_encoder->base.crtc);
6cc5f341 1181 struct drm_display_mode *adjusted_mode =
eeb47937
DV		 1182 &crtc->config.adjusted_mode;
1183 struct drm_display_mode *mode = &crtc->config.requested_mode;
8aca63aa 1184 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
6c9547ff 1185 u32 sdvox;
e2f0ba97 1186 struct intel_sdvo_in_out_map in_out;
6651819b 1187 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff 1188 int rate;
e2f0ba97
JB		 1189
1190 if (!mode)
1191 return;
1192
1193 /* First, set the input mapping for the first input to our controlled
1194 * output. This is only correct if we're a single-input device, in
1195 * which case the first input is the output from the appropriate SDVO
1196 * channel on the motherboard. In a two-input device, the first input
1197 * will be SDVOB and the second SDVOC.
1198 */
ea5b213a 1199 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1200 in_out.in1 = 0;
1201
c74696b9
PR		 1202 intel_sdvo_set_value(intel_sdvo,
1203 SDVO_CMD_SET_IN_OUT_MAP,
1204 &in_out, sizeof(in_out));
e2f0ba97 1205
6c9547ff
CW		 1206 /* Set the output timings to the screen */
1207 if (!intel_sdvo_set_target_output(intel_sdvo,
1208 intel_sdvo->attached_output))
1209 return;
e2f0ba97 1210
6651819b
DV		 1211 /* lvds has a special fixed output timing. */
1212 if (intel_sdvo->is_lvds)
1213 intel_sdvo_get_dtd_from_mode(&output_dtd,
1214 intel_sdvo->sdvo_lvds_fixed_mode);
1215 else
1216 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1217 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1218 DRM_INFO("Setting output timings on %s failed\n",
1219 SDVO_NAME(intel_sdvo));
79e53945
JB		 1220
1221 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1222 if (!intel_sdvo_set_target_input(intel_sdvo))
1223 return;
79e53945 1224
97aaf910
CW		 1225 if (intel_sdvo->has_hdmi_monitor) {
1226 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1227 intel_sdvo_set_colorimetry(intel_sdvo,
1228 SDVO_COLORIMETRY_RGB256);
abedc077 1229 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
97aaf910
CW		 1230 } else
1231 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1232
6c9547ff
CW		 1233 if (intel_sdvo->is_tv &&
1234 !intel_sdvo_set_tv_format(intel_sdvo))
1235 return;
e2f0ba97 1236
6651819b 1237 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
eeb47937 1238
e751823d
EE		 1239 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1240 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1241 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1242 DRM_INFO("Setting input timings on %s failed\n",
1243 SDVO_NAME(intel_sdvo));
79e53945 1244
eeb47937 1245 switch (crtc->config.pixel_multiplier) {
6c9547ff 1246 default:
ef1b460d 1247 WARN(1, "unknown pixel mutlipler specified\n");
32aad86f
CW		 1248 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1249 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1250 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1251 }
32aad86f
CW		 1252 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1253 return;
79e53945
JB		 1254
1255 /* Set the SDVO control regs. */
a6c45cf0 1256 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1257 /* The real mode polarity is set by the SDVO commands, using
1258 * struct intel_sdvo_dtd. */
1259 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
69f5acc8
DV		 1260 if (!HAS_PCH_SPLIT(dev) && crtc->config.limited_color_range)
1261 sdvox |= HDMI_COLOR_RANGE_16_235;
6714afb1
CW		 1262 if (INTEL_INFO(dev)->gen < 5)
1263 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1264 } else {
6c9547ff 1265 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1266 switch (intel_sdvo->sdvo_reg) {
e2debe91 1267 case GEN3_SDVOB:
e2f0ba97
JB		 1268 sdvox &= SDVOB_PRESERVE_MASK;
1269 break;
e2debe91 1270 case GEN3_SDVOC:
e2f0ba97
JB		 1271 sdvox &= SDVOC_PRESERVE_MASK;
1272 break;
1273 }
1274 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1275 }
3573c410
PZ		 1276
1277 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
eeb47937 1278 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
3573c410 1279 else
eeb47937 1280 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
3573c410 1281
da79de97 1282 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1283 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1284
a6c45cf0 1285 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1286 /* done in crtc_mode_set as the dpll_md reg must be written early */
1287 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1288 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1289 } else {
eeb47937 1290 sdvox |= (crtc->config.pixel_multiplier - 1)
6cc5f341 1291 << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1292 }
1293
6714afb1
CW		 1294 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1295 INTEL_INFO(dev)->gen < 5)
12682a97 1296 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1297 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1298}
1299
4ac41f47 1300static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1301{
4ac41f47
DV		 1302 struct intel_sdvo_connector *intel_sdvo_connector =
1303 to_intel_sdvo_connector(&connector->base);
1304 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
2f28c50b 1305 u16 active_outputs = 0;
4ac41f47
DV		 1306
1307 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1308
1309 if (active_outputs & intel_sdvo_connector->output_flag)
1310 return true;
1311 else
1312 return false;
1313}
1314
1315static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1316 enum pipe *pipe)
1317{
1318 struct drm_device *dev = encoder->base.dev;
79e53945 1319 struct drm_i915_private *dev_priv = dev->dev_private;
8aca63aa 1320 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2f28c50b 1321 u16 active_outputs = 0;
4ac41f47
DV		 1322 u32 tmp;
1323
1324 tmp = I915_READ(intel_sdvo->sdvo_reg);
7a7d1fb7 1325 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
4ac41f47 1326
7a7d1fb7 1327 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
4ac41f47
DV		 1328 return false;
1329
1330 if (HAS_PCH_CPT(dev))
1331 *pipe = PORT_TO_PIPE_CPT(tmp);
1332 else
1333 *pipe = PORT_TO_PIPE(tmp);
1334
1335 return true;
1336}
1337
045ac3b5
JB		 1338static void intel_sdvo_get_config(struct intel_encoder *encoder,
1339 struct intel_crtc_config *pipe_config)
1340{
6c49f241
DV		 1341 struct drm_device *dev = encoder->base.dev;
1342 struct drm_i915_private *dev_priv = dev->dev_private;
8aca63aa 1343 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
045ac3b5 1344 struct intel_sdvo_dtd dtd;
6c49f241 1345 int encoder_pixel_multiplier = 0;
18442d08 1346 int dotclock;
6c49f241
DV		 1347 u32 flags = 0, sdvox;
1348 u8 val;
045ac3b5
JB		 1349 bool ret;
1350
b5a9fa09
DV		 1351 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1352
045ac3b5
JB		 1353 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1354 if (!ret) {
bb760063
DV		 1355 /* Some sdvo encoders are not spec compliant and don't
1356 * implement the mandatory get_timings function. */
045ac3b5 1357 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
bb760063
DV		 1358 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1359 } else {
1360 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1361 flags |= DRM_MODE_FLAG_PHSYNC;
1362 else
1363 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1364
bb760063
DV		 1365 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1366 flags |= DRM_MODE_FLAG_PVSYNC;
1367 else
1368 flags |= DRM_MODE_FLAG_NVSYNC;
045ac3b5
JB		 1369 }
1370
045ac3b5 1371 pipe_config->adjusted_mode.flags |= flags;
045ac3b5 1372
fdafa9e2
DV		 1373 /*
1374 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1375 * the sdvo port register, on all other platforms it is part of the dpll
1376 * state. Since the general pipe state readout happens before the
1377 * encoder->get_config we so already have a valid pixel multplier on all
1378 * other platfroms.
1379 */
6c49f241 1380 if (IS_I915G(dev) || IS_I915GM(dev)) {
6c49f241
DV		 1381 pipe_config->pixel_multiplier =
1382 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1383 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1384 }
045ac3b5 1385
18442d08
VS		 1386 dotclock = pipe_config->port_clock / pipe_config->pixel_multiplier;
1387
1388 if (HAS_PCH_SPLIT(dev))
1389 ironlake_check_encoder_dotclock(pipe_config, dotclock);
1390
241bfc38 1391 pipe_config->adjusted_mode.crtc_clock = dotclock;
18442d08 1392
6c49f241 1393 /* Cross check the port pixel multiplier with the sdvo encoder state. */
53b91408
DL		 1394 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1395 &val, 1)) {
1396 switch (val) {
1397 case SDVO_CLOCK_RATE_MULT_1X:
1398 encoder_pixel_multiplier = 1;
1399 break;
1400 case SDVO_CLOCK_RATE_MULT_2X:
1401 encoder_pixel_multiplier = 2;
1402 break;
1403 case SDVO_CLOCK_RATE_MULT_4X:
1404 encoder_pixel_multiplier = 4;
1405 break;
1406 }
6c49f241 1407 }
fdafa9e2 1408
b5a9fa09
DV		 1409 if (sdvox & HDMI_COLOR_RANGE_16_235)
1410 pipe_config->limited_color_range = true;
1411
6c49f241
DV		 1412 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1413 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1414 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
045ac3b5
JB		 1415}
1416
ce22c320
DV		 1417static void intel_disable_sdvo(struct intel_encoder *encoder)
1418{
1419 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
8aca63aa 1420 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
ce22c320
DV		 1421 u32 temp;
1422
1423 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1424 if (0)
1425 intel_sdvo_set_encoder_power_state(intel_sdvo,
1426 DRM_MODE_DPMS_OFF);
1427
1428 temp = I915_READ(intel_sdvo->sdvo_reg);
1429 if ((temp & SDVO_ENABLE) != 0) {
776ca7cf
CW		 1430 /* HW workaround for IBX, we need to move the port to
1431 * transcoder A before disabling it. */
1432 if (HAS_PCH_IBX(encoder->base.dev)) {
1433 struct drm_crtc *crtc = encoder->base.crtc;
1434 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1435
1436 if (temp & SDVO_PIPE_B_SELECT) {
1437 temp &= ~SDVO_PIPE_B_SELECT;
1438 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1439 POSTING_READ(intel_sdvo->sdvo_reg);
1440
1441 /* Again we need to write this twice. */
1442 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1443 POSTING_READ(intel_sdvo->sdvo_reg);
1444
1445 /* Transcoder selection bits only update
1446 * effectively on vblank. */
1447 if (crtc)
1448 intel_wait_for_vblank(encoder->base.dev, pipe);
1449 else
1450 msleep(50);
1451 }
1452 }
1453
ce22c320
DV		 1454 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1455 }
1456}
1457
1458static void intel_enable_sdvo(struct intel_encoder *encoder)
1459{
1460 struct drm_device *dev = encoder->base.dev;
1461 struct drm_i915_private *dev_priv = dev->dev_private;
8aca63aa 1462 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
ce22c320 1463 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 1464 u32 temp;
ce22c320
DV		 1465 bool input1, input2;
1466 int i;
d0a7b6de 1467 bool success;
ce22c320
DV		 1468
1469 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf
CW		 1470 if ((temp & SDVO_ENABLE) == 0) {
1471 /* HW workaround for IBX, we need to move the port
dc0fa718
PZ		 1472 * to transcoder A before disabling it, so restore it here. */
1473 if (HAS_PCH_IBX(dev))
1474 temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
776ca7cf 1475
ce22c320 1476 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
776ca7cf 1477 }
ce22c320
DV		 1478 for (i = 0; i < 2; i++)
1479 intel_wait_for_vblank(dev, intel_crtc->pipe);
1480
d0a7b6de 1481 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
ce22c320
DV		 1482 /* Warn if the device reported failure to sync.
1483 * A lot of SDVO devices fail to notify of sync, but it's
1484 * a given it the status is a success, we succeeded.
1485 */
d0a7b6de 1486 if (success && !input1) {
ce22c320
DV		 1487 DRM_DEBUG_KMS("First %s output reported failure to "
1488 "sync\n", SDVO_NAME(intel_sdvo));
1489 }
1490
1491 if (0)
1492 intel_sdvo_set_encoder_power_state(intel_sdvo,
1493 DRM_MODE_DPMS_ON);
1494 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1495}
1496
6b1c087b 1497/* Special dpms function to support cloning between dvo/sdvo/crt. */
b2cabb0e 1498static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
79e53945 1499{
b2cabb0e
DV		 1500 struct drm_crtc *crtc;
1501 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1502
1503 /* dvo supports only 2 dpms states. */
1504 if (mode != DRM_MODE_DPMS_ON)
1505 mode = DRM_MODE_DPMS_OFF;
1506
1507 if (mode == connector->dpms)
1508 return;
1509
1510 connector->dpms = mode;
1511
1512 /* Only need to change hw state when actually enabled */
1513 crtc = intel_sdvo->base.base.crtc;
1514 if (!crtc) {
1515 intel_sdvo->base.connectors_active = false;
1516 return;
1517 }
79e53945 1518
6b1c087b
JN		 1519 /* We set active outputs manually below in case pipe dpms doesn't change
1520 * due to cloning. */
79e53945 1521 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1522 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1523 if (0)
ea5b213a 1524 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945 1525
b2cabb0e
DV		 1526 intel_sdvo->base.connectors_active = false;
1527
1528 intel_crtc_update_dpms(crtc);
79e53945 1529 } else {
b2cabb0e
DV		 1530 intel_sdvo->base.connectors_active = true;
1531
1532 intel_crtc_update_dpms(crtc);
79e53945
JB		 1533
1534 if (0)
ea5b213a
CW		 1535 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1536 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945 1537 }
0a91ca29 1538
b980514c 1539 intel_modeset_check_state(connector->dev);
79e53945
JB		 1540}
1541
c19de8eb
DL		 1542static enum drm_mode_status
1543intel_sdvo_mode_valid(struct drm_connector *connector,
1544 struct drm_display_mode *mode)
79e53945 1545{
df0e9248 1546 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1547
1548 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1549 return MODE_NO_DBLESCAN;
1550
ea5b213a 1551 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1552 return MODE_CLOCK_LOW;
1553
ea5b213a 1554 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1555 return MODE_CLOCK_HIGH;
1556
8545423a 1557 if (intel_sdvo->is_lvds) {
ea5b213a 1558 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1559 return MODE_PANEL;
1560
ea5b213a 1561 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1562 return MODE_PANEL;
1563 }
1564
79e53945
JB		 1565 return MODE_OK;
1566}
1567
ea5b213a 1568static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1569{
1a3665c8 1570 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1571 if (!intel_sdvo_get_value(intel_sdvo,
1572 SDVO_CMD_GET_DEVICE_CAPS,
1573 caps, sizeof(*caps)))
1574 return false;
1575
1576 DRM_DEBUG_KMS("SDVO capabilities:\n"
1577 " vendor_id: %d\n"
1578 " device_id: %d\n"
1579 " device_rev_id: %d\n"
1580 " sdvo_version_major: %d\n"
1581 " sdvo_version_minor: %d\n"
1582 " sdvo_inputs_mask: %d\n"
1583 " smooth_scaling: %d\n"
1584 " sharp_scaling: %d\n"
1585 " up_scaling: %d\n"
1586 " down_scaling: %d\n"
1587 " stall_support: %d\n"
1588 " output_flags: %d\n",
1589 caps->vendor_id,
1590 caps->device_id,
1591 caps->device_rev_id,
1592 caps->sdvo_version_major,
1593 caps->sdvo_version_minor,
1594 caps->sdvo_inputs_mask,
1595 caps->smooth_scaling,
1596 caps->sharp_scaling,
1597 caps->up_scaling,
1598 caps->down_scaling,
1599 caps->stall_support,
1600 caps->output_flags);
1601
1602 return true;
79e53945
JB		 1603}
1604
5fa7ac9c 1605static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1606{
768b107e 1607 struct drm_device *dev = intel_sdvo->base.base.dev;
5fa7ac9c 1608 uint16_t hotplug;
79e53945 1609
768b107e
DV		 1610 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1611 * on the line. */
1612 if (IS_I945G(dev) || IS_I945GM(dev))
5fa7ac9c 1613 return 0;
768b107e 1614
5fa7ac9c
JN		 1615 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1616 &hotplug, sizeof(hotplug)))
1617 return 0;
768b107e 1618
5fa7ac9c 1619 return hotplug;
79e53945
JB		 1620}
1621
cc68c81a 1622static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1623{
8aca63aa 1624 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
79e53945 1625
5fa7ac9c
JN		 1626 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1627 &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1628}
1629
fb7a46f3 1630static bool
ea5b213a 1631intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1632{
bc65212c 1633 /* Is there more than one type of output? */
2294488d 1634 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1635}
1636
f899fc64 1637static struct edid *
e957d772 1638intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1639{
e957d772
CW		 1640 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1641 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1642}
1643
ff482d83
CW		 1644/* Mac mini hack -- use the same DDC as the analog connector */
1645static struct edid *
1646intel_sdvo_get_analog_edid(struct drm_connector *connector)
1647{
f899fc64 1648 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1649
0c1dab89 1650 return drm_get_edid(connector,
3bd7d909 1651 intel_gmbus_get_adapter(dev_priv,
41aa3448 1652 dev_priv->vbt.crt_ddc_pin));
ff482d83
CW		 1653}
1654
c43b5634 1655static enum drm_connector_status
8bf38485 1656intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1657{
df0e9248 1658 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1659 enum drm_connector_status status;
1660 struct edid *edid;
9dff6af8 1661
e957d772 1662 edid = intel_sdvo_get_edid(connector);
57cdaf90 1663
ea5b213a 1664 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1665 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1666
7c3f0a27
ZY		 1667 /*
1668 * Don't use the 1 as the argument of DDC bus switch to get
1669 * the EDID. It is used for SDVO SPD ROM.
1670 */
9d1a903d 1671 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1672 intel_sdvo->ddc_bus = ddc;
1673 edid = intel_sdvo_get_edid(connector);
1674 if (edid)
7c3f0a27 1675 break;
7c3f0a27 1676 }
e957d772
CW		 1677 /*
1678 * If we found the EDID on the other bus,
1679 * assume that is the correct DDC bus.
1680 */
1681 if (edid == NULL)
1682 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1683 }
9d1a903d
CW		 1684
1685 /*
1686 * When there is no edid and no monitor is connected with VGA
1687 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1688 */
ff482d83
CW		 1689 if (edid == NULL)
1690 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1691
2f551c84 1692 status = connector_status_unknown;
9dff6af8 1693 if (edid != NULL) {
149c36a3 1694 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1695 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1696 status = connector_status_connected;
da79de97
CW		 1697 if (intel_sdvo->is_hdmi) {
1698 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1699 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
abedc077
VS		 1700 intel_sdvo->rgb_quant_range_selectable =
1701 drm_rgb_quant_range_selectable(edid);
da79de97 1702 }
13946743
CW		 1703 } else
1704 status = connector_status_disconnected;
9d1a903d
CW		 1705 kfree(edid);
1706 }
7f36e7ed
CW		 1707
1708 if (status == connector_status_connected) {
1709 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1710 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1711 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1712 }
1713
2b8d33f7 1714 return status;
9dff6af8
ML		 1715}
1716
52220085
CW		 1717static bool
1718intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1719 struct edid *edid)
1720{
1721 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1722 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1723
1724 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1725 connector_is_digital, monitor_is_digital);
1726 return connector_is_digital == monitor_is_digital;
1727}
1728
7b334fcb 1729static enum drm_connector_status
930a9e28 1730intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1731{
fb7a46f3 1732 uint16_t response;
df0e9248 1733 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1734 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1735 enum drm_connector_status ret;
79e53945 1736
164c8598
CW		 1737 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1738 connector->base.id, drm_get_connector_name(connector));
1739
fc37381c
CW		 1740 if (!intel_sdvo_get_value(intel_sdvo,
1741 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1742 &response, 2))
32aad86f 1743 return connector_status_unknown;
79e53945 1744
e957d772
CW		 1745 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1746 response & 0xff, response >> 8,
1747 intel_sdvo_connector->output_flag);
e2f0ba97 1748
fb7a46f3 1749 if (response == 0)
79e53945 1750 return connector_status_disconnected;
fb7a46f3 1751
ea5b213a 1752 intel_sdvo->attached_output = response;
14571b4c 1753
97aaf910
CW		 1754 intel_sdvo->has_hdmi_monitor = false;
1755 intel_sdvo->has_hdmi_audio = false;
abedc077 1756 intel_sdvo->rgb_quant_range_selectable = false;
97aaf910 1757
615fb93f 1758 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1759 ret = connector_status_disconnected;
13946743 1760 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1761 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1762 else {
1763 struct edid *edid;
1764
1765 /* if we have an edid check it matches the connection */
1766 edid = intel_sdvo_get_edid(connector);
1767 if (edid == NULL)
1768 edid = intel_sdvo_get_analog_edid(connector);
1769 if (edid != NULL) {
52220085
CW		 1770 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1771 edid))
13946743 1772 ret = connector_status_connected;
52220085
CW		 1773 else
1774 ret = connector_status_disconnected;
1775
13946743
CW		 1776 kfree(edid);
1777 } else
1778 ret = connector_status_connected;
1779 }
14571b4c
ZW		 1780
1781 /* May update encoder flag for like clock for SDVO TV, etc.*/
1782 if (ret == connector_status_connected) {
ea5b213a
CW		 1783 intel_sdvo->is_tv = false;
1784 intel_sdvo->is_lvds = false;
14571b4c 1785
09ede541 1786 if (response & SDVO_TV_MASK)
ea5b213a 1787 intel_sdvo->is_tv = true;
14571b4c 1788 if (response & SDVO_LVDS_MASK)
8545423a 1789 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1790 }
14571b4c
ZW		 1791
1792 return ret;
79e53945
JB		 1793}
1794
e2f0ba97 1795static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1796{
ff482d83 1797 struct edid *edid;
79e53945 1798
46a3f4a3
CW		 1799 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1800 connector->base.id, drm_get_connector_name(connector));
1801
79e53945 1802 /* set the bus switch and get the modes */
e957d772 1803 edid = intel_sdvo_get_edid(connector);
79e53945 1804
57cdaf90
KP		 1805 /*
1806 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1807 * link between analog and digital outputs. So, if the regular SDVO
1808 * DDC fails, check to see if the analog output is disconnected, in
1809 * which case we'll look there for the digital DDC data.
e2f0ba97 1810 */
f899fc64
CW		 1811 if (edid == NULL)
1812 edid = intel_sdvo_get_analog_edid(connector);
1813
ff482d83 1814 if (edid != NULL) {
52220085
CW		 1815 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1816 edid)) {
0c1dab89
CW		 1817 drm_mode_connector_update_edid_property(connector, edid);
1818 drm_add_edid_modes(connector, edid);
1819 }
13946743 1820
ff482d83 1821 kfree(edid);
e2f0ba97 1822 }
e2f0ba97
JB		 1823}
1824
1825/*
1826 * Set of SDVO TV modes.
1827 * Note! This is in reply order (see loop in get_tv_modes).
1828 * XXX: all 60Hz refresh?
1829 */
b1f559ec 1830static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1831 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1832 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1833 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1834 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1835 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1836 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1837 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1838 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1839 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1840 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1841 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1842 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1843 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1844 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1845 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1846 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1847 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1848 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1849 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1850 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1851 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1852 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1853 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1854 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1855 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1856 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1857 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1858 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1859 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1860 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1861 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1862 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1863 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1864 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1865 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1866 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1867 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1868 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1869 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1870 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1871 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1872 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1873 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1874 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1875 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1876 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1877 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1878 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1879 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1880 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1881 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1882 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1883 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1884 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1885 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1886 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1887 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1888};
1889
1890static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1891{
df0e9248 1892 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1893 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1894 uint32_t reply = 0, format_map = 0;
1895 int i;
e2f0ba97 1896
46a3f4a3
CW		 1897 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1898 connector->base.id, drm_get_connector_name(connector));
1899
e2f0ba97
JB		 1900 /* Read the list of supported input resolutions for the selected TV
1901 * format.
1902 */
40039750 1903 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1904 memcpy(&tv_res, &format_map,
32aad86f 1905 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1906
32aad86f
CW		 1907 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1908 return;
ce6feabd 1909
32aad86f 1910 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1911 if (!intel_sdvo_write_cmd(intel_sdvo,
1912 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1913 &tv_res, sizeof(tv_res)))
1914 return;
1915 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1916 return;
1917
1918 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1919 if (reply & (1 << i)) {
1920 struct drm_display_mode *nmode;
1921 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1922 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1923 if (nmode)
1924 drm_mode_probed_add(connector, nmode);
1925 }
e2f0ba97
JB		 1926}
1927
7086c87f
ML		 1928static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1929{
df0e9248 1930 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1931 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1932 struct drm_display_mode *newmode;
7086c87f 1933
46a3f4a3
CW		 1934 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1935 connector->base.id, drm_get_connector_name(connector));
1936
7086c87f 1937 /*
c3456fb3 1938 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
4300a0f8 1939 * SDVO->LVDS transcoders can't cope with the EDID mode.
7086c87f 1940 */
41aa3448 1941 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
7086c87f 1942 newmode = drm_mode_duplicate(connector->dev,
41aa3448 1943 dev_priv->vbt.sdvo_lvds_vbt_mode);
7086c87f
ML		 1944 if (newmode != NULL) {
1945 /* Guarantee the mode is preferred */
1946 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1947 DRM_MODE_TYPE_DRIVER);
1948 drm_mode_probed_add(connector, newmode);
1949 }
1950 }
12682a97 1951
4300a0f8
DA		 1952 /*
1953 * Attempt to get the mode list from DDC.
1954 * Assume that the preferred modes are
1955 * arranged in priority order.
1956 */
1957 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
1958
12682a97 1959 list_for_each_entry(newmode, &connector->probed_modes, head) {
1960 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1961 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1962 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1963
8545423a 1964 intel_sdvo->is_lvds = true;
12682a97 1965 break;
1966 }
1967 }
7086c87f
ML		 1968}
1969
e2f0ba97
JB		 1970static int intel_sdvo_get_modes(struct drm_connector *connector)
1971{
615fb93f 1972 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1973
615fb93f 1974 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1975 intel_sdvo_get_tv_modes(connector);
615fb93f 1976 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1977 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1978 else
1979 intel_sdvo_get_ddc_modes(connector);
1980
32aad86f 1981 return !list_empty(&connector->probed_modes);
79e53945
JB		 1982}
1983
fcc8d672
CW		 1984static void
1985intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1986{
615fb93f 1987 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1988 struct drm_device *dev = connector->dev;
1989
c5521706
CW		 1990 if (intel_sdvo_connector->left)
1991 drm_property_destroy(dev, intel_sdvo_connector->left);
1992 if (intel_sdvo_connector->right)
1993 drm_property_destroy(dev, intel_sdvo_connector->right);
1994 if (intel_sdvo_connector->top)
1995 drm_property_destroy(dev, intel_sdvo_connector->top);
1996 if (intel_sdvo_connector->bottom)
1997 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1998 if (intel_sdvo_connector->hpos)
1999 drm_property_destroy(dev, intel_sdvo_connector->hpos);
2000 if (intel_sdvo_connector->vpos)
2001 drm_property_destroy(dev, intel_sdvo_connector->vpos);
2002 if (intel_sdvo_connector->saturation)
2003 drm_property_destroy(dev, intel_sdvo_connector->saturation);
2004 if (intel_sdvo_connector->contrast)
2005 drm_property_destroy(dev, intel_sdvo_connector->contrast);
2006 if (intel_sdvo_connector->hue)
2007 drm_property_destroy(dev, intel_sdvo_connector->hue);
2008 if (intel_sdvo_connector->sharpness)
2009 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
2010 if (intel_sdvo_connector->flicker_filter)
2011 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
2012 if (intel_sdvo_connector->flicker_filter_2d)
2013 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
2014 if (intel_sdvo_connector->flicker_filter_adaptive)
2015 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
2016 if (intel_sdvo_connector->tv_luma_filter)
2017 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
2018 if (intel_sdvo_connector->tv_chroma_filter)
2019 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 2020 if (intel_sdvo_connector->dot_crawl)
2021 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 2022 if (intel_sdvo_connector->brightness)
2023 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 2024}
2025
79e53945
JB		 2026static void intel_sdvo_destroy(struct drm_connector *connector)
2027{
615fb93f 2028 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 2029
c5521706 2030 if (intel_sdvo_connector->tv_format)
ce6feabd 2031 drm_property_destroy(connector->dev,
c5521706 2032 intel_sdvo_connector->tv_format);
b9219c5e 2033
d2a82a6f 2034 intel_sdvo_destroy_enhance_property(connector);
79e53945 2035 drm_connector_cleanup(connector);
4b745b1e 2036 kfree(intel_sdvo_connector);
79e53945
JB		 2037}
2038
1aad7ac0
CW		 2039static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
2040{
2041 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
2042 struct edid *edid;
2043 bool has_audio = false;
2044
2045 if (!intel_sdvo->is_hdmi)
2046 return false;
2047
2048 edid = intel_sdvo_get_edid(connector);
2049 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
2050 has_audio = drm_detect_monitor_audio(edid);
38ab8a20 2051 kfree(edid);
1aad7ac0
CW		 2052
2053 return has_audio;
2054}
2055
ce6feabd
ZY		 2056static int
2057intel_sdvo_set_property(struct drm_connector *connector,
2058 struct drm_property *property,
2059 uint64_t val)
2060{
df0e9248 2061 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 2062 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 2063 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 2064 uint16_t temp_value;
32aad86f
CW		 2065 uint8_t cmd;
2066 int ret;
ce6feabd 2067
662595df 2068 ret = drm_object_property_set_value(&connector->base, property, val);
32aad86f
CW		 2069 if (ret)
2070 return ret;
ce6feabd 2071
3f43c48d 2072 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2073 int i = val;
2074 bool has_audio;
2075
2076 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 2077 return 0;
2078
1aad7ac0 2079 intel_sdvo_connector->force_audio = i;
7f36e7ed 2080
c3e5f67b 2081 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2082 has_audio = intel_sdvo_detect_hdmi_audio(connector);
2083 else
c3e5f67b 2084 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 2085
1aad7ac0 2086 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 2087 return 0;
7f36e7ed 2088
1aad7ac0 2089 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 2090 goto done;
2091 }
2092
e953fd7b 2093 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 2094 bool old_auto = intel_sdvo->color_range_auto;
2095 uint32_t old_range = intel_sdvo->color_range;
2096
55bc60db
VS		 2097 switch (val) {
2098 case INTEL_BROADCAST_RGB_AUTO:
2099 intel_sdvo->color_range_auto = true;
2100 break;
2101 case INTEL_BROADCAST_RGB_FULL:
2102 intel_sdvo->color_range_auto = false;
2103 intel_sdvo->color_range = 0;
2104 break;
2105 case INTEL_BROADCAST_RGB_LIMITED:
2106 intel_sdvo->color_range_auto = false;
4f3a8bc7
PZ		 2107 /* FIXME: this bit is only valid when using TMDS
2108 * encoding and 8 bit per color mode. */
2109 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 2110 break;
2111 default:
2112 return -EINVAL;
2113 }
ae4edb80
DV		 2114
2115 if (old_auto == intel_sdvo->color_range_auto &&
2116 old_range == intel_sdvo->color_range)
2117 return 0;
2118
7f36e7ed
CW		 2119 goto done;
2120 }
2121
c5521706
CW		 2122#define CHECK_PROPERTY(name, NAME) \
2123 if (intel_sdvo_connector->name == property) { \
2124 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
2125 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
2126 cmd = SDVO_CMD_SET_##NAME; \
2127 intel_sdvo_connector->cur_##name = temp_value; \
2128 goto set_value; \
2129 }
2130
2131 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 2132 if (val >= TV_FORMAT_NUM)
2133 return -EINVAL;
2134
40039750 2135 if (intel_sdvo->tv_format_index ==
615fb93f 2136 intel_sdvo_connector->tv_format_supported[val])
32aad86f 2137 return 0;
ce6feabd 2138
40039750 2139 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 2140 goto done;
32aad86f 2141 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 2142 temp_value = val;
c5521706 2143 if (intel_sdvo_connector->left == property) {
662595df 2144 drm_object_property_set_value(&connector->base,
c5521706 2145 intel_sdvo_connector->right, val);
615fb93f 2146 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 2147 return 0;
b9219c5e 2148
615fb93f
CW		 2149 intel_sdvo_connector->left_margin = temp_value;
2150 intel_sdvo_connector->right_margin = temp_value;
2151 temp_value = intel_sdvo_connector->max_hscan -
c5521706 2152 intel_sdvo_connector->left_margin;
b9219c5e 2153 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2154 goto set_value;
2155 } else if (intel_sdvo_connector->right == property) {
662595df 2156 drm_object_property_set_value(&connector->base,
c5521706 2157 intel_sdvo_connector->left, val);
615fb93f 2158 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 2159 return 0;
b9219c5e 2160
615fb93f
CW		 2161 intel_sdvo_connector->left_margin = temp_value;
2162 intel_sdvo_connector->right_margin = temp_value;
2163 temp_value = intel_sdvo_connector->max_hscan -
2164 intel_sdvo_connector->left_margin;
b9219c5e 2165 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2166 goto set_value;
2167 } else if (intel_sdvo_connector->top == property) {
662595df 2168 drm_object_property_set_value(&connector->base,
c5521706 2169 intel_sdvo_connector->bottom, val);
615fb93f 2170 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 2171 return 0;
b9219c5e 2172
615fb93f
CW		 2173 intel_sdvo_connector->top_margin = temp_value;
2174 intel_sdvo_connector->bottom_margin = temp_value;
2175 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2176 intel_sdvo_connector->top_margin;
b9219c5e 2177 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2178 goto set_value;
2179 } else if (intel_sdvo_connector->bottom == property) {
662595df 2180 drm_object_property_set_value(&connector->base,
c5521706 2181 intel_sdvo_connector->top, val);
615fb93f 2182 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 2183 return 0;
2184
615fb93f
CW		 2185 intel_sdvo_connector->top_margin = temp_value;
2186 intel_sdvo_connector->bottom_margin = temp_value;
2187 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2188 intel_sdvo_connector->top_margin;
b9219c5e 2189 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2190 goto set_value;
2191 }
2192 CHECK_PROPERTY(hpos, HPOS)
2193 CHECK_PROPERTY(vpos, VPOS)
2194 CHECK_PROPERTY(saturation, SATURATION)
2195 CHECK_PROPERTY(contrast, CONTRAST)
2196 CHECK_PROPERTY(hue, HUE)
2197 CHECK_PROPERTY(brightness, BRIGHTNESS)
2198 CHECK_PROPERTY(sharpness, SHARPNESS)
2199 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
2200 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
2201 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
2202 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
2203 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 2204 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 2205 }
b9219c5e 2206
c5521706 2207 return -EINVAL; /* unknown property */
b9219c5e 2208
c5521706
CW		 2209set_value:
2210 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
2211 return -EIO;
b9219c5e 2212
b9219c5e 2213
c5521706 2214done:
c0c36b94
CW		 2215 if (intel_sdvo->base.base.crtc)
2216 intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
c5521706 2217
32aad86f 2218 return 0;
c5521706 2219#undef CHECK_PROPERTY
ce6feabd
ZY		 2220}
2221
79e53945 2222static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
b2cabb0e 2223 .dpms = intel_sdvo_dpms,
79e53945
JB		 2224 .detect = intel_sdvo_detect,
2225 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 2226 .set_property = intel_sdvo_set_property,
79e53945
JB		 2227 .destroy = intel_sdvo_destroy,
2228};
2229
2230static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2231 .get_modes = intel_sdvo_get_modes,
2232 .mode_valid = intel_sdvo_mode_valid,
df0e9248 2233 .best_encoder = intel_best_encoder,
79e53945
JB		 2234};
2235
b358d0a6 2236static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2237{
8aca63aa 2238 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
d2a82a6f 2239
ea5b213a 2240 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2241 drm_mode_destroy(encoder->dev,
ea5b213a 2242 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2243
e957d772 2244 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2245 intel_encoder_destroy(encoder);
79e53945
JB		 2246}
2247
2248static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2249 .destroy = intel_sdvo_enc_destroy,
2250};
2251
b66d8424
CW		 2252static void
2253intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2254{
2255 uint16_t mask = 0;
2256 unsigned int num_bits;
2257
2258 /* Make a mask of outputs less than or equal to our own priority in the
2259 * list.
2260 */
2261 switch (sdvo->controlled_output) {
2262 case SDVO_OUTPUT_LVDS1:
2263 mask |= SDVO_OUTPUT_LVDS1;
2264 case SDVO_OUTPUT_LVDS0:
2265 mask |= SDVO_OUTPUT_LVDS0;
2266 case SDVO_OUTPUT_TMDS1:
2267 mask |= SDVO_OUTPUT_TMDS1;
2268 case SDVO_OUTPUT_TMDS0:
2269 mask |= SDVO_OUTPUT_TMDS0;
2270 case SDVO_OUTPUT_RGB1:
2271 mask |= SDVO_OUTPUT_RGB1;
2272 case SDVO_OUTPUT_RGB0:
2273 mask |= SDVO_OUTPUT_RGB0;
2274 break;
2275 }
2276
2277 /* Count bits to find what number we are in the priority list. */
2278 mask &= sdvo->caps.output_flags;
2279 num_bits = hweight16(mask);
2280 /* If more than 3 outputs, default to DDC bus 3 for now. */
2281 if (num_bits > 3)
2282 num_bits = 3;
2283
2284 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2285 sdvo->ddc_bus = 1 << num_bits;
2286}
79e53945 2287
e2f0ba97
JB		 2288/**
2289 * Choose the appropriate DDC bus for control bus switch command for this
2290 * SDVO output based on the controlled output.
2291 *
2292 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2293 * outputs, then LVDS outputs.
2294 */
2295static void
b1083333 2296intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 2297 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 2298{
b1083333 2299 struct sdvo_device_mapping *mapping;
e2f0ba97 2300
eef4eacb 2301 if (sdvo->is_sdvob)
b1083333
AJ		 2302 mapping = &(dev_priv->sdvo_mappings[0]);
2303 else
2304 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 2305
b66d8424
CW		 2306 if (mapping->initialized)
2307 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2308 else
2309 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2310}
2311
e957d772
CW		 2312static void
2313intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2314 struct intel_sdvo *sdvo, u32 reg)
2315{
2316 struct sdvo_device_mapping *mapping;
46eb3036 2317 u8 pin;
e957d772 2318
eef4eacb 2319 if (sdvo->is_sdvob)
e957d772
CW		 2320 mapping = &dev_priv->sdvo_mappings[0];
2321 else
2322 mapping = &dev_priv->sdvo_mappings[1];
2323
6cb1612a 2324 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
e957d772 2325 pin = mapping->i2c_pin;
6cb1612a
JN		 2326 else
2327 pin = GMBUS_PORT_DPB;
e957d772 2328
6cb1612a
JN		 2329 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2330
2331 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2332 * our code totally fails once we start using gmbus. Hence fall back to
2333 * bit banging for now. */
2334 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2335}
2336
fbfcc4f3
JN		 2337/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2338static void
2339intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2340{
2341 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2342}
2343
e2f0ba97 2344static bool
e27d8538 2345intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2346{
97aaf910 2347 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2348}
2349
714605e4 2350static u8
eef4eacb 2351intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 2352{
2353 struct drm_i915_private *dev_priv = dev->dev_private;
2354 struct sdvo_device_mapping *my_mapping, *other_mapping;
2355
eef4eacb 2356 if (sdvo->is_sdvob) {
714605e4 2357 my_mapping = &dev_priv->sdvo_mappings[0];
2358 other_mapping = &dev_priv->sdvo_mappings[1];
2359 } else {
2360 my_mapping = &dev_priv->sdvo_mappings[1];
2361 other_mapping = &dev_priv->sdvo_mappings[0];
2362 }
2363
2364 /* If the BIOS described our SDVO device, take advantage of it. */
2365 if (my_mapping->slave_addr)
2366 return my_mapping->slave_addr;
2367
2368 /* If the BIOS only described a different SDVO device, use the
2369 * address that it isn't using.
2370 */
2371 if (other_mapping->slave_addr) {
2372 if (other_mapping->slave_addr == 0x70)
2373 return 0x72;
2374 else
2375 return 0x70;
2376 }
2377
2378 /* No SDVO device info is found for another DVO port,
2379 * so use mapping assumption we had before BIOS parsing.
2380 */
eef4eacb 2381 if (sdvo->is_sdvob)
714605e4 2382 return 0x70;
2383 else
2384 return 0x72;
2385}
2386
931c1c26
ID		 2387static void
2388intel_sdvo_connector_unregister(struct intel_connector *intel_connector)
2389{
2390 struct drm_connector *drm_connector;
2391 struct intel_sdvo *sdvo_encoder;
2392
2393 drm_connector = &intel_connector->base;
2394 sdvo_encoder = intel_attached_sdvo(&intel_connector->base);
2395
2396 sysfs_remove_link(&drm_connector->kdev->kobj,
2397 sdvo_encoder->ddc.dev.kobj.name);
2398 intel_connector_unregister(intel_connector);
2399}
2400
c393454d 2401static int
df0e9248
CW		 2402intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2403 struct intel_sdvo *encoder)
14571b4c 2404{
c393454d
ID		 2405 struct drm_connector *drm_connector;
2406 int ret;
2407
2408 drm_connector = &connector->base.base;
2409 ret = drm_connector_init(encoder->base.base.dev,
2410 drm_connector,
df0e9248
CW		 2411 &intel_sdvo_connector_funcs,
2412 connector->base.base.connector_type);
c393454d
ID		 2413 if (ret < 0)
2414 return ret;
6070a4a9 2415
c393454d 2416 drm_connector_helper_add(drm_connector,
df0e9248 2417 &intel_sdvo_connector_helper_funcs);
14571b4c 2418
8f4839e2 2419 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2420 connector->base.base.doublescan_allowed = 0;
2421 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2422 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
931c1c26 2423 connector->base.unregister = intel_sdvo_connector_unregister;
14571b4c 2424
df0e9248 2425 intel_connector_attach_encoder(&connector->base, &encoder->base);
c393454d
ID		 2426 ret = drm_sysfs_connector_add(drm_connector);
2427 if (ret < 0)
2428 goto err1;
2429
4d43e9bd
EE		 2430 ret = sysfs_create_link(&drm_connector->kdev->kobj,
2431 &encoder->ddc.dev.kobj,
931c1c26
ID		 2432 encoder->ddc.dev.kobj.name);
2433 if (ret < 0)
2434 goto err2;
2435
c393454d
ID		 2436 return 0;
2437
931c1c26
ID		 2438err2:
2439 drm_sysfs_connector_remove(drm_connector);
c393454d
ID		 2440err1:
2441 drm_connector_cleanup(drm_connector);
2442
2443 return ret;
14571b4c 2444}
6070a4a9 2445
7f36e7ed 2446static void
55bc60db
VS		 2447intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2448 struct intel_sdvo_connector *connector)
7f36e7ed
CW		 2449{
2450 struct drm_device *dev = connector->base.base.dev;
2451
3f43c48d 2452 intel_attach_force_audio_property(&connector->base.base);
55bc60db 2453 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
e953fd7b 2454 intel_attach_broadcast_rgb_property(&connector->base.base);
55bc60db
VS		 2455 intel_sdvo->color_range_auto = true;
2456 }
7f36e7ed
CW		 2457}
2458
fb7a46f3 2459static bool
ea5b213a 2460intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2461{
4ef69c7a 2462 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2463 struct drm_connector *connector;
cc68c81a 2464 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2465 struct intel_connector *intel_connector;
615fb93f 2466 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2467
46a3f4a3
CW		 2468 DRM_DEBUG_KMS("initialising DVI device %d\n", device);
2469
b14c5679 2470 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
615fb93f 2471 if (!intel_sdvo_connector)
14571b4c
ZW		 2472 return false;
2473
14571b4c 2474 if (device == 0) {
ea5b213a 2475 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2476 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2477 } else if (device == 1) {
ea5b213a 2478 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2479 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2480 }
2481
615fb93f 2482 intel_connector = &intel_sdvo_connector->base;
14571b4c 2483 connector = &intel_connector->base;
5fa7ac9c
JN		 2484 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2485 intel_sdvo_connector->output_flag) {
5fa7ac9c 2486 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
cc68c81a
SF		 2487 /* Some SDVO devices have one-shot hotplug interrupts.
2488 * Ensure that they get re-enabled when an interrupt happens.
2489 */
2490 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2491 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2492 } else {
821450c6 2493 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2494 }
14571b4c
ZW		 2495 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2496 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2497
e27d8538 2498 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2499 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2500 intel_sdvo->is_hdmi = true;
14571b4c 2501 }
14571b4c 2502
c393454d
ID		 2503 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2504 kfree(intel_sdvo_connector);
2505 return false;
2506 }
2507
f797d221 2508 if (intel_sdvo->is_hdmi)
55bc60db 2509 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
14571b4c
ZW		 2510
2511 return true;
2512}
2513
2514static bool
ea5b213a 2515intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2516{
4ef69c7a
CW		 2517 struct drm_encoder *encoder = &intel_sdvo->base.base;
2518 struct drm_connector *connector;
2519 struct intel_connector *intel_connector;
2520 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2521
46a3f4a3
CW		 2522 DRM_DEBUG_KMS("initialising TV type %d\n", type);
2523
b14c5679 2524 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
615fb93f
CW		 2525 if (!intel_sdvo_connector)
2526 return false;
14571b4c 2527
615fb93f 2528 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2529 connector = &intel_connector->base;
2530 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2531 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2532
4ef69c7a
CW		 2533 intel_sdvo->controlled_output |= type;
2534 intel_sdvo_connector->output_flag = type;
14571b4c 2535
4ef69c7a 2536 intel_sdvo->is_tv = true;
14571b4c 2537
c393454d
ID		 2538 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2539 kfree(intel_sdvo_connector);
2540 return false;
2541 }
14571b4c 2542
4ef69c7a 2543 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2544 goto err;
14571b4c 2545
4ef69c7a 2546 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2547 goto err;
14571b4c 2548
4ef69c7a 2549 return true;
32aad86f
CW		 2550
2551err:
d9255d57 2552 drm_sysfs_connector_remove(connector);
123d5c01 2553 intel_sdvo_destroy(connector);
32aad86f 2554 return false;
14571b4c
ZW		 2555}
2556
2557static bool
ea5b213a 2558intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2559{
4ef69c7a
CW		 2560 struct drm_encoder *encoder = &intel_sdvo->base.base;
2561 struct drm_connector *connector;
2562 struct intel_connector *intel_connector;
2563 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2564
46a3f4a3
CW		 2565 DRM_DEBUG_KMS("initialising analog device %d\n", device);
2566
b14c5679 2567 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
615fb93f
CW		 2568 if (!intel_sdvo_connector)
2569 return false;
14571b4c 2570
615fb93f 2571 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2572 connector = &intel_connector->base;
821450c6 2573 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2574 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2575 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2576
2577 if (device == 0) {
2578 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2579 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2580 } else if (device == 1) {
2581 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2582 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2583 }
2584
c393454d
ID		 2585 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2586 kfree(intel_sdvo_connector);
2587 return false;
2588 }
2589
4ef69c7a 2590 return true;
14571b4c
ZW		 2591}
2592
2593static bool
ea5b213a 2594intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2595{
4ef69c7a
CW		 2596 struct drm_encoder *encoder = &intel_sdvo->base.base;
2597 struct drm_connector *connector;
2598 struct intel_connector *intel_connector;
2599 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2600
46a3f4a3
CW		 2601 DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
2602
b14c5679 2603 intel_sdvo_connector = kzalloc(sizeof(*intel_sdvo_connector), GFP_KERNEL);
615fb93f
CW		 2604 if (!intel_sdvo_connector)
2605 return false;
14571b4c 2606
615fb93f
CW		 2607 intel_connector = &intel_sdvo_connector->base;
2608 connector = &intel_connector->base;
4ef69c7a
CW		 2609 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2610 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2611
2612 if (device == 0) {
2613 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2614 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2615 } else if (device == 1) {
2616 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2617 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2618 }
2619
c393454d
ID		 2620 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2621 kfree(intel_sdvo_connector);
2622 return false;
2623 }
2624
4ef69c7a 2625 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2626 goto err;
2627
2628 return true;
2629
2630err:
d9255d57 2631 drm_sysfs_connector_remove(connector);
123d5c01 2632 intel_sdvo_destroy(connector);
32aad86f 2633 return false;
14571b4c
ZW		 2634}
2635
2636static bool
ea5b213a 2637intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2638{
ea5b213a 2639 intel_sdvo->is_tv = false;
ea5b213a 2640 intel_sdvo->is_lvds = false;
fb7a46f3 2641
14571b4c 2642 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2643
14571b4c 2644 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2645 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2646 return false;
2647
2648 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2649 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2650 return false;
2651
2652 /* TV has no XXX1 function block */
a1f4b7ff 2653 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2654 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2655 return false;
2656
2657 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2658 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2659 return false;
fb7a46f3 2660
a0b1c7a5
CW		 2661 if (flags & SDVO_OUTPUT_YPRPB0)
2662 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2663 return false;
2664
14571b4c 2665 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2666 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2667 return false;
2668
2669 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2670 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2671 return false;
2672
2673 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2674 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2675 return false;
2676
2677 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2678 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2679 return false;
fb7a46f3 2680
14571b4c 2681 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2682 unsigned char bytes[2];
2683
ea5b213a
CW		 2684 intel_sdvo->controlled_output = 0;
2685 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2686 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2687 SDVO_NAME(intel_sdvo),
51c8b407 2688 bytes[0], bytes[1]);
14571b4c 2689 return false;
fb7a46f3 2690 }
27f8227b 2691 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2692
14571b4c 2693 return true;
fb7a46f3 2694}
2695
d0ddfbd3
JN		 2696static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2697{
2698 struct drm_device *dev = intel_sdvo->base.base.dev;
2699 struct drm_connector *connector, *tmp;
2700
2701 list_for_each_entry_safe(connector, tmp,
2702 &dev->mode_config.connector_list, head) {
d9255d57
PZ		 2703 if (intel_attached_encoder(connector) == &intel_sdvo->base) {
2704 drm_sysfs_connector_remove(connector);
d0ddfbd3 2705 intel_sdvo_destroy(connector);
d9255d57 2706 }
d0ddfbd3
JN		 2707 }
2708}
2709
32aad86f
CW		 2710static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2711 struct intel_sdvo_connector *intel_sdvo_connector,
2712 int type)
ce6feabd 2713{
4ef69c7a 2714 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2715 struct intel_sdvo_tv_format format;
2716 uint32_t format_map, i;
ce6feabd 2717
32aad86f
CW		 2718 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2719 return false;
ce6feabd 2720
1a3665c8 2721 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2722 if (!intel_sdvo_get_value(intel_sdvo,
2723 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2724 &format, sizeof(format)))
2725 return false;
ce6feabd 2726
32aad86f 2727 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2728
2729 if (format_map == 0)
32aad86f 2730 return false;
ce6feabd 2731
615fb93f 2732 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2733 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2734 if (format_map & (1 << i))
2735 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2736
2737
c5521706 2738 intel_sdvo_connector->tv_format =
32aad86f
CW		 2739 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2740 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2741 if (!intel_sdvo_connector->tv_format)
fcc8d672 2742 return false;
ce6feabd 2743
615fb93f 2744 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2745 drm_property_add_enum(
c5521706 2746 intel_sdvo_connector->tv_format, i,
40039750 2747 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2748
40039750 2749 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
662595df 2750 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
c5521706 2751 intel_sdvo_connector->tv_format, 0);
32aad86f 2752 return true;
ce6feabd
ZY		 2753
2754}
2755
c5521706
CW		 2756#define ENHANCEMENT(name, NAME) do { \
2757 if (enhancements.name) { \
2758 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2759 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2760 return false; \
2761 intel_sdvo_connector->max_##name = data_value[0]; \
2762 intel_sdvo_connector->cur_##name = response; \
2763 intel_sdvo_connector->name = \
d9bc3c02 2764 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2765 if (!intel_sdvo_connector->name) return false; \
662595df 2766 drm_object_attach_property(&connector->base, \
c5521706
CW		 2767 intel_sdvo_connector->name, \
2768 intel_sdvo_connector->cur_##name); \
2769 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2770 data_value[0], data_value[1], response); \
2771 } \
0206e353 2772} while (0)
c5521706
CW		 2773
2774static bool
2775intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2776 struct intel_sdvo_connector *intel_sdvo_connector,
2777 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2778{
4ef69c7a 2779 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2780 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2781 uint16_t response, data_value[2];
2782
c5521706
CW		 2783 /* when horizontal overscan is supported, Add the left/right property */
2784 if (enhancements.overscan_h) {
2785 if (!intel_sdvo_get_value(intel_sdvo,
2786 SDVO_CMD_GET_MAX_OVERSCAN_H,
2787 &data_value, 4))
2788 return false;
32aad86f 2789
c5521706
CW		 2790 if (!intel_sdvo_get_value(intel_sdvo,
2791 SDVO_CMD_GET_OVERSCAN_H,
2792 &response, 2))
2793 return false;
fcc8d672 2794
c5521706
CW		 2795 intel_sdvo_connector->max_hscan = data_value[0];
2796 intel_sdvo_connector->left_margin = data_value[0] - response;
2797 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2798 intel_sdvo_connector->left =
d9bc3c02 2799 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2800 if (!intel_sdvo_connector->left)
2801 return false;
fcc8d672 2802
662595df 2803 drm_object_attach_property(&connector->base,
c5521706
CW		 2804 intel_sdvo_connector->left,
2805 intel_sdvo_connector->left_margin);
fcc8d672 2806
c5521706 2807 intel_sdvo_connector->right =
d9bc3c02 2808 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2809 if (!intel_sdvo_connector->right)
2810 return false;
32aad86f 2811
662595df 2812 drm_object_attach_property(&connector->base,
c5521706
CW		 2813 intel_sdvo_connector->right,
2814 intel_sdvo_connector->right_margin);
2815 DRM_DEBUG_KMS("h_overscan: max %d, "
2816 "default %d, current %d\n",
2817 data_value[0], data_value[1], response);
2818 }
32aad86f 2819
c5521706
CW		 2820 if (enhancements.overscan_v) {
2821 if (!intel_sdvo_get_value(intel_sdvo,
2822 SDVO_CMD_GET_MAX_OVERSCAN_V,
2823 &data_value, 4))
2824 return false;
fcc8d672 2825
c5521706
CW		 2826 if (!intel_sdvo_get_value(intel_sdvo,
2827 SDVO_CMD_GET_OVERSCAN_V,
2828 &response, 2))
2829 return false;
32aad86f 2830
c5521706
CW		 2831 intel_sdvo_connector->max_vscan = data_value[0];
2832 intel_sdvo_connector->top_margin = data_value[0] - response;
2833 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2834 intel_sdvo_connector->top =
d9bc3c02
SH		 2835 drm_property_create_range(dev, 0,
2836 "top_margin", 0, data_value[0]);
c5521706
CW		 2837 if (!intel_sdvo_connector->top)
2838 return false;
32aad86f 2839
662595df 2840 drm_object_attach_property(&connector->base,
c5521706
CW		 2841 intel_sdvo_connector->top,
2842 intel_sdvo_connector->top_margin);
fcc8d672 2843
c5521706 2844 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2845 drm_property_create_range(dev, 0,
2846 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2847 if (!intel_sdvo_connector->bottom)
2848 return false;
32aad86f 2849
662595df 2850 drm_object_attach_property(&connector->base,
c5521706
CW		 2851 intel_sdvo_connector->bottom,
2852 intel_sdvo_connector->bottom_margin);
2853 DRM_DEBUG_KMS("v_overscan: max %d, "
2854 "default %d, current %d\n",
2855 data_value[0], data_value[1], response);
2856 }
32aad86f 2857
c5521706
CW		 2858 ENHANCEMENT(hpos, HPOS);
2859 ENHANCEMENT(vpos, VPOS);
2860 ENHANCEMENT(saturation, SATURATION);
2861 ENHANCEMENT(contrast, CONTRAST);
2862 ENHANCEMENT(hue, HUE);
2863 ENHANCEMENT(sharpness, SHARPNESS);
2864 ENHANCEMENT(brightness, BRIGHTNESS);
2865 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2866 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2867 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2868 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2869 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2870
e044218a
CW		 2871 if (enhancements.dot_crawl) {
2872 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2873 return false;
2874
2875 intel_sdvo_connector->max_dot_crawl = 1;
2876 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2877 intel_sdvo_connector->dot_crawl =
d9bc3c02 2878 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2879 if (!intel_sdvo_connector->dot_crawl)
2880 return false;
2881
662595df 2882 drm_object_attach_property(&connector->base,
e044218a
CW		 2883 intel_sdvo_connector->dot_crawl,
2884 intel_sdvo_connector->cur_dot_crawl);
2885 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2886 }
2887
c5521706
CW		 2888 return true;
2889}
32aad86f 2890
c5521706
CW		 2891static bool
2892intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2893 struct intel_sdvo_connector *intel_sdvo_connector,
2894 struct intel_sdvo_enhancements_reply enhancements)
2895{
4ef69c7a 2896 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2897 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2898 uint16_t response, data_value[2];
32aad86f 2899
c5521706 2900 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2901
c5521706
CW		 2902 return true;
2903}
2904#undef ENHANCEMENT
32aad86f 2905
c5521706
CW		 2906static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2907 struct intel_sdvo_connector *intel_sdvo_connector)
2908{
2909 union {
2910 struct intel_sdvo_enhancements_reply reply;
2911 uint16_t response;
2912 } enhancements;
32aad86f 2913
1a3665c8
CW		 2914 BUILD_BUG_ON(sizeof(enhancements) != 2);
2915
cf9a2f3a
CW		 2916 enhancements.response = 0;
2917 intel_sdvo_get_value(intel_sdvo,
2918 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2919 &enhancements, sizeof(enhancements));
c5521706
CW		 2920 if (enhancements.response == 0) {
2921 DRM_DEBUG_KMS("No enhancement is supported\n");
2922 return true;
b9219c5e 2923 }
32aad86f 2924
c5521706
CW		 2925 if (IS_TV(intel_sdvo_connector))
2926 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2927 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2928 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2929 else
2930 return true;
e957d772
CW		 2931}
2932
2933static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2934 struct i2c_msg *msgs,
2935 int num)
2936{
2937 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2938
e957d772
CW		 2939 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2940 return -EIO;
2941
2942 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2943}
2944
2945static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2946{
2947 struct intel_sdvo *sdvo = adapter->algo_data;
2948 return sdvo->i2c->algo->functionality(sdvo->i2c);
2949}
2950
2951static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2952 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2953 .functionality = intel_sdvo_ddc_proxy_func
2954};
2955
2956static bool
2957intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2958 struct drm_device *dev)
2959{
2960 sdvo->ddc.owner = THIS_MODULE;
2961 sdvo->ddc.class = I2C_CLASS_DDC;
2962 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2963 sdvo->ddc.dev.parent = &dev->pdev->dev;
2964 sdvo->ddc.algo_data = sdvo;
2965 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2966
2967 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2968}
2969
eef4eacb 2970bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2971{
b01f2c3a 2972 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2973 struct intel_encoder *intel_encoder;
ea5b213a 2974 struct intel_sdvo *intel_sdvo;
79e53945 2975 int i;
b14c5679 2976 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
ea5b213a 2977 if (!intel_sdvo)
7d57382e 2978 return false;
79e53945 2979
56184e3d 2980 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2981 intel_sdvo->is_sdvob = is_sdvob;
2982 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2983 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
fbfcc4f3
JN		 2984 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
2985 goto err_i2c_bus;
e957d772 2986
56184e3d 2987 /* encoder type will be decided later */
ea5b213a 2988 intel_encoder = &intel_sdvo->base;
21d40d37 2989 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2990 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2991
79e53945
JB		 2992 /* Read the regs to test if we can talk to the device */
2993 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2994 u8 byte;
2995
2996 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2997 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2998 SDVO_NAME(intel_sdvo));
f899fc64 2999 goto err;
79e53945
JB		 3000 }
3001 }
3002
6cc5f341 3003 intel_encoder->compute_config = intel_sdvo_compute_config;
ce22c320 3004 intel_encoder->disable = intel_disable_sdvo;
192d47a6 3005 intel_encoder->pre_enable = intel_sdvo_pre_enable;
ce22c320 3006 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 3007 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
045ac3b5 3008 intel_encoder->get_config = intel_sdvo_get_config;
ce22c320 3009
af901ca1 3010 /* In default case sdvo lvds is false */
32aad86f 3011 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 3012 goto err;
79e53945 3013
ea5b213a
CW		 3014 if (intel_sdvo_output_setup(intel_sdvo,
3015 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 3016 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
3017 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 3018 /* Output_setup can leave behind connectors! */
3019 goto err_output;
79e53945
JB		 3020 }
3021
7ba220ce
CW		 3022 /* Only enable the hotplug irq if we need it, to work around noisy
3023 * hotplug lines.
3024 */
3025 if (intel_sdvo->hotplug_active) {
3026 intel_encoder->hpd_pin =
3027 intel_sdvo->is_sdvob ? HPD_SDVO_B : HPD_SDVO_C;
3028 }
3029
e506d6fd
DV		 3030 /*
3031 * Cloning SDVO with anything is often impossible, since the SDVO
3032 * encoder can request a special input timing mode. And even if that's
3033 * not the case we have evidence that cloning a plain unscaled mode with
3034 * VGA doesn't really work. Furthermore the cloning flags are way too
3035 * simplistic anyway to express such constraints, so just give up on
3036 * cloning for SDVO encoders.
3037 */
bc079e8b 3038 intel_sdvo->base.cloneable = 0;
e506d6fd 3039
ea5b213a 3040 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 3041
79e53945 3042 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 3043 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 3044 goto err_output;
79e53945 3045
32aad86f
CW		 3046 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3047 &intel_sdvo->pixel_clock_min,
3048 &intel_sdvo->pixel_clock_max))
d0ddfbd3 3049 goto err_output;
79e53945 3050
8a4c47f3 3051 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 3052 "clock range %dMHz - %dMHz, "
3053 "input 1: %c, input 2: %c, "
3054 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 3055 SDVO_NAME(intel_sdvo),
3056 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3057 intel_sdvo->caps.device_rev_id,
3058 intel_sdvo->pixel_clock_min / 1000,
3059 intel_sdvo->pixel_clock_max / 1000,
3060 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3061 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 3062 /* check currently supported outputs */
ea5b213a 3063 intel_sdvo->caps.output_flags &
79e53945 3064 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 3065 intel_sdvo->caps.output_flags &
79e53945 3066 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 3067 return true;
79e53945 3068
d0ddfbd3
JN		 3069err_output:
3070 intel_sdvo_output_cleanup(intel_sdvo);
3071
f899fc64 3072err:
373a3cf7 3073 drm_encoder_cleanup(&intel_encoder->base);
e957d772 3074 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 3075err_i2c_bus:
3076 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 3077 kfree(intel_sdvo);
79e53945 3078
7d57382e 3079 return false;
79e53945 3080}
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