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drm/i915: distinguish between error messages in DIDL initialization
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
ea5b213a 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
79e53945
JB		 37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 46 SDVO_TV_MASK)
14571b4c
ZW		 47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 50#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 51#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 52#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 53
79e53945 54
2e88e40b 55static const char *tv_format_names[] = {
ce6feabd
ZY		 56 "NTSC_M" , "NTSC_J" , "NTSC_443",
57 "PAL_B" , "PAL_D" , "PAL_G" ,
58 "PAL_H" , "PAL_I" , "PAL_M" ,
59 "PAL_N" , "PAL_NC" , "PAL_60" ,
60 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
61 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
62 "SECAM_60"
63};
64
65#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
66
ea5b213a
CW		 67struct intel_sdvo {
68 struct intel_encoder base;
69
f899fc64 70 struct i2c_adapter *i2c;
f9c10a9b 71 u8 slave_addr;
e2f0ba97 72
e957d772
CW		 73 struct i2c_adapter ddc;
74
e2f0ba97 75 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 76 uint32_t sdvo_reg;
79e53945 77
e2f0ba97
JB		 78 /* Active outputs controlled by this SDVO output */
79 uint16_t controlled_output;
79e53945 80
e2f0ba97
JB		 81 /*
82 * Capabilities of the SDVO device returned by
83 * i830_sdvo_get_capabilities()
84 */
79e53945 85 struct intel_sdvo_caps caps;
e2f0ba97
JB		 86
87 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 88 int pixel_clock_min, pixel_clock_max;
89
fb7a46f3 90 /*
91 * For multiple function SDVO device,
92 * this is for current attached outputs.
93 */
94 uint16_t attached_output;
95
cc68c81a
SF		 96 /*
97 * Hotplug activation bits for this device
98 */
5fa7ac9c 99 uint16_t hotplug_active;
cc68c81a 100
e953fd7b
CW		 101 /**
102 * This is used to select the color range of RBG outputs in HDMI mode.
103 * It is only valid when using TMDS encoding and 8 bit per color mode.
104 */
105 uint32_t color_range;
55bc60db 106 bool color_range_auto;
e953fd7b 107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
eef4eacb
DV		 117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
ce6feabd 120 /* This is for current tv format name */
40039750 121 int tv_format_index;
ce6feabd 122
e2f0ba97
JB		 123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
da79de97
CW		 127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
abedc077 129 bool rgb_quant_range_selectable;
12682a97 130
7086c87f 131 /**
6c9547ff
CW		 132 * This is set if we detect output of sdvo device as LVDS and
133 * have a valid fixed mode to use with the panel.
7086c87f
ML		 134 */
135 bool is_lvds;
e2f0ba97 136
12682a97 137 /**
138 * This is sdvo fixed pannel mode pointer
139 */
140 struct drm_display_mode *sdvo_lvds_fixed_mode;
141
c751ce4f 142 /* DDC bus used by this SDVO encoder */
e2f0ba97 143 uint8_t ddc_bus;
e751823d
EE		 144
145 /*
146 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
147 */
148 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 149};
150
151struct intel_sdvo_connector {
615fb93f
CW		 152 struct intel_connector base;
153
14571b4c
ZW		 154 /* Mark the type of connector */
155 uint16_t output_flag;
156
c3e5f67b 157 enum hdmi_force_audio force_audio;
7f36e7ed 158
14571b4c 159 /* This contains all current supported TV format */
40039750 160 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 161 int format_supported_num;
c5521706 162 struct drm_property *tv_format;
14571b4c 163
b9219c5e 164 /* add the property for the SDVO-TV */
c5521706
CW		 165 struct drm_property *left;
166 struct drm_property *right;
167 struct drm_property *top;
168 struct drm_property *bottom;
169 struct drm_property *hpos;
170 struct drm_property *vpos;
171 struct drm_property *contrast;
172 struct drm_property *saturation;
173 struct drm_property *hue;
174 struct drm_property *sharpness;
175 struct drm_property *flicker_filter;
176 struct drm_property *flicker_filter_adaptive;
177 struct drm_property *flicker_filter_2d;
178 struct drm_property *tv_chroma_filter;
179 struct drm_property *tv_luma_filter;
e044218a 180 struct drm_property *dot_crawl;
b9219c5e
ZY		 181
182 /* add the property for the SDVO-TV/LVDS */
c5521706 183 struct drm_property *brightness;
b9219c5e
ZY		 184
185 /* Add variable to record current setting for the above property */
186 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 187
b9219c5e
ZY		 188 /* this is to get the range of margin.*/
189 u32 max_hscan, max_vscan;
190 u32 max_hpos, cur_hpos;
191 u32 max_vpos, cur_vpos;
192 u32 cur_brightness, max_brightness;
193 u32 cur_contrast, max_contrast;
194 u32 cur_saturation, max_saturation;
195 u32 cur_hue, max_hue;
c5521706
CW		 196 u32 cur_sharpness, max_sharpness;
197 u32 cur_flicker_filter, max_flicker_filter;
198 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
199 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
200 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
201 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 202 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 203};
204
890f3359 205static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 206{
4ef69c7a 207 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 208}
209
df0e9248
CW		 210static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
211{
212 return container_of(intel_attached_encoder(connector),
213 struct intel_sdvo, base);
214}
215
615fb93f
CW		 216static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
217{
218 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
219}
220
fb7a46f3 221static bool
ea5b213a 222intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 223static bool
224intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
225 struct intel_sdvo_connector *intel_sdvo_connector,
226 int type);
227static bool
228intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
229 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 230
79e53945
JB		 231/**
232 * Writes the SDVOB or SDVOC with the given value, but always writes both
233 * SDVOB and SDVOC to work around apparent hardware issues (according to
234 * comments in the BIOS).
235 */
ea5b213a 236static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 237{
4ef69c7a 238 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 239 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 240 u32 bval = val, cval = val;
241 int i;
242
ea5b213a
CW		 243 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
244 I915_WRITE(intel_sdvo->sdvo_reg, val);
245 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 246 return;
247 }
248
e2debe91
PZ		 249 if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
250 cval = I915_READ(GEN3_SDVOC);
251 else
252 bval = I915_READ(GEN3_SDVOB);
253
79e53945
JB		 254 /*
255 * Write the registers twice for luck. Sometimes,
256 * writing them only once doesn't appear to 'stick'.
257 * The BIOS does this too. Yay, magic
258 */
259 for (i = 0; i < 2; i++)
260 {
e2debe91
PZ		 261 I915_WRITE(GEN3_SDVOB, bval);
262 I915_READ(GEN3_SDVOB);
263 I915_WRITE(GEN3_SDVOC, cval);
264 I915_READ(GEN3_SDVOC);
79e53945
JB		 265 }
266}
267
32aad86f 268static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 269{
79e53945
JB		 270 struct i2c_msg msgs[] = {
271 {
e957d772 272 .addr = intel_sdvo->slave_addr,
79e53945
JB		 273 .flags = 0,
274 .len = 1,
e957d772 275 .buf = &addr,
79e53945
JB		 276 },
277 {
e957d772 278 .addr = intel_sdvo->slave_addr,
79e53945
JB		 279 .flags = I2C_M_RD,
280 .len = 1,
e957d772 281 .buf = ch,
79e53945
JB		 282 }
283 };
32aad86f 284 int ret;
79e53945 285
f899fc64 286 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 287 return true;
79e53945 288
8a4c47f3 289 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 290 return false;
291}
292
79e53945
JB		 293#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
294/** Mapping of command numbers to names, for debug output */
005568be 295static const struct _sdvo_cmd_name {
e2f0ba97 296 u8 cmd;
2e88e40b 297 const char *name;
79e53945 298} sdvo_cmd_names[] = {
0206e353
AJ		 299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
342
343 /* Add the op code for SDVO enhancements */
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
388
389 /* HDMI op code */
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 410};
411
eef4eacb 412#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 413
ea5b213a 414static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 415 const void *args, int args_len)
79e53945 416{
79e53945
JB		 417 int i;
418
8a4c47f3 419 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 420 SDVO_NAME(intel_sdvo), cmd);
79e53945 421 for (i = 0; i < args_len; i++)
342dc382 422 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 423 for (; i < 8; i++)
342dc382 424 DRM_LOG_KMS(" ");
04ad327f 425 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 426 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 427 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 428 break;
429 }
430 }
04ad327f 431 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 432 DRM_LOG_KMS("(%02X)", cmd);
433 DRM_LOG_KMS("\n");
79e53945 434}
79e53945 435
e957d772
CW		 436static const char *cmd_status_names[] = {
437 "Power on",
438 "Success",
439 "Not supported",
440 "Invalid arg",
441 "Pending",
442 "Target not specified",
443 "Scaling not supported"
444};
445
32aad86f
CW		 446static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
447 const void *args, int args_len)
79e53945 448{
3bf3f452
BW		 449 u8 *buf, status;
450 struct i2c_msg *msgs;
451 int i, ret = true;
452
0274df3e 453 /* Would be simpler to allocate both in one go ? */
5c67eeb6 454 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3bf3f452
BW		 455 if (!buf)
456 return false;
457
458 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e
AC		 459 if (!msgs) {
460 kfree(buf);
3bf3f452 461 return false;
0274df3e 462 }
79e53945 463
ea5b213a 464 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 465
466 for (i = 0; i < args_len; i++) {
e957d772
CW		 467 msgs[i].addr = intel_sdvo->slave_addr;
468 msgs[i].flags = 0;
469 msgs[i].len = 2;
470 msgs[i].buf = buf + 2 *i;
471 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
472 buf[2*i + 1] = ((u8*)args)[i];
473 }
474 msgs[i].addr = intel_sdvo->slave_addr;
475 msgs[i].flags = 0;
476 msgs[i].len = 2;
477 msgs[i].buf = buf + 2*i;
478 buf[2*i + 0] = SDVO_I2C_OPCODE;
479 buf[2*i + 1] = cmd;
480
481 /* the following two are to read the response */
482 status = SDVO_I2C_CMD_STATUS;
483 msgs[i+1].addr = intel_sdvo->slave_addr;
484 msgs[i+1].flags = 0;
485 msgs[i+1].len = 1;
486 msgs[i+1].buf = &status;
487
488 msgs[i+2].addr = intel_sdvo->slave_addr;
489 msgs[i+2].flags = I2C_M_RD;
490 msgs[i+2].len = 1;
491 msgs[i+2].buf = &status;
492
493 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
494 if (ret < 0) {
495 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 496 ret = false;
497 goto out;
e957d772
CW		 498 }
499 if (ret != i+3) {
500 /* failure in I2C transfer */
501 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 502 ret = false;
e957d772
CW		 503 }
504
3bf3f452
BW		 505out:
506 kfree(msgs);
507 kfree(buf);
508 return ret;
79e53945
JB		 509}
510
b5c616a7
CW		 511static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
512 void *response, int response_len)
79e53945 513{
fc37381c 514 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 515 u8 status;
33b52961 516 int i;
79e53945 517
d121a5d2
CW		 518 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
519
b5c616a7
CW		 520 /*
521 * The documentation states that all commands will be
522 * processed within 15µs, and that we need only poll
523 * the status byte a maximum of 3 times in order for the
524 * command to be complete.
525 *
526 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 527 *
528 * Also beware that the first response by many devices is to
529 * reply PENDING and stall for time. TVs are notorious for
530 * requiring longer than specified to complete their replies.
531 * Originally (in the DDX long ago), the delay was only ever 15ms
532 * with an additional delay of 30ms applied for TVs added later after
533 * many experiments. To accommodate both sets of delays, we do a
534 * sequence of slow checks if the device is falling behind and fails
535 * to reply within 5*15µs.
b5c616a7 536 */
d121a5d2
CW		 537 if (!intel_sdvo_read_byte(intel_sdvo,
538 SDVO_I2C_CMD_STATUS,
539 &status))
540 goto log_fail;
541
fc37381c
CW		 542 while (status == SDVO_CMD_STATUS_PENDING && --retry) {
543 if (retry < 10)
544 msleep(15);
545 else
546 udelay(15);
547
b5c616a7
CW		 548 if (!intel_sdvo_read_byte(intel_sdvo,
549 SDVO_I2C_CMD_STATUS,
550 &status))
d121a5d2
CW		 551 goto log_fail;
552 }
b5c616a7 553
79e53945 554 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 555 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 556 else
342dc382 557 DRM_LOG_KMS("(??? %d)", status);
79e53945 558
b5c616a7
CW		 559 if (status != SDVO_CMD_STATUS_SUCCESS)
560 goto log_fail;
79e53945 561
b5c616a7
CW		 562 /* Read the command response */
563 for (i = 0; i < response_len; i++) {
564 if (!intel_sdvo_read_byte(intel_sdvo,
565 SDVO_I2C_RETURN_0 + i,
566 &((u8 *)response)[i]))
567 goto log_fail;
e957d772 568 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 569 }
b5c616a7 570 DRM_LOG_KMS("\n");
b5c616a7 571 return true;
79e53945 572
b5c616a7 573log_fail:
d121a5d2 574 DRM_LOG_KMS("... failed\n");
b5c616a7 575 return false;
79e53945
JB		 576}
577
b358d0a6 578static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 579{
580 if (mode->clock >= 100000)
581 return 1;
582 else if (mode->clock >= 50000)
583 return 2;
584 else
585 return 4;
586}
587
e957d772
CW		 588static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
589 u8 ddc_bus)
79e53945 590{
d121a5d2 591 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 592 return intel_sdvo_write_cmd(intel_sdvo,
593 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
594 &ddc_bus, 1);
79e53945
JB		 595}
596
32aad86f 597static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 598{
d121a5d2
CW		 599 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
600 return false;
601
602 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 603}
79e53945 604
32aad86f
CW		 605static bool
606intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
607{
608 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
609 return false;
79e53945 610
32aad86f
CW		 611 return intel_sdvo_read_response(intel_sdvo, value, len);
612}
79e53945 613
32aad86f
CW		 614static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
615{
616 struct intel_sdvo_set_target_input_args targets = {0};
617 return intel_sdvo_set_value(intel_sdvo,
618 SDVO_CMD_SET_TARGET_INPUT,
619 &targets, sizeof(targets));
79e53945
JB		 620}
621
622/**
623 * Return whether each input is trained.
624 *
625 * This function is making an assumption about the layout of the response,
626 * which should be checked against the docs.
627 */
ea5b213a 628static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 629{
630 struct intel_sdvo_get_trained_inputs_response response;
79e53945 631
1a3665c8 632 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 633 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
634 &response, sizeof(response)))
79e53945
JB		 635 return false;
636
637 *input_1 = response.input0_trained;
638 *input_2 = response.input1_trained;
639 return true;
640}
641
ea5b213a 642static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 643 u16 outputs)
644{
32aad86f
CW		 645 return intel_sdvo_set_value(intel_sdvo,
646 SDVO_CMD_SET_ACTIVE_OUTPUTS,
647 &outputs, sizeof(outputs));
79e53945
JB		 648}
649
4ac41f47
DV		 650static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
651 u16 *outputs)
652{
653 return intel_sdvo_get_value(intel_sdvo,
654 SDVO_CMD_GET_ACTIVE_OUTPUTS,
655 outputs, sizeof(*outputs));
656}
657
ea5b213a 658static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 659 int mode)
660{
32aad86f 661 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 662
663 switch (mode) {
664 case DRM_MODE_DPMS_ON:
665 state = SDVO_ENCODER_STATE_ON;
666 break;
667 case DRM_MODE_DPMS_STANDBY:
668 state = SDVO_ENCODER_STATE_STANDBY;
669 break;
670 case DRM_MODE_DPMS_SUSPEND:
671 state = SDVO_ENCODER_STATE_SUSPEND;
672 break;
673 case DRM_MODE_DPMS_OFF:
674 state = SDVO_ENCODER_STATE_OFF;
675 break;
676 }
677
32aad86f
CW		 678 return intel_sdvo_set_value(intel_sdvo,
679 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 680}
681
ea5b213a 682static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 683 int *clock_min,
684 int *clock_max)
685{
686 struct intel_sdvo_pixel_clock_range clocks;
79e53945 687
1a3665c8 688 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 689 if (!intel_sdvo_get_value(intel_sdvo,
690 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
691 &clocks, sizeof(clocks)))
79e53945
JB		 692 return false;
693
694 /* Convert the values from units of 10 kHz to kHz. */
695 *clock_min = clocks.min * 10;
696 *clock_max = clocks.max * 10;
79e53945
JB		 697 return true;
698}
699
ea5b213a 700static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 701 u16 outputs)
702{
32aad86f
CW		 703 return intel_sdvo_set_value(intel_sdvo,
704 SDVO_CMD_SET_TARGET_OUTPUT,
705 &outputs, sizeof(outputs));
79e53945
JB		 706}
707
ea5b213a 708static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 709 struct intel_sdvo_dtd *dtd)
710{
32aad86f
CW		 711 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
712 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 713}
714
045ac3b5
JB		 715static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
716 struct intel_sdvo_dtd *dtd)
717{
718 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
719 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
720}
721
ea5b213a 722static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 723 struct intel_sdvo_dtd *dtd)
724{
ea5b213a 725 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 726 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
727}
728
ea5b213a 729static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 730 struct intel_sdvo_dtd *dtd)
731{
ea5b213a 732 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 733 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
734}
735
045ac3b5
JB		 736static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
737 struct intel_sdvo_dtd *dtd)
738{
739 return intel_sdvo_get_timing(intel_sdvo,
740 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
741}
742
e2f0ba97 743static bool
ea5b213a 744intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 745 uint16_t clock,
746 uint16_t width,
747 uint16_t height)
748{
749 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 750
e642c6f1 751 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 752 args.clock = clock;
753 args.width = width;
754 args.height = height;
e642c6f1 755 args.interlace = 0;
12682a97 756
ea5b213a
CW		 757 if (intel_sdvo->is_lvds &&
758 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
759 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 760 args.scaled = 1;
761
32aad86f
CW		 762 return intel_sdvo_set_value(intel_sdvo,
763 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
764 &args, sizeof(args));
e2f0ba97
JB		 765}
766
ea5b213a 767static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 768 struct intel_sdvo_dtd *dtd)
769{
1a3665c8
CW		 770 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
771 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 772 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
773 &dtd->part1, sizeof(dtd->part1)) &&
774 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
775 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 776}
79e53945 777
ea5b213a 778static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 779{
32aad86f 780 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 781}
782
e2f0ba97 783static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 784 const struct drm_display_mode *mode)
79e53945 785{
e2f0ba97
JB		 786 uint16_t width, height;
787 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
788 uint16_t h_sync_offset, v_sync_offset;
6651819b 789 int mode_clock;
79e53945 790
c6ebd4c0
DV		 791 width = mode->hdisplay;
792 height = mode->vdisplay;
79e53945
JB		 793
794 /* do some mode translations */
c6ebd4c0
DV		 795 h_blank_len = mode->htotal - mode->hdisplay;
796 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 797
c6ebd4c0
DV		 798 v_blank_len = mode->vtotal - mode->vdisplay;
799 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 800
c6ebd4c0
DV		 801 h_sync_offset = mode->hsync_start - mode->hdisplay;
802 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 803
6651819b 804 mode_clock = mode->clock;
6651819b
DV		 805 mode_clock /= 10;
806 dtd->part1.clock = mode_clock;
807
e2f0ba97
JB		 808 dtd->part1.h_active = width & 0xff;
809 dtd->part1.h_blank = h_blank_len & 0xff;
810 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 811 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 812 dtd->part1.v_active = height & 0xff;
813 dtd->part1.v_blank = v_blank_len & 0xff;
814 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 815 ((v_blank_len >> 8) & 0xf);
816
171a9e96 817 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 818 dtd->part2.h_sync_width = h_sync_len & 0xff;
819 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 820 (v_sync_len & 0xf);
e2f0ba97 821 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 822 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
823 ((v_sync_len & 0x30) >> 4);
824
e2f0ba97 825 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 826 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
827 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 828 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 829 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 830 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 831 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97
JB		 832
833 dtd->part2.sdvo_flags = 0;
834 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
835 dtd->part2.reserved = 0;
836}
837
838static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 839 const struct intel_sdvo_dtd *dtd)
e2f0ba97 840{
e2f0ba97
JB		 841 mode->hdisplay = dtd->part1.h_active;
842 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
843 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 844 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 845 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
846 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
847 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
848 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
849
850 mode->vdisplay = dtd->part1.v_active;
851 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
852 mode->vsync_start = mode->vdisplay;
853 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 854 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 855 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
856 mode->vsync_end = mode->vsync_start +
857 (dtd->part2.v_sync_off_width & 0xf);
858 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
859 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
860 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
861
862 mode->clock = dtd->part1.clock * 10;
863
171a9e96 864 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
59d92bfa
DV		 865 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
866 mode->flags |= DRM_MODE_FLAG_INTERLACE;
867 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
e2f0ba97 868 mode->flags |= DRM_MODE_FLAG_PHSYNC;
59d92bfa 869 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
e2f0ba97
JB		 870 mode->flags |= DRM_MODE_FLAG_PVSYNC;
871}
872
e27d8538 873static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 874{
e27d8538 875 struct intel_sdvo_encode encode;
e2f0ba97 876
1a3665c8 877 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 878 return intel_sdvo_get_value(intel_sdvo,
879 SDVO_CMD_GET_SUPP_ENCODE,
880 &encode, sizeof(encode));
e2f0ba97
JB		 881}
882
ea5b213a 883static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 884 uint8_t mode)
e2f0ba97 885{
32aad86f 886 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 887}
888
ea5b213a 889static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 890 uint8_t mode)
891{
32aad86f 892 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 893}
894
895#if 0
ea5b213a 896static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 897{
898 int i, j;
899 uint8_t set_buf_index[2];
900 uint8_t av_split;
901 uint8_t buf_size;
902 uint8_t buf[48];
903 uint8_t *pos;
904
32aad86f 905 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 906
907 for (i = 0; i <= av_split; i++) {
908 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 909 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 910 set_buf_index, 2);
c751ce4f
EA		 911 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
912 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 913
914 pos = buf;
915 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 916 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 917 NULL, 0);
c751ce4f 918 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 919 pos += 8;
920 }
921 }
922}
923#endif
924
b6e0e543
DV		 925static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
926 unsigned if_index, uint8_t tx_rate,
927 uint8_t *data, unsigned length)
928{
929 uint8_t set_buf_index[2] = { if_index, 0 };
930 uint8_t hbuf_size, tmp[8];
931 int i;
932
933 if (!intel_sdvo_set_value(intel_sdvo,
934 SDVO_CMD_SET_HBUF_INDEX,
935 set_buf_index, 2))
936 return false;
937
938 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
939 &hbuf_size, 1))
940 return false;
941
942 /* Buffer size is 0 based, hooray! */
943 hbuf_size++;
944
945 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
946 if_index, length, hbuf_size);
947
948 for (i = 0; i < hbuf_size; i += 8) {
949 memset(tmp, 0, 8);
950 if (i < length)
951 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
952
953 if (!intel_sdvo_set_value(intel_sdvo,
954 SDVO_CMD_SET_HBUF_DATA,
955 tmp, 8))
956 return false;
957 }
958
959 return intel_sdvo_set_value(intel_sdvo,
960 SDVO_CMD_SET_HBUF_TXRATE,
961 &tx_rate, 1);
962}
963
abedc077
VS		 964static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
965 const struct drm_display_mode *adjusted_mode)
e2f0ba97
JB		 966{
967 struct dip_infoframe avi_if = {
968 .type = DIP_TYPE_AVI,
3c17fe4b 969 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 970 .len = DIP_LEN_AVI,
971 };
81014b9d 972 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
50f3b016 973 struct intel_crtc *intel_crtc = to_intel_crtc(intel_sdvo->base.base.crtc);
3c17fe4b 974
abedc077 975 if (intel_sdvo->rgb_quant_range_selectable) {
50f3b016 976 if (intel_crtc->config.limited_color_range)
abedc077
VS		 977 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
978 else
979 avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
980 }
981
96b219fa
VS		 982 avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode);
983
3c17fe4b
DH		 984 intel_dip_infoframe_csum(&avi_if);
985
81014b9d
DV		 986 /* sdvo spec says that the ecc is handled by the hw, and it looks like
987 * we must not send the ecc field, either. */
988 memcpy(sdvo_data, &avi_if, 3);
989 sdvo_data[3] = avi_if.checksum;
990 memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
991
b6e0e543
DV		 992 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
993 SDVO_HBUF_TX_VSYNC,
994 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 995}
996
32aad86f 997static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 998{
ce6feabd 999 struct intel_sdvo_tv_format format;
40039750 1000 uint32_t format_map;
ce6feabd 1001
40039750 1002 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1003 memset(&format, 0, sizeof(format));
32aad86f 1004 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1005
32aad86f
CW		 1006 BUILD_BUG_ON(sizeof(format) != 6);
1007 return intel_sdvo_set_value(intel_sdvo,
1008 SDVO_CMD_SET_TV_FORMAT,
1009 &format, sizeof(format));
7026d4ac
ZW		 1010}
1011
32aad86f
CW		 1012static bool
1013intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1014 const struct drm_display_mode *mode)
e2f0ba97 1015{
32aad86f 1016 struct intel_sdvo_dtd output_dtd;
79e53945 1017
32aad86f
CW		 1018 if (!intel_sdvo_set_target_output(intel_sdvo,
1019 intel_sdvo->attached_output))
1020 return false;
e2f0ba97 1021
32aad86f
CW		 1022 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1023 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1024 return false;
e2f0ba97 1025
32aad86f
CW		 1026 return true;
1027}
1028
c9a29698
DV		 1029/* Asks the sdvo controller for the preferred input mode given the output mode.
1030 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 1031static bool
c9a29698 1032intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1033 const struct drm_display_mode *mode,
c9a29698 1034 struct drm_display_mode *adjusted_mode)
32aad86f 1035{
c9a29698
DV		 1036 struct intel_sdvo_dtd input_dtd;
1037
32aad86f
CW		 1038 /* Reset the input timing to the screen. Assume always input 0. */
1039 if (!intel_sdvo_set_target_input(intel_sdvo))
1040 return false;
e2f0ba97 1041
32aad86f
CW		 1042 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1043 mode->clock / 10,
1044 mode->hdisplay,
1045 mode->vdisplay))
1046 return false;
e2f0ba97 1047
32aad86f 1048 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1049 &input_dtd))
32aad86f 1050 return false;
e2f0ba97 1051
c9a29698 1052 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1053 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1054
32aad86f
CW		 1055 return true;
1056}
12682a97 1057
70484559
DV		 1058static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_config *pipe_config)
1059{
1060 unsigned dotclock = pipe_config->adjusted_mode.clock;
1061 struct dpll *clock = &pipe_config->dpll;
1062
1063 /* SDVO TV has fixed PLL values depend on its clock range,
1064 this mirrors vbios setting. */
1065 if (dotclock >= 100000 && dotclock < 140500) {
1066 clock->p1 = 2;
1067 clock->p2 = 10;
1068 clock->n = 3;
1069 clock->m1 = 16;
1070 clock->m2 = 8;
1071 } else if (dotclock >= 140500 && dotclock <= 200000) {
1072 clock->p1 = 1;
1073 clock->p2 = 10;
1074 clock->n = 6;
1075 clock->m1 = 12;
1076 clock->m2 = 8;
1077 } else {
1078 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1079 }
1080
1081 pipe_config->clock_set = true;
1082}
1083
6cc5f341
DV		 1084static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
1085 struct intel_crtc_config *pipe_config)
32aad86f 1086{
6cc5f341
DV		 1087 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1088 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
1089 struct drm_display_mode *mode = &pipe_config->requested_mode;
12682a97 1090
5d2d38dd
DV		 1091 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1092 pipe_config->pipe_bpp = 8*3;
1093
5bfe2ac0
DV		 1094 if (HAS_PCH_SPLIT(encoder->base.dev))
1095 pipe_config->has_pch_encoder = true;
1096
32aad86f
CW		 1097 /* We need to construct preferred input timings based on our
1098 * output timings. To do that, we have to set the output
1099 * timings, even though this isn't really the right place in
1100 * the sequence to do it. Oh well.
1101 */
1102 if (intel_sdvo->is_tv) {
1103 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1104 return false;
12682a97 1105
c9a29698
DV		 1106 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1107 mode,
1108 adjusted_mode);
09ede541 1109 pipe_config->sdvo_tv_clock = true;
ea5b213a 1110 } else if (intel_sdvo->is_lvds) {
32aad86f 1111 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1112 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1113 return false;
12682a97 1114
c9a29698
DV		 1115 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1116 mode,
1117 adjusted_mode);
e2f0ba97 1118 }
32aad86f
CW		 1119
1120 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1121 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1122 */
6cc5f341
DV		 1123 pipe_config->pixel_multiplier =
1124 intel_sdvo_get_pixel_multiplier(adjusted_mode);
1125 adjusted_mode->clock *= pipe_config->pixel_multiplier;
32aad86f 1126
55bc60db
VS		 1127 if (intel_sdvo->color_range_auto) {
1128 /* See CEA-861-E - 5.1 Default Encoding Parameters */
4f3a8bc7
PZ		 1129 /* FIXME: This bit is only valid when using TMDS encoding and 8
1130 * bit per color mode. */
55bc60db 1131 if (intel_sdvo->has_hdmi_monitor &&
18316c8c 1132 drm_match_cea_mode(adjusted_mode) > 1)
4f3a8bc7 1133 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 1134 else
1135 intel_sdvo->color_range = 0;
1136 }
1137
3685a8f3 1138 if (intel_sdvo->color_range)
50f3b016 1139 pipe_config->limited_color_range = true;
3685a8f3 1140
70484559
DV		 1141 /* Clock computation needs to happen after pixel multiplier. */
1142 if (intel_sdvo->is_tv)
1143 i9xx_adjust_sdvo_tv_clock(pipe_config);
1144
e2f0ba97
JB		 1145 return true;
1146}
1147
6cc5f341 1148static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
e2f0ba97 1149{
6cc5f341 1150 struct drm_device *dev = intel_encoder->base.dev;
e2f0ba97 1151 struct drm_i915_private *dev_priv = dev->dev_private;
6cc5f341 1152 struct drm_crtc *crtc = intel_encoder->base.crtc;
e2f0ba97 1153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 1154 struct drm_display_mode *adjusted_mode =
1155 &intel_crtc->config.adjusted_mode;
1156 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
1157 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&intel_encoder->base);
6c9547ff 1158 u32 sdvox;
e2f0ba97 1159 struct intel_sdvo_in_out_map in_out;
6651819b 1160 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff 1161 int rate;
e2f0ba97
JB		 1162
1163 if (!mode)
1164 return;
1165
1166 /* First, set the input mapping for the first input to our controlled
1167 * output. This is only correct if we're a single-input device, in
1168 * which case the first input is the output from the appropriate SDVO
1169 * channel on the motherboard. In a two-input device, the first input
1170 * will be SDVOB and the second SDVOC.
1171 */
ea5b213a 1172 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1173 in_out.in1 = 0;
1174
c74696b9
PR		 1175 intel_sdvo_set_value(intel_sdvo,
1176 SDVO_CMD_SET_IN_OUT_MAP,
1177 &in_out, sizeof(in_out));
e2f0ba97 1178
6c9547ff
CW		 1179 /* Set the output timings to the screen */
1180 if (!intel_sdvo_set_target_output(intel_sdvo,
1181 intel_sdvo->attached_output))
1182 return;
e2f0ba97 1183
6651819b
DV		 1184 /* lvds has a special fixed output timing. */
1185 if (intel_sdvo->is_lvds)
1186 intel_sdvo_get_dtd_from_mode(&output_dtd,
1187 intel_sdvo->sdvo_lvds_fixed_mode);
1188 else
1189 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1190 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1191 DRM_INFO("Setting output timings on %s failed\n",
1192 SDVO_NAME(intel_sdvo));
79e53945
JB		 1193
1194 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1195 if (!intel_sdvo_set_target_input(intel_sdvo))
1196 return;
79e53945 1197
97aaf910
CW		 1198 if (intel_sdvo->has_hdmi_monitor) {
1199 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1200 intel_sdvo_set_colorimetry(intel_sdvo,
1201 SDVO_COLORIMETRY_RGB256);
abedc077 1202 intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
97aaf910
CW		 1203 } else
1204 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1205
6c9547ff
CW		 1206 if (intel_sdvo->is_tv &&
1207 !intel_sdvo_set_tv_format(intel_sdvo))
1208 return;
e2f0ba97 1209
6651819b
DV		 1210 /* We have tried to get input timing in mode_fixup, and filled into
1211 * adjusted_mode.
1212 */
1213 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
e751823d
EE		 1214 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1215 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1216 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1217 DRM_INFO("Setting input timings on %s failed\n",
1218 SDVO_NAME(intel_sdvo));
79e53945 1219
6cc5f341 1220 switch (intel_crtc->config.pixel_multiplier) {
6c9547ff 1221 default:
32aad86f
CW		 1222 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1223 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1224 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1225 }
32aad86f
CW		 1226 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1227 return;
79e53945
JB		 1228
1229 /* Set the SDVO control regs. */
a6c45cf0 1230 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1231 /* The real mode polarity is set by the SDVO commands, using
1232 * struct intel_sdvo_dtd. */
1233 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
3685a8f3 1234 if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
e953fd7b 1235 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1236 if (INTEL_INFO(dev)->gen < 5)
1237 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1238 } else {
6c9547ff 1239 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1240 switch (intel_sdvo->sdvo_reg) {
e2debe91 1241 case GEN3_SDVOB:
e2f0ba97
JB		 1242 sdvox &= SDVOB_PRESERVE_MASK;
1243 break;
e2debe91 1244 case GEN3_SDVOC:
e2f0ba97
JB		 1245 sdvox &= SDVOC_PRESERVE_MASK;
1246 break;
1247 }
1248 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1249 }
3573c410
PZ		 1250
1251 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
dc0fa718 1252 sdvox |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe);
3573c410 1253 else
dc0fa718 1254 sdvox |= SDVO_PIPE_SEL(intel_crtc->pipe);
3573c410 1255
da79de97 1256 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1257 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1258
a6c45cf0 1259 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1260 /* done in crtc_mode_set as the dpll_md reg must be written early */
1261 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1262 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1263 } else {
6cc5f341
DV		 1264 sdvox |= (intel_crtc->config.pixel_multiplier - 1)
1265 << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1266 }
1267
6714afb1
CW		 1268 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1269 INTEL_INFO(dev)->gen < 5)
12682a97 1270 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1271 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1272}
1273
4ac41f47 1274static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1275{
4ac41f47
DV		 1276 struct intel_sdvo_connector *intel_sdvo_connector =
1277 to_intel_sdvo_connector(&connector->base);
1278 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
1279 u16 active_outputs;
1280
1281 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1282
1283 if (active_outputs & intel_sdvo_connector->output_flag)
1284 return true;
1285 else
1286 return false;
1287}
1288
1289static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1290 enum pipe *pipe)
1291{
1292 struct drm_device *dev = encoder->base.dev;
79e53945 1293 struct drm_i915_private *dev_priv = dev->dev_private;
4ac41f47 1294 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
7a7d1fb7 1295 u16 active_outputs;
4ac41f47
DV		 1296 u32 tmp;
1297
1298 tmp = I915_READ(intel_sdvo->sdvo_reg);
7a7d1fb7 1299 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
4ac41f47 1300
7a7d1fb7 1301 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
4ac41f47
DV		 1302 return false;
1303
1304 if (HAS_PCH_CPT(dev))
1305 *pipe = PORT_TO_PIPE_CPT(tmp);
1306 else
1307 *pipe = PORT_TO_PIPE(tmp);
1308
1309 return true;
1310}
1311
045ac3b5
JB		 1312static void intel_sdvo_get_config(struct intel_encoder *encoder,
1313 struct intel_crtc_config *pipe_config)
1314{
1315 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1316 struct intel_sdvo_dtd dtd;
1317 u32 flags = 0;
1318 bool ret;
1319
1320 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1321 if (!ret) {
1322 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
1323 return;
1324 }
1325
1326 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1327 flags |= DRM_MODE_FLAG_PHSYNC;
1328 else
1329 flags |= DRM_MODE_FLAG_NHSYNC;
1330
1331 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1332 flags |= DRM_MODE_FLAG_PVSYNC;
1333 else
1334 flags |= DRM_MODE_FLAG_NVSYNC;
1335
1336 pipe_config->adjusted_mode.flags |= flags;
1337}
1338
ce22c320
DV		 1339static void intel_disable_sdvo(struct intel_encoder *encoder)
1340{
1341 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1342 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1343 u32 temp;
1344
1345 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1346 if (0)
1347 intel_sdvo_set_encoder_power_state(intel_sdvo,
1348 DRM_MODE_DPMS_OFF);
1349
1350 temp = I915_READ(intel_sdvo->sdvo_reg);
1351 if ((temp & SDVO_ENABLE) != 0) {
776ca7cf
CW		 1352 /* HW workaround for IBX, we need to move the port to
1353 * transcoder A before disabling it. */
1354 if (HAS_PCH_IBX(encoder->base.dev)) {
1355 struct drm_crtc *crtc = encoder->base.crtc;
1356 int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
1357
1358 if (temp & SDVO_PIPE_B_SELECT) {
1359 temp &= ~SDVO_PIPE_B_SELECT;
1360 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1361 POSTING_READ(intel_sdvo->sdvo_reg);
1362
1363 /* Again we need to write this twice. */
1364 I915_WRITE(intel_sdvo->sdvo_reg, temp);
1365 POSTING_READ(intel_sdvo->sdvo_reg);
1366
1367 /* Transcoder selection bits only update
1368 * effectively on vblank. */
1369 if (crtc)
1370 intel_wait_for_vblank(encoder->base.dev, pipe);
1371 else
1372 msleep(50);
1373 }
1374 }
1375
ce22c320
DV		 1376 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
1377 }
1378}
1379
1380static void intel_enable_sdvo(struct intel_encoder *encoder)
1381{
1382 struct drm_device *dev = encoder->base.dev;
1383 struct drm_i915_private *dev_priv = dev->dev_private;
1384 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
1385 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 1386 u32 temp;
ce22c320
DV		 1387 bool input1, input2;
1388 int i;
1389 u8 status;
1390
1391 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf
CW		 1392 if ((temp & SDVO_ENABLE) == 0) {
1393 /* HW workaround for IBX, we need to move the port
dc0fa718
PZ		 1394 * to transcoder A before disabling it, so restore it here. */
1395 if (HAS_PCH_IBX(dev))
1396 temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
776ca7cf 1397
ce22c320 1398 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
776ca7cf 1399 }
ce22c320
DV		 1400 for (i = 0; i < 2; i++)
1401 intel_wait_for_vblank(dev, intel_crtc->pipe);
1402
1403 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
1404 /* Warn if the device reported failure to sync.
1405 * A lot of SDVO devices fail to notify of sync, but it's
1406 * a given it the status is a success, we succeeded.
1407 */
1408 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1409 DRM_DEBUG_KMS("First %s output reported failure to "
1410 "sync\n", SDVO_NAME(intel_sdvo));
1411 }
1412
1413 if (0)
1414 intel_sdvo_set_encoder_power_state(intel_sdvo,
1415 DRM_MODE_DPMS_ON);
1416 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1417}
1418
6b1c087b 1419/* Special dpms function to support cloning between dvo/sdvo/crt. */
b2cabb0e 1420static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
79e53945 1421{
b2cabb0e
DV		 1422 struct drm_crtc *crtc;
1423 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1424
1425 /* dvo supports only 2 dpms states. */
1426 if (mode != DRM_MODE_DPMS_ON)
1427 mode = DRM_MODE_DPMS_OFF;
1428
1429 if (mode == connector->dpms)
1430 return;
1431
1432 connector->dpms = mode;
1433
1434 /* Only need to change hw state when actually enabled */
1435 crtc = intel_sdvo->base.base.crtc;
1436 if (!crtc) {
1437 intel_sdvo->base.connectors_active = false;
1438 return;
1439 }
79e53945 1440
6b1c087b
JN		 1441 /* We set active outputs manually below in case pipe dpms doesn't change
1442 * due to cloning. */
79e53945 1443 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1444 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1445 if (0)
ea5b213a 1446 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945 1447
b2cabb0e
DV		 1448 intel_sdvo->base.connectors_active = false;
1449
1450 intel_crtc_update_dpms(crtc);
79e53945 1451 } else {
b2cabb0e
DV		 1452 intel_sdvo->base.connectors_active = true;
1453
1454 intel_crtc_update_dpms(crtc);
79e53945
JB		 1455
1456 if (0)
ea5b213a
CW		 1457 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1458 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945 1459 }
0a91ca29 1460
b980514c 1461 intel_modeset_check_state(connector->dev);
79e53945
JB		 1462}
1463
79e53945
JB		 1464static int intel_sdvo_mode_valid(struct drm_connector *connector,
1465 struct drm_display_mode *mode)
1466{
df0e9248 1467 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1468
1469 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1470 return MODE_NO_DBLESCAN;
1471
ea5b213a 1472 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1473 return MODE_CLOCK_LOW;
1474
ea5b213a 1475 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1476 return MODE_CLOCK_HIGH;
1477
8545423a 1478 if (intel_sdvo->is_lvds) {
ea5b213a 1479 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1480 return MODE_PANEL;
1481
ea5b213a 1482 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1483 return MODE_PANEL;
1484 }
1485
79e53945
JB		 1486 return MODE_OK;
1487}
1488
ea5b213a 1489static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1490{
1a3665c8 1491 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1492 if (!intel_sdvo_get_value(intel_sdvo,
1493 SDVO_CMD_GET_DEVICE_CAPS,
1494 caps, sizeof(*caps)))
1495 return false;
1496
1497 DRM_DEBUG_KMS("SDVO capabilities:\n"
1498 " vendor_id: %d\n"
1499 " device_id: %d\n"
1500 " device_rev_id: %d\n"
1501 " sdvo_version_major: %d\n"
1502 " sdvo_version_minor: %d\n"
1503 " sdvo_inputs_mask: %d\n"
1504 " smooth_scaling: %d\n"
1505 " sharp_scaling: %d\n"
1506 " up_scaling: %d\n"
1507 " down_scaling: %d\n"
1508 " stall_support: %d\n"
1509 " output_flags: %d\n",
1510 caps->vendor_id,
1511 caps->device_id,
1512 caps->device_rev_id,
1513 caps->sdvo_version_major,
1514 caps->sdvo_version_minor,
1515 caps->sdvo_inputs_mask,
1516 caps->smooth_scaling,
1517 caps->sharp_scaling,
1518 caps->up_scaling,
1519 caps->down_scaling,
1520 caps->stall_support,
1521 caps->output_flags);
1522
1523 return true;
79e53945
JB		 1524}
1525
5fa7ac9c 1526static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1527{
768b107e 1528 struct drm_device *dev = intel_sdvo->base.base.dev;
5fa7ac9c 1529 uint16_t hotplug;
79e53945 1530
768b107e
DV		 1531 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1532 * on the line. */
1533 if (IS_I945G(dev) || IS_I945GM(dev))
5fa7ac9c 1534 return 0;
768b107e 1535
5fa7ac9c
JN		 1536 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1537 &hotplug, sizeof(hotplug)))
1538 return 0;
768b107e 1539
5fa7ac9c 1540 return hotplug;
79e53945
JB		 1541}
1542
cc68c81a 1543static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1544{
cc68c81a 1545 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1546
5fa7ac9c
JN		 1547 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1548 &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1549}
1550
fb7a46f3 1551static bool
ea5b213a 1552intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1553{
bc65212c 1554 /* Is there more than one type of output? */
2294488d 1555 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1556}
1557
f899fc64 1558static struct edid *
e957d772 1559intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1560{
e957d772
CW		 1561 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1562 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1563}
1564
ff482d83
CW		 1565/* Mac mini hack -- use the same DDC as the analog connector */
1566static struct edid *
1567intel_sdvo_get_analog_edid(struct drm_connector *connector)
1568{
f899fc64 1569 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1570
0c1dab89 1571 return drm_get_edid(connector,
3bd7d909 1572 intel_gmbus_get_adapter(dev_priv,
41aa3448 1573 dev_priv->vbt.crt_ddc_pin));
ff482d83
CW		 1574}
1575
c43b5634 1576static enum drm_connector_status
8bf38485 1577intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1578{
df0e9248 1579 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1580 enum drm_connector_status status;
1581 struct edid *edid;
9dff6af8 1582
e957d772 1583 edid = intel_sdvo_get_edid(connector);
57cdaf90 1584
ea5b213a 1585 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1586 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1587
7c3f0a27
ZY		 1588 /*
1589 * Don't use the 1 as the argument of DDC bus switch to get
1590 * the EDID. It is used for SDVO SPD ROM.
1591 */
9d1a903d 1592 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1593 intel_sdvo->ddc_bus = ddc;
1594 edid = intel_sdvo_get_edid(connector);
1595 if (edid)
7c3f0a27 1596 break;
7c3f0a27 1597 }
e957d772
CW		 1598 /*
1599 * If we found the EDID on the other bus,
1600 * assume that is the correct DDC bus.
1601 */
1602 if (edid == NULL)
1603 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1604 }
9d1a903d
CW		 1605
1606 /*
1607 * When there is no edid and no monitor is connected with VGA
1608 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1609 */
ff482d83
CW		 1610 if (edid == NULL)
1611 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1612
2f551c84 1613 status = connector_status_unknown;
9dff6af8 1614 if (edid != NULL) {
149c36a3 1615 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1616 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1617 status = connector_status_connected;
da79de97
CW		 1618 if (intel_sdvo->is_hdmi) {
1619 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1620 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
abedc077
VS		 1621 intel_sdvo->rgb_quant_range_selectable =
1622 drm_rgb_quant_range_selectable(edid);
da79de97 1623 }
13946743
CW		 1624 } else
1625 status = connector_status_disconnected;
9d1a903d
CW		 1626 kfree(edid);
1627 }
7f36e7ed
CW		 1628
1629 if (status == connector_status_connected) {
1630 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1631 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1632 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1633 }
1634
2b8d33f7 1635 return status;
9dff6af8
ML		 1636}
1637
52220085
CW		 1638static bool
1639intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1640 struct edid *edid)
1641{
1642 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1643 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1644
1645 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1646 connector_is_digital, monitor_is_digital);
1647 return connector_is_digital == monitor_is_digital;
1648}
1649
7b334fcb 1650static enum drm_connector_status
930a9e28 1651intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1652{
fb7a46f3 1653 uint16_t response;
df0e9248 1654 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1655 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1656 enum drm_connector_status ret;
79e53945 1657
fc37381c
CW		 1658 if (!intel_sdvo_get_value(intel_sdvo,
1659 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1660 &response, 2))
32aad86f 1661 return connector_status_unknown;
79e53945 1662
e957d772
CW		 1663 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1664 response & 0xff, response >> 8,
1665 intel_sdvo_connector->output_flag);
e2f0ba97 1666
fb7a46f3 1667 if (response == 0)
79e53945 1668 return connector_status_disconnected;
fb7a46f3 1669
ea5b213a 1670 intel_sdvo->attached_output = response;
14571b4c 1671
97aaf910
CW		 1672 intel_sdvo->has_hdmi_monitor = false;
1673 intel_sdvo->has_hdmi_audio = false;
abedc077 1674 intel_sdvo->rgb_quant_range_selectable = false;
97aaf910 1675
615fb93f 1676 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1677 ret = connector_status_disconnected;
13946743 1678 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1679 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1680 else {
1681 struct edid *edid;
1682
1683 /* if we have an edid check it matches the connection */
1684 edid = intel_sdvo_get_edid(connector);
1685 if (edid == NULL)
1686 edid = intel_sdvo_get_analog_edid(connector);
1687 if (edid != NULL) {
52220085
CW		 1688 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1689 edid))
13946743 1690 ret = connector_status_connected;
52220085
CW		 1691 else
1692 ret = connector_status_disconnected;
1693
13946743
CW		 1694 kfree(edid);
1695 } else
1696 ret = connector_status_connected;
1697 }
14571b4c
ZW		 1698
1699 /* May update encoder flag for like clock for SDVO TV, etc.*/
1700 if (ret == connector_status_connected) {
ea5b213a
CW		 1701 intel_sdvo->is_tv = false;
1702 intel_sdvo->is_lvds = false;
14571b4c 1703
09ede541 1704 if (response & SDVO_TV_MASK)
ea5b213a 1705 intel_sdvo->is_tv = true;
14571b4c 1706 if (response & SDVO_LVDS_MASK)
8545423a 1707 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1708 }
14571b4c
ZW		 1709
1710 return ret;
79e53945
JB		 1711}
1712
e2f0ba97 1713static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1714{
ff482d83 1715 struct edid *edid;
79e53945
JB		 1716
1717 /* set the bus switch and get the modes */
e957d772 1718 edid = intel_sdvo_get_edid(connector);
79e53945 1719
57cdaf90
KP		 1720 /*
1721 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1722 * link between analog and digital outputs. So, if the regular SDVO
1723 * DDC fails, check to see if the analog output is disconnected, in
1724 * which case we'll look there for the digital DDC data.
e2f0ba97 1725 */
f899fc64
CW		 1726 if (edid == NULL)
1727 edid = intel_sdvo_get_analog_edid(connector);
1728
ff482d83 1729 if (edid != NULL) {
52220085
CW		 1730 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1731 edid)) {
0c1dab89
CW		 1732 drm_mode_connector_update_edid_property(connector, edid);
1733 drm_add_edid_modes(connector, edid);
1734 }
13946743 1735
ff482d83 1736 kfree(edid);
e2f0ba97 1737 }
e2f0ba97
JB		 1738}
1739
1740/*
1741 * Set of SDVO TV modes.
1742 * Note! This is in reply order (see loop in get_tv_modes).
1743 * XXX: all 60Hz refresh?
1744 */
b1f559ec 1745static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1746 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1747 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1748 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1749 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1750 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1751 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1752 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1753 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1754 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1755 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1756 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1757 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1758 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1759 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1760 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1761 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1762 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1763 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1764 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1765 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1766 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1767 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1768 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1769 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1770 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1771 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1772 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1773 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1774 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1775 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1776 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1777 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1778 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1779 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1780 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1781 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1782 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1783 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1784 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1785 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1786 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1787 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1788 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1789 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1790 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1791 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1792 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1793 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1794 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1795 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1796 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1797 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1798 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1799 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1800 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1801 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1802 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1803};
1804
1805static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1806{
df0e9248 1807 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1808 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1809 uint32_t reply = 0, format_map = 0;
1810 int i;
e2f0ba97
JB		 1811
1812 /* Read the list of supported input resolutions for the selected TV
1813 * format.
1814 */
40039750 1815 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1816 memcpy(&tv_res, &format_map,
32aad86f 1817 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1818
32aad86f
CW		 1819 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1820 return;
ce6feabd 1821
32aad86f 1822 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1823 if (!intel_sdvo_write_cmd(intel_sdvo,
1824 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1825 &tv_res, sizeof(tv_res)))
1826 return;
1827 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1828 return;
1829
1830 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1831 if (reply & (1 << i)) {
1832 struct drm_display_mode *nmode;
1833 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1834 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1835 if (nmode)
1836 drm_mode_probed_add(connector, nmode);
1837 }
e2f0ba97
JB		 1838}
1839
7086c87f
ML		 1840static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1841{
df0e9248 1842 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1843 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1844 struct drm_display_mode *newmode;
7086c87f
ML		 1845
1846 /*
1847 * Attempt to get the mode list from DDC.
1848 * Assume that the preferred modes are
1849 * arranged in priority order.
1850 */
f899fc64 1851 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1852 if (list_empty(&connector->probed_modes) == false)
12682a97 1853 goto end;
7086c87f
ML		 1854
1855 /* Fetch modes from VBT */
41aa3448 1856 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
7086c87f 1857 newmode = drm_mode_duplicate(connector->dev,
41aa3448 1858 dev_priv->vbt.sdvo_lvds_vbt_mode);
7086c87f
ML		 1859 if (newmode != NULL) {
1860 /* Guarantee the mode is preferred */
1861 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1862 DRM_MODE_TYPE_DRIVER);
1863 drm_mode_probed_add(connector, newmode);
1864 }
1865 }
12682a97 1866
1867end:
1868 list_for_each_entry(newmode, &connector->probed_modes, head) {
1869 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1870 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1871 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1872
8545423a 1873 intel_sdvo->is_lvds = true;
12682a97 1874 break;
1875 }
1876 }
1877
7086c87f
ML		 1878}
1879
e2f0ba97
JB		 1880static int intel_sdvo_get_modes(struct drm_connector *connector)
1881{
615fb93f 1882 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1883
615fb93f 1884 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1885 intel_sdvo_get_tv_modes(connector);
615fb93f 1886 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1887 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1888 else
1889 intel_sdvo_get_ddc_modes(connector);
1890
32aad86f 1891 return !list_empty(&connector->probed_modes);
79e53945
JB		 1892}
1893
fcc8d672
CW		 1894static void
1895intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1896{
615fb93f 1897 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1898 struct drm_device *dev = connector->dev;
1899
c5521706
CW		 1900 if (intel_sdvo_connector->left)
1901 drm_property_destroy(dev, intel_sdvo_connector->left);
1902 if (intel_sdvo_connector->right)
1903 drm_property_destroy(dev, intel_sdvo_connector->right);
1904 if (intel_sdvo_connector->top)
1905 drm_property_destroy(dev, intel_sdvo_connector->top);
1906 if (intel_sdvo_connector->bottom)
1907 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1908 if (intel_sdvo_connector->hpos)
1909 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1910 if (intel_sdvo_connector->vpos)
1911 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1912 if (intel_sdvo_connector->saturation)
1913 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1914 if (intel_sdvo_connector->contrast)
1915 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1916 if (intel_sdvo_connector->hue)
1917 drm_property_destroy(dev, intel_sdvo_connector->hue);
1918 if (intel_sdvo_connector->sharpness)
1919 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1920 if (intel_sdvo_connector->flicker_filter)
1921 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1922 if (intel_sdvo_connector->flicker_filter_2d)
1923 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1924 if (intel_sdvo_connector->flicker_filter_adaptive)
1925 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1926 if (intel_sdvo_connector->tv_luma_filter)
1927 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1928 if (intel_sdvo_connector->tv_chroma_filter)
1929 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1930 if (intel_sdvo_connector->dot_crawl)
1931 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1932 if (intel_sdvo_connector->brightness)
1933 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1934}
1935
79e53945
JB		 1936static void intel_sdvo_destroy(struct drm_connector *connector)
1937{
615fb93f 1938 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1939
c5521706 1940 if (intel_sdvo_connector->tv_format)
ce6feabd 1941 drm_property_destroy(connector->dev,
c5521706 1942 intel_sdvo_connector->tv_format);
b9219c5e 1943
d2a82a6f 1944 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1945 drm_sysfs_connector_remove(connector);
1946 drm_connector_cleanup(connector);
4b745b1e 1947 kfree(intel_sdvo_connector);
79e53945
JB		 1948}
1949
1aad7ac0
CW		 1950static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1951{
1952 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1953 struct edid *edid;
1954 bool has_audio = false;
1955
1956 if (!intel_sdvo->is_hdmi)
1957 return false;
1958
1959 edid = intel_sdvo_get_edid(connector);
1960 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1961 has_audio = drm_detect_monitor_audio(edid);
38ab8a20 1962 kfree(edid);
1aad7ac0
CW		 1963
1964 return has_audio;
1965}
1966
ce6feabd
ZY		 1967static int
1968intel_sdvo_set_property(struct drm_connector *connector,
1969 struct drm_property *property,
1970 uint64_t val)
1971{
df0e9248 1972 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1973 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1974 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1975 uint16_t temp_value;
32aad86f
CW		 1976 uint8_t cmd;
1977 int ret;
ce6feabd 1978
662595df 1979 ret = drm_object_property_set_value(&connector->base, property, val);
32aad86f
CW		 1980 if (ret)
1981 return ret;
ce6feabd 1982
3f43c48d 1983 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1984 int i = val;
1985 bool has_audio;
1986
1987 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1988 return 0;
1989
1aad7ac0 1990 intel_sdvo_connector->force_audio = i;
7f36e7ed 1991
c3e5f67b 1992 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 1993 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1994 else
c3e5f67b 1995 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 1996
1aad7ac0 1997 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1998 return 0;
7f36e7ed 1999
1aad7ac0 2000 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 2001 goto done;
2002 }
2003
e953fd7b 2004 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 2005 bool old_auto = intel_sdvo->color_range_auto;
2006 uint32_t old_range = intel_sdvo->color_range;
2007
55bc60db
VS		 2008 switch (val) {
2009 case INTEL_BROADCAST_RGB_AUTO:
2010 intel_sdvo->color_range_auto = true;
2011 break;
2012 case INTEL_BROADCAST_RGB_FULL:
2013 intel_sdvo->color_range_auto = false;
2014 intel_sdvo->color_range = 0;
2015 break;
2016 case INTEL_BROADCAST_RGB_LIMITED:
2017 intel_sdvo->color_range_auto = false;
4f3a8bc7
PZ		 2018 /* FIXME: this bit is only valid when using TMDS
2019 * encoding and 8 bit per color mode. */
2020 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 2021 break;
2022 default:
2023 return -EINVAL;
2024 }
ae4edb80
DV		 2025
2026 if (old_auto == intel_sdvo->color_range_auto &&
2027 old_range == intel_sdvo->color_range)
2028 return 0;
2029
7f36e7ed
CW		 2030 goto done;
2031 }
2032
c5521706
CW		 2033#define CHECK_PROPERTY(name, NAME) \
2034 if (intel_sdvo_connector->name == property) { \
2035 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
2036 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
2037 cmd = SDVO_CMD_SET_##NAME; \
2038 intel_sdvo_connector->cur_##name = temp_value; \
2039 goto set_value; \
2040 }
2041
2042 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 2043 if (val >= TV_FORMAT_NUM)
2044 return -EINVAL;
2045
40039750 2046 if (intel_sdvo->tv_format_index ==
615fb93f 2047 intel_sdvo_connector->tv_format_supported[val])
32aad86f 2048 return 0;
ce6feabd 2049
40039750 2050 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 2051 goto done;
32aad86f 2052 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 2053 temp_value = val;
c5521706 2054 if (intel_sdvo_connector->left == property) {
662595df 2055 drm_object_property_set_value(&connector->base,
c5521706 2056 intel_sdvo_connector->right, val);
615fb93f 2057 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 2058 return 0;
b9219c5e 2059
615fb93f
CW		 2060 intel_sdvo_connector->left_margin = temp_value;
2061 intel_sdvo_connector->right_margin = temp_value;
2062 temp_value = intel_sdvo_connector->max_hscan -
c5521706 2063 intel_sdvo_connector->left_margin;
b9219c5e 2064 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2065 goto set_value;
2066 } else if (intel_sdvo_connector->right == property) {
662595df 2067 drm_object_property_set_value(&connector->base,
c5521706 2068 intel_sdvo_connector->left, val);
615fb93f 2069 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 2070 return 0;
b9219c5e 2071
615fb93f
CW		 2072 intel_sdvo_connector->left_margin = temp_value;
2073 intel_sdvo_connector->right_margin = temp_value;
2074 temp_value = intel_sdvo_connector->max_hscan -
2075 intel_sdvo_connector->left_margin;
b9219c5e 2076 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2077 goto set_value;
2078 } else if (intel_sdvo_connector->top == property) {
662595df 2079 drm_object_property_set_value(&connector->base,
c5521706 2080 intel_sdvo_connector->bottom, val);
615fb93f 2081 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 2082 return 0;
b9219c5e 2083
615fb93f
CW		 2084 intel_sdvo_connector->top_margin = temp_value;
2085 intel_sdvo_connector->bottom_margin = temp_value;
2086 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2087 intel_sdvo_connector->top_margin;
b9219c5e 2088 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2089 goto set_value;
2090 } else if (intel_sdvo_connector->bottom == property) {
662595df 2091 drm_object_property_set_value(&connector->base,
c5521706 2092 intel_sdvo_connector->top, val);
615fb93f 2093 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 2094 return 0;
2095
615fb93f
CW		 2096 intel_sdvo_connector->top_margin = temp_value;
2097 intel_sdvo_connector->bottom_margin = temp_value;
2098 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2099 intel_sdvo_connector->top_margin;
b9219c5e 2100 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2101 goto set_value;
2102 }
2103 CHECK_PROPERTY(hpos, HPOS)
2104 CHECK_PROPERTY(vpos, VPOS)
2105 CHECK_PROPERTY(saturation, SATURATION)
2106 CHECK_PROPERTY(contrast, CONTRAST)
2107 CHECK_PROPERTY(hue, HUE)
2108 CHECK_PROPERTY(brightness, BRIGHTNESS)
2109 CHECK_PROPERTY(sharpness, SHARPNESS)
2110 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
2111 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
2112 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
2113 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
2114 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 2115 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 2116 }
b9219c5e 2117
c5521706 2118 return -EINVAL; /* unknown property */
b9219c5e 2119
c5521706
CW		 2120set_value:
2121 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
2122 return -EIO;
b9219c5e 2123
b9219c5e 2124
c5521706 2125done:
c0c36b94
CW		 2126 if (intel_sdvo->base.base.crtc)
2127 intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
c5521706 2128
32aad86f 2129 return 0;
c5521706 2130#undef CHECK_PROPERTY
ce6feabd
ZY		 2131}
2132
79e53945 2133static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
b2cabb0e 2134 .dpms = intel_sdvo_dpms,
79e53945
JB		 2135 .detect = intel_sdvo_detect,
2136 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 2137 .set_property = intel_sdvo_set_property,
79e53945
JB		 2138 .destroy = intel_sdvo_destroy,
2139};
2140
2141static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2142 .get_modes = intel_sdvo_get_modes,
2143 .mode_valid = intel_sdvo_mode_valid,
df0e9248 2144 .best_encoder = intel_best_encoder,
79e53945
JB		 2145};
2146
b358d0a6 2147static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2148{
890f3359 2149 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 2150
ea5b213a 2151 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2152 drm_mode_destroy(encoder->dev,
ea5b213a 2153 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2154
e957d772 2155 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2156 intel_encoder_destroy(encoder);
79e53945
JB		 2157}
2158
2159static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2160 .destroy = intel_sdvo_enc_destroy,
2161};
2162
b66d8424
CW		 2163static void
2164intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2165{
2166 uint16_t mask = 0;
2167 unsigned int num_bits;
2168
2169 /* Make a mask of outputs less than or equal to our own priority in the
2170 * list.
2171 */
2172 switch (sdvo->controlled_output) {
2173 case SDVO_OUTPUT_LVDS1:
2174 mask |= SDVO_OUTPUT_LVDS1;
2175 case SDVO_OUTPUT_LVDS0:
2176 mask |= SDVO_OUTPUT_LVDS0;
2177 case SDVO_OUTPUT_TMDS1:
2178 mask |= SDVO_OUTPUT_TMDS1;
2179 case SDVO_OUTPUT_TMDS0:
2180 mask |= SDVO_OUTPUT_TMDS0;
2181 case SDVO_OUTPUT_RGB1:
2182 mask |= SDVO_OUTPUT_RGB1;
2183 case SDVO_OUTPUT_RGB0:
2184 mask |= SDVO_OUTPUT_RGB0;
2185 break;
2186 }
2187
2188 /* Count bits to find what number we are in the priority list. */
2189 mask &= sdvo->caps.output_flags;
2190 num_bits = hweight16(mask);
2191 /* If more than 3 outputs, default to DDC bus 3 for now. */
2192 if (num_bits > 3)
2193 num_bits = 3;
2194
2195 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2196 sdvo->ddc_bus = 1 << num_bits;
2197}
79e53945 2198
e2f0ba97
JB		 2199/**
2200 * Choose the appropriate DDC bus for control bus switch command for this
2201 * SDVO output based on the controlled output.
2202 *
2203 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2204 * outputs, then LVDS outputs.
2205 */
2206static void
b1083333 2207intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 2208 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 2209{
b1083333 2210 struct sdvo_device_mapping *mapping;
e2f0ba97 2211
eef4eacb 2212 if (sdvo->is_sdvob)
b1083333
AJ		 2213 mapping = &(dev_priv->sdvo_mappings[0]);
2214 else
2215 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 2216
b66d8424
CW		 2217 if (mapping->initialized)
2218 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2219 else
2220 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2221}
2222
e957d772
CW		 2223static void
2224intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
2225 struct intel_sdvo *sdvo, u32 reg)
2226{
2227 struct sdvo_device_mapping *mapping;
46eb3036 2228 u8 pin;
e957d772 2229
eef4eacb 2230 if (sdvo->is_sdvob)
e957d772
CW		 2231 mapping = &dev_priv->sdvo_mappings[0];
2232 else
2233 mapping = &dev_priv->sdvo_mappings[1];
2234
6cb1612a 2235 if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
e957d772 2236 pin = mapping->i2c_pin;
6cb1612a
JN		 2237 else
2238 pin = GMBUS_PORT_DPB;
e957d772 2239
6cb1612a
JN		 2240 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2241
2242 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2243 * our code totally fails once we start using gmbus. Hence fall back to
2244 * bit banging for now. */
2245 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2246}
2247
fbfcc4f3
JN		 2248/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2249static void
2250intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2251{
2252 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2253}
2254
e2f0ba97 2255static bool
e27d8538 2256intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2257{
97aaf910 2258 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2259}
2260
714605e4 2261static u8
eef4eacb 2262intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 2263{
2264 struct drm_i915_private *dev_priv = dev->dev_private;
2265 struct sdvo_device_mapping *my_mapping, *other_mapping;
2266
eef4eacb 2267 if (sdvo->is_sdvob) {
714605e4 2268 my_mapping = &dev_priv->sdvo_mappings[0];
2269 other_mapping = &dev_priv->sdvo_mappings[1];
2270 } else {
2271 my_mapping = &dev_priv->sdvo_mappings[1];
2272 other_mapping = &dev_priv->sdvo_mappings[0];
2273 }
2274
2275 /* If the BIOS described our SDVO device, take advantage of it. */
2276 if (my_mapping->slave_addr)
2277 return my_mapping->slave_addr;
2278
2279 /* If the BIOS only described a different SDVO device, use the
2280 * address that it isn't using.
2281 */
2282 if (other_mapping->slave_addr) {
2283 if (other_mapping->slave_addr == 0x70)
2284 return 0x72;
2285 else
2286 return 0x70;
2287 }
2288
2289 /* No SDVO device info is found for another DVO port,
2290 * so use mapping assumption we had before BIOS parsing.
2291 */
eef4eacb 2292 if (sdvo->is_sdvob)
714605e4 2293 return 0x70;
2294 else
2295 return 0x72;
2296}
2297
14571b4c 2298static void
df0e9248
CW		 2299intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2300 struct intel_sdvo *encoder)
14571b4c 2301{
df0e9248
CW		 2302 drm_connector_init(encoder->base.base.dev,
2303 &connector->base.base,
2304 &intel_sdvo_connector_funcs,
2305 connector->base.base.connector_type);
6070a4a9 2306
df0e9248
CW		 2307 drm_connector_helper_add(&connector->base.base,
2308 &intel_sdvo_connector_helper_funcs);
14571b4c 2309
8f4839e2 2310 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2311 connector->base.base.doublescan_allowed = 0;
2312 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2313 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2314
df0e9248
CW		 2315 intel_connector_attach_encoder(&connector->base, &encoder->base);
2316 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2317}
6070a4a9 2318
7f36e7ed 2319static void
55bc60db
VS		 2320intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2321 struct intel_sdvo_connector *connector)
7f36e7ed
CW		 2322{
2323 struct drm_device *dev = connector->base.base.dev;
2324
3f43c48d 2325 intel_attach_force_audio_property(&connector->base.base);
55bc60db 2326 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
e953fd7b 2327 intel_attach_broadcast_rgb_property(&connector->base.base);
55bc60db
VS		 2328 intel_sdvo->color_range_auto = true;
2329 }
7f36e7ed
CW		 2330}
2331
fb7a46f3 2332static bool
ea5b213a 2333intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2334{
4ef69c7a 2335 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2336 struct drm_connector *connector;
cc68c81a 2337 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2338 struct intel_connector *intel_connector;
615fb93f 2339 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2340
615fb93f
CW		 2341 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2342 if (!intel_sdvo_connector)
14571b4c
ZW		 2343 return false;
2344
14571b4c 2345 if (device == 0) {
ea5b213a 2346 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2347 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2348 } else if (device == 1) {
ea5b213a 2349 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2350 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2351 }
2352
615fb93f 2353 intel_connector = &intel_sdvo_connector->base;
14571b4c 2354 connector = &intel_connector->base;
5fa7ac9c
JN		 2355 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2356 intel_sdvo_connector->output_flag) {
5fa7ac9c 2357 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
cc68c81a
SF		 2358 /* Some SDVO devices have one-shot hotplug interrupts.
2359 * Ensure that they get re-enabled when an interrupt happens.
2360 */
2361 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2362 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2363 } else {
821450c6 2364 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2365 }
14571b4c
ZW		 2366 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2367 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2368
e27d8538 2369 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2370 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2371 intel_sdvo->is_hdmi = true;
14571b4c 2372 }
14571b4c 2373
df0e9248 2374 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221 2375 if (intel_sdvo->is_hdmi)
55bc60db 2376 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
14571b4c
ZW		 2377
2378 return true;
2379}
2380
2381static bool
ea5b213a 2382intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2383{
4ef69c7a
CW		 2384 struct drm_encoder *encoder = &intel_sdvo->base.base;
2385 struct drm_connector *connector;
2386 struct intel_connector *intel_connector;
2387 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2388
615fb93f
CW		 2389 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2390 if (!intel_sdvo_connector)
2391 return false;
14571b4c 2392
615fb93f 2393 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2394 connector = &intel_connector->base;
2395 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2396 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2397
4ef69c7a
CW		 2398 intel_sdvo->controlled_output |= type;
2399 intel_sdvo_connector->output_flag = type;
14571b4c 2400
4ef69c7a 2401 intel_sdvo->is_tv = true;
14571b4c 2402
df0e9248 2403 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2404
4ef69c7a 2405 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2406 goto err;
14571b4c 2407
4ef69c7a 2408 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2409 goto err;
14571b4c 2410
4ef69c7a 2411 return true;
32aad86f
CW		 2412
2413err:
123d5c01 2414 intel_sdvo_destroy(connector);
32aad86f 2415 return false;
14571b4c
ZW		 2416}
2417
2418static bool
ea5b213a 2419intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2420{
4ef69c7a
CW		 2421 struct drm_encoder *encoder = &intel_sdvo->base.base;
2422 struct drm_connector *connector;
2423 struct intel_connector *intel_connector;
2424 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2425
615fb93f
CW		 2426 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2427 if (!intel_sdvo_connector)
2428 return false;
14571b4c 2429
615fb93f 2430 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2431 connector = &intel_connector->base;
821450c6 2432 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2433 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2434 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2435
2436 if (device == 0) {
2437 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2438 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2439 } else if (device == 1) {
2440 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2441 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2442 }
2443
df0e9248
CW		 2444 intel_sdvo_connector_init(intel_sdvo_connector,
2445 intel_sdvo);
4ef69c7a 2446 return true;
14571b4c
ZW		 2447}
2448
2449static bool
ea5b213a 2450intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2451{
4ef69c7a
CW		 2452 struct drm_encoder *encoder = &intel_sdvo->base.base;
2453 struct drm_connector *connector;
2454 struct intel_connector *intel_connector;
2455 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2456
615fb93f
CW		 2457 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2458 if (!intel_sdvo_connector)
2459 return false;
14571b4c 2460
615fb93f
CW		 2461 intel_connector = &intel_sdvo_connector->base;
2462 connector = &intel_connector->base;
4ef69c7a
CW		 2463 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2464 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2465
2466 if (device == 0) {
2467 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2468 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2469 } else if (device == 1) {
2470 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2471 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2472 }
2473
df0e9248 2474 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2475 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2476 goto err;
2477
2478 return true;
2479
2480err:
123d5c01 2481 intel_sdvo_destroy(connector);
32aad86f 2482 return false;
14571b4c
ZW		 2483}
2484
2485static bool
ea5b213a 2486intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2487{
ea5b213a 2488 intel_sdvo->is_tv = false;
ea5b213a 2489 intel_sdvo->is_lvds = false;
fb7a46f3 2490
14571b4c 2491 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2492
14571b4c 2493 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2494 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2495 return false;
2496
2497 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2498 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2499 return false;
2500
2501 /* TV has no XXX1 function block */
a1f4b7ff 2502 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2503 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2504 return false;
2505
2506 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2507 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2508 return false;
fb7a46f3 2509
a0b1c7a5
CW		 2510 if (flags & SDVO_OUTPUT_YPRPB0)
2511 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2512 return false;
2513
14571b4c 2514 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2515 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2516 return false;
2517
2518 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2519 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2520 return false;
2521
2522 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2523 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2524 return false;
2525
2526 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2527 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2528 return false;
fb7a46f3 2529
14571b4c 2530 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2531 unsigned char bytes[2];
2532
ea5b213a
CW		 2533 intel_sdvo->controlled_output = 0;
2534 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2535 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2536 SDVO_NAME(intel_sdvo),
51c8b407 2537 bytes[0], bytes[1]);
14571b4c 2538 return false;
fb7a46f3 2539 }
27f8227b 2540 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2541
14571b4c 2542 return true;
fb7a46f3 2543}
2544
d0ddfbd3
JN		 2545static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2546{
2547 struct drm_device *dev = intel_sdvo->base.base.dev;
2548 struct drm_connector *connector, *tmp;
2549
2550 list_for_each_entry_safe(connector, tmp,
2551 &dev->mode_config.connector_list, head) {
2552 if (intel_attached_encoder(connector) == &intel_sdvo->base)
2553 intel_sdvo_destroy(connector);
2554 }
2555}
2556
32aad86f
CW		 2557static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2558 struct intel_sdvo_connector *intel_sdvo_connector,
2559 int type)
ce6feabd 2560{
4ef69c7a 2561 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2562 struct intel_sdvo_tv_format format;
2563 uint32_t format_map, i;
ce6feabd 2564
32aad86f
CW		 2565 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2566 return false;
ce6feabd 2567
1a3665c8 2568 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2569 if (!intel_sdvo_get_value(intel_sdvo,
2570 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2571 &format, sizeof(format)))
2572 return false;
ce6feabd 2573
32aad86f 2574 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2575
2576 if (format_map == 0)
32aad86f 2577 return false;
ce6feabd 2578
615fb93f 2579 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2580 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2581 if (format_map & (1 << i))
2582 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2583
2584
c5521706 2585 intel_sdvo_connector->tv_format =
32aad86f
CW		 2586 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2587 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2588 if (!intel_sdvo_connector->tv_format)
fcc8d672 2589 return false;
ce6feabd 2590
615fb93f 2591 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2592 drm_property_add_enum(
c5521706 2593 intel_sdvo_connector->tv_format, i,
40039750 2594 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2595
40039750 2596 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
662595df 2597 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
c5521706 2598 intel_sdvo_connector->tv_format, 0);
32aad86f 2599 return true;
ce6feabd
ZY		 2600
2601}
2602
c5521706
CW		 2603#define ENHANCEMENT(name, NAME) do { \
2604 if (enhancements.name) { \
2605 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2606 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2607 return false; \
2608 intel_sdvo_connector->max_##name = data_value[0]; \
2609 intel_sdvo_connector->cur_##name = response; \
2610 intel_sdvo_connector->name = \
d9bc3c02 2611 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2612 if (!intel_sdvo_connector->name) return false; \
662595df 2613 drm_object_attach_property(&connector->base, \
c5521706
CW		 2614 intel_sdvo_connector->name, \
2615 intel_sdvo_connector->cur_##name); \
2616 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2617 data_value[0], data_value[1], response); \
2618 } \
0206e353 2619} while (0)
c5521706
CW		 2620
2621static bool
2622intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2623 struct intel_sdvo_connector *intel_sdvo_connector,
2624 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2625{
4ef69c7a 2626 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2627 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2628 uint16_t response, data_value[2];
2629
c5521706
CW		 2630 /* when horizontal overscan is supported, Add the left/right property */
2631 if (enhancements.overscan_h) {
2632 if (!intel_sdvo_get_value(intel_sdvo,
2633 SDVO_CMD_GET_MAX_OVERSCAN_H,
2634 &data_value, 4))
2635 return false;
32aad86f 2636
c5521706
CW		 2637 if (!intel_sdvo_get_value(intel_sdvo,
2638 SDVO_CMD_GET_OVERSCAN_H,
2639 &response, 2))
2640 return false;
fcc8d672 2641
c5521706
CW		 2642 intel_sdvo_connector->max_hscan = data_value[0];
2643 intel_sdvo_connector->left_margin = data_value[0] - response;
2644 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2645 intel_sdvo_connector->left =
d9bc3c02 2646 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2647 if (!intel_sdvo_connector->left)
2648 return false;
fcc8d672 2649
662595df 2650 drm_object_attach_property(&connector->base,
c5521706
CW		 2651 intel_sdvo_connector->left,
2652 intel_sdvo_connector->left_margin);
fcc8d672 2653
c5521706 2654 intel_sdvo_connector->right =
d9bc3c02 2655 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2656 if (!intel_sdvo_connector->right)
2657 return false;
32aad86f 2658
662595df 2659 drm_object_attach_property(&connector->base,
c5521706
CW		 2660 intel_sdvo_connector->right,
2661 intel_sdvo_connector->right_margin);
2662 DRM_DEBUG_KMS("h_overscan: max %d, "
2663 "default %d, current %d\n",
2664 data_value[0], data_value[1], response);
2665 }
32aad86f 2666
c5521706
CW		 2667 if (enhancements.overscan_v) {
2668 if (!intel_sdvo_get_value(intel_sdvo,
2669 SDVO_CMD_GET_MAX_OVERSCAN_V,
2670 &data_value, 4))
2671 return false;
fcc8d672 2672
c5521706
CW		 2673 if (!intel_sdvo_get_value(intel_sdvo,
2674 SDVO_CMD_GET_OVERSCAN_V,
2675 &response, 2))
2676 return false;
32aad86f 2677
c5521706
CW		 2678 intel_sdvo_connector->max_vscan = data_value[0];
2679 intel_sdvo_connector->top_margin = data_value[0] - response;
2680 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2681 intel_sdvo_connector->top =
d9bc3c02
SH		 2682 drm_property_create_range(dev, 0,
2683 "top_margin", 0, data_value[0]);
c5521706
CW		 2684 if (!intel_sdvo_connector->top)
2685 return false;
32aad86f 2686
662595df 2687 drm_object_attach_property(&connector->base,
c5521706
CW		 2688 intel_sdvo_connector->top,
2689 intel_sdvo_connector->top_margin);
fcc8d672 2690
c5521706 2691 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2692 drm_property_create_range(dev, 0,
2693 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2694 if (!intel_sdvo_connector->bottom)
2695 return false;
32aad86f 2696
662595df 2697 drm_object_attach_property(&connector->base,
c5521706
CW		 2698 intel_sdvo_connector->bottom,
2699 intel_sdvo_connector->bottom_margin);
2700 DRM_DEBUG_KMS("v_overscan: max %d, "
2701 "default %d, current %d\n",
2702 data_value[0], data_value[1], response);
2703 }
32aad86f 2704
c5521706
CW		 2705 ENHANCEMENT(hpos, HPOS);
2706 ENHANCEMENT(vpos, VPOS);
2707 ENHANCEMENT(saturation, SATURATION);
2708 ENHANCEMENT(contrast, CONTRAST);
2709 ENHANCEMENT(hue, HUE);
2710 ENHANCEMENT(sharpness, SHARPNESS);
2711 ENHANCEMENT(brightness, BRIGHTNESS);
2712 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2713 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2714 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2715 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2716 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2717
e044218a
CW		 2718 if (enhancements.dot_crawl) {
2719 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2720 return false;
2721
2722 intel_sdvo_connector->max_dot_crawl = 1;
2723 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2724 intel_sdvo_connector->dot_crawl =
d9bc3c02 2725 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2726 if (!intel_sdvo_connector->dot_crawl)
2727 return false;
2728
662595df 2729 drm_object_attach_property(&connector->base,
e044218a
CW		 2730 intel_sdvo_connector->dot_crawl,
2731 intel_sdvo_connector->cur_dot_crawl);
2732 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2733 }
2734
c5521706
CW		 2735 return true;
2736}
32aad86f 2737
c5521706
CW		 2738static bool
2739intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2740 struct intel_sdvo_connector *intel_sdvo_connector,
2741 struct intel_sdvo_enhancements_reply enhancements)
2742{
4ef69c7a 2743 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2744 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2745 uint16_t response, data_value[2];
32aad86f 2746
c5521706 2747 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2748
c5521706
CW		 2749 return true;
2750}
2751#undef ENHANCEMENT
32aad86f 2752
c5521706
CW		 2753static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2754 struct intel_sdvo_connector *intel_sdvo_connector)
2755{
2756 union {
2757 struct intel_sdvo_enhancements_reply reply;
2758 uint16_t response;
2759 } enhancements;
32aad86f 2760
1a3665c8
CW		 2761 BUILD_BUG_ON(sizeof(enhancements) != 2);
2762
cf9a2f3a
CW		 2763 enhancements.response = 0;
2764 intel_sdvo_get_value(intel_sdvo,
2765 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2766 &enhancements, sizeof(enhancements));
c5521706
CW		 2767 if (enhancements.response == 0) {
2768 DRM_DEBUG_KMS("No enhancement is supported\n");
2769 return true;
b9219c5e 2770 }
32aad86f 2771
c5521706
CW		 2772 if (IS_TV(intel_sdvo_connector))
2773 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2774 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2775 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2776 else
2777 return true;
e957d772
CW		 2778}
2779
2780static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2781 struct i2c_msg *msgs,
2782 int num)
2783{
2784 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2785
e957d772
CW		 2786 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2787 return -EIO;
2788
2789 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2790}
2791
2792static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2793{
2794 struct intel_sdvo *sdvo = adapter->algo_data;
2795 return sdvo->i2c->algo->functionality(sdvo->i2c);
2796}
2797
2798static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2799 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2800 .functionality = intel_sdvo_ddc_proxy_func
2801};
2802
2803static bool
2804intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2805 struct drm_device *dev)
2806{
2807 sdvo->ddc.owner = THIS_MODULE;
2808 sdvo->ddc.class = I2C_CLASS_DDC;
2809 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2810 sdvo->ddc.dev.parent = &dev->pdev->dev;
2811 sdvo->ddc.algo_data = sdvo;
2812 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2813
2814 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2815}
2816
eef4eacb 2817bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2818{
b01f2c3a 2819 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2820 struct intel_encoder *intel_encoder;
ea5b213a 2821 struct intel_sdvo *intel_sdvo;
084b612e 2822 u32 hotplug_mask;
79e53945 2823 int i;
ea5b213a
CW		 2824 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2825 if (!intel_sdvo)
7d57382e 2826 return false;
79e53945 2827
56184e3d 2828 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2829 intel_sdvo->is_sdvob = is_sdvob;
2830 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2831 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
fbfcc4f3
JN		 2832 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
2833 goto err_i2c_bus;
e957d772 2834
56184e3d 2835 /* encoder type will be decided later */
ea5b213a 2836 intel_encoder = &intel_sdvo->base;
21d40d37 2837 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2838 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2839
79e53945
JB		 2840 /* Read the regs to test if we can talk to the device */
2841 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2842 u8 byte;
2843
2844 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2845 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2846 SDVO_NAME(intel_sdvo));
f899fc64 2847 goto err;
79e53945
JB		 2848 }
2849 }
2850
084b612e
CW		 2851 hotplug_mask = 0;
2852 if (IS_G4X(dev)) {
2853 hotplug_mask = intel_sdvo->is_sdvob ?
2854 SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X;
2855 } else if (IS_GEN4(dev)) {
2856 hotplug_mask = intel_sdvo->is_sdvob ?
2857 SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965;
2858 } else {
2859 hotplug_mask = intel_sdvo->is_sdvob ?
2860 SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
2861 }
619ac3b7 2862
4f770a5b
EE		 2863 /* Only enable the hotplug irq if we need it, to work around noisy
2864 * hotplug lines.
2865 */
1d843f9d
EE		 2866 if (intel_sdvo->hotplug_active)
2867 intel_encoder->hpd_pin = HPD_SDVO_B ? HPD_SDVO_B : HPD_SDVO_C;
2868
6cc5f341 2869 intel_encoder->compute_config = intel_sdvo_compute_config;
ce22c320 2870 intel_encoder->disable = intel_disable_sdvo;
6cc5f341 2871 intel_encoder->mode_set = intel_sdvo_mode_set;
ce22c320 2872 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 2873 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
045ac3b5 2874 intel_encoder->get_config = intel_sdvo_get_config;
ce22c320 2875
af901ca1 2876 /* In default case sdvo lvds is false */
32aad86f 2877 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2878 goto err;
79e53945 2879
ea5b213a
CW		 2880 if (intel_sdvo_output_setup(intel_sdvo,
2881 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 2882 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2883 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 2884 /* Output_setup can leave behind connectors! */
2885 goto err_output;
79e53945
JB		 2886 }
2887
e506d6fd
DV		 2888 /*
2889 * Cloning SDVO with anything is often impossible, since the SDVO
2890 * encoder can request a special input timing mode. And even if that's
2891 * not the case we have evidence that cloning a plain unscaled mode with
2892 * VGA doesn't really work. Furthermore the cloning flags are way too
2893 * simplistic anyway to express such constraints, so just give up on
2894 * cloning for SDVO encoders.
2895 */
2896 intel_sdvo->base.cloneable = false;
2897
ea5b213a 2898 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2899
79e53945 2900 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2901 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 2902 goto err_output;
79e53945 2903
32aad86f
CW		 2904 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2905 &intel_sdvo->pixel_clock_min,
2906 &intel_sdvo->pixel_clock_max))
d0ddfbd3 2907 goto err_output;
79e53945 2908
8a4c47f3 2909 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2910 "clock range %dMHz - %dMHz, "
2911 "input 1: %c, input 2: %c, "
2912 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2913 SDVO_NAME(intel_sdvo),
2914 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2915 intel_sdvo->caps.device_rev_id,
2916 intel_sdvo->pixel_clock_min / 1000,
2917 intel_sdvo->pixel_clock_max / 1000,
2918 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2919 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2920 /* check currently supported outputs */
ea5b213a 2921 intel_sdvo->caps.output_flags &
79e53945 2922 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2923 intel_sdvo->caps.output_flags &
79e53945 2924 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2925 return true;
79e53945 2926
d0ddfbd3
JN		 2927err_output:
2928 intel_sdvo_output_cleanup(intel_sdvo);
2929
f899fc64 2930err:
373a3cf7 2931 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2932 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 2933err_i2c_bus:
2934 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 2935 kfree(intel_sdvo);
79e53945 2936
7d57382e 2937 return false;
79e53945 2938}
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