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Merge tag 'drm-misc-next-2017-05-16' of git://anongit.freedesktop.org/git/drm-misc...
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7 32#include <drm/drmP.h>
c6f95f27 33#include <drm/drm_atomic_helper.h>
760285e7
DH		 34#include <drm/drm_crtc.h>
35#include <drm/drm_edid.h>
ea5b213a 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945
JB		 38#include "i915_drv.h"
39#include "intel_sdvo_regs.h"
40
14571b4c
ZW		 41#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 44#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 45
46#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 47 SDVO_TV_MASK)
14571b4c
ZW		 48
49#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 50#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 51#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 52#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 53#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 54
79e53945 55
4d9194de 56static const char * const tv_format_names[] = {
ce6feabd
ZY		 57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64};
65
53abb679 66#define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)
ce6feabd 67
ea5b213a
CW		 68struct intel_sdvo {
69 struct intel_encoder base;
70
f899fc64 71 struct i2c_adapter *i2c;
f9c10a9b 72 u8 slave_addr;
e2f0ba97 73
e957d772
CW		 74 struct i2c_adapter ddc;
75
e2f0ba97 76 /* Register for the SDVO device: SDVOB or SDVOC */
f0f59a00 77 i915_reg_t sdvo_reg;
79e53945 78
e2f0ba97
JB		 79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
79e53945 81
e2f0ba97
JB		 82 /*
83 * Capabilities of the SDVO device returned by
19d415a2 84 * intel_sdvo_get_capabilities()
e2f0ba97 85 */
79e53945 86 struct intel_sdvo_caps caps;
e2f0ba97
JB		 87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 89 int pixel_clock_min, pixel_clock_max;
90
fb7a46f3 91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
cc68c81a
SF		 97 /*
98 * Hotplug activation bits for this device
99 */
5fa7ac9c 100 uint16_t hotplug_active;
cc68c81a 101
e953fd7b
CW		 102 /**
103 * This is used to select the color range of RBG outputs in HDMI mode.
104 * It is only valid when using TMDS encoding and 8 bit per color mode.
105 */
106 uint32_t color_range;
55bc60db 107 bool color_range_auto;
e953fd7b 108
e2f0ba97
JB		 109 /**
110 * This is set if we're going to treat the device as TV-out.
111 *
112 * While we have these nice friendly flags for output types that ought
113 * to decide this for us, the S-Video output on our HDMI+S-Video card
114 * shows up as RGB1 (VGA).
115 */
116 bool is_tv;
117
2a5c0832 118 enum port port;
eef4eacb 119
ce6feabd 120 /* This is for current tv format name */
40039750 121 int tv_format_index;
ce6feabd 122
e2f0ba97
JB		 123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
da79de97
CW		 127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
abedc077 129 bool rgb_quant_range_selectable;
12682a97 130
7086c87f 131 /**
6c9547ff
CW		 132 * This is set if we detect output of sdvo device as LVDS and
133 * have a valid fixed mode to use with the panel.
7086c87f
ML		 134 */
135 bool is_lvds;
e2f0ba97 136
12682a97 137 /**
138 * This is sdvo fixed pannel mode pointer
139 */
140 struct drm_display_mode *sdvo_lvds_fixed_mode;
141
c751ce4f 142 /* DDC bus used by this SDVO encoder */
e2f0ba97 143 uint8_t ddc_bus;
e751823d
EE		 144
145 /*
146 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
147 */
148 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 149};
150
151struct intel_sdvo_connector {
615fb93f
CW		 152 struct intel_connector base;
153
14571b4c
ZW		 154 /* Mark the type of connector */
155 uint16_t output_flag;
156
c3e5f67b 157 enum hdmi_force_audio force_audio;
7f36e7ed 158
14571b4c 159 /* This contains all current supported TV format */
40039750 160 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 161 int format_supported_num;
c5521706 162 struct drm_property *tv_format;
14571b4c 163
b9219c5e 164 /* add the property for the SDVO-TV */
c5521706
CW		 165 struct drm_property *left;
166 struct drm_property *right;
167 struct drm_property *top;
168 struct drm_property *bottom;
169 struct drm_property *hpos;
170 struct drm_property *vpos;
171 struct drm_property *contrast;
172 struct drm_property *saturation;
173 struct drm_property *hue;
174 struct drm_property *sharpness;
175 struct drm_property *flicker_filter;
176 struct drm_property *flicker_filter_adaptive;
177 struct drm_property *flicker_filter_2d;
178 struct drm_property *tv_chroma_filter;
179 struct drm_property *tv_luma_filter;
e044218a 180 struct drm_property *dot_crawl;
b9219c5e
ZY		 181
182 /* add the property for the SDVO-TV/LVDS */
c5521706 183 struct drm_property *brightness;
b9219c5e
ZY		 184
185 /* Add variable to record current setting for the above property */
186 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 187
b9219c5e
ZY		 188 /* this is to get the range of margin.*/
189 u32 max_hscan, max_vscan;
190 u32 max_hpos, cur_hpos;
191 u32 max_vpos, cur_vpos;
192 u32 cur_brightness, max_brightness;
193 u32 cur_contrast, max_contrast;
194 u32 cur_saturation, max_saturation;
195 u32 cur_hue, max_hue;
c5521706
CW		 196 u32 cur_sharpness, max_sharpness;
197 u32 cur_flicker_filter, max_flicker_filter;
198 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
199 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
200 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
201 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 202 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 203};
204
8aca63aa 205static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
ea5b213a 206{
8aca63aa 207 return container_of(encoder, struct intel_sdvo, base);
ea5b213a
CW		 208}
209
df0e9248
CW		 210static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
211{
8aca63aa 212 return to_sdvo(intel_attached_encoder(connector));
df0e9248
CW		 213}
214
615fb93f
CW		 215static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
216{
217 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
218}
219
fb7a46f3 220static bool
ea5b213a 221intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 222static bool
223intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
224 struct intel_sdvo_connector *intel_sdvo_connector,
225 int type);
226static bool
227intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
228 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 229
79e53945
JB		 230/**
231 * Writes the SDVOB or SDVOC with the given value, but always writes both
232 * SDVOB and SDVOC to work around apparent hardware issues (according to
233 * comments in the BIOS).
234 */
ea5b213a 235static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 236{
4ef69c7a 237 struct drm_device *dev = intel_sdvo->base.base.dev;
fac5e23e 238 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945
JB		 239 u32 bval = val, cval = val;
240 int i;
241
2a5c0832 242 if (HAS_PCH_SPLIT(dev_priv)) {
ea5b213a 243 I915_WRITE(intel_sdvo->sdvo_reg, val);
abab6311 244 POSTING_READ(intel_sdvo->sdvo_reg);
e8504ee2
VS		 245 /*
246 * HW workaround, need to write this twice for issue
247 * that may result in first write getting masked.
248 */
6e266956 249 if (HAS_PCH_IBX(dev_priv)) {
e8504ee2
VS		 250 I915_WRITE(intel_sdvo->sdvo_reg, val);
251 POSTING_READ(intel_sdvo->sdvo_reg);
252 }
461ed3ca
ZY		 253 return;
254 }
255
2a5c0832 256 if (intel_sdvo->port == PORT_B)
e2debe91
PZ		 257 cval = I915_READ(GEN3_SDVOC);
258 else
259 bval = I915_READ(GEN3_SDVOB);
260
79e53945
JB		 261 /*
262 * Write the registers twice for luck. Sometimes,
263 * writing them only once doesn't appear to 'stick'.
264 * The BIOS does this too. Yay, magic
265 */
266 for (i = 0; i < 2; i++)
267 {
e2debe91 268 I915_WRITE(GEN3_SDVOB, bval);
abab6311 269 POSTING_READ(GEN3_SDVOB);
e2debe91 270 I915_WRITE(GEN3_SDVOC, cval);
abab6311 271 POSTING_READ(GEN3_SDVOC);
79e53945
JB		 272 }
273}
274
32aad86f 275static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 276{
79e53945
JB		 277 struct i2c_msg msgs[] = {
278 {
e957d772 279 .addr = intel_sdvo->slave_addr,
79e53945
JB		 280 .flags = 0,
281 .len = 1,
e957d772 282 .buf = &addr,
79e53945
JB		 283 },
284 {
e957d772 285 .addr = intel_sdvo->slave_addr,
79e53945
JB		 286 .flags = I2C_M_RD,
287 .len = 1,
e957d772 288 .buf = ch,
79e53945
JB		 289 }
290 };
32aad86f 291 int ret;
79e53945 292
f899fc64 293 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 294 return true;
79e53945 295
8a4c47f3 296 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 297 return false;
298}
299
79e53945
JB		 300#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
301/** Mapping of command numbers to names, for debug output */
005568be 302static const struct _sdvo_cmd_name {
e2f0ba97 303 u8 cmd;
2e88e40b 304 const char *name;
579627ea 305} __attribute__ ((packed)) sdvo_cmd_names[] = {
0206e353
AJ		 306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
349
350 /* Add the op code for SDVO enhancements */
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
395
396 /* HDMI op code */
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
410 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
411 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
412 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
413 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
414 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
415 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
416 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 417};
418
2a5c0832 419#define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
79e53945 420
ea5b213a 421static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 422 const void *args, int args_len)
79e53945 423{
84fcb469
DV		 424 int i, pos = 0;
425#define BUF_LEN 256
426 char buffer[BUF_LEN];
427
428#define BUF_PRINT(args...) \
429 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
430
79e53945 431
84fcb469
DV		 432 for (i = 0; i < args_len; i++) {
433 BUF_PRINT("%02X ", ((u8 *)args)[i]);
434 }
435 for (; i < 8; i++) {
436 BUF_PRINT(" ");
437 }
04ad327f 438 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 439 if (cmd == sdvo_cmd_names[i].cmd) {
84fcb469 440 BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 441 break;
442 }
443 }
84fcb469
DV		 444 if (i == ARRAY_SIZE(sdvo_cmd_names)) {
445 BUF_PRINT("(%02X)", cmd);
446 }
447 BUG_ON(pos >= BUF_LEN - 1);
448#undef BUF_PRINT
449#undef BUF_LEN
450
451 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
79e53945 452}
79e53945 453
4d9194de 454static const char * const cmd_status_names[] = {
e957d772
CW		 455 "Power on",
456 "Success",
457 "Not supported",
458 "Invalid arg",
459 "Pending",
460 "Target not specified",
461 "Scaling not supported"
462};
463
32aad86f
CW		 464static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
465 const void *args, int args_len)
79e53945 466{
3bf3f452
BW		 467 u8 *buf, status;
468 struct i2c_msg *msgs;
469 int i, ret = true;
470
0274df3e 471 /* Would be simpler to allocate both in one go ? */
5c67eeb6 472 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3bf3f452
BW		 473 if (!buf)
474 return false;
475
476 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e
AC		 477 if (!msgs) {
478 kfree(buf);
3bf3f452 479 return false;
0274df3e 480 }
79e53945 481
ea5b213a 482 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 483
484 for (i = 0; i < args_len; i++) {
e957d772
CW		 485 msgs[i].addr = intel_sdvo->slave_addr;
486 msgs[i].flags = 0;
487 msgs[i].len = 2;
488 msgs[i].buf = buf + 2 *i;
489 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
490 buf[2*i + 1] = ((u8*)args)[i];
491 }
492 msgs[i].addr = intel_sdvo->slave_addr;
493 msgs[i].flags = 0;
494 msgs[i].len = 2;
495 msgs[i].buf = buf + 2*i;
496 buf[2*i + 0] = SDVO_I2C_OPCODE;
497 buf[2*i + 1] = cmd;
498
499 /* the following two are to read the response */
500 status = SDVO_I2C_CMD_STATUS;
501 msgs[i+1].addr = intel_sdvo->slave_addr;
502 msgs[i+1].flags = 0;
503 msgs[i+1].len = 1;
504 msgs[i+1].buf = &status;
505
506 msgs[i+2].addr = intel_sdvo->slave_addr;
507 msgs[i+2].flags = I2C_M_RD;
508 msgs[i+2].len = 1;
509 msgs[i+2].buf = &status;
510
511 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
512 if (ret < 0) {
513 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 514 ret = false;
515 goto out;
e957d772
CW		 516 }
517 if (ret != i+3) {
518 /* failure in I2C transfer */
519 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 520 ret = false;
e957d772
CW		 521 }
522
3bf3f452
BW		 523out:
524 kfree(msgs);
525 kfree(buf);
526 return ret;
79e53945
JB		 527}
528
b5c616a7
CW		 529static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
530 void *response, int response_len)
79e53945 531{
fc37381c 532 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 533 u8 status;
84fcb469
DV		 534 int i, pos = 0;
535#define BUF_LEN 256
536 char buffer[BUF_LEN];
79e53945 537
d121a5d2 538
b5c616a7
CW		 539 /*
540 * The documentation states that all commands will be
541 * processed within 15µs, and that we need only poll
542 * the status byte a maximum of 3 times in order for the
543 * command to be complete.
544 *
545 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 546 *
547 * Also beware that the first response by many devices is to
548 * reply PENDING and stall for time. TVs are notorious for
549 * requiring longer than specified to complete their replies.
550 * Originally (in the DDX long ago), the delay was only ever 15ms
551 * with an additional delay of 30ms applied for TVs added later after
552 * many experiments. To accommodate both sets of delays, we do a
553 * sequence of slow checks if the device is falling behind and fails
554 * to reply within 5*15µs.
b5c616a7 555 */
d121a5d2
CW		 556 if (!intel_sdvo_read_byte(intel_sdvo,
557 SDVO_I2C_CMD_STATUS,
558 &status))
559 goto log_fail;
560
1ad87e72 561 while ((status == SDVO_CMD_STATUS_PENDING ||
46a3f4a3 562 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
fc37381c
CW		 563 if (retry < 10)
564 msleep(15);
565 else
566 udelay(15);
567
b5c616a7
CW		 568 if (!intel_sdvo_read_byte(intel_sdvo,
569 SDVO_I2C_CMD_STATUS,
570 &status))
d121a5d2
CW		 571 goto log_fail;
572 }
b5c616a7 573
84fcb469
DV		 574#define BUF_PRINT(args...) \
575 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
576
79e53945 577 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
84fcb469 578 BUF_PRINT("(%s)", cmd_status_names[status]);
79e53945 579 else
84fcb469 580 BUF_PRINT("(??? %d)", status);
79e53945 581
b5c616a7
CW		 582 if (status != SDVO_CMD_STATUS_SUCCESS)
583 goto log_fail;
79e53945 584
b5c616a7
CW		 585 /* Read the command response */
586 for (i = 0; i < response_len; i++) {
587 if (!intel_sdvo_read_byte(intel_sdvo,
588 SDVO_I2C_RETURN_0 + i,
589 &((u8 *)response)[i]))
590 goto log_fail;
84fcb469 591 BUF_PRINT(" %02X", ((u8 *)response)[i]);
b5c616a7 592 }
84fcb469
DV		 593 BUG_ON(pos >= BUF_LEN - 1);
594#undef BUF_PRINT
595#undef BUF_LEN
596
597 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
b5c616a7 598 return true;
79e53945 599
b5c616a7 600log_fail:
84fcb469 601 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
b5c616a7 602 return false;
79e53945
JB		 603}
604
5e7234c9 605static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
79e53945 606{
aad941d5 607 if (adjusted_mode->crtc_clock >= 100000)
79e53945 608 return 1;
aad941d5 609 else if (adjusted_mode->crtc_clock >= 50000)
79e53945
JB		 610 return 2;
611 else
612 return 4;
613}
614
e957d772
CW		 615static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
616 u8 ddc_bus)
79e53945 617{
d121a5d2 618 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 619 return intel_sdvo_write_cmd(intel_sdvo,
620 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
621 &ddc_bus, 1);
79e53945
JB		 622}
623
32aad86f 624static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 625{
d121a5d2
CW		 626 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
627 return false;
628
629 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 630}
79e53945 631
32aad86f
CW		 632static bool
633intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
634{
635 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
636 return false;
79e53945 637
32aad86f
CW		 638 return intel_sdvo_read_response(intel_sdvo, value, len);
639}
79e53945 640
32aad86f
CW		 641static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
642{
643 struct intel_sdvo_set_target_input_args targets = {0};
644 return intel_sdvo_set_value(intel_sdvo,
645 SDVO_CMD_SET_TARGET_INPUT,
646 &targets, sizeof(targets));
79e53945
JB		 647}
648
649/**
650 * Return whether each input is trained.
651 *
652 * This function is making an assumption about the layout of the response,
653 * which should be checked against the docs.
654 */
ea5b213a 655static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 656{
657 struct intel_sdvo_get_trained_inputs_response response;
79e53945 658
1a3665c8 659 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 660 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
661 &response, sizeof(response)))
79e53945
JB		 662 return false;
663
664 *input_1 = response.input0_trained;
665 *input_2 = response.input1_trained;
666 return true;
667}
668
ea5b213a 669static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 670 u16 outputs)
671{
32aad86f
CW		 672 return intel_sdvo_set_value(intel_sdvo,
673 SDVO_CMD_SET_ACTIVE_OUTPUTS,
674 &outputs, sizeof(outputs));
79e53945
JB		 675}
676
4ac41f47
DV		 677static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
678 u16 *outputs)
679{
680 return intel_sdvo_get_value(intel_sdvo,
681 SDVO_CMD_GET_ACTIVE_OUTPUTS,
682 outputs, sizeof(*outputs));
683}
684
ea5b213a 685static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 686 int mode)
687{
32aad86f 688 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 689
690 switch (mode) {
691 case DRM_MODE_DPMS_ON:
692 state = SDVO_ENCODER_STATE_ON;
693 break;
694 case DRM_MODE_DPMS_STANDBY:
695 state = SDVO_ENCODER_STATE_STANDBY;
696 break;
697 case DRM_MODE_DPMS_SUSPEND:
698 state = SDVO_ENCODER_STATE_SUSPEND;
699 break;
700 case DRM_MODE_DPMS_OFF:
701 state = SDVO_ENCODER_STATE_OFF;
702 break;
703 }
704
32aad86f
CW		 705 return intel_sdvo_set_value(intel_sdvo,
706 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 707}
708
ea5b213a 709static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 710 int *clock_min,
711 int *clock_max)
712{
713 struct intel_sdvo_pixel_clock_range clocks;
79e53945 714
1a3665c8 715 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 716 if (!intel_sdvo_get_value(intel_sdvo,
717 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
718 &clocks, sizeof(clocks)))
79e53945
JB		 719 return false;
720
721 /* Convert the values from units of 10 kHz to kHz. */
722 *clock_min = clocks.min * 10;
723 *clock_max = clocks.max * 10;
79e53945
JB		 724 return true;
725}
726
ea5b213a 727static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 728 u16 outputs)
729{
32aad86f
CW		 730 return intel_sdvo_set_value(intel_sdvo,
731 SDVO_CMD_SET_TARGET_OUTPUT,
732 &outputs, sizeof(outputs));
79e53945
JB		 733}
734
ea5b213a 735static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 736 struct intel_sdvo_dtd *dtd)
737{
32aad86f
CW		 738 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
739 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 740}
741
045ac3b5
JB		 742static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
743 struct intel_sdvo_dtd *dtd)
744{
745 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
746 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
747}
748
ea5b213a 749static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 750 struct intel_sdvo_dtd *dtd)
751{
ea5b213a 752 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 753 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
754}
755
ea5b213a 756static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 757 struct intel_sdvo_dtd *dtd)
758{
ea5b213a 759 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 760 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
761}
762
045ac3b5
JB		 763static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
764 struct intel_sdvo_dtd *dtd)
765{
766 return intel_sdvo_get_timing(intel_sdvo,
767 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
768}
769
e2f0ba97 770static bool
ea5b213a 771intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 772 uint16_t clock,
773 uint16_t width,
774 uint16_t height)
775{
776 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 777
e642c6f1 778 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 779 args.clock = clock;
780 args.width = width;
781 args.height = height;
e642c6f1 782 args.interlace = 0;
12682a97 783
ea5b213a
CW		 784 if (intel_sdvo->is_lvds &&
785 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
786 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 787 args.scaled = 1;
788
32aad86f
CW		 789 return intel_sdvo_set_value(intel_sdvo,
790 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
791 &args, sizeof(args));
e2f0ba97
JB		 792}
793
ea5b213a 794static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 795 struct intel_sdvo_dtd *dtd)
796{
1a3665c8
CW		 797 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
798 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 799 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
800 &dtd->part1, sizeof(dtd->part1)) &&
801 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
802 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 803}
79e53945 804
ea5b213a 805static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 806{
32aad86f 807 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 808}
809
e2f0ba97 810static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 811 const struct drm_display_mode *mode)
79e53945 812{
e2f0ba97
JB		 813 uint16_t width, height;
814 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
815 uint16_t h_sync_offset, v_sync_offset;
6651819b 816 int mode_clock;
79e53945 817
1c4a814e
DV		 818 memset(dtd, 0, sizeof(*dtd));
819
c6ebd4c0
DV		 820 width = mode->hdisplay;
821 height = mode->vdisplay;
79e53945
JB		 822
823 /* do some mode translations */
c6ebd4c0
DV		 824 h_blank_len = mode->htotal - mode->hdisplay;
825 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 826
c6ebd4c0
DV		 827 v_blank_len = mode->vtotal - mode->vdisplay;
828 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 829
c6ebd4c0
DV		 830 h_sync_offset = mode->hsync_start - mode->hdisplay;
831 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 832
6651819b 833 mode_clock = mode->clock;
6651819b
DV		 834 mode_clock /= 10;
835 dtd->part1.clock = mode_clock;
836
e2f0ba97
JB		 837 dtd->part1.h_active = width & 0xff;
838 dtd->part1.h_blank = h_blank_len & 0xff;
839 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 840 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 841 dtd->part1.v_active = height & 0xff;
842 dtd->part1.v_blank = v_blank_len & 0xff;
843 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 844 ((v_blank_len >> 8) & 0xf);
845
171a9e96 846 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 847 dtd->part2.h_sync_width = h_sync_len & 0xff;
848 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 849 (v_sync_len & 0xf);
e2f0ba97 850 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 851 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
852 ((v_sync_len & 0x30) >> 4);
853
e2f0ba97 854 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 855 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
856 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 857 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 858 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 859 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 860 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97 861
e2f0ba97 862 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
e2f0ba97
JB		 863}
864
1c4a814e 865static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
32aad86f 866 const struct intel_sdvo_dtd *dtd)
e2f0ba97 867{
1c4a814e
DV		 868 struct drm_display_mode mode = {};
869
870 mode.hdisplay = dtd->part1.h_active;
871 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
872 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
873 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
874 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
875 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
876 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
877 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
878
879 mode.vdisplay = dtd->part1.v_active;
880 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
881 mode.vsync_start = mode.vdisplay;
882 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
883 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
884 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
885 mode.vsync_end = mode.vsync_start +
e2f0ba97 886 (dtd->part2.v_sync_off_width & 0xf);
1c4a814e
DV		 887 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
888 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
889 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
e2f0ba97 890
1c4a814e 891 mode.clock = dtd->part1.clock * 10;
e2f0ba97 892
59d92bfa 893 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
1c4a814e 894 mode.flags |= DRM_MODE_FLAG_INTERLACE;
59d92bfa 895 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1c4a814e 896 mode.flags |= DRM_MODE_FLAG_PHSYNC;
3cea210f 897 else
1c4a814e 898 mode.flags |= DRM_MODE_FLAG_NHSYNC;
59d92bfa 899 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1c4a814e 900 mode.flags |= DRM_MODE_FLAG_PVSYNC;
3cea210f 901 else
1c4a814e
DV		 902 mode.flags |= DRM_MODE_FLAG_NVSYNC;
903
904 drm_mode_set_crtcinfo(&mode, 0);
905
906 drm_mode_copy(pmode, &mode);
e2f0ba97
JB		 907}
908
e27d8538 909static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 910{
e27d8538 911 struct intel_sdvo_encode encode;
e2f0ba97 912
1a3665c8 913 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 914 return intel_sdvo_get_value(intel_sdvo,
915 SDVO_CMD_GET_SUPP_ENCODE,
916 &encode, sizeof(encode));
e2f0ba97
JB		 917}
918
ea5b213a 919static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 920 uint8_t mode)
e2f0ba97 921{
32aad86f 922 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 923}
924
ea5b213a 925static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 926 uint8_t mode)
927{
32aad86f 928 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 929}
930
931#if 0
ea5b213a 932static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 933{
934 int i, j;
935 uint8_t set_buf_index[2];
936 uint8_t av_split;
937 uint8_t buf_size;
938 uint8_t buf[48];
939 uint8_t *pos;
940
32aad86f 941 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 942
943 for (i = 0; i <= av_split; i++) {
944 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 945 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 946 set_buf_index, 2);
c751ce4f
EA		 947 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
948 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 949
950 pos = buf;
951 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 952 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 953 NULL, 0);
c751ce4f 954 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 955 pos += 8;
956 }
957 }
958}
959#endif
960
b6e0e543
DV		 961static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
962 unsigned if_index, uint8_t tx_rate,
fff63867 963 const uint8_t *data, unsigned length)
b6e0e543
DV		 964{
965 uint8_t set_buf_index[2] = { if_index, 0 };
966 uint8_t hbuf_size, tmp[8];
967 int i;
968
969 if (!intel_sdvo_set_value(intel_sdvo,
970 SDVO_CMD_SET_HBUF_INDEX,
971 set_buf_index, 2))
972 return false;
973
974 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
975 &hbuf_size, 1))
976 return false;
977
978 /* Buffer size is 0 based, hooray! */
979 hbuf_size++;
980
981 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
982 if_index, length, hbuf_size);
983
984 for (i = 0; i < hbuf_size; i += 8) {
985 memset(tmp, 0, 8);
986 if (i < length)
987 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
988
989 if (!intel_sdvo_set_value(intel_sdvo,
990 SDVO_CMD_SET_HBUF_DATA,
991 tmp, 8))
992 return false;
993 }
994
995 return intel_sdvo_set_value(intel_sdvo,
996 SDVO_CMD_SET_HBUF_TXRATE,
997 &tx_rate, 1);
998}
999
abedc077 1000static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
f9fe0530 1001 struct intel_crtc_state *pipe_config)
e2f0ba97 1002{
15dcd350 1003 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
15dcd350
DL		 1004 union hdmi_infoframe frame;
1005 int ret;
1006 ssize_t len;
1007
1008 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
f9fe0530 1009 &pipe_config->base.adjusted_mode);
15dcd350
DL		 1010 if (ret < 0) {
1011 DRM_ERROR("couldn't fill AVI infoframe\n");
1012 return false;
1013 }
3c17fe4b 1014
abedc077 1015 if (intel_sdvo->rgb_quant_range_selectable) {
f9fe0530 1016 if (pipe_config->limited_color_range)
15dcd350
DL		 1017 frame.avi.quantization_range =
1018 HDMI_QUANTIZATION_RANGE_LIMITED;
abedc077 1019 else
15dcd350
DL		 1020 frame.avi.quantization_range =
1021 HDMI_QUANTIZATION_RANGE_FULL;
abedc077
VS		 1022 }
1023
15dcd350
DL		 1024 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
1025 if (len < 0)
1026 return false;
81014b9d 1027
b6e0e543
DV		 1028 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1029 SDVO_HBUF_TX_VSYNC,
1030 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 1031}
1032
32aad86f 1033static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 1034{
ce6feabd 1035 struct intel_sdvo_tv_format format;
40039750 1036 uint32_t format_map;
ce6feabd 1037
40039750 1038 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1039 memset(&format, 0, sizeof(format));
32aad86f 1040 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1041
32aad86f
CW		 1042 BUILD_BUG_ON(sizeof(format) != 6);
1043 return intel_sdvo_set_value(intel_sdvo,
1044 SDVO_CMD_SET_TV_FORMAT,
1045 &format, sizeof(format));
7026d4ac
ZW		 1046}
1047
32aad86f
CW		 1048static bool
1049intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1050 const struct drm_display_mode *mode)
e2f0ba97 1051{
32aad86f 1052 struct intel_sdvo_dtd output_dtd;
79e53945 1053
32aad86f
CW		 1054 if (!intel_sdvo_set_target_output(intel_sdvo,
1055 intel_sdvo->attached_output))
1056 return false;
e2f0ba97 1057
32aad86f
CW		 1058 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1059 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1060 return false;
e2f0ba97 1061
32aad86f
CW		 1062 return true;
1063}
1064
c9a29698
DV		 1065/* Asks the sdvo controller for the preferred input mode given the output mode.
1066 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 1067static bool
c9a29698 1068intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1069 const struct drm_display_mode *mode,
c9a29698 1070 struct drm_display_mode *adjusted_mode)
32aad86f 1071{
c9a29698
DV		 1072 struct intel_sdvo_dtd input_dtd;
1073
32aad86f
CW		 1074 /* Reset the input timing to the screen. Assume always input 0. */
1075 if (!intel_sdvo_set_target_input(intel_sdvo))
1076 return false;
e2f0ba97 1077
32aad86f
CW		 1078 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1079 mode->clock / 10,
1080 mode->hdisplay,
1081 mode->vdisplay))
1082 return false;
e2f0ba97 1083
32aad86f 1084 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1085 &input_dtd))
32aad86f 1086 return false;
e2f0ba97 1087
c9a29698 1088 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1089 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1090
32aad86f
CW		 1091 return true;
1092}
12682a97 1093
5cec258b 1094static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
70484559 1095{
3c52f4eb 1096 unsigned dotclock = pipe_config->port_clock;
70484559
DV		 1097 struct dpll *clock = &pipe_config->dpll;
1098
1099 /* SDVO TV has fixed PLL values depend on its clock range,
1100 this mirrors vbios setting. */
1101 if (dotclock >= 100000 && dotclock < 140500) {
1102 clock->p1 = 2;
1103 clock->p2 = 10;
1104 clock->n = 3;
1105 clock->m1 = 16;
1106 clock->m2 = 8;
1107 } else if (dotclock >= 140500 && dotclock <= 200000) {
1108 clock->p1 = 1;
1109 clock->p2 = 10;
1110 clock->n = 6;
1111 clock->m1 = 12;
1112 clock->m2 = 8;
1113 } else {
1114 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1115 }
1116
1117 pipe_config->clock_set = true;
1118}
1119
6cc5f341 1120static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 1121 struct intel_crtc_state *pipe_config,
1122 struct drm_connector_state *conn_state)
32aad86f 1123{
8aca63aa 1124 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2d112de7
ACO		 1125 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1126 struct drm_display_mode *mode = &pipe_config->base.mode;
12682a97 1127
5d2d38dd
DV		 1128 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1129 pipe_config->pipe_bpp = 8*3;
1130
6e266956 1131 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
5bfe2ac0
DV		 1132 pipe_config->has_pch_encoder = true;
1133
32aad86f
CW		 1134 /* We need to construct preferred input timings based on our
1135 * output timings. To do that, we have to set the output
1136 * timings, even though this isn't really the right place in
1137 * the sequence to do it. Oh well.
1138 */
1139 if (intel_sdvo->is_tv) {
1140 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1141 return false;
12682a97 1142
c9a29698
DV		 1143 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1144 mode,
1145 adjusted_mode);
09ede541 1146 pipe_config->sdvo_tv_clock = true;
ea5b213a 1147 } else if (intel_sdvo->is_lvds) {
32aad86f 1148 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1149 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1150 return false;
12682a97 1151
c9a29698
DV		 1152 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1153 mode,
1154 adjusted_mode);
e2f0ba97 1155 }
32aad86f
CW		 1156
1157 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1158 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1159 */
6cc5f341
DV		 1160 pipe_config->pixel_multiplier =
1161 intel_sdvo_get_pixel_multiplier(adjusted_mode);
32aad86f 1162
9f04003e
DV		 1163 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor;
1164
55bc60db
VS		 1165 if (intel_sdvo->color_range_auto) {
1166 /* See CEA-861-E - 5.1 Default Encoding Parameters */
4f3a8bc7
PZ		 1167 /* FIXME: This bit is only valid when using TMDS encoding and 8
1168 * bit per color mode. */
9f04003e 1169 if (pipe_config->has_hdmi_sink &&
18316c8c 1170 drm_match_cea_mode(adjusted_mode) > 1)
69f5acc8
DV		 1171 pipe_config->limited_color_range = true;
1172 } else {
9f04003e 1173 if (pipe_config->has_hdmi_sink &&
69f5acc8
DV		 1174 intel_sdvo->color_range == HDMI_COLOR_RANGE_16_235)
1175 pipe_config->limited_color_range = true;
55bc60db
VS		 1176 }
1177
70484559
DV		 1178 /* Clock computation needs to happen after pixel multiplier. */
1179 if (intel_sdvo->is_tv)
1180 i9xx_adjust_sdvo_tv_clock(pipe_config);
1181
7949dd47
VS		 1182 /* Set user selected PAR to incoming mode's member */
1183 if (intel_sdvo->is_hdmi)
0e9f25d0 1184 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
7949dd47 1185
e2f0ba97
JB		 1186 return true;
1187}
1188
fd6bbda9
ML		 1189static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
1190 struct intel_crtc_state *crtc_state,
1191 struct drm_connector_state *conn_state)
e2f0ba97 1192{
66478475 1193 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
f9fe0530
ML		 1194 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1195 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
1196 struct drm_display_mode *mode = &crtc_state->base.mode;
8aca63aa 1197 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
6c9547ff 1198 u32 sdvox;
e2f0ba97 1199 struct intel_sdvo_in_out_map in_out;
6651819b 1200 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff 1201 int rate;
e2f0ba97 1202
e2f0ba97
JB		 1203 /* First, set the input mapping for the first input to our controlled
1204 * output. This is only correct if we're a single-input device, in
1205 * which case the first input is the output from the appropriate SDVO
1206 * channel on the motherboard. In a two-input device, the first input
1207 * will be SDVOB and the second SDVOC.
1208 */
ea5b213a 1209 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1210 in_out.in1 = 0;
1211
c74696b9
PR		 1212 intel_sdvo_set_value(intel_sdvo,
1213 SDVO_CMD_SET_IN_OUT_MAP,
1214 &in_out, sizeof(in_out));
e2f0ba97 1215
6c9547ff
CW		 1216 /* Set the output timings to the screen */
1217 if (!intel_sdvo_set_target_output(intel_sdvo,
1218 intel_sdvo->attached_output))
1219 return;
e2f0ba97 1220
6651819b
DV		 1221 /* lvds has a special fixed output timing. */
1222 if (intel_sdvo->is_lvds)
1223 intel_sdvo_get_dtd_from_mode(&output_dtd,
1224 intel_sdvo->sdvo_lvds_fixed_mode);
1225 else
1226 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1227 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1228 DRM_INFO("Setting output timings on %s failed\n",
1229 SDVO_NAME(intel_sdvo));
79e53945
JB		 1230
1231 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1232 if (!intel_sdvo_set_target_input(intel_sdvo))
1233 return;
79e53945 1234
f9fe0530 1235 if (crtc_state->has_hdmi_sink) {
97aaf910
CW		 1236 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1237 intel_sdvo_set_colorimetry(intel_sdvo,
1238 SDVO_COLORIMETRY_RGB256);
f9fe0530 1239 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
97aaf910
CW		 1240 } else
1241 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1242
6c9547ff
CW		 1243 if (intel_sdvo->is_tv &&
1244 !intel_sdvo_set_tv_format(intel_sdvo))
1245 return;
e2f0ba97 1246
6651819b 1247 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
eeb47937 1248
e751823d
EE		 1249 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1250 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1251 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1252 DRM_INFO("Setting input timings on %s failed\n",
1253 SDVO_NAME(intel_sdvo));
79e53945 1254
f9fe0530 1255 switch (crtc_state->pixel_multiplier) {
6c9547ff 1256 default:
fd0753cf 1257 WARN(1, "unknown pixel multiplier specified\n");
32aad86f
CW		 1258 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1259 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1260 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1261 }
32aad86f
CW		 1262 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1263 return;
79e53945
JB		 1264
1265 /* Set the SDVO control regs. */
66478475 1266 if (INTEL_GEN(dev_priv) >= 4) {
ba68e086
PZ		 1267 /* The real mode polarity is set by the SDVO commands, using
1268 * struct intel_sdvo_dtd. */
1269 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
6e266956 1270 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
69f5acc8 1271 sdvox |= HDMI_COLOR_RANGE_16_235;
66478475 1272 if (INTEL_GEN(dev_priv) < 5)
6714afb1 1273 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1274 } else {
6c9547ff 1275 sdvox = I915_READ(intel_sdvo->sdvo_reg);
2a5c0832 1276 if (intel_sdvo->port == PORT_B)
e2f0ba97 1277 sdvox &= SDVOB_PRESERVE_MASK;
2a5c0832 1278 else
e2f0ba97 1279 sdvox &= SDVOC_PRESERVE_MASK;
e2f0ba97
JB		 1280 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1281 }
3573c410 1282
6e266956 1283 if (INTEL_PCH_TYPE(dev_priv) >= PCH_CPT)
eeb47937 1284 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
3573c410 1285 else
eeb47937 1286 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
3573c410 1287
da79de97 1288 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1289 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1290
66478475 1291 if (INTEL_GEN(dev_priv) >= 4) {
e2f0ba97 1292 /* done in crtc_mode_set as the dpll_md reg must be written early */
50a0bc90 1293 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
73f67aa8 1294 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
e2f0ba97 1295 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1296 } else {
f9fe0530 1297 sdvox |= (crtc_state->pixel_multiplier - 1)
6cc5f341 1298 << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1299 }
1300
6714afb1 1301 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
66478475 1302 INTEL_GEN(dev_priv) < 5)
12682a97 1303 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1304 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1305}
1306
4ac41f47 1307static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1308{
4ac41f47
DV		 1309 struct intel_sdvo_connector *intel_sdvo_connector =
1310 to_intel_sdvo_connector(&connector->base);
1311 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
2f28c50b 1312 u16 active_outputs = 0;
4ac41f47
DV		 1313
1314 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1315
1316 if (active_outputs & intel_sdvo_connector->output_flag)
1317 return true;
1318 else
1319 return false;
1320}
1321
1322static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1323 enum pipe *pipe)
1324{
1325 struct drm_device *dev = encoder->base.dev;
fac5e23e 1326 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1327 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2f28c50b 1328 u16 active_outputs = 0;
4ac41f47
DV		 1329 u32 tmp;
1330
1331 tmp = I915_READ(intel_sdvo->sdvo_reg);
7a7d1fb7 1332 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
4ac41f47 1333
7a7d1fb7 1334 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
4ac41f47
DV		 1335 return false;
1336
6e266956 1337 if (HAS_PCH_CPT(dev_priv))
4ac41f47
DV		 1338 *pipe = PORT_TO_PIPE_CPT(tmp);
1339 else
1340 *pipe = PORT_TO_PIPE(tmp);
1341
1342 return true;
1343}
1344
045ac3b5 1345static void intel_sdvo_get_config(struct intel_encoder *encoder,
5cec258b 1346 struct intel_crtc_state *pipe_config)
045ac3b5 1347{
6c49f241 1348 struct drm_device *dev = encoder->base.dev;
fac5e23e 1349 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1350 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
045ac3b5 1351 struct intel_sdvo_dtd dtd;
6c49f241 1352 int encoder_pixel_multiplier = 0;
18442d08 1353 int dotclock;
6c49f241
DV		 1354 u32 flags = 0, sdvox;
1355 u8 val;
045ac3b5
JB		 1356 bool ret;
1357
b5a9fa09
DV		 1358 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1359
045ac3b5
JB		 1360 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1361 if (!ret) {
bb760063
DV		 1362 /* Some sdvo encoders are not spec compliant and don't
1363 * implement the mandatory get_timings function. */
045ac3b5 1364 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
bb760063
DV		 1365 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1366 } else {
1367 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1368 flags |= DRM_MODE_FLAG_PHSYNC;
1369 else
1370 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1371
bb760063
DV		 1372 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1373 flags |= DRM_MODE_FLAG_PVSYNC;
1374 else
1375 flags |= DRM_MODE_FLAG_NVSYNC;
045ac3b5
JB		 1376 }
1377
2d112de7 1378 pipe_config->base.adjusted_mode.flags |= flags;
045ac3b5 1379
fdafa9e2
DV		 1380 /*
1381 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1382 * the sdvo port register, on all other platforms it is part of the dpll
1383 * state. Since the general pipe state readout happens before the
1384 * encoder->get_config we so already have a valid pixel multplier on all
1385 * other platfroms.
1386 */
50a0bc90 1387 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
6c49f241
DV		 1388 pipe_config->pixel_multiplier =
1389 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1390 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1391 }
045ac3b5 1392
2b85886a 1393 dotclock = pipe_config->port_clock;
e3b247da 1394
2b85886a
VS		 1395 if (pipe_config->pixel_multiplier)
1396 dotclock /= pipe_config->pixel_multiplier;
18442d08 1397
2d112de7 1398 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
18442d08 1399
6c49f241 1400 /* Cross check the port pixel multiplier with the sdvo encoder state. */
53b91408
DL		 1401 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1402 &val, 1)) {
1403 switch (val) {
1404 case SDVO_CLOCK_RATE_MULT_1X:
1405 encoder_pixel_multiplier = 1;
1406 break;
1407 case SDVO_CLOCK_RATE_MULT_2X:
1408 encoder_pixel_multiplier = 2;
1409 break;
1410 case SDVO_CLOCK_RATE_MULT_4X:
1411 encoder_pixel_multiplier = 4;
1412 break;
1413 }
6c49f241 1414 }
fdafa9e2 1415
b5a9fa09
DV		 1416 if (sdvox & HDMI_COLOR_RANGE_16_235)
1417 pipe_config->limited_color_range = true;
1418
9f04003e
DV		 1419 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1420 &val, 1)) {
1421 if (val == SDVO_ENCODE_HDMI)
1422 pipe_config->has_hdmi_sink = true;
1423 }
1424
6c49f241
DV		 1425 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1426 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1427 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
045ac3b5
JB		 1428}
1429
fd6bbda9
ML		 1430static void intel_disable_sdvo(struct intel_encoder *encoder,
1431 struct intel_crtc_state *old_crtc_state,
1432 struct drm_connector_state *conn_state)
ce22c320 1433{
fac5e23e 1434 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
8aca63aa 1435 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1612c8bd 1436 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
ce22c320
DV		 1437 u32 temp;
1438
1439 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1440 if (0)
1441 intel_sdvo_set_encoder_power_state(intel_sdvo,
1442 DRM_MODE_DPMS_OFF);
1443
1444 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf 1445
1612c8bd
VS		 1446 temp &= ~SDVO_ENABLE;
1447 intel_sdvo_write_sdvox(intel_sdvo, temp);
1448
1449 /*
1450 * HW workaround for IBX, we need to move the port
1451 * to transcoder A after disabling it to allow the
1452 * matching DP port to be enabled on transcoder A.
1453 */
1454 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
0c241d5b
VS		 1455 /*
1456 * We get CPU/PCH FIFO underruns on the other pipe when
1457 * doing the workaround. Sweep them under the rug.
1458 */
1459 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1460 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1461
1612c8bd
VS		 1462 temp &= ~SDVO_PIPE_B_SELECT;
1463 temp |= SDVO_ENABLE;
1464 intel_sdvo_write_sdvox(intel_sdvo, temp);
1465
1466 temp &= ~SDVO_ENABLE;
1467 intel_sdvo_write_sdvox(intel_sdvo, temp);
0c241d5b 1468
0f0f74bc 1469 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
0c241d5b
VS		 1470 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1471 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
ce22c320
DV		 1472 }
1473}
1474
fd6bbda9
ML		 1475static void pch_disable_sdvo(struct intel_encoder *encoder,
1476 struct intel_crtc_state *old_crtc_state,
1477 struct drm_connector_state *old_conn_state)
3c65d1d1
VS		 1478{
1479}
1480
fd6bbda9
ML		 1481static void pch_post_disable_sdvo(struct intel_encoder *encoder,
1482 struct intel_crtc_state *old_crtc_state,
1483 struct drm_connector_state *old_conn_state)
3c65d1d1 1484{
fd6bbda9 1485 intel_disable_sdvo(encoder, old_crtc_state, old_conn_state);
3c65d1d1
VS		 1486}
1487
fd6bbda9
ML		 1488static void intel_enable_sdvo(struct intel_encoder *encoder,
1489 struct intel_crtc_state *pipe_config,
1490 struct drm_connector_state *conn_state)
ce22c320
DV		 1491{
1492 struct drm_device *dev = encoder->base.dev;
fac5e23e 1493 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1494 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
ce22c320 1495 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 1496 u32 temp;
ce22c320
DV		 1497 bool input1, input2;
1498 int i;
d0a7b6de 1499 bool success;
ce22c320
DV		 1500
1501 temp = I915_READ(intel_sdvo->sdvo_reg);
3c65d1d1
VS		 1502 temp |= SDVO_ENABLE;
1503 intel_sdvo_write_sdvox(intel_sdvo, temp);
776ca7cf 1504
ce22c320 1505 for (i = 0; i < 2; i++)
0f0f74bc 1506 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
ce22c320 1507
d0a7b6de 1508 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
ce22c320
DV		 1509 /* Warn if the device reported failure to sync.
1510 * A lot of SDVO devices fail to notify of sync, but it's
1511 * a given it the status is a success, we succeeded.
1512 */
d0a7b6de 1513 if (success && !input1) {
ce22c320
DV		 1514 DRM_DEBUG_KMS("First %s output reported failure to "
1515 "sync\n", SDVO_NAME(intel_sdvo));
1516 }
1517
1518 if (0)
1519 intel_sdvo_set_encoder_power_state(intel_sdvo,
1520 DRM_MODE_DPMS_ON);
1521 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
1522}
1523
c19de8eb
DL		 1524static enum drm_mode_status
1525intel_sdvo_mode_valid(struct drm_connector *connector,
1526 struct drm_display_mode *mode)
79e53945 1527{
df0e9248 1528 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
24b23882 1529 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
79e53945
JB		 1530
1531 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1532 return MODE_NO_DBLESCAN;
1533
ea5b213a 1534 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1535 return MODE_CLOCK_LOW;
1536
ea5b213a 1537 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1538 return MODE_CLOCK_HIGH;
1539
24b23882
MK		 1540 if (mode->clock > max_dotclk)
1541 return MODE_CLOCK_HIGH;
1542
8545423a 1543 if (intel_sdvo->is_lvds) {
ea5b213a 1544 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1545 return MODE_PANEL;
1546
ea5b213a 1547 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1548 return MODE_PANEL;
1549 }
1550
79e53945
JB		 1551 return MODE_OK;
1552}
1553
ea5b213a 1554static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1555{
1a3665c8 1556 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1557 if (!intel_sdvo_get_value(intel_sdvo,
1558 SDVO_CMD_GET_DEVICE_CAPS,
1559 caps, sizeof(*caps)))
1560 return false;
1561
1562 DRM_DEBUG_KMS("SDVO capabilities:\n"
1563 " vendor_id: %d\n"
1564 " device_id: %d\n"
1565 " device_rev_id: %d\n"
1566 " sdvo_version_major: %d\n"
1567 " sdvo_version_minor: %d\n"
1568 " sdvo_inputs_mask: %d\n"
1569 " smooth_scaling: %d\n"
1570 " sharp_scaling: %d\n"
1571 " up_scaling: %d\n"
1572 " down_scaling: %d\n"
1573 " stall_support: %d\n"
1574 " output_flags: %d\n",
1575 caps->vendor_id,
1576 caps->device_id,
1577 caps->device_rev_id,
1578 caps->sdvo_version_major,
1579 caps->sdvo_version_minor,
1580 caps->sdvo_inputs_mask,
1581 caps->smooth_scaling,
1582 caps->sharp_scaling,
1583 caps->up_scaling,
1584 caps->down_scaling,
1585 caps->stall_support,
1586 caps->output_flags);
1587
1588 return true;
79e53945
JB		 1589}
1590
5fa7ac9c 1591static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1592{
50a0bc90 1593 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
5fa7ac9c 1594 uint16_t hotplug;
79e53945 1595
50a0bc90 1596 if (!I915_HAS_HOTPLUG(dev_priv))
1d83d957
VS		 1597 return 0;
1598
768b107e
DV		 1599 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1600 * on the line. */
50a0bc90 1601 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
5fa7ac9c 1602 return 0;
768b107e 1603
5fa7ac9c
JN		 1604 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1605 &hotplug, sizeof(hotplug)))
1606 return 0;
768b107e 1607
5fa7ac9c 1608 return hotplug;
79e53945
JB		 1609}
1610
cc68c81a 1611static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1612{
8aca63aa 1613 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
79e53945 1614
5fa7ac9c
JN		 1615 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1616 &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1617}
1618
fb7a46f3 1619static bool
ea5b213a 1620intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1621{
bc65212c 1622 /* Is there more than one type of output? */
2294488d 1623 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1624}
1625
f899fc64 1626static struct edid *
e957d772 1627intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1628{
e957d772
CW		 1629 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1630 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1631}
1632
ff482d83
CW		 1633/* Mac mini hack -- use the same DDC as the analog connector */
1634static struct edid *
1635intel_sdvo_get_analog_edid(struct drm_connector *connector)
1636{
fac5e23e 1637 struct drm_i915_private *dev_priv = to_i915(connector->dev);
ff482d83 1638
0c1dab89 1639 return drm_get_edid(connector,
3bd7d909 1640 intel_gmbus_get_adapter(dev_priv,
41aa3448 1641 dev_priv->vbt.crt_ddc_pin));
ff482d83
CW		 1642}
1643
c43b5634 1644static enum drm_connector_status
8bf38485 1645intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1646{
df0e9248 1647 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1648 enum drm_connector_status status;
1649 struct edid *edid;
9dff6af8 1650
e957d772 1651 edid = intel_sdvo_get_edid(connector);
57cdaf90 1652
ea5b213a 1653 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1654 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1655
7c3f0a27
ZY		 1656 /*
1657 * Don't use the 1 as the argument of DDC bus switch to get
1658 * the EDID. It is used for SDVO SPD ROM.
1659 */
9d1a903d 1660 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1661 intel_sdvo->ddc_bus = ddc;
1662 edid = intel_sdvo_get_edid(connector);
1663 if (edid)
7c3f0a27 1664 break;
7c3f0a27 1665 }
e957d772
CW		 1666 /*
1667 * If we found the EDID on the other bus,
1668 * assume that is the correct DDC bus.
1669 */
1670 if (edid == NULL)
1671 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1672 }
9d1a903d
CW		 1673
1674 /*
1675 * When there is no edid and no monitor is connected with VGA
1676 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1677 */
ff482d83
CW		 1678 if (edid == NULL)
1679 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1680
2f551c84 1681 status = connector_status_unknown;
9dff6af8 1682 if (edid != NULL) {
149c36a3 1683 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1684 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1685 status = connector_status_connected;
da79de97
CW		 1686 if (intel_sdvo->is_hdmi) {
1687 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1688 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
abedc077
VS		 1689 intel_sdvo->rgb_quant_range_selectable =
1690 drm_rgb_quant_range_selectable(edid);
da79de97 1691 }
13946743
CW		 1692 } else
1693 status = connector_status_disconnected;
9d1a903d
CW		 1694 kfree(edid);
1695 }
7f36e7ed
CW		 1696
1697 if (status == connector_status_connected) {
1698 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1699 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1700 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1701 }
1702
2b8d33f7 1703 return status;
9dff6af8
ML		 1704}
1705
52220085
CW		 1706static bool
1707intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1708 struct edid *edid)
1709{
1710 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1711 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1712
1713 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1714 connector_is_digital, monitor_is_digital);
1715 return connector_is_digital == monitor_is_digital;
1716}
1717
7b334fcb 1718static enum drm_connector_status
930a9e28 1719intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1720{
fb7a46f3 1721 uint16_t response;
df0e9248 1722 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1723 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1724 enum drm_connector_status ret;
79e53945 1725
164c8598 1726 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1727 connector->base.id, connector->name);
164c8598 1728
fc37381c
CW		 1729 if (!intel_sdvo_get_value(intel_sdvo,
1730 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1731 &response, 2))
32aad86f 1732 return connector_status_unknown;
79e53945 1733
e957d772
CW		 1734 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1735 response & 0xff, response >> 8,
1736 intel_sdvo_connector->output_flag);
e2f0ba97 1737
fb7a46f3 1738 if (response == 0)
79e53945 1739 return connector_status_disconnected;
fb7a46f3 1740
ea5b213a 1741 intel_sdvo->attached_output = response;
14571b4c 1742
97aaf910
CW		 1743 intel_sdvo->has_hdmi_monitor = false;
1744 intel_sdvo->has_hdmi_audio = false;
abedc077 1745 intel_sdvo->rgb_quant_range_selectable = false;
97aaf910 1746
615fb93f 1747 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1748 ret = connector_status_disconnected;
13946743 1749 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1750 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1751 else {
1752 struct edid *edid;
1753
1754 /* if we have an edid check it matches the connection */
1755 edid = intel_sdvo_get_edid(connector);
1756 if (edid == NULL)
1757 edid = intel_sdvo_get_analog_edid(connector);
1758 if (edid != NULL) {
52220085
CW		 1759 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1760 edid))
13946743 1761 ret = connector_status_connected;
52220085
CW		 1762 else
1763 ret = connector_status_disconnected;
1764
13946743
CW		 1765 kfree(edid);
1766 } else
1767 ret = connector_status_connected;
1768 }
14571b4c
ZW		 1769
1770 /* May update encoder flag for like clock for SDVO TV, etc.*/
1771 if (ret == connector_status_connected) {
ea5b213a
CW		 1772 intel_sdvo->is_tv = false;
1773 intel_sdvo->is_lvds = false;
14571b4c 1774
09ede541 1775 if (response & SDVO_TV_MASK)
ea5b213a 1776 intel_sdvo->is_tv = true;
14571b4c 1777 if (response & SDVO_LVDS_MASK)
8545423a 1778 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1779 }
14571b4c
ZW		 1780
1781 return ret;
79e53945
JB		 1782}
1783
e2f0ba97 1784static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1785{
ff482d83 1786 struct edid *edid;
79e53945 1787
46a3f4a3 1788 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1789 connector->base.id, connector->name);
46a3f4a3 1790
79e53945 1791 /* set the bus switch and get the modes */
e957d772 1792 edid = intel_sdvo_get_edid(connector);
79e53945 1793
57cdaf90
KP		 1794 /*
1795 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1796 * link between analog and digital outputs. So, if the regular SDVO
1797 * DDC fails, check to see if the analog output is disconnected, in
1798 * which case we'll look there for the digital DDC data.
e2f0ba97 1799 */
f899fc64
CW		 1800 if (edid == NULL)
1801 edid = intel_sdvo_get_analog_edid(connector);
1802
ff482d83 1803 if (edid != NULL) {
52220085
CW		 1804 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1805 edid)) {
0c1dab89
CW		 1806 drm_mode_connector_update_edid_property(connector, edid);
1807 drm_add_edid_modes(connector, edid);
1808 }
13946743 1809
ff482d83 1810 kfree(edid);
e2f0ba97 1811 }
e2f0ba97
JB		 1812}
1813
1814/*
1815 * Set of SDVO TV modes.
1816 * Note! This is in reply order (see loop in get_tv_modes).
1817 * XXX: all 60Hz refresh?
1818 */
b1f559ec 1819static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1820 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1821 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1822 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1823 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1824 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1825 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1826 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1827 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1828 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1829 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1830 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1832 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1833 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1834 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1835 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1836 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1837 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1838 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1839 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1840 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1841 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1842 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1843 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1844 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1845 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1846 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1847 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1848 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1849 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1850 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1851 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1852 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1853 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1854 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1855 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1856 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1857 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1858 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1859 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1860 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1861 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1862 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1863 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1864 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1865 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1866 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1867 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1868 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1869 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1870 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1871 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1872 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1873 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1874 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1875 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1876 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1877};
1878
1879static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1880{
df0e9248 1881 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1882 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1883 uint32_t reply = 0, format_map = 0;
1884 int i;
e2f0ba97 1885
46a3f4a3 1886 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1887 connector->base.id, connector->name);
46a3f4a3 1888
e2f0ba97
JB		 1889 /* Read the list of supported input resolutions for the selected TV
1890 * format.
1891 */
40039750 1892 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1893 memcpy(&tv_res, &format_map,
32aad86f 1894 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1895
32aad86f
CW		 1896 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1897 return;
ce6feabd 1898
32aad86f 1899 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1900 if (!intel_sdvo_write_cmd(intel_sdvo,
1901 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1902 &tv_res, sizeof(tv_res)))
1903 return;
1904 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1905 return;
1906
1907 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1908 if (reply & (1 << i)) {
1909 struct drm_display_mode *nmode;
1910 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1911 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1912 if (nmode)
1913 drm_mode_probed_add(connector, nmode);
1914 }
e2f0ba97
JB		 1915}
1916
7086c87f
ML		 1917static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1918{
df0e9248 1919 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
fac5e23e 1920 struct drm_i915_private *dev_priv = to_i915(connector->dev);
12682a97 1921 struct drm_display_mode *newmode;
7086c87f 1922
46a3f4a3 1923 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1924 connector->base.id, connector->name);
46a3f4a3 1925
7086c87f 1926 /*
c3456fb3 1927 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
4300a0f8 1928 * SDVO->LVDS transcoders can't cope with the EDID mode.
7086c87f 1929 */
41aa3448 1930 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
7086c87f 1931 newmode = drm_mode_duplicate(connector->dev,
41aa3448 1932 dev_priv->vbt.sdvo_lvds_vbt_mode);
7086c87f
ML		 1933 if (newmode != NULL) {
1934 /* Guarantee the mode is preferred */
1935 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1936 DRM_MODE_TYPE_DRIVER);
1937 drm_mode_probed_add(connector, newmode);
1938 }
1939 }
12682a97 1940
4300a0f8
DA		 1941 /*
1942 * Attempt to get the mode list from DDC.
1943 * Assume that the preferred modes are
1944 * arranged in priority order.
1945 */
1946 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
1947
12682a97 1948 list_for_each_entry(newmode, &connector->probed_modes, head) {
1949 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1950 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1951 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1952
8545423a 1953 intel_sdvo->is_lvds = true;
12682a97 1954 break;
1955 }
1956 }
7086c87f
ML		 1957}
1958
e2f0ba97
JB		 1959static int intel_sdvo_get_modes(struct drm_connector *connector)
1960{
615fb93f 1961 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1962
615fb93f 1963 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1964 intel_sdvo_get_tv_modes(connector);
615fb93f 1965 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1966 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1967 else
1968 intel_sdvo_get_ddc_modes(connector);
1969
32aad86f 1970 return !list_empty(&connector->probed_modes);
79e53945
JB		 1971}
1972
1973static void intel_sdvo_destroy(struct drm_connector *connector)
1974{
615fb93f 1975 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1976
79e53945 1977 drm_connector_cleanup(connector);
4b745b1e 1978 kfree(intel_sdvo_connector);
79e53945
JB		 1979}
1980
1aad7ac0
CW		 1981static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1982{
1983 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1984 struct edid *edid;
1985 bool has_audio = false;
1986
1987 if (!intel_sdvo->is_hdmi)
1988 return false;
1989
1990 edid = intel_sdvo_get_edid(connector);
1991 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1992 has_audio = drm_detect_monitor_audio(edid);
38ab8a20 1993 kfree(edid);
1aad7ac0
CW		 1994
1995 return has_audio;
1996}
1997
ce6feabd
ZY		 1998static int
1999intel_sdvo_set_property(struct drm_connector *connector,
2000 struct drm_property *property,
2001 uint64_t val)
2002{
df0e9248 2003 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 2004 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
fac5e23e 2005 struct drm_i915_private *dev_priv = to_i915(connector->dev);
b9219c5e 2006 uint16_t temp_value;
32aad86f
CW		 2007 uint8_t cmd;
2008 int ret;
ce6feabd 2009
662595df 2010 ret = drm_object_property_set_value(&connector->base, property, val);
32aad86f
CW		 2011 if (ret)
2012 return ret;
ce6feabd 2013
3f43c48d 2014 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 2015 int i = val;
2016 bool has_audio;
2017
2018 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 2019 return 0;
2020
1aad7ac0 2021 intel_sdvo_connector->force_audio = i;
7f36e7ed 2022
c3e5f67b 2023 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 2024 has_audio = intel_sdvo_detect_hdmi_audio(connector);
2025 else
c3e5f67b 2026 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 2027
1aad7ac0 2028 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 2029 return 0;
7f36e7ed 2030
1aad7ac0 2031 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 2032 goto done;
2033 }
2034
e953fd7b 2035 if (property == dev_priv->broadcast_rgb_property) {
ae4edb80
DV		 2036 bool old_auto = intel_sdvo->color_range_auto;
2037 uint32_t old_range = intel_sdvo->color_range;
2038
55bc60db
VS		 2039 switch (val) {
2040 case INTEL_BROADCAST_RGB_AUTO:
2041 intel_sdvo->color_range_auto = true;
2042 break;
2043 case INTEL_BROADCAST_RGB_FULL:
2044 intel_sdvo->color_range_auto = false;
2045 intel_sdvo->color_range = 0;
2046 break;
2047 case INTEL_BROADCAST_RGB_LIMITED:
2048 intel_sdvo->color_range_auto = false;
4f3a8bc7
PZ		 2049 /* FIXME: this bit is only valid when using TMDS
2050 * encoding and 8 bit per color mode. */
2051 intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
55bc60db
VS		 2052 break;
2053 default:
2054 return -EINVAL;
2055 }
ae4edb80
DV		 2056
2057 if (old_auto == intel_sdvo->color_range_auto &&
2058 old_range == intel_sdvo->color_range)
2059 return 0;
2060
7f36e7ed
CW		 2061 goto done;
2062 }
2063
7949dd47 2064 if (property == connector->dev->mode_config.aspect_ratio_property) {
0e9f25d0 2065 connector->state->picture_aspect_ratio = val;
7949dd47
VS		 2066 goto done;
2067 }
2068
c5521706
CW		 2069#define CHECK_PROPERTY(name, NAME) \
2070 if (intel_sdvo_connector->name == property) { \
2071 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
2072 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
2073 cmd = SDVO_CMD_SET_##NAME; \
2074 intel_sdvo_connector->cur_##name = temp_value; \
2075 goto set_value; \
2076 }
2077
2078 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 2079 if (val >= TV_FORMAT_NUM)
2080 return -EINVAL;
2081
40039750 2082 if (intel_sdvo->tv_format_index ==
615fb93f 2083 intel_sdvo_connector->tv_format_supported[val])
32aad86f 2084 return 0;
ce6feabd 2085
40039750 2086 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 2087 goto done;
32aad86f 2088 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 2089 temp_value = val;
c5521706 2090 if (intel_sdvo_connector->left == property) {
662595df 2091 drm_object_property_set_value(&connector->base,
c5521706 2092 intel_sdvo_connector->right, val);
615fb93f 2093 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 2094 return 0;
b9219c5e 2095
615fb93f
CW		 2096 intel_sdvo_connector->left_margin = temp_value;
2097 intel_sdvo_connector->right_margin = temp_value;
2098 temp_value = intel_sdvo_connector->max_hscan -
c5521706 2099 intel_sdvo_connector->left_margin;
b9219c5e 2100 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2101 goto set_value;
2102 } else if (intel_sdvo_connector->right == property) {
662595df 2103 drm_object_property_set_value(&connector->base,
c5521706 2104 intel_sdvo_connector->left, val);
615fb93f 2105 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 2106 return 0;
b9219c5e 2107
615fb93f
CW		 2108 intel_sdvo_connector->left_margin = temp_value;
2109 intel_sdvo_connector->right_margin = temp_value;
2110 temp_value = intel_sdvo_connector->max_hscan -
2111 intel_sdvo_connector->left_margin;
b9219c5e 2112 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 2113 goto set_value;
2114 } else if (intel_sdvo_connector->top == property) {
662595df 2115 drm_object_property_set_value(&connector->base,
c5521706 2116 intel_sdvo_connector->bottom, val);
615fb93f 2117 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 2118 return 0;
b9219c5e 2119
615fb93f
CW		 2120 intel_sdvo_connector->top_margin = temp_value;
2121 intel_sdvo_connector->bottom_margin = temp_value;
2122 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2123 intel_sdvo_connector->top_margin;
b9219c5e 2124 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2125 goto set_value;
2126 } else if (intel_sdvo_connector->bottom == property) {
662595df 2127 drm_object_property_set_value(&connector->base,
c5521706 2128 intel_sdvo_connector->top, val);
615fb93f 2129 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 2130 return 0;
2131
615fb93f
CW		 2132 intel_sdvo_connector->top_margin = temp_value;
2133 intel_sdvo_connector->bottom_margin = temp_value;
2134 temp_value = intel_sdvo_connector->max_vscan -
c5521706 2135 intel_sdvo_connector->top_margin;
b9219c5e 2136 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 2137 goto set_value;
2138 }
2139 CHECK_PROPERTY(hpos, HPOS)
2140 CHECK_PROPERTY(vpos, VPOS)
2141 CHECK_PROPERTY(saturation, SATURATION)
2142 CHECK_PROPERTY(contrast, CONTRAST)
2143 CHECK_PROPERTY(hue, HUE)
2144 CHECK_PROPERTY(brightness, BRIGHTNESS)
2145 CHECK_PROPERTY(sharpness, SHARPNESS)
2146 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
2147 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
2148 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
2149 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
2150 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 2151 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 2152 }
b9219c5e 2153
c5521706 2154 return -EINVAL; /* unknown property */
b9219c5e 2155
c5521706
CW		 2156set_value:
2157 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
2158 return -EIO;
b9219c5e 2159
b9219c5e 2160
c5521706 2161done:
c0c36b94
CW		 2162 if (intel_sdvo->base.base.crtc)
2163 intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
c5521706 2164
32aad86f 2165 return 0;
c5521706 2166#undef CHECK_PROPERTY
ce6feabd
ZY		 2167}
2168
7a418e34
CW		 2169static int
2170intel_sdvo_connector_register(struct drm_connector *connector)
2171{
2172 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1ebaa0b9
CW		 2173 int ret;
2174
2175 ret = intel_connector_register(connector);
2176 if (ret)
2177 return ret;
7a418e34
CW		 2178
2179 return sysfs_create_link(&connector->kdev->kobj,
2180 &sdvo->ddc.dev.kobj,
2181 sdvo->ddc.dev.kobj.name);
2182}
2183
c191eca1
CW		 2184static void
2185intel_sdvo_connector_unregister(struct drm_connector *connector)
2186{
2187 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
2188
2189 sysfs_remove_link(&connector->kdev->kobj,
2190 sdvo->ddc.dev.kobj.name);
2191 intel_connector_unregister(connector);
2192}
2193
79e53945 2194static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
4d688a2a 2195 .dpms = drm_atomic_helper_connector_dpms,
79e53945
JB		 2196 .detect = intel_sdvo_detect,
2197 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 2198 .set_property = intel_sdvo_set_property,
2545e4a6 2199 .atomic_get_property = intel_connector_atomic_get_property,
7a418e34 2200 .late_register = intel_sdvo_connector_register,
c191eca1 2201 .early_unregister = intel_sdvo_connector_unregister,
79e53945 2202 .destroy = intel_sdvo_destroy,
c6f95f27 2203 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 2204 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
79e53945
JB		 2205};
2206
2207static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2208 .get_modes = intel_sdvo_get_modes,
2209 .mode_valid = intel_sdvo_mode_valid,
79e53945
JB		 2210};
2211
b358d0a6 2212static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2213{
8aca63aa 2214 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
d2a82a6f 2215
ea5b213a 2216 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2217 drm_mode_destroy(encoder->dev,
ea5b213a 2218 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2219
e957d772 2220 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2221 intel_encoder_destroy(encoder);
79e53945
JB		 2222}
2223
2224static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2225 .destroy = intel_sdvo_enc_destroy,
2226};
2227
b66d8424
CW		 2228static void
2229intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2230{
2231 uint16_t mask = 0;
2232 unsigned int num_bits;
2233
2234 /* Make a mask of outputs less than or equal to our own priority in the
2235 * list.
2236 */
2237 switch (sdvo->controlled_output) {
2238 case SDVO_OUTPUT_LVDS1:
2239 mask |= SDVO_OUTPUT_LVDS1;
2240 case SDVO_OUTPUT_LVDS0:
2241 mask |= SDVO_OUTPUT_LVDS0;
2242 case SDVO_OUTPUT_TMDS1:
2243 mask |= SDVO_OUTPUT_TMDS1;
2244 case SDVO_OUTPUT_TMDS0:
2245 mask |= SDVO_OUTPUT_TMDS0;
2246 case SDVO_OUTPUT_RGB1:
2247 mask |= SDVO_OUTPUT_RGB1;
2248 case SDVO_OUTPUT_RGB0:
2249 mask |= SDVO_OUTPUT_RGB0;
2250 break;
2251 }
2252
2253 /* Count bits to find what number we are in the priority list. */
2254 mask &= sdvo->caps.output_flags;
2255 num_bits = hweight16(mask);
2256 /* If more than 3 outputs, default to DDC bus 3 for now. */
2257 if (num_bits > 3)
2258 num_bits = 3;
2259
2260 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2261 sdvo->ddc_bus = 1 << num_bits;
2262}
79e53945 2263
e2f0ba97
JB		 2264/**
2265 * Choose the appropriate DDC bus for control bus switch command for this
2266 * SDVO output based on the controlled output.
2267 *
2268 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2269 * outputs, then LVDS outputs.
2270 */
2271static void
b1083333 2272intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
8bd864b8 2273 struct intel_sdvo *sdvo)
e2f0ba97 2274{
b1083333 2275 struct sdvo_device_mapping *mapping;
e2f0ba97 2276
2a5c0832 2277 if (sdvo->port == PORT_B)
9d6c875d 2278 mapping = &dev_priv->vbt.sdvo_mappings[0];
b1083333 2279 else
9d6c875d 2280 mapping = &dev_priv->vbt.sdvo_mappings[1];
e2f0ba97 2281
b66d8424
CW		 2282 if (mapping->initialized)
2283 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2284 else
2285 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2286}
2287
e957d772
CW		 2288static void
2289intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
8bd864b8 2290 struct intel_sdvo *sdvo)
e957d772
CW		 2291{
2292 struct sdvo_device_mapping *mapping;
46eb3036 2293 u8 pin;
e957d772 2294
2a5c0832 2295 if (sdvo->port == PORT_B)
9d6c875d 2296 mapping = &dev_priv->vbt.sdvo_mappings[0];
e957d772 2297 else
9d6c875d 2298 mapping = &dev_priv->vbt.sdvo_mappings[1];
e957d772 2299
88ac7939
JN		 2300 if (mapping->initialized &&
2301 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
e957d772 2302 pin = mapping->i2c_pin;
6cb1612a 2303 else
988c7015 2304 pin = GMBUS_PIN_DPB;
e957d772 2305
6cb1612a
JN		 2306 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2307
2308 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2309 * our code totally fails once we start using gmbus. Hence fall back to
2310 * bit banging for now. */
2311 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2312}
2313
fbfcc4f3
JN		 2314/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2315static void
2316intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2317{
2318 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2319}
2320
e2f0ba97 2321static bool
e27d8538 2322intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2323{
97aaf910 2324 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2325}
2326
714605e4 2327static u8
c39055b0
ACO		 2328intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv,
2329 struct intel_sdvo *sdvo)
714605e4 2330{
714605e4 2331 struct sdvo_device_mapping *my_mapping, *other_mapping;
2332
2a5c0832 2333 if (sdvo->port == PORT_B) {
9d6c875d
JN		 2334 my_mapping = &dev_priv->vbt.sdvo_mappings[0];
2335 other_mapping = &dev_priv->vbt.sdvo_mappings[1];
714605e4 2336 } else {
9d6c875d
JN		 2337 my_mapping = &dev_priv->vbt.sdvo_mappings[1];
2338 other_mapping = &dev_priv->vbt.sdvo_mappings[0];
714605e4 2339 }
2340
2341 /* If the BIOS described our SDVO device, take advantage of it. */
2342 if (my_mapping->slave_addr)
2343 return my_mapping->slave_addr;
2344
2345 /* If the BIOS only described a different SDVO device, use the
2346 * address that it isn't using.
2347 */
2348 if (other_mapping->slave_addr) {
2349 if (other_mapping->slave_addr == 0x70)
2350 return 0x72;
2351 else
2352 return 0x70;
2353 }
2354
2355 /* No SDVO device info is found for another DVO port,
2356 * so use mapping assumption we had before BIOS parsing.
2357 */
2a5c0832 2358 if (sdvo->port == PORT_B)
714605e4 2359 return 0x70;
2360 else
2361 return 0x72;
2362}
2363
c393454d 2364static int
df0e9248
CW		 2365intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2366 struct intel_sdvo *encoder)
14571b4c 2367{
c393454d
ID		 2368 struct drm_connector *drm_connector;
2369 int ret;
2370
2371 drm_connector = &connector->base.base;
2372 ret = drm_connector_init(encoder->base.base.dev,
2373 drm_connector,
df0e9248
CW		 2374 &intel_sdvo_connector_funcs,
2375 connector->base.base.connector_type);
c393454d
ID		 2376 if (ret < 0)
2377 return ret;
6070a4a9 2378
c393454d 2379 drm_connector_helper_add(drm_connector,
df0e9248 2380 &intel_sdvo_connector_helper_funcs);
14571b4c 2381
8f4839e2 2382 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2383 connector->base.base.doublescan_allowed = 0;
2384 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2385 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2386
df0e9248 2387 intel_connector_attach_encoder(&connector->base, &encoder->base);
c393454d
ID		 2388
2389 return 0;
14571b4c 2390}
6070a4a9 2391
7f36e7ed 2392static void
55bc60db
VS		 2393intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2394 struct intel_sdvo_connector *connector)
7f36e7ed 2395{
646d5772 2396 struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev);
7f36e7ed 2397
3f43c48d 2398 intel_attach_force_audio_property(&connector->base.base);
646d5772 2399 if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) {
e953fd7b 2400 intel_attach_broadcast_rgb_property(&connector->base.base);
55bc60db
VS		 2401 intel_sdvo->color_range_auto = true;
2402 }
7949dd47 2403 intel_attach_aspect_ratio_property(&connector->base.base);
0e9f25d0 2404 connector->base.base.state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
7f36e7ed
CW		 2405}
2406
08d9bc92
ACO		 2407static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
2408{
2409 struct intel_sdvo_connector *sdvo_connector;
2410
2411 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
2412 if (!sdvo_connector)
2413 return NULL;
2414
2415 if (intel_connector_init(&sdvo_connector->base) < 0) {
2416 kfree(sdvo_connector);
2417 return NULL;
2418 }
2419
2420 return sdvo_connector;
2421}
2422
fb7a46f3 2423static bool
ea5b213a 2424intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2425{
4ef69c7a 2426 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2427 struct drm_connector *connector;
cc68c81a 2428 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2429 struct intel_connector *intel_connector;
615fb93f 2430 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2431
46a3f4a3
CW		 2432 DRM_DEBUG_KMS("initialising DVI device %d\n", device);
2433
08d9bc92 2434 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f 2435 if (!intel_sdvo_connector)
14571b4c
ZW		 2436 return false;
2437
14571b4c 2438 if (device == 0) {
ea5b213a 2439 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2440 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2441 } else if (device == 1) {
ea5b213a 2442 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2443 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2444 }
2445
615fb93f 2446 intel_connector = &intel_sdvo_connector->base;
14571b4c 2447 connector = &intel_connector->base;
5fa7ac9c
JN		 2448 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2449 intel_sdvo_connector->output_flag) {
5fa7ac9c 2450 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
cc68c81a
SF		 2451 /* Some SDVO devices have one-shot hotplug interrupts.
2452 * Ensure that they get re-enabled when an interrupt happens.
2453 */
2454 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
3a2fb2c3 2455 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2456 } else {
821450c6 2457 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2458 }
14571b4c
ZW		 2459 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2460 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2461
e27d8538 2462 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2463 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2464 intel_sdvo->is_hdmi = true;
14571b4c 2465 }
14571b4c 2466
c393454d
ID		 2467 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2468 kfree(intel_sdvo_connector);
2469 return false;
2470 }
2471
f797d221 2472 if (intel_sdvo->is_hdmi)
55bc60db 2473 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
14571b4c
ZW		 2474
2475 return true;
2476}
2477
2478static bool
ea5b213a 2479intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2480{
4ef69c7a
CW		 2481 struct drm_encoder *encoder = &intel_sdvo->base.base;
2482 struct drm_connector *connector;
2483 struct intel_connector *intel_connector;
2484 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2485
46a3f4a3
CW		 2486 DRM_DEBUG_KMS("initialising TV type %d\n", type);
2487
08d9bc92 2488 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2489 if (!intel_sdvo_connector)
2490 return false;
14571b4c 2491
615fb93f 2492 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2493 connector = &intel_connector->base;
2494 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2495 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2496
4ef69c7a
CW		 2497 intel_sdvo->controlled_output |= type;
2498 intel_sdvo_connector->output_flag = type;
14571b4c 2499
4ef69c7a 2500 intel_sdvo->is_tv = true;
14571b4c 2501
c393454d
ID		 2502 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2503 kfree(intel_sdvo_connector);
2504 return false;
2505 }
14571b4c 2506
4ef69c7a 2507 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2508 goto err;
14571b4c 2509
4ef69c7a 2510 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2511 goto err;
14571b4c 2512
4ef69c7a 2513 return true;
32aad86f
CW		 2514
2515err:
123d5c01 2516 intel_sdvo_destroy(connector);
32aad86f 2517 return false;
14571b4c
ZW		 2518}
2519
2520static bool
ea5b213a 2521intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2522{
4ef69c7a
CW		 2523 struct drm_encoder *encoder = &intel_sdvo->base.base;
2524 struct drm_connector *connector;
2525 struct intel_connector *intel_connector;
2526 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2527
46a3f4a3
CW		 2528 DRM_DEBUG_KMS("initialising analog device %d\n", device);
2529
8ce7da47 2530 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2531 if (!intel_sdvo_connector)
2532 return false;
14571b4c 2533
615fb93f 2534 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2535 connector = &intel_connector->base;
821450c6 2536 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2537 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2538 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2539
2540 if (device == 0) {
2541 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2542 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2543 } else if (device == 1) {
2544 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2545 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2546 }
2547
c393454d
ID		 2548 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2549 kfree(intel_sdvo_connector);
2550 return false;
2551 }
2552
4ef69c7a 2553 return true;
14571b4c
ZW		 2554}
2555
2556static bool
ea5b213a 2557intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2558{
4ef69c7a
CW		 2559 struct drm_encoder *encoder = &intel_sdvo->base.base;
2560 struct drm_connector *connector;
2561 struct intel_connector *intel_connector;
2562 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2563
46a3f4a3
CW		 2564 DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
2565
08d9bc92 2566 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2567 if (!intel_sdvo_connector)
2568 return false;
14571b4c 2569
615fb93f
CW		 2570 intel_connector = &intel_sdvo_connector->base;
2571 connector = &intel_connector->base;
4ef69c7a
CW		 2572 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2573 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2574
2575 if (device == 0) {
2576 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2577 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2578 } else if (device == 1) {
2579 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2580 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2581 }
2582
c393454d
ID		 2583 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2584 kfree(intel_sdvo_connector);
2585 return false;
2586 }
2587
4ef69c7a 2588 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2589 goto err;
2590
2591 return true;
2592
2593err:
123d5c01 2594 intel_sdvo_destroy(connector);
32aad86f 2595 return false;
14571b4c
ZW		 2596}
2597
2598static bool
ea5b213a 2599intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2600{
ea5b213a 2601 intel_sdvo->is_tv = false;
ea5b213a 2602 intel_sdvo->is_lvds = false;
fb7a46f3 2603
14571b4c 2604 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2605
14571b4c 2606 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2607 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2608 return false;
2609
2610 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2611 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2612 return false;
2613
2614 /* TV has no XXX1 function block */
a1f4b7ff 2615 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2616 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2617 return false;
2618
2619 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2620 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2621 return false;
fb7a46f3 2622
a0b1c7a5
CW		 2623 if (flags & SDVO_OUTPUT_YPRPB0)
2624 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2625 return false;
2626
14571b4c 2627 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2628 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2629 return false;
2630
2631 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2632 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2633 return false;
2634
2635 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2636 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2637 return false;
2638
2639 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2640 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2641 return false;
fb7a46f3 2642
14571b4c 2643 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2644 unsigned char bytes[2];
2645
ea5b213a
CW		 2646 intel_sdvo->controlled_output = 0;
2647 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2648 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2649 SDVO_NAME(intel_sdvo),
51c8b407 2650 bytes[0], bytes[1]);
14571b4c 2651 return false;
fb7a46f3 2652 }
27f8227b 2653 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2654
14571b4c 2655 return true;
fb7a46f3 2656}
2657
d0ddfbd3
JN		 2658static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2659{
2660 struct drm_device *dev = intel_sdvo->base.base.dev;
2661 struct drm_connector *connector, *tmp;
2662
2663 list_for_each_entry_safe(connector, tmp,
2664 &dev->mode_config.connector_list, head) {
d9255d57 2665 if (intel_attached_encoder(connector) == &intel_sdvo->base) {
34ea3d38 2666 drm_connector_unregister(connector);
d0ddfbd3 2667 intel_sdvo_destroy(connector);
d9255d57 2668 }
d0ddfbd3
JN		 2669 }
2670}
2671
32aad86f
CW		 2672static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2673 struct intel_sdvo_connector *intel_sdvo_connector,
2674 int type)
ce6feabd 2675{
4ef69c7a 2676 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2677 struct intel_sdvo_tv_format format;
2678 uint32_t format_map, i;
ce6feabd 2679
32aad86f
CW		 2680 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2681 return false;
ce6feabd 2682
1a3665c8 2683 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2684 if (!intel_sdvo_get_value(intel_sdvo,
2685 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2686 &format, sizeof(format)))
2687 return false;
ce6feabd 2688
32aad86f 2689 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2690
2691 if (format_map == 0)
32aad86f 2692 return false;
ce6feabd 2693
615fb93f 2694 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2695 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2696 if (format_map & (1 << i))
2697 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2698
2699
c5521706 2700 intel_sdvo_connector->tv_format =
32aad86f
CW		 2701 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2702 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2703 if (!intel_sdvo_connector->tv_format)
fcc8d672 2704 return false;
ce6feabd 2705
615fb93f 2706 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2707 drm_property_add_enum(
c5521706 2708 intel_sdvo_connector->tv_format, i,
40039750 2709 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2710
40039750 2711 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
662595df 2712 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
c5521706 2713 intel_sdvo_connector->tv_format, 0);
32aad86f 2714 return true;
ce6feabd
ZY		 2715
2716}
2717
c5521706
CW		 2718#define ENHANCEMENT(name, NAME) do { \
2719 if (enhancements.name) { \
2720 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2721 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2722 return false; \
2723 intel_sdvo_connector->max_##name = data_value[0]; \
2724 intel_sdvo_connector->cur_##name = response; \
2725 intel_sdvo_connector->name = \
d9bc3c02 2726 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2727 if (!intel_sdvo_connector->name) return false; \
662595df 2728 drm_object_attach_property(&connector->base, \
c5521706
CW		 2729 intel_sdvo_connector->name, \
2730 intel_sdvo_connector->cur_##name); \
2731 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2732 data_value[0], data_value[1], response); \
2733 } \
0206e353 2734} while (0)
c5521706
CW		 2735
2736static bool
2737intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2738 struct intel_sdvo_connector *intel_sdvo_connector,
2739 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2740{
4ef69c7a 2741 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2742 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2743 uint16_t response, data_value[2];
2744
c5521706
CW		 2745 /* when horizontal overscan is supported, Add the left/right property */
2746 if (enhancements.overscan_h) {
2747 if (!intel_sdvo_get_value(intel_sdvo,
2748 SDVO_CMD_GET_MAX_OVERSCAN_H,
2749 &data_value, 4))
2750 return false;
32aad86f 2751
c5521706
CW		 2752 if (!intel_sdvo_get_value(intel_sdvo,
2753 SDVO_CMD_GET_OVERSCAN_H,
2754 &response, 2))
2755 return false;
fcc8d672 2756
c5521706
CW		 2757 intel_sdvo_connector->max_hscan = data_value[0];
2758 intel_sdvo_connector->left_margin = data_value[0] - response;
2759 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2760 intel_sdvo_connector->left =
d9bc3c02 2761 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2762 if (!intel_sdvo_connector->left)
2763 return false;
fcc8d672 2764
662595df 2765 drm_object_attach_property(&connector->base,
c5521706
CW		 2766 intel_sdvo_connector->left,
2767 intel_sdvo_connector->left_margin);
fcc8d672 2768
c5521706 2769 intel_sdvo_connector->right =
d9bc3c02 2770 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2771 if (!intel_sdvo_connector->right)
2772 return false;
32aad86f 2773
662595df 2774 drm_object_attach_property(&connector->base,
c5521706
CW		 2775 intel_sdvo_connector->right,
2776 intel_sdvo_connector->right_margin);
2777 DRM_DEBUG_KMS("h_overscan: max %d, "
2778 "default %d, current %d\n",
2779 data_value[0], data_value[1], response);
2780 }
32aad86f 2781
c5521706
CW		 2782 if (enhancements.overscan_v) {
2783 if (!intel_sdvo_get_value(intel_sdvo,
2784 SDVO_CMD_GET_MAX_OVERSCAN_V,
2785 &data_value, 4))
2786 return false;
fcc8d672 2787
c5521706
CW		 2788 if (!intel_sdvo_get_value(intel_sdvo,
2789 SDVO_CMD_GET_OVERSCAN_V,
2790 &response, 2))
2791 return false;
32aad86f 2792
c5521706
CW		 2793 intel_sdvo_connector->max_vscan = data_value[0];
2794 intel_sdvo_connector->top_margin = data_value[0] - response;
2795 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2796 intel_sdvo_connector->top =
d9bc3c02
SH		 2797 drm_property_create_range(dev, 0,
2798 "top_margin", 0, data_value[0]);
c5521706
CW		 2799 if (!intel_sdvo_connector->top)
2800 return false;
32aad86f 2801
662595df 2802 drm_object_attach_property(&connector->base,
c5521706
CW		 2803 intel_sdvo_connector->top,
2804 intel_sdvo_connector->top_margin);
fcc8d672 2805
c5521706 2806 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2807 drm_property_create_range(dev, 0,
2808 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2809 if (!intel_sdvo_connector->bottom)
2810 return false;
32aad86f 2811
662595df 2812 drm_object_attach_property(&connector->base,
c5521706
CW		 2813 intel_sdvo_connector->bottom,
2814 intel_sdvo_connector->bottom_margin);
2815 DRM_DEBUG_KMS("v_overscan: max %d, "
2816 "default %d, current %d\n",
2817 data_value[0], data_value[1], response);
2818 }
32aad86f 2819
c5521706
CW		 2820 ENHANCEMENT(hpos, HPOS);
2821 ENHANCEMENT(vpos, VPOS);
2822 ENHANCEMENT(saturation, SATURATION);
2823 ENHANCEMENT(contrast, CONTRAST);
2824 ENHANCEMENT(hue, HUE);
2825 ENHANCEMENT(sharpness, SHARPNESS);
2826 ENHANCEMENT(brightness, BRIGHTNESS);
2827 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2828 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2829 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2830 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2831 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2832
e044218a
CW		 2833 if (enhancements.dot_crawl) {
2834 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2835 return false;
2836
2837 intel_sdvo_connector->max_dot_crawl = 1;
2838 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2839 intel_sdvo_connector->dot_crawl =
d9bc3c02 2840 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2841 if (!intel_sdvo_connector->dot_crawl)
2842 return false;
2843
662595df 2844 drm_object_attach_property(&connector->base,
e044218a
CW		 2845 intel_sdvo_connector->dot_crawl,
2846 intel_sdvo_connector->cur_dot_crawl);
2847 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2848 }
2849
c5521706
CW		 2850 return true;
2851}
32aad86f 2852
c5521706
CW		 2853static bool
2854intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2855 struct intel_sdvo_connector *intel_sdvo_connector,
2856 struct intel_sdvo_enhancements_reply enhancements)
2857{
4ef69c7a 2858 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2859 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2860 uint16_t response, data_value[2];
32aad86f 2861
c5521706 2862 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2863
c5521706
CW		 2864 return true;
2865}
2866#undef ENHANCEMENT
32aad86f 2867
c5521706
CW		 2868static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2869 struct intel_sdvo_connector *intel_sdvo_connector)
2870{
2871 union {
2872 struct intel_sdvo_enhancements_reply reply;
2873 uint16_t response;
2874 } enhancements;
32aad86f 2875
1a3665c8
CW		 2876 BUILD_BUG_ON(sizeof(enhancements) != 2);
2877
cf9a2f3a
CW		 2878 enhancements.response = 0;
2879 intel_sdvo_get_value(intel_sdvo,
2880 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2881 &enhancements, sizeof(enhancements));
c5521706
CW		 2882 if (enhancements.response == 0) {
2883 DRM_DEBUG_KMS("No enhancement is supported\n");
2884 return true;
b9219c5e 2885 }
32aad86f 2886
c5521706
CW		 2887 if (IS_TV(intel_sdvo_connector))
2888 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2889 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2890 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2891 else
2892 return true;
e957d772
CW		 2893}
2894
2895static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2896 struct i2c_msg *msgs,
2897 int num)
2898{
2899 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2900
e957d772
CW		 2901 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2902 return -EIO;
2903
2904 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2905}
2906
2907static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2908{
2909 struct intel_sdvo *sdvo = adapter->algo_data;
2910 return sdvo->i2c->algo->functionality(sdvo->i2c);
2911}
2912
2913static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2914 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2915 .functionality = intel_sdvo_ddc_proxy_func
2916};
2917
2918static bool
2919intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
c39055b0 2920 struct drm_i915_private *dev_priv)
e957d772 2921{
c39055b0 2922 struct pci_dev *pdev = dev_priv->drm.pdev;
52a05c30 2923
e957d772
CW		 2924 sdvo->ddc.owner = THIS_MODULE;
2925 sdvo->ddc.class = I2C_CLASS_DDC;
2926 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
52a05c30 2927 sdvo->ddc.dev.parent = &pdev->dev;
e957d772
CW		 2928 sdvo->ddc.algo_data = sdvo;
2929 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2930
2931 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2932}
2933
2a5c0832
VS		 2934static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv,
2935 enum port port)
2936{
2937 if (HAS_PCH_SPLIT(dev_priv))
2938 WARN_ON(port != PORT_B);
2939 else
2940 WARN_ON(port != PORT_B && port != PORT_C);
2941}
2942
c39055b0 2943bool intel_sdvo_init(struct drm_i915_private *dev_priv,
f0f59a00 2944 i915_reg_t sdvo_reg, enum port port)
79e53945 2945{
21d40d37 2946 struct intel_encoder *intel_encoder;
ea5b213a 2947 struct intel_sdvo *intel_sdvo;
79e53945 2948 int i;
2a5c0832
VS		 2949
2950 assert_sdvo_port_valid(dev_priv, port);
2951
b14c5679 2952 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
ea5b213a 2953 if (!intel_sdvo)
7d57382e 2954 return false;
79e53945 2955
56184e3d 2956 intel_sdvo->sdvo_reg = sdvo_reg;
2a5c0832 2957 intel_sdvo->port = port;
c39055b0
ACO		 2958 intel_sdvo->slave_addr =
2959 intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1;
8bd864b8 2960 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
c39055b0 2961 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv))
fbfcc4f3 2962 goto err_i2c_bus;
e957d772 2963
56184e3d 2964 /* encoder type will be decided later */
ea5b213a 2965 intel_encoder = &intel_sdvo->base;
21d40d37 2966 intel_encoder->type = INTEL_OUTPUT_SDVO;
79f255a0 2967 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
03cdc1d4 2968 intel_encoder->port = port;
c39055b0
ACO		 2969 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2970 &intel_sdvo_enc_funcs, 0,
580d8ed5 2971 "SDVO %c", port_name(port));
79e53945 2972
79e53945
JB		 2973 /* Read the regs to test if we can talk to the device */
2974 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2975 u8 byte;
2976
2977 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2978 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2979 SDVO_NAME(intel_sdvo));
f899fc64 2980 goto err;
79e53945
JB		 2981 }
2982 }
2983
6cc5f341 2984 intel_encoder->compute_config = intel_sdvo_compute_config;
6e266956 2985 if (HAS_PCH_SPLIT(dev_priv)) {
3c65d1d1
VS		 2986 intel_encoder->disable = pch_disable_sdvo;
2987 intel_encoder->post_disable = pch_post_disable_sdvo;
2988 } else {
2989 intel_encoder->disable = intel_disable_sdvo;
2990 }
192d47a6 2991 intel_encoder->pre_enable = intel_sdvo_pre_enable;
ce22c320 2992 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 2993 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
045ac3b5 2994 intel_encoder->get_config = intel_sdvo_get_config;
ce22c320 2995
af901ca1 2996 /* In default case sdvo lvds is false */
32aad86f 2997 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2998 goto err;
79e53945 2999
ea5b213a
CW		 3000 if (intel_sdvo_output_setup(intel_sdvo,
3001 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 3002 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
3003 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 3004 /* Output_setup can leave behind connectors! */
3005 goto err_output;
79e53945
JB		 3006 }
3007
7ba220ce
CW		 3008 /* Only enable the hotplug irq if we need it, to work around noisy
3009 * hotplug lines.
3010 */
3011 if (intel_sdvo->hotplug_active) {
2a5c0832
VS		 3012 if (intel_sdvo->port == PORT_B)
3013 intel_encoder->hpd_pin = HPD_SDVO_B;
3014 else
3015 intel_encoder->hpd_pin = HPD_SDVO_C;
7ba220ce
CW		 3016 }
3017
e506d6fd
DV		 3018 /*
3019 * Cloning SDVO with anything is often impossible, since the SDVO
3020 * encoder can request a special input timing mode. And even if that's
3021 * not the case we have evidence that cloning a plain unscaled mode with
3022 * VGA doesn't really work. Furthermore the cloning flags are way too
3023 * simplistic anyway to express such constraints, so just give up on
3024 * cloning for SDVO encoders.
3025 */
bc079e8b 3026 intel_sdvo->base.cloneable = 0;
e506d6fd 3027
8bd864b8 3028 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
e2f0ba97 3029
79e53945 3030 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 3031 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 3032 goto err_output;
79e53945 3033
32aad86f
CW		 3034 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3035 &intel_sdvo->pixel_clock_min,
3036 &intel_sdvo->pixel_clock_max))
d0ddfbd3 3037 goto err_output;
79e53945 3038
8a4c47f3 3039 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 3040 "clock range %dMHz - %dMHz, "
3041 "input 1: %c, input 2: %c, "
3042 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 3043 SDVO_NAME(intel_sdvo),
3044 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3045 intel_sdvo->caps.device_rev_id,
3046 intel_sdvo->pixel_clock_min / 1000,
3047 intel_sdvo->pixel_clock_max / 1000,
3048 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3049 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 3050 /* check currently supported outputs */
ea5b213a 3051 intel_sdvo->caps.output_flags &
79e53945 3052 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 3053 intel_sdvo->caps.output_flags &
79e53945 3054 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 3055 return true;
79e53945 3056
d0ddfbd3
JN		 3057err_output:
3058 intel_sdvo_output_cleanup(intel_sdvo);
3059
f899fc64 3060err:
373a3cf7 3061 drm_encoder_cleanup(&intel_encoder->base);
e957d772 3062 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 3063err_i2c_bus:
3064 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 3065 kfree(intel_sdvo);
79e53945 3066
7d57382e 3067 return false;
79e53945 3068}
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