]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/gpu/drm/i915/intel_sdvo.c
projects / mirror_ubuntu-zesty-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Use msleep instead of mdelay during wait_vblank_off
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945
JB		 30#include <linux/delay.h>
31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
2b8d33f7 34#include "drm_edid.h"
ea5b213a 35#include "intel_drv.h"
79e53945
JB		 36#include "i915_drm.h"
37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
46 SDVO_TV_MASK)
47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 50#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
14571b4c 51
79e53945 52
2e88e40b 53static const char *tv_format_names[] = {
ce6feabd
ZY		 54 "NTSC_M" , "NTSC_J" , "NTSC_443",
55 "PAL_B" , "PAL_D" , "PAL_G" ,
56 "PAL_H" , "PAL_I" , "PAL_M" ,
57 "PAL_N" , "PAL_NC" , "PAL_60" ,
58 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
59 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
60 "SECAM_60"
61};
62
63#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
64
ea5b213a
CW		 65struct intel_sdvo {
66 struct intel_encoder base;
67
f9c10a9b 68 u8 slave_addr;
e2f0ba97
JB		 69
70 /* Register for the SDVO device: SDVOB or SDVOC */
c751ce4f 71 int sdvo_reg;
79e53945 72
e2f0ba97
JB		 73 /* Active outputs controlled by this SDVO output */
74 uint16_t controlled_output;
79e53945 75
e2f0ba97
JB		 76 /*
77 * Capabilities of the SDVO device returned by
78 * i830_sdvo_get_capabilities()
79 */
79e53945 80 struct intel_sdvo_caps caps;
e2f0ba97
JB		 81
82 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 83 int pixel_clock_min, pixel_clock_max;
84
fb7a46f3 85 /*
86 * For multiple function SDVO device,
87 * this is for current attached outputs.
88 */
89 uint16_t attached_output;
90
e2f0ba97
JB		 91 /**
92 * This is set if we're going to treat the device as TV-out.
93 *
94 * While we have these nice friendly flags for output types that ought
95 * to decide this for us, the S-Video output on our HDMI+S-Video card
96 * shows up as RGB1 (VGA).
97 */
98 bool is_tv;
99
ce6feabd 100 /* This is for current tv format name */
40039750 101 int tv_format_index;
ce6feabd 102
e2f0ba97
JB		 103 /**
104 * This is set if we treat the device as HDMI, instead of DVI.
105 */
106 bool is_hdmi;
12682a97 107
7086c87f 108 /**
6c9547ff
CW		 109 * This is set if we detect output of sdvo device as LVDS and
110 * have a valid fixed mode to use with the panel.
7086c87f
ML		 111 */
112 bool is_lvds;
e2f0ba97 113
12682a97 114 /**
115 * This is sdvo fixed pannel mode pointer
116 */
117 struct drm_display_mode *sdvo_lvds_fixed_mode;
118
e2f0ba97
JB		 119 /*
120 * supported encoding mode, used to determine whether HDMI is
121 * supported
122 */
123 struct intel_sdvo_encode encode;
124
c751ce4f 125 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 126 uint8_t ddc_bus;
127
57cdaf90
KP		 128 /* Mac mini hack -- use the same DDC as the analog connector */
129 struct i2c_adapter *analog_ddc_bus;
130
6c9547ff
CW		 131 /* Input timings for adjusted_mode */
132 struct intel_sdvo_dtd input_dtd;
14571b4c
ZW		 133};
134
135struct intel_sdvo_connector {
615fb93f
CW		 136 struct intel_connector base;
137
14571b4c
ZW		 138 /* Mark the type of connector */
139 uint16_t output_flag;
140
141 /* This contains all current supported TV format */
40039750 142 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 143 int format_supported_num;
c5521706 144 struct drm_property *tv_format;
14571b4c 145
b9219c5e 146 /* add the property for the SDVO-TV */
c5521706
CW		 147 struct drm_property *left;
148 struct drm_property *right;
149 struct drm_property *top;
150 struct drm_property *bottom;
151 struct drm_property *hpos;
152 struct drm_property *vpos;
153 struct drm_property *contrast;
154 struct drm_property *saturation;
155 struct drm_property *hue;
156 struct drm_property *sharpness;
157 struct drm_property *flicker_filter;
158 struct drm_property *flicker_filter_adaptive;
159 struct drm_property *flicker_filter_2d;
160 struct drm_property *tv_chroma_filter;
161 struct drm_property *tv_luma_filter;
e044218a 162 struct drm_property *dot_crawl;
b9219c5e
ZY		 163
164 /* add the property for the SDVO-TV/LVDS */
c5521706 165 struct drm_property *brightness;
b9219c5e
ZY		 166
167 /* Add variable to record current setting for the above property */
168 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 169
b9219c5e
ZY		 170 /* this is to get the range of margin.*/
171 u32 max_hscan, max_vscan;
172 u32 max_hpos, cur_hpos;
173 u32 max_vpos, cur_vpos;
174 u32 cur_brightness, max_brightness;
175 u32 cur_contrast, max_contrast;
176 u32 cur_saturation, max_saturation;
177 u32 cur_hue, max_hue;
c5521706
CW		 178 u32 cur_sharpness, max_sharpness;
179 u32 cur_flicker_filter, max_flicker_filter;
180 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
181 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
182 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
183 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 184 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 185};
186
ea5b213a
CW		 187static struct intel_sdvo *enc_to_intel_sdvo(struct drm_encoder *encoder)
188{
4ef69c7a 189 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 190}
191
df0e9248
CW		 192static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
193{
194 return container_of(intel_attached_encoder(connector),
195 struct intel_sdvo, base);
196}
197
615fb93f
CW		 198static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
199{
200 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
201}
202
fb7a46f3 203static bool
ea5b213a 204intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 205static bool
206intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
207 struct intel_sdvo_connector *intel_sdvo_connector,
208 int type);
209static bool
210intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
211 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 212
79e53945
JB		 213/**
214 * Writes the SDVOB or SDVOC with the given value, but always writes both
215 * SDVOB and SDVOC to work around apparent hardware issues (according to
216 * comments in the BIOS).
217 */
ea5b213a 218static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 219{
4ef69c7a 220 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 221 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 222 u32 bval = val, cval = val;
223 int i;
224
ea5b213a
CW		 225 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
226 I915_WRITE(intel_sdvo->sdvo_reg, val);
227 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 228 return;
229 }
230
ea5b213a 231 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 232 cval = I915_READ(SDVOC);
233 } else {
234 bval = I915_READ(SDVOB);
235 }
236 /*
237 * Write the registers twice for luck. Sometimes,
238 * writing them only once doesn't appear to 'stick'.
239 * The BIOS does this too. Yay, magic
240 */
241 for (i = 0; i < 2; i++)
242 {
243 I915_WRITE(SDVOB, bval);
244 I915_READ(SDVOB);
245 I915_WRITE(SDVOC, cval);
246 I915_READ(SDVOC);
247 }
248}
249
32aad86f 250static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 251{
32aad86f 252 u8 out_buf[2] = { addr, 0 };
79e53945 253 u8 buf[2];
79e53945
JB		 254 struct i2c_msg msgs[] = {
255 {
ea5b213a 256 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 257 .flags = 0,
258 .len = 1,
259 .buf = out_buf,
260 },
261 {
ea5b213a 262 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 263 .flags = I2C_M_RD,
264 .len = 1,
265 .buf = buf,
266 }
267 };
32aad86f 268 int ret;
79e53945 269
ea5b213a 270 if ((ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 2)) == 2)
79e53945
JB		 271 {
272 *ch = buf[0];
273 return true;
274 }
275
8a4c47f3 276 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 277 return false;
278}
279
32aad86f 280static bool intel_sdvo_write_byte(struct intel_sdvo *intel_sdvo, int addr, u8 ch)
79e53945 281{
32aad86f 282 u8 out_buf[2] = { addr, ch };
79e53945
JB		 283 struct i2c_msg msgs[] = {
284 {
ea5b213a 285 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 286 .flags = 0,
287 .len = 2,
288 .buf = out_buf,
289 }
290 };
291
32aad86f 292 return i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 1) == 1;
79e53945
JB		 293}
294
295#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
296/** Mapping of command numbers to names, for debug output */
005568be 297static const struct _sdvo_cmd_name {
e2f0ba97 298 u8 cmd;
2e88e40b 299 const char *name;
79e53945
JB		 300} sdvo_cmd_names[] = {
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
e2f0ba97
JB		 336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
79e53945 340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
e2f0ba97
JB		 341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
c5521706 344
b9219c5e 345 /* Add the op code for SDVO enhancements */
c5521706
CW		 346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
b9219c5e
ZY		 352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
c5521706
CW		 370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
390
e2f0ba97
JB		 391 /* HDMI op code */
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
409 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
410 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
411 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 412};
413
461ed3ca 414#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
ea5b213a 415#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
79e53945 416
ea5b213a 417static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 418 const void *args, int args_len)
79e53945 419{
79e53945
JB		 420 int i;
421
8a4c47f3 422 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 423 SDVO_NAME(intel_sdvo), cmd);
79e53945 424 for (i = 0; i < args_len; i++)
342dc382 425 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 426 for (; i < 8; i++)
342dc382 427 DRM_LOG_KMS(" ");
04ad327f 428 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 429 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 430 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 431 break;
432 }
433 }
04ad327f 434 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 435 DRM_LOG_KMS("(%02X)", cmd);
436 DRM_LOG_KMS("\n");
79e53945 437}
79e53945 438
32aad86f
CW		 439static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
440 const void *args, int args_len)
79e53945
JB		 441{
442 int i;
443
ea5b213a 444 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 445
446 for (i = 0; i < args_len; i++) {
32aad86f
CW		 447 if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0 - i,
448 ((u8*)args)[i]))
449 return false;
79e53945
JB		 450 }
451
32aad86f 452 return intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_OPCODE, cmd);
79e53945
JB		 453}
454
79e53945
JB		 455static const char *cmd_status_names[] = {
456 "Power on",
457 "Success",
458 "Not supported",
459 "Invalid arg",
460 "Pending",
461 "Target not specified",
462 "Scaling not supported"
463};
464
ea5b213a 465static void intel_sdvo_debug_response(struct intel_sdvo *intel_sdvo,
79e53945
JB		 466 void *response, int response_len,
467 u8 status)
468{
33b52961 469 int i;
79e53945 470
ea5b213a 471 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
79e53945 472 for (i = 0; i < response_len; i++)
342dc382 473 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
79e53945 474 for (; i < 8; i++)
342dc382 475 DRM_LOG_KMS(" ");
79e53945 476 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 477 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 478 else
342dc382 479 DRM_LOG_KMS("(??? %d)", status);
480 DRM_LOG_KMS("\n");
79e53945 481}
79e53945 482
32aad86f
CW		 483static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
484 void *response, int response_len)
79e53945
JB		 485{
486 int i;
487 u8 status;
488 u8 retry = 50;
489
490 while (retry--) {
491 /* Read the command response */
492 for (i = 0; i < response_len; i++) {
32aad86f
CW		 493 if (!intel_sdvo_read_byte(intel_sdvo,
494 SDVO_I2C_RETURN_0 + i,
495 &((u8 *)response)[i]))
496 return false;
79e53945
JB		 497 }
498
499 /* read the return status */
32aad86f
CW		 500 if (!intel_sdvo_read_byte(intel_sdvo, SDVO_I2C_CMD_STATUS,
501 &status))
502 return false;
79e53945 503
ea5b213a 504 intel_sdvo_debug_response(intel_sdvo, response, response_len,
79e53945
JB		 505 status);
506 if (status != SDVO_CMD_STATUS_PENDING)
32aad86f 507 break;
79e53945
JB		 508
509 mdelay(50);
510 }
511
32aad86f 512 return status == SDVO_CMD_STATUS_SUCCESS;
79e53945
JB		 513}
514
b358d0a6 515static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 516{
517 if (mode->clock >= 100000)
518 return 1;
519 else if (mode->clock >= 50000)
520 return 2;
521 else
522 return 4;
523}
524
525/**
6a304caf
ZY		 526 * Try to read the response after issuie the DDC switch command. But it
527 * is noted that we must do the action of reading response and issuing DDC
528 * switch command in one I2C transaction. Otherwise when we try to start
529 * another I2C transaction after issuing the DDC bus switch, it will be
530 * switched to the internal SDVO register.
79e53945 531 */
ea5b213a 532static void intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
b358d0a6 533 u8 target)
79e53945 534{
6a304caf
ZY		 535 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
536 struct i2c_msg msgs[] = {
537 {
ea5b213a 538 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 539 .flags = 0,
540 .len = 2,
541 .buf = out_buf,
542 },
543 /* the following two are to read the response */
544 {
ea5b213a 545 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 546 .flags = 0,
547 .len = 1,
548 .buf = cmd_buf,
549 },
550 {
ea5b213a 551 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 552 .flags = I2C_M_RD,
553 .len = 1,
554 .buf = ret_value,
555 },
556 };
557
ea5b213a 558 intel_sdvo_debug_write(intel_sdvo, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
6a304caf
ZY		 559 &target, 1);
560 /* write the DDC switch command argument */
ea5b213a 561 intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0, target);
6a304caf
ZY		 562
563 out_buf[0] = SDVO_I2C_OPCODE;
564 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
565 cmd_buf[0] = SDVO_I2C_CMD_STATUS;
566 cmd_buf[1] = 0;
567 ret_value[0] = 0;
568 ret_value[1] = 0;
569
ea5b213a 570 ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 3);
6a304caf
ZY		 571 if (ret != 3) {
572 /* failure in I2C transfer */
573 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
574 return;
575 }
576 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
577 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
578 ret_value[0]);
579 return;
580 }
581 return;
79e53945
JB		 582}
583
32aad86f 584static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 585{
32aad86f
CW		 586 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
587 return false;
79e53945 588
32aad86f
CW		 589 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
590}
79e53945 591
32aad86f
CW		 592static bool
593intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
594{
595 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
596 return false;
79e53945 597
32aad86f
CW		 598 return intel_sdvo_read_response(intel_sdvo, value, len);
599}
79e53945 600
32aad86f
CW		 601static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
602{
603 struct intel_sdvo_set_target_input_args targets = {0};
604 return intel_sdvo_set_value(intel_sdvo,
605 SDVO_CMD_SET_TARGET_INPUT,
606 &targets, sizeof(targets));
79e53945
JB		 607}
608
609/**
610 * Return whether each input is trained.
611 *
612 * This function is making an assumption about the layout of the response,
613 * which should be checked against the docs.
614 */
ea5b213a 615static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 616{
617 struct intel_sdvo_get_trained_inputs_response response;
79e53945 618
32aad86f
CW		 619 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
620 &response, sizeof(response)))
79e53945
JB		 621 return false;
622
623 *input_1 = response.input0_trained;
624 *input_2 = response.input1_trained;
625 return true;
626}
627
ea5b213a 628static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 629 u16 outputs)
630{
32aad86f
CW		 631 return intel_sdvo_set_value(intel_sdvo,
632 SDVO_CMD_SET_ACTIVE_OUTPUTS,
633 &outputs, sizeof(outputs));
79e53945
JB		 634}
635
ea5b213a 636static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 637 int mode)
638{
32aad86f 639 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 640
641 switch (mode) {
642 case DRM_MODE_DPMS_ON:
643 state = SDVO_ENCODER_STATE_ON;
644 break;
645 case DRM_MODE_DPMS_STANDBY:
646 state = SDVO_ENCODER_STATE_STANDBY;
647 break;
648 case DRM_MODE_DPMS_SUSPEND:
649 state = SDVO_ENCODER_STATE_SUSPEND;
650 break;
651 case DRM_MODE_DPMS_OFF:
652 state = SDVO_ENCODER_STATE_OFF;
653 break;
654 }
655
32aad86f
CW		 656 return intel_sdvo_set_value(intel_sdvo,
657 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 658}
659
ea5b213a 660static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 661 int *clock_min,
662 int *clock_max)
663{
664 struct intel_sdvo_pixel_clock_range clocks;
79e53945 665
32aad86f
CW		 666 if (!intel_sdvo_get_value(intel_sdvo,
667 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
668 &clocks, sizeof(clocks)))
79e53945
JB		 669 return false;
670
671 /* Convert the values from units of 10 kHz to kHz. */
672 *clock_min = clocks.min * 10;
673 *clock_max = clocks.max * 10;
79e53945
JB		 674 return true;
675}
676
ea5b213a 677static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 678 u16 outputs)
679{
32aad86f
CW		 680 return intel_sdvo_set_value(intel_sdvo,
681 SDVO_CMD_SET_TARGET_OUTPUT,
682 &outputs, sizeof(outputs));
79e53945
JB		 683}
684
ea5b213a 685static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 686 struct intel_sdvo_dtd *dtd)
687{
32aad86f
CW		 688 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
689 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 690}
691
ea5b213a 692static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 693 struct intel_sdvo_dtd *dtd)
694{
ea5b213a 695 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 696 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
697}
698
ea5b213a 699static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 700 struct intel_sdvo_dtd *dtd)
701{
ea5b213a 702 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 703 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
704}
705
e2f0ba97 706static bool
ea5b213a 707intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 708 uint16_t clock,
709 uint16_t width,
710 uint16_t height)
711{
712 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 713
e642c6f1 714 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 715 args.clock = clock;
716 args.width = width;
717 args.height = height;
e642c6f1 718 args.interlace = 0;
12682a97 719
ea5b213a
CW		 720 if (intel_sdvo->is_lvds &&
721 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
722 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 723 args.scaled = 1;
724
32aad86f
CW		 725 return intel_sdvo_set_value(intel_sdvo,
726 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
727 &args, sizeof(args));
e2f0ba97
JB		 728}
729
ea5b213a 730static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 731 struct intel_sdvo_dtd *dtd)
732{
32aad86f
CW		 733 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
734 &dtd->part1, sizeof(dtd->part1)) &&
735 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
736 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 737}
79e53945 738
ea5b213a 739static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 740{
32aad86f 741 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 742}
743
e2f0ba97 744static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 745 const struct drm_display_mode *mode)
79e53945 746{
e2f0ba97
JB		 747 uint16_t width, height;
748 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
749 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 750
751 width = mode->crtc_hdisplay;
752 height = mode->crtc_vdisplay;
753
754 /* do some mode translations */
755 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
756 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
757
758 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
759 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
760
761 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
762 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
763
e2f0ba97
JB		 764 dtd->part1.clock = mode->clock / 10;
765 dtd->part1.h_active = width & 0xff;
766 dtd->part1.h_blank = h_blank_len & 0xff;
767 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 768 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 769 dtd->part1.v_active = height & 0xff;
770 dtd->part1.v_blank = v_blank_len & 0xff;
771 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 772 ((v_blank_len >> 8) & 0xf);
773
171a9e96 774 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 775 dtd->part2.h_sync_width = h_sync_len & 0xff;
776 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 777 (v_sync_len & 0xf);
e2f0ba97 778 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 779 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
780 ((v_sync_len & 0x30) >> 4);
781
e2f0ba97 782 dtd->part2.dtd_flags = 0x18;
79e53945 783 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 784 dtd->part2.dtd_flags |= 0x2;
79e53945 785 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 786 dtd->part2.dtd_flags |= 0x4;
787
788 dtd->part2.sdvo_flags = 0;
789 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
790 dtd->part2.reserved = 0;
791}
792
793static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 794 const struct intel_sdvo_dtd *dtd)
e2f0ba97 795{
e2f0ba97
JB		 796 mode->hdisplay = dtd->part1.h_active;
797 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
798 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 799 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 800 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
801 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
802 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
803 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
804
805 mode->vdisplay = dtd->part1.v_active;
806 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
807 mode->vsync_start = mode->vdisplay;
808 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 809 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 810 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
811 mode->vsync_end = mode->vsync_start +
812 (dtd->part2.v_sync_off_width & 0xf);
813 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
814 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
815 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
816
817 mode->clock = dtd->part1.clock * 10;
818
171a9e96 819 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 820 if (dtd->part2.dtd_flags & 0x2)
821 mode->flags |= DRM_MODE_FLAG_PHSYNC;
822 if (dtd->part2.dtd_flags & 0x4)
823 mode->flags |= DRM_MODE_FLAG_PVSYNC;
824}
825
ea5b213a 826static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 827 struct intel_sdvo_encode *encode)
828{
32aad86f
CW		 829 if (intel_sdvo_get_value(intel_sdvo,
830 SDVO_CMD_GET_SUPP_ENCODE,
831 encode, sizeof(*encode)))
832 return true;
e2f0ba97 833
32aad86f
CW		 834 /* non-support means DVI */
835 memset(encode, 0, sizeof(*encode));
836 return false;
e2f0ba97
JB		 837}
838
ea5b213a 839static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 840 uint8_t mode)
e2f0ba97 841{
32aad86f 842 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 843}
844
ea5b213a 845static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 846 uint8_t mode)
847{
32aad86f 848 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 849}
850
851#if 0
ea5b213a 852static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 853{
854 int i, j;
855 uint8_t set_buf_index[2];
856 uint8_t av_split;
857 uint8_t buf_size;
858 uint8_t buf[48];
859 uint8_t *pos;
860
32aad86f 861 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 862
863 for (i = 0; i <= av_split; i++) {
864 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 865 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 866 set_buf_index, 2);
c751ce4f
EA		 867 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
868 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 869
870 pos = buf;
871 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 872 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 873 NULL, 0);
c751ce4f 874 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 875 pos += 8;
876 }
877 }
878}
879#endif
880
32aad86f 881static bool intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo,
c751ce4f
EA		 882 int index,
883 uint8_t *data, int8_t size, uint8_t tx_rate)
e2f0ba97
JB		 884{
885 uint8_t set_buf_index[2];
886
887 set_buf_index[0] = index;
888 set_buf_index[1] = 0;
889
32aad86f
CW		 890 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX,
891 set_buf_index, 2))
892 return false;
e2f0ba97
JB		 893
894 for (; size > 0; size -= 8) {
32aad86f
CW		 895 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8))
896 return false;
897
e2f0ba97
JB		 898 data += 8;
899 }
900
32aad86f 901 return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
e2f0ba97
JB		 902}
903
904static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
905{
906 uint8_t csum = 0;
907 int i;
908
909 for (i = 0; i < size; i++)
910 csum += data[i];
911
912 return 0x100 - csum;
913}
914
915#define DIP_TYPE_AVI 0x82
916#define DIP_VERSION_AVI 0x2
917#define DIP_LEN_AVI 13
918
919struct dip_infoframe {
920 uint8_t type;
921 uint8_t version;
922 uint8_t len;
923 uint8_t checksum;
924 union {
925 struct {
926 /* Packet Byte #1 */
927 uint8_t S:2;
928 uint8_t B:2;
929 uint8_t A:1;
930 uint8_t Y:2;
931 uint8_t rsvd1:1;
932 /* Packet Byte #2 */
933 uint8_t R:4;
934 uint8_t M:2;
935 uint8_t C:2;
936 /* Packet Byte #3 */
937 uint8_t SC:2;
938 uint8_t Q:2;
939 uint8_t EC:3;
940 uint8_t ITC:1;
941 /* Packet Byte #4 */
942 uint8_t VIC:7;
943 uint8_t rsvd2:1;
944 /* Packet Byte #5 */
945 uint8_t PR:4;
946 uint8_t rsvd3:4;
947 /* Packet Byte #6~13 */
948 uint16_t top_bar_end;
949 uint16_t bottom_bar_start;
950 uint16_t left_bar_end;
951 uint16_t right_bar_start;
952 } avi;
953 struct {
954 /* Packet Byte #1 */
955 uint8_t channel_count:3;
956 uint8_t rsvd1:1;
957 uint8_t coding_type:4;
958 /* Packet Byte #2 */
959 uint8_t sample_size:2; /* SS0, SS1 */
960 uint8_t sample_frequency:3;
961 uint8_t rsvd2:3;
962 /* Packet Byte #3 */
963 uint8_t coding_type_private:5;
964 uint8_t rsvd3:3;
965 /* Packet Byte #4 */
966 uint8_t channel_allocation;
967 /* Packet Byte #5 */
968 uint8_t rsvd4:3;
969 uint8_t level_shift:4;
970 uint8_t downmix_inhibit:1;
971 } audio;
972 uint8_t payload[28];
973 } __attribute__ ((packed)) u;
974} __attribute__((packed));
975
32aad86f 976static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 977 struct drm_display_mode * mode)
978{
979 struct dip_infoframe avi_if = {
980 .type = DIP_TYPE_AVI,
981 .version = DIP_VERSION_AVI,
982 .len = DIP_LEN_AVI,
983 };
984
985 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
986 4 + avi_if.len);
32aad86f
CW		 987 return intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if,
988 4 + avi_if.len,
989 SDVO_HBUF_TX_VSYNC);
e2f0ba97
JB		 990}
991
32aad86f 992static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 993{
ce6feabd 994 struct intel_sdvo_tv_format format;
40039750 995 uint32_t format_map;
ce6feabd 996
40039750 997 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 998 memset(&format, 0, sizeof(format));
32aad86f 999 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1000
32aad86f
CW		 1001 BUILD_BUG_ON(sizeof(format) != 6);
1002 return intel_sdvo_set_value(intel_sdvo,
1003 SDVO_CMD_SET_TV_FORMAT,
1004 &format, sizeof(format));
7026d4ac
ZW		 1005}
1006
32aad86f
CW		 1007static bool
1008intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1009 struct drm_display_mode *mode)
e2f0ba97 1010{
32aad86f 1011 struct intel_sdvo_dtd output_dtd;
79e53945 1012
32aad86f
CW		 1013 if (!intel_sdvo_set_target_output(intel_sdvo,
1014 intel_sdvo->attached_output))
1015 return false;
e2f0ba97 1016
32aad86f
CW		 1017 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1018 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1019 return false;
e2f0ba97 1020
32aad86f
CW		 1021 return true;
1022}
1023
1024static bool
1025intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
1026 struct drm_display_mode *mode,
1027 struct drm_display_mode *adjusted_mode)
1028{
32aad86f
CW		 1029 /* Reset the input timing to the screen. Assume always input 0. */
1030 if (!intel_sdvo_set_target_input(intel_sdvo))
1031 return false;
e2f0ba97 1032
32aad86f
CW		 1033 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1034 mode->clock / 10,
1035 mode->hdisplay,
1036 mode->vdisplay))
1037 return false;
e2f0ba97 1038
32aad86f 1039 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
6c9547ff 1040 &intel_sdvo->input_dtd))
32aad86f 1041 return false;
e2f0ba97 1042
6c9547ff 1043 intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
79e53945 1044
32aad86f 1045 drm_mode_set_crtcinfo(adjusted_mode, 0);
32aad86f
CW		 1046 return true;
1047}
12682a97 1048
32aad86f
CW		 1049static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1050 struct drm_display_mode *mode,
1051 struct drm_display_mode *adjusted_mode)
1052{
1053 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
6c9547ff 1054 int multiplier;
12682a97 1055
32aad86f
CW		 1056 /* We need to construct preferred input timings based on our
1057 * output timings. To do that, we have to set the output
1058 * timings, even though this isn't really the right place in
1059 * the sequence to do it. Oh well.
1060 */
1061 if (intel_sdvo->is_tv) {
1062 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1063 return false;
12682a97 1064
c74696b9
PR		 1065 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1066 mode,
1067 adjusted_mode);
ea5b213a 1068 } else if (intel_sdvo->is_lvds) {
32aad86f 1069 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1070 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1071 return false;
12682a97 1072
c74696b9
PR		 1073 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1074 mode,
1075 adjusted_mode);
e2f0ba97 1076 }
32aad86f
CW		 1077
1078 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1079 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1080 */
6c9547ff
CW		 1081 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
1082 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 1083
e2f0ba97
JB		 1084 return true;
1085}
1086
1087static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1088 struct drm_display_mode *mode,
1089 struct drm_display_mode *adjusted_mode)
1090{
1091 struct drm_device *dev = encoder->dev;
1092 struct drm_i915_private *dev_priv = dev->dev_private;
1093 struct drm_crtc *crtc = encoder->crtc;
1094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea5b213a 1095 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
6c9547ff 1096 u32 sdvox;
e2f0ba97
JB		 1097 struct intel_sdvo_in_out_map in_out;
1098 struct intel_sdvo_dtd input_dtd;
6c9547ff
CW		 1099 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1100 int rate;
e2f0ba97
JB		 1101
1102 if (!mode)
1103 return;
1104
1105 /* First, set the input mapping for the first input to our controlled
1106 * output. This is only correct if we're a single-input device, in
1107 * which case the first input is the output from the appropriate SDVO
1108 * channel on the motherboard. In a two-input device, the first input
1109 * will be SDVOB and the second SDVOC.
1110 */
ea5b213a 1111 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1112 in_out.in1 = 0;
1113
c74696b9
PR		 1114 intel_sdvo_set_value(intel_sdvo,
1115 SDVO_CMD_SET_IN_OUT_MAP,
1116 &in_out, sizeof(in_out));
e2f0ba97 1117
6c9547ff
CW		 1118 /* Set the output timings to the screen */
1119 if (!intel_sdvo_set_target_output(intel_sdvo,
1120 intel_sdvo->attached_output))
1121 return;
e2f0ba97 1122
7026d4ac 1123 /* We have tried to get input timing in mode_fixup, and filled into
6c9547ff 1124 * adjusted_mode.
e2f0ba97 1125 */
6c9547ff
CW		 1126 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
1127 input_dtd = intel_sdvo->input_dtd;
1128 } else {
e2f0ba97 1129 /* Set the output timing to the screen */
32aad86f
CW		 1130 if (!intel_sdvo_set_target_output(intel_sdvo,
1131 intel_sdvo->attached_output))
1132 return;
1133
6c9547ff 1134 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c74696b9 1135 (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
e2f0ba97 1136 }
79e53945
JB		 1137
1138 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1139 if (!intel_sdvo_set_target_input(intel_sdvo))
1140 return;
79e53945 1141
6c9547ff
CW		 1142 if (intel_sdvo->is_hdmi &&
1143 !intel_sdvo_set_avi_infoframe(intel_sdvo, mode))
1144 return;
7026d4ac 1145
6c9547ff
CW		 1146 if (intel_sdvo->is_tv &&
1147 !intel_sdvo_set_tv_format(intel_sdvo))
1148 return;
e2f0ba97 1149
c74696b9 1150 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
79e53945 1151
6c9547ff
CW		 1152 switch (pixel_multiplier) {
1153 default:
32aad86f
CW		 1154 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1155 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1156 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1157 }
32aad86f
CW		 1158 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1159 return;
79e53945
JB		 1160
1161 /* Set the SDVO control regs. */
e2f0ba97 1162 if (IS_I965G(dev)) {
6c9547ff 1163 sdvox = SDVO_BORDER_ENABLE;
81a14b46
AJ		 1164 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1165 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
1166 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1167 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
e2f0ba97 1168 } else {
6c9547ff 1169 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1170 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1171 case SDVOB:
1172 sdvox &= SDVOB_PRESERVE_MASK;
1173 break;
1174 case SDVOC:
1175 sdvox &= SDVOC_PRESERVE_MASK;
1176 break;
1177 }
1178 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1179 }
79e53945
JB		 1180 if (intel_crtc->pipe == 1)
1181 sdvox |= SDVO_PIPE_B_SELECT;
6c9547ff
CW		 1182 if (intel_sdvo->is_hdmi)
1183 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1184
79e53945 1185 if (IS_I965G(dev)) {
e2f0ba97
JB		 1186 /* done in crtc_mode_set as the dpll_md reg must be written early */
1187 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1188 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1189 } else {
6c9547ff 1190 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1191 }
1192
6c9547ff 1193 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL)
12682a97 1194 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1195 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1196}
1197
1198static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1199{
1200 struct drm_device *dev = encoder->dev;
1201 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 1202 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
9d0498a2 1203 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1204 u32 temp;
1205
1206 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1207 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1208 if (0)
ea5b213a 1209 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1210
1211 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1212 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1213 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1214 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1215 }
1216 }
1217 } else {
1218 bool input1, input2;
1219 int i;
1220 u8 status;
1221
ea5b213a 1222 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1223 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1224 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1225 for (i = 0; i < 2; i++)
9d0498a2 1226 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1227
32aad86f 1228 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1229 /* Warn if the device reported failure to sync.
1230 * A lot of SDVO devices fail to notify of sync, but it's
1231 * a given it the status is a success, we succeeded.
1232 */
1233 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1234 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1235 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1236 }
1237
1238 if (0)
ea5b213a
CW		 1239 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1240 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1241 }
1242 return;
1243}
1244
79e53945
JB		 1245static int intel_sdvo_mode_valid(struct drm_connector *connector,
1246 struct drm_display_mode *mode)
1247{
df0e9248 1248 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1249
1250 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1251 return MODE_NO_DBLESCAN;
1252
ea5b213a 1253 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1254 return MODE_CLOCK_LOW;
1255
ea5b213a 1256 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1257 return MODE_CLOCK_HIGH;
1258
8545423a 1259 if (intel_sdvo->is_lvds) {
ea5b213a 1260 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1261 return MODE_PANEL;
1262
ea5b213a 1263 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1264 return MODE_PANEL;
1265 }
1266
79e53945
JB		 1267 return MODE_OK;
1268}
1269
ea5b213a 1270static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1271{
32aad86f 1272 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, caps, sizeof(*caps));
79e53945
JB		 1273}
1274
d2a82a6f
ZW		 1275/* No use! */
1276#if 0
79e53945
JB		 1277struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1278{
1279 struct drm_connector *connector = NULL;
ea5b213a
CW		 1280 struct intel_sdvo *iout = NULL;
1281 struct intel_sdvo *sdvo;
79e53945
JB		 1282
1283 /* find the sdvo connector */
1284 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
ea5b213a 1285 iout = to_intel_sdvo(connector);
79e53945
JB		 1286
1287 if (iout->type != INTEL_OUTPUT_SDVO)
1288 continue;
1289
1290 sdvo = iout->dev_priv;
1291
c751ce4f 1292 if (sdvo->sdvo_reg == SDVOB && sdvoB)
79e53945
JB		 1293 return connector;
1294
c751ce4f 1295 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
79e53945
JB		 1296 return connector;
1297
1298 }
1299
1300 return NULL;
1301}
1302
1303int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1304{
1305 u8 response[2];
1306 u8 status;
ea5b213a 1307 struct intel_sdvo *intel_sdvo;
8a4c47f3 1308 DRM_DEBUG_KMS("\n");
79e53945
JB		 1309
1310 if (!connector)
1311 return 0;
1312
ea5b213a 1313 intel_sdvo = to_intel_sdvo(connector);
79e53945 1314
32aad86f
CW		 1315 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1316 &response, 2) && response[0];
79e53945
JB		 1317}
1318
1319void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1320{
1321 u8 response[2];
1322 u8 status;
ea5b213a 1323 struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector);
79e53945 1324
ea5b213a
CW		 1325 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1326 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945
JB		 1327
1328 if (on) {
ea5b213a
CW		 1329 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1330 status = intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1331
ea5b213a 1332 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1333 } else {
1334 response[0] = 0;
1335 response[1] = 0;
ea5b213a 1336 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1337 }
1338
ea5b213a
CW		 1339 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1340 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1341}
d2a82a6f 1342#endif
79e53945 1343
fb7a46f3 1344static bool
ea5b213a 1345intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1346{
fb7a46f3 1347 int caps = 0;
1348
ea5b213a 1349 if (intel_sdvo->caps.output_flags &
fb7a46f3 1350 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1351 caps++;
ea5b213a 1352 if (intel_sdvo->caps.output_flags &
fb7a46f3 1353 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1354 caps++;
ea5b213a 1355 if (intel_sdvo->caps.output_flags &
19e1f888 1356 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
fb7a46f3 1357 caps++;
ea5b213a 1358 if (intel_sdvo->caps.output_flags &
fb7a46f3 1359 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1360 caps++;
ea5b213a 1361 if (intel_sdvo->caps.output_flags &
fb7a46f3 1362 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1363 caps++;
1364
ea5b213a 1365 if (intel_sdvo->caps.output_flags &
fb7a46f3 1366 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1367 caps++;
1368
ea5b213a 1369 if (intel_sdvo->caps.output_flags &
fb7a46f3 1370 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1371 caps++;
1372
1373 return (caps > 1);
1374}
1375
57cdaf90
KP		 1376static struct drm_connector *
1377intel_find_analog_connector(struct drm_device *dev)
1378{
1379 struct drm_connector *connector;
df0e9248
CW		 1380 struct intel_sdvo *encoder;
1381
1382 list_for_each_entry(encoder,
1383 &dev->mode_config.encoder_list,
1384 base.base.head) {
1385 if (encoder->base.type == INTEL_OUTPUT_ANALOG) {
1386 list_for_each_entry(connector,
1387 &dev->mode_config.connector_list,
1388 head) {
1389 if (&encoder->base ==
1390 intel_attached_encoder(connector))
d2a82a6f
ZW		 1391 return connector;
1392 }
1393 }
57cdaf90 1394 }
df0e9248 1395
57cdaf90
KP		 1396 return NULL;
1397}
1398
1399static int
1400intel_analog_is_connected(struct drm_device *dev)
1401{
1402 struct drm_connector *analog_connector;
57cdaf90 1403
32aad86f 1404 analog_connector = intel_find_analog_connector(dev);
57cdaf90
KP		 1405 if (!analog_connector)
1406 return false;
1407
1408 if (analog_connector->funcs->detect(analog_connector) ==
1409 connector_status_disconnected)
1410 return false;
1411
1412 return true;
1413}
1414
2b8d33f7 1415enum drm_connector_status
149c36a3 1416intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
9dff6af8 1417{
df0e9248 1418 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1419 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2b8d33f7 1420 enum drm_connector_status status = connector_status_connected;
9dff6af8
ML		 1421 struct edid *edid = NULL;
1422
ea5b213a 1423 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
57cdaf90 1424
7c3f0a27 1425 /* This is only applied to SDVO cards with multiple outputs */
ea5b213a 1426 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
7c3f0a27 1427 uint8_t saved_ddc, temp_ddc;
ea5b213a
CW		 1428 saved_ddc = intel_sdvo->ddc_bus;
1429 temp_ddc = intel_sdvo->ddc_bus >> 1;
7c3f0a27
ZY		 1430 /*
1431 * Don't use the 1 as the argument of DDC bus switch to get
1432 * the EDID. It is used for SDVO SPD ROM.
1433 */
1434 while(temp_ddc > 1) {
ea5b213a
CW		 1435 intel_sdvo->ddc_bus = temp_ddc;
1436 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
7c3f0a27
ZY		 1437 if (edid) {
1438 /*
1439 * When we can get the EDID, maybe it is the
1440 * correct DDC bus. Update it.
1441 */
ea5b213a 1442 intel_sdvo->ddc_bus = temp_ddc;
7c3f0a27
ZY		 1443 break;
1444 }
1445 temp_ddc >>= 1;
1446 }
1447 if (edid == NULL)
ea5b213a 1448 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1449 }
57cdaf90
KP		 1450 /* when there is no edid and no monitor is connected with VGA
1451 * port, try to use the CRT ddc to read the EDID for DVI-connector
1452 */
ea5b213a 1453 if (edid == NULL && intel_sdvo->analog_ddc_bus &&
d2a82a6f 1454 !intel_analog_is_connected(connector->dev))
ea5b213a 1455 edid = drm_get_edid(connector, intel_sdvo->analog_ddc_bus);
149c36a3 1456
9dff6af8 1457 if (edid != NULL) {
149c36a3 1458 bool is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
615fb93f 1459 bool need_digital = !!(intel_sdvo_connector->output_flag & SDVO_TMDS_MASK);
2b8d33f7 1460
149c36a3
AJ		 1461 /* DDC bus is shared, match EDID to connector type */
1462 if (is_digital && need_digital)
ea5b213a 1463 intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid);
149c36a3
AJ		 1464 else if (is_digital != need_digital)
1465 status = connector_status_disconnected;
2b8d33f7 1466
149c36a3
AJ		 1467 connector->display_info.raw_edid = NULL;
1468 } else
2b8d33f7 1469 status = connector_status_disconnected;
149c36a3
AJ		 1470
1471 kfree(edid);
2b8d33f7 1472
1473 return status;
9dff6af8
ML		 1474}
1475
79e53945
JB		 1476static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1477{
fb7a46f3 1478 uint16_t response;
df0e9248 1479 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1480 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1481 enum drm_connector_status ret;
79e53945 1482
32aad86f
CW		 1483 if (!intel_sdvo_write_cmd(intel_sdvo,
1484 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
1485 return connector_status_unknown;
ea5b213a 1486 if (intel_sdvo->is_tv) {
d09c23de
ZY		 1487 /* add 30ms delay when the output type is SDVO-TV */
1488 mdelay(30);
1489 }
32aad86f
CW		 1490 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1491 return connector_status_unknown;
79e53945 1492
51c8b407 1493 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
e2f0ba97 1494
fb7a46f3 1495 if (response == 0)
79e53945 1496 return connector_status_disconnected;
fb7a46f3 1497
ea5b213a 1498 intel_sdvo->attached_output = response;
14571b4c 1499
615fb93f 1500 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1501 ret = connector_status_disconnected;
149c36a3
AJ		 1502 else if (response & SDVO_TMDS_MASK)
1503 ret = intel_sdvo_hdmi_sink_detect(connector);
14571b4c
ZW		 1504 else
1505 ret = connector_status_connected;
1506
1507 /* May update encoder flag for like clock for SDVO TV, etc.*/
1508 if (ret == connector_status_connected) {
ea5b213a
CW		 1509 intel_sdvo->is_tv = false;
1510 intel_sdvo->is_lvds = false;
1511 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1512
1513 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1514 intel_sdvo->is_tv = true;
1515 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1516 }
1517 if (response & SDVO_LVDS_MASK)
8545423a 1518 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1519 }
14571b4c
ZW		 1520
1521 return ret;
79e53945
JB		 1522}
1523
e2f0ba97 1524static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1525{
df0e9248 1526 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
57cdaf90 1527 int num_modes;
79e53945
JB		 1528
1529 /* set the bus switch and get the modes */
ea5b213a 1530 num_modes = intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
79e53945 1531
57cdaf90
KP		 1532 /*
1533 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1534 * link between analog and digital outputs. So, if the regular SDVO
1535 * DDC fails, check to see if the analog output is disconnected, in
1536 * which case we'll look there for the digital DDC data.
e2f0ba97 1537 */
57cdaf90 1538 if (num_modes == 0 &&
ea5b213a 1539 intel_sdvo->analog_ddc_bus &&
d2a82a6f 1540 !intel_analog_is_connected(connector->dev)) {
57cdaf90
KP		 1541 /* Switch to the analog ddc bus and try that
1542 */
ea5b213a 1543 (void) intel_ddc_get_modes(connector, intel_sdvo->analog_ddc_bus);
e2f0ba97 1544 }
e2f0ba97
JB		 1545}
1546
1547/*
1548 * Set of SDVO TV modes.
1549 * Note! This is in reply order (see loop in get_tv_modes).
1550 * XXX: all 60Hz refresh?
1551 */
1552struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1553 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1554 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1555 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1556 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1557 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1558 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1559 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1560 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1561 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1562 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1563 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1565 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1566 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1567 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1568 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1569 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1570 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1571 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1572 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1573 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1574 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1575 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1577 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1578 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1580 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1581 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1583 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1584 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1586 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1587 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1589 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1590 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1592 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1593 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1595 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1596 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1598 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1599 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1601 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1602 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1603 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1604 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1605 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1606 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1607 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1608 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1610};
1611
1612static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1613{
df0e9248 1614 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1615 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1616 uint32_t reply = 0, format_map = 0;
1617 int i;
e2f0ba97
JB		 1618
1619 /* Read the list of supported input resolutions for the selected TV
1620 * format.
1621 */
40039750 1622 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1623 memcpy(&tv_res, &format_map,
32aad86f 1624 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1625
32aad86f
CW		 1626 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1627 return;
ce6feabd 1628
32aad86f
CW		 1629 BUILD_BUG_ON(sizeof(tv_res) != 3);
1630 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1631 &tv_res, sizeof(tv_res)))
1632 return;
1633 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1634 return;
1635
1636 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1637 if (reply & (1 << i)) {
1638 struct drm_display_mode *nmode;
1639 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1640 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1641 if (nmode)
1642 drm_mode_probed_add(connector, nmode);
1643 }
e2f0ba97
JB		 1644}
1645
7086c87f
ML		 1646static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1647{
df0e9248 1648 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1649 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1650 struct drm_display_mode *newmode;
7086c87f
ML		 1651
1652 /*
1653 * Attempt to get the mode list from DDC.
1654 * Assume that the preferred modes are
1655 * arranged in priority order.
1656 */
ea5b213a 1657 intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
7086c87f 1658 if (list_empty(&connector->probed_modes) == false)
12682a97 1659 goto end;
7086c87f
ML		 1660
1661 /* Fetch modes from VBT */
1662 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1663 newmode = drm_mode_duplicate(connector->dev,
1664 dev_priv->sdvo_lvds_vbt_mode);
1665 if (newmode != NULL) {
1666 /* Guarantee the mode is preferred */
1667 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1668 DRM_MODE_TYPE_DRIVER);
1669 drm_mode_probed_add(connector, newmode);
1670 }
1671 }
12682a97 1672
1673end:
1674 list_for_each_entry(newmode, &connector->probed_modes, head) {
1675 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1676 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1677 drm_mode_duplicate(connector->dev, newmode);
6c9547ff
CW		 1678
1679 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode,
1680 0);
1681
8545423a 1682 intel_sdvo->is_lvds = true;
12682a97 1683 break;
1684 }
1685 }
1686
7086c87f
ML		 1687}
1688
e2f0ba97
JB		 1689static int intel_sdvo_get_modes(struct drm_connector *connector)
1690{
615fb93f 1691 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1692
615fb93f 1693 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1694 intel_sdvo_get_tv_modes(connector);
615fb93f 1695 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1696 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1697 else
1698 intel_sdvo_get_ddc_modes(connector);
1699
32aad86f 1700 return !list_empty(&connector->probed_modes);
79e53945
JB		 1701}
1702
fcc8d672
CW		 1703static void
1704intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1705{
615fb93f 1706 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1707 struct drm_device *dev = connector->dev;
1708
c5521706
CW		 1709 if (intel_sdvo_connector->left)
1710 drm_property_destroy(dev, intel_sdvo_connector->left);
1711 if (intel_sdvo_connector->right)
1712 drm_property_destroy(dev, intel_sdvo_connector->right);
1713 if (intel_sdvo_connector->top)
1714 drm_property_destroy(dev, intel_sdvo_connector->top);
1715 if (intel_sdvo_connector->bottom)
1716 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1717 if (intel_sdvo_connector->hpos)
1718 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1719 if (intel_sdvo_connector->vpos)
1720 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1721 if (intel_sdvo_connector->saturation)
1722 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1723 if (intel_sdvo_connector->contrast)
1724 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1725 if (intel_sdvo_connector->hue)
1726 drm_property_destroy(dev, intel_sdvo_connector->hue);
1727 if (intel_sdvo_connector->sharpness)
1728 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1729 if (intel_sdvo_connector->flicker_filter)
1730 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1731 if (intel_sdvo_connector->flicker_filter_2d)
1732 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1733 if (intel_sdvo_connector->flicker_filter_adaptive)
1734 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1735 if (intel_sdvo_connector->tv_luma_filter)
1736 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1737 if (intel_sdvo_connector->tv_chroma_filter)
1738 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1739 if (intel_sdvo_connector->dot_crawl)
1740 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1741 if (intel_sdvo_connector->brightness)
1742 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1743}
1744
79e53945
JB		 1745static void intel_sdvo_destroy(struct drm_connector *connector)
1746{
615fb93f 1747 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1748
c5521706 1749 if (intel_sdvo_connector->tv_format)
ce6feabd 1750 drm_property_destroy(connector->dev,
c5521706 1751 intel_sdvo_connector->tv_format);
b9219c5e 1752
d2a82a6f 1753 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1754 drm_sysfs_connector_remove(connector);
1755 drm_connector_cleanup(connector);
d2a82a6f 1756 kfree(connector);
79e53945
JB		 1757}
1758
ce6feabd
ZY		 1759static int
1760intel_sdvo_set_property(struct drm_connector *connector,
1761 struct drm_property *property,
1762 uint64_t val)
1763{
df0e9248 1764 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1765 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e 1766 uint16_t temp_value;
32aad86f
CW		 1767 uint8_t cmd;
1768 int ret;
ce6feabd
ZY		 1769
1770 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1771 if (ret)
1772 return ret;
ce6feabd 1773
c5521706
CW		 1774#define CHECK_PROPERTY(name, NAME) \
1775 if (intel_sdvo_connector->name == property) { \
1776 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1777 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1778 cmd = SDVO_CMD_SET_##NAME; \
1779 intel_sdvo_connector->cur_##name = temp_value; \
1780 goto set_value; \
1781 }
1782
1783 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1784 if (val >= TV_FORMAT_NUM)
1785 return -EINVAL;
1786
40039750 1787 if (intel_sdvo->tv_format_index ==
615fb93f 1788 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1789 return 0;
ce6feabd 1790
40039750 1791 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1792 goto done;
32aad86f 1793 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1794 temp_value = val;
c5521706 1795 if (intel_sdvo_connector->left == property) {
b9219c5e 1796 drm_connector_property_set_value(connector,
c5521706 1797 intel_sdvo_connector->right, val);
615fb93f 1798 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1799 return 0;
b9219c5e 1800
615fb93f
CW		 1801 intel_sdvo_connector->left_margin = temp_value;
1802 intel_sdvo_connector->right_margin = temp_value;
1803 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1804 intel_sdvo_connector->left_margin;
b9219c5e 1805 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1806 goto set_value;
1807 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1808 drm_connector_property_set_value(connector,
c5521706 1809 intel_sdvo_connector->left, val);
615fb93f 1810 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1811 return 0;
b9219c5e 1812
615fb93f
CW		 1813 intel_sdvo_connector->left_margin = temp_value;
1814 intel_sdvo_connector->right_margin = temp_value;
1815 temp_value = intel_sdvo_connector->max_hscan -
1816 intel_sdvo_connector->left_margin;
b9219c5e 1817 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1818 goto set_value;
1819 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1820 drm_connector_property_set_value(connector,
c5521706 1821 intel_sdvo_connector->bottom, val);
615fb93f 1822 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1823 return 0;
b9219c5e 1824
615fb93f
CW		 1825 intel_sdvo_connector->top_margin = temp_value;
1826 intel_sdvo_connector->bottom_margin = temp_value;
1827 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1828 intel_sdvo_connector->top_margin;
b9219c5e 1829 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1830 goto set_value;
1831 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1832 drm_connector_property_set_value(connector,
c5521706 1833 intel_sdvo_connector->top, val);
615fb93f 1834 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1835 return 0;
1836
615fb93f
CW		 1837 intel_sdvo_connector->top_margin = temp_value;
1838 intel_sdvo_connector->bottom_margin = temp_value;
1839 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1840 intel_sdvo_connector->top_margin;
b9219c5e 1841 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1842 goto set_value;
1843 }
1844 CHECK_PROPERTY(hpos, HPOS)
1845 CHECK_PROPERTY(vpos, VPOS)
1846 CHECK_PROPERTY(saturation, SATURATION)
1847 CHECK_PROPERTY(contrast, CONTRAST)
1848 CHECK_PROPERTY(hue, HUE)
1849 CHECK_PROPERTY(brightness, BRIGHTNESS)
1850 CHECK_PROPERTY(sharpness, SHARPNESS)
1851 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1852 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1853 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1854 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1855 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1856 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1857 }
b9219c5e 1858
c5521706 1859 return -EINVAL; /* unknown property */
b9219c5e 1860
c5521706
CW		 1861set_value:
1862 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1863 return -EIO;
b9219c5e 1864
b9219c5e 1865
c5521706 1866done:
df0e9248
CW		 1867 if (intel_sdvo->base.base.crtc) {
1868 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
ce6feabd 1869 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1870 crtc->y, crtc->fb);
1871 }
1872
32aad86f 1873 return 0;
c5521706 1874#undef CHECK_PROPERTY
ce6feabd
ZY		 1875}
1876
79e53945
JB		 1877static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1878 .dpms = intel_sdvo_dpms,
1879 .mode_fixup = intel_sdvo_mode_fixup,
1880 .prepare = intel_encoder_prepare,
1881 .mode_set = intel_sdvo_mode_set,
1882 .commit = intel_encoder_commit,
1883};
1884
1885static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1886 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1887 .detect = intel_sdvo_detect,
1888 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1889 .set_property = intel_sdvo_set_property,
79e53945
JB		 1890 .destroy = intel_sdvo_destroy,
1891};
1892
1893static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1894 .get_modes = intel_sdvo_get_modes,
1895 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1896 .best_encoder = intel_best_encoder,
79e53945
JB		 1897};
1898
b358d0a6 1899static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1900{
ea5b213a 1901 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
d2a82a6f 1902
ea5b213a
CW		 1903 if (intel_sdvo->analog_ddc_bus)
1904 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
d2a82a6f 1905
ea5b213a 1906 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1907 drm_mode_destroy(encoder->dev,
ea5b213a 1908 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1909
ea5b213a 1910 intel_encoder_destroy(encoder);
79e53945
JB		 1911}
1912
1913static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1914 .destroy = intel_sdvo_enc_destroy,
1915};
1916
b66d8424
CW		 1917static void
1918intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1919{
1920 uint16_t mask = 0;
1921 unsigned int num_bits;
1922
1923 /* Make a mask of outputs less than or equal to our own priority in the
1924 * list.
1925 */
1926 switch (sdvo->controlled_output) {
1927 case SDVO_OUTPUT_LVDS1:
1928 mask |= SDVO_OUTPUT_LVDS1;
1929 case SDVO_OUTPUT_LVDS0:
1930 mask |= SDVO_OUTPUT_LVDS0;
1931 case SDVO_OUTPUT_TMDS1:
1932 mask |= SDVO_OUTPUT_TMDS1;
1933 case SDVO_OUTPUT_TMDS0:
1934 mask |= SDVO_OUTPUT_TMDS0;
1935 case SDVO_OUTPUT_RGB1:
1936 mask |= SDVO_OUTPUT_RGB1;
1937 case SDVO_OUTPUT_RGB0:
1938 mask |= SDVO_OUTPUT_RGB0;
1939 break;
1940 }
1941
1942 /* Count bits to find what number we are in the priority list. */
1943 mask &= sdvo->caps.output_flags;
1944 num_bits = hweight16(mask);
1945 /* If more than 3 outputs, default to DDC bus 3 for now. */
1946 if (num_bits > 3)
1947 num_bits = 3;
1948
1949 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1950 sdvo->ddc_bus = 1 << num_bits;
1951}
79e53945 1952
e2f0ba97
JB		 1953/**
1954 * Choose the appropriate DDC bus for control bus switch command for this
1955 * SDVO output based on the controlled output.
1956 *
1957 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1958 * outputs, then LVDS outputs.
1959 */
1960static void
b1083333 1961intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1962 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1963{
b1083333 1964 struct sdvo_device_mapping *mapping;
e2f0ba97 1965
b1083333
AJ		 1966 if (IS_SDVOB(reg))
1967 mapping = &(dev_priv->sdvo_mappings[0]);
1968 else
1969 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1970
b66d8424
CW		 1971 if (mapping->initialized)
1972 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1973 else
1974 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1975}
1976
1977static bool
ea5b213a 1978intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1979{
32aad86f
CW		 1980 return intel_sdvo_set_target_output(intel_sdvo,
1981 device == 0 ? SDVO_OUTPUT_TMDS0 : SDVO_OUTPUT_TMDS1) &&
1982 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1983 &intel_sdvo->is_hdmi, 1);
e2f0ba97
JB		 1984}
1985
ea5b213a
CW		 1986static struct intel_sdvo *
1987intel_sdvo_chan_to_intel_sdvo(struct intel_i2c_chan *chan)
619ac3b7
ML		 1988{
1989 struct drm_device *dev = chan->drm_dev;
d2a82a6f 1990 struct drm_encoder *encoder;
619ac3b7 1991
d2a82a6f 1992 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
ea5b213a
CW		 1993 struct intel_sdvo *intel_sdvo = enc_to_intel_sdvo(encoder);
1994 if (intel_sdvo->base.ddc_bus == &chan->adapter)
1995 return intel_sdvo;
619ac3b7 1996 }
ea5b213a 1997
32aad86f 1998 return NULL;
619ac3b7
ML		 1999}
2000
2001static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
2002 struct i2c_msg msgs[], int num)
2003{
ea5b213a 2004 struct intel_sdvo *intel_sdvo;
619ac3b7 2005 struct i2c_algo_bit_data *algo_data;
f9c10a9b 2006 const struct i2c_algorithm *algo;
619ac3b7
ML		 2007
2008 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
ea5b213a
CW		 2009 intel_sdvo =
2010 intel_sdvo_chan_to_intel_sdvo((struct intel_i2c_chan *)
2011 (algo_data->data));
2012 if (intel_sdvo == NULL)
619ac3b7
ML		 2013 return -EINVAL;
2014
ea5b213a 2015 algo = intel_sdvo->base.i2c_bus->algo;
619ac3b7 2016
ea5b213a 2017 intel_sdvo_set_control_bus_switch(intel_sdvo, intel_sdvo->ddc_bus);
619ac3b7
ML		 2018 return algo->master_xfer(i2c_adap, msgs, num);
2019}
2020
2021static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
2022 .master_xfer = intel_sdvo_master_xfer,
2023};
2024
714605e4 2025static u8
c751ce4f 2026intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
714605e4 2027{
2028 struct drm_i915_private *dev_priv = dev->dev_private;
2029 struct sdvo_device_mapping *my_mapping, *other_mapping;
2030
461ed3ca 2031 if (IS_SDVOB(sdvo_reg)) {
714605e4 2032 my_mapping = &dev_priv->sdvo_mappings[0];
2033 other_mapping = &dev_priv->sdvo_mappings[1];
2034 } else {
2035 my_mapping = &dev_priv->sdvo_mappings[1];
2036 other_mapping = &dev_priv->sdvo_mappings[0];
2037 }
2038
2039 /* If the BIOS described our SDVO device, take advantage of it. */
2040 if (my_mapping->slave_addr)
2041 return my_mapping->slave_addr;
2042
2043 /* If the BIOS only described a different SDVO device, use the
2044 * address that it isn't using.
2045 */
2046 if (other_mapping->slave_addr) {
2047 if (other_mapping->slave_addr == 0x70)
2048 return 0x72;
2049 else
2050 return 0x70;
2051 }
2052
2053 /* No SDVO device info is found for another DVO port,
2054 * so use mapping assumption we had before BIOS parsing.
2055 */
461ed3ca 2056 if (IS_SDVOB(sdvo_reg))
714605e4 2057 return 0x70;
2058 else
2059 return 0x72;
2060}
2061
14571b4c 2062static void
df0e9248
CW		 2063intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2064 struct intel_sdvo *encoder)
14571b4c 2065{
df0e9248
CW		 2066 drm_connector_init(encoder->base.base.dev,
2067 &connector->base.base,
2068 &intel_sdvo_connector_funcs,
2069 connector->base.base.connector_type);
6070a4a9 2070
df0e9248
CW		 2071 drm_connector_helper_add(&connector->base.base,
2072 &intel_sdvo_connector_helper_funcs);
14571b4c 2073
df0e9248
CW		 2074 connector->base.base.interlace_allowed = 0;
2075 connector->base.base.doublescan_allowed = 0;
2076 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
14571b4c 2077
df0e9248
CW		 2078 intel_connector_attach_encoder(&connector->base, &encoder->base);
2079 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2080}
6070a4a9 2081
fb7a46f3 2082static bool
ea5b213a 2083intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2084{
4ef69c7a 2085 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c
ZW		 2086 struct drm_connector *connector;
2087 struct intel_connector *intel_connector;
615fb93f 2088 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2089
615fb93f
CW		 2090 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2091 if (!intel_sdvo_connector)
14571b4c
ZW		 2092 return false;
2093
14571b4c 2094 if (device == 0) {
ea5b213a 2095 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2096 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2097 } else if (device == 1) {
ea5b213a 2098 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2099 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2100 }
2101
615fb93f 2102 intel_connector = &intel_sdvo_connector->base;
14571b4c 2103 connector = &intel_connector->base;
eb1f8e4f 2104 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2105 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2106 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2107
ea5b213a
CW		 2108 if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode)
2109 && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device)
2110 && intel_sdvo->is_hdmi) {
14571b4c 2111 /* enable hdmi encoding mode if supported */
ea5b213a
CW		 2112 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
2113 intel_sdvo_set_colorimetry(intel_sdvo,
14571b4c
ZW		 2114 SDVO_COLORIMETRY_RGB256);
2115 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2116 }
ea5b213a
CW		 2117 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2118 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2119
df0e9248 2120 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c
ZW		 2121
2122 return true;
2123}
2124
2125static bool
ea5b213a 2126intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2127{
4ef69c7a
CW		 2128 struct drm_encoder *encoder = &intel_sdvo->base.base;
2129 struct drm_connector *connector;
2130 struct intel_connector *intel_connector;
2131 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2132
615fb93f
CW		 2133 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2134 if (!intel_sdvo_connector)
2135 return false;
14571b4c 2136
615fb93f 2137 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2138 connector = &intel_connector->base;
2139 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2140 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2141
4ef69c7a
CW		 2142 intel_sdvo->controlled_output |= type;
2143 intel_sdvo_connector->output_flag = type;
14571b4c 2144
4ef69c7a
CW		 2145 intel_sdvo->is_tv = true;
2146 intel_sdvo->base.needs_tv_clock = true;
2147 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2148
df0e9248 2149 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2150
4ef69c7a 2151 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2152 goto err;
14571b4c 2153
4ef69c7a 2154 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2155 goto err;
14571b4c 2156
4ef69c7a 2157 return true;
32aad86f
CW		 2158
2159err:
fcc8d672 2160 intel_sdvo_destroy_enhance_property(connector);
32aad86f
CW		 2161 kfree(intel_sdvo_connector);
2162 return false;
14571b4c
ZW		 2163}
2164
2165static bool
ea5b213a 2166intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2167{
4ef69c7a
CW		 2168 struct drm_encoder *encoder = &intel_sdvo->base.base;
2169 struct drm_connector *connector;
2170 struct intel_connector *intel_connector;
2171 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2172
615fb93f
CW		 2173 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2174 if (!intel_sdvo_connector)
2175 return false;
14571b4c 2176
615fb93f 2177 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2178 connector = &intel_connector->base;
eb1f8e4f 2179 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2180 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2181 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2182
2183 if (device == 0) {
2184 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2185 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2186 } else if (device == 1) {
2187 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2188 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2189 }
2190
2191 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
ea5b213a 2192 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2193
df0e9248
CW		 2194 intel_sdvo_connector_init(intel_sdvo_connector,
2195 intel_sdvo);
4ef69c7a 2196 return true;
14571b4c
ZW		 2197}
2198
2199static bool
ea5b213a 2200intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2201{
4ef69c7a
CW		 2202 struct drm_encoder *encoder = &intel_sdvo->base.base;
2203 struct drm_connector *connector;
2204 struct intel_connector *intel_connector;
2205 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2206
615fb93f
CW		 2207 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2208 if (!intel_sdvo_connector)
2209 return false;
14571b4c 2210
615fb93f
CW		 2211 intel_connector = &intel_sdvo_connector->base;
2212 connector = &intel_connector->base;
4ef69c7a
CW		 2213 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2214 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2215
2216 if (device == 0) {
2217 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2218 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2219 } else if (device == 1) {
2220 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2221 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2222 }
2223
2224 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
ea5b213a 2225 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2226
df0e9248 2227 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2228 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2229 goto err;
2230
2231 return true;
2232
2233err:
fcc8d672 2234 intel_sdvo_destroy_enhance_property(connector);
32aad86f
CW		 2235 kfree(intel_sdvo_connector);
2236 return false;
14571b4c
ZW		 2237}
2238
2239static bool
ea5b213a 2240intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2241{
ea5b213a
CW		 2242 intel_sdvo->is_tv = false;
2243 intel_sdvo->base.needs_tv_clock = false;
2244 intel_sdvo->is_lvds = false;
fb7a46f3 2245
14571b4c 2246 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2247
14571b4c 2248 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2249 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2250 return false;
2251
2252 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2253 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2254 return false;
2255
2256 /* TV has no XXX1 function block */
a1f4b7ff 2257 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2258 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2259 return false;
2260
2261 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2262 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2263 return false;
fb7a46f3 2264
14571b4c 2265 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2266 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2267 return false;
2268
2269 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2270 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2271 return false;
2272
2273 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2274 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2275 return false;
2276
2277 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2278 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2279 return false;
fb7a46f3 2280
14571b4c 2281 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2282 unsigned char bytes[2];
2283
ea5b213a
CW		 2284 intel_sdvo->controlled_output = 0;
2285 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2286 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2287 SDVO_NAME(intel_sdvo),
51c8b407 2288 bytes[0], bytes[1]);
14571b4c 2289 return false;
fb7a46f3 2290 }
ea5b213a 2291 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
fb7a46f3 2292
14571b4c 2293 return true;
fb7a46f3 2294}
2295
32aad86f
CW		 2296static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2297 struct intel_sdvo_connector *intel_sdvo_connector,
2298 int type)
ce6feabd 2299{
4ef69c7a 2300 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2301 struct intel_sdvo_tv_format format;
2302 uint32_t format_map, i;
ce6feabd 2303
32aad86f
CW		 2304 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2305 return false;
ce6feabd 2306
32aad86f
CW		 2307 if (!intel_sdvo_get_value(intel_sdvo,
2308 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2309 &format, sizeof(format)))
2310 return false;
ce6feabd 2311
32aad86f 2312 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2313
2314 if (format_map == 0)
32aad86f 2315 return false;
ce6feabd 2316
615fb93f 2317 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2318 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2319 if (format_map & (1 << i))
2320 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2321
2322
c5521706 2323 intel_sdvo_connector->tv_format =
32aad86f
CW		 2324 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2325 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2326 if (!intel_sdvo_connector->tv_format)
fcc8d672 2327 return false;
ce6feabd 2328
615fb93f 2329 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2330 drm_property_add_enum(
c5521706 2331 intel_sdvo_connector->tv_format, i,
40039750 2332 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2333
40039750 2334 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2335 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2336 intel_sdvo_connector->tv_format, 0);
32aad86f 2337 return true;
ce6feabd
ZY		 2338
2339}
2340
c5521706
CW		 2341#define ENHANCEMENT(name, NAME) do { \
2342 if (enhancements.name) { \
2343 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2344 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2345 return false; \
2346 intel_sdvo_connector->max_##name = data_value[0]; \
2347 intel_sdvo_connector->cur_##name = response; \
2348 intel_sdvo_connector->name = \
2349 drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
2350 if (!intel_sdvo_connector->name) return false; \
2351 intel_sdvo_connector->name->values[0] = 0; \
2352 intel_sdvo_connector->name->values[1] = data_value[0]; \
2353 drm_connector_attach_property(connector, \
2354 intel_sdvo_connector->name, \
2355 intel_sdvo_connector->cur_##name); \
2356 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2357 data_value[0], data_value[1], response); \
2358 } \
2359} while(0)
2360
2361static bool
2362intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2363 struct intel_sdvo_connector *intel_sdvo_connector,
2364 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2365{
4ef69c7a 2366 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2367 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2368 uint16_t response, data_value[2];
2369
c5521706
CW		 2370 /* when horizontal overscan is supported, Add the left/right property */
2371 if (enhancements.overscan_h) {
2372 if (!intel_sdvo_get_value(intel_sdvo,
2373 SDVO_CMD_GET_MAX_OVERSCAN_H,
2374 &data_value, 4))
2375 return false;
32aad86f 2376
c5521706
CW		 2377 if (!intel_sdvo_get_value(intel_sdvo,
2378 SDVO_CMD_GET_OVERSCAN_H,
2379 &response, 2))
2380 return false;
fcc8d672 2381
c5521706
CW		 2382 intel_sdvo_connector->max_hscan = data_value[0];
2383 intel_sdvo_connector->left_margin = data_value[0] - response;
2384 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2385 intel_sdvo_connector->left =
2386 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2387 "left_margin", 2);
2388 if (!intel_sdvo_connector->left)
2389 return false;
fcc8d672 2390
c5521706
CW		 2391 intel_sdvo_connector->left->values[0] = 0;
2392 intel_sdvo_connector->left->values[1] = data_value[0];
2393 drm_connector_attach_property(connector,
2394 intel_sdvo_connector->left,
2395 intel_sdvo_connector->left_margin);
fcc8d672 2396
c5521706
CW		 2397 intel_sdvo_connector->right =
2398 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2399 "right_margin", 2);
2400 if (!intel_sdvo_connector->right)
2401 return false;
32aad86f 2402
c5521706
CW		 2403 intel_sdvo_connector->right->values[0] = 0;
2404 intel_sdvo_connector->right->values[1] = data_value[0];
2405 drm_connector_attach_property(connector,
2406 intel_sdvo_connector->right,
2407 intel_sdvo_connector->right_margin);
2408 DRM_DEBUG_KMS("h_overscan: max %d, "
2409 "default %d, current %d\n",
2410 data_value[0], data_value[1], response);
2411 }
32aad86f 2412
c5521706
CW		 2413 if (enhancements.overscan_v) {
2414 if (!intel_sdvo_get_value(intel_sdvo,
2415 SDVO_CMD_GET_MAX_OVERSCAN_V,
2416 &data_value, 4))
2417 return false;
fcc8d672 2418
c5521706
CW		 2419 if (!intel_sdvo_get_value(intel_sdvo,
2420 SDVO_CMD_GET_OVERSCAN_V,
2421 &response, 2))
2422 return false;
32aad86f 2423
c5521706
CW		 2424 intel_sdvo_connector->max_vscan = data_value[0];
2425 intel_sdvo_connector->top_margin = data_value[0] - response;
2426 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2427 intel_sdvo_connector->top =
2428 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2429 "top_margin", 2);
2430 if (!intel_sdvo_connector->top)
2431 return false;
32aad86f 2432
c5521706
CW		 2433 intel_sdvo_connector->top->values[0] = 0;
2434 intel_sdvo_connector->top->values[1] = data_value[0];
2435 drm_connector_attach_property(connector,
2436 intel_sdvo_connector->top,
2437 intel_sdvo_connector->top_margin);
fcc8d672 2438
c5521706
CW		 2439 intel_sdvo_connector->bottom =
2440 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2441 "bottom_margin", 2);
2442 if (!intel_sdvo_connector->bottom)
2443 return false;
32aad86f 2444
c5521706
CW		 2445 intel_sdvo_connector->bottom->values[0] = 0;
2446 intel_sdvo_connector->bottom->values[1] = data_value[0];
2447 drm_connector_attach_property(connector,
2448 intel_sdvo_connector->bottom,
2449 intel_sdvo_connector->bottom_margin);
2450 DRM_DEBUG_KMS("v_overscan: max %d, "
2451 "default %d, current %d\n",
2452 data_value[0], data_value[1], response);
2453 }
32aad86f 2454
c5521706
CW		 2455 ENHANCEMENT(hpos, HPOS);
2456 ENHANCEMENT(vpos, VPOS);
2457 ENHANCEMENT(saturation, SATURATION);
2458 ENHANCEMENT(contrast, CONTRAST);
2459 ENHANCEMENT(hue, HUE);
2460 ENHANCEMENT(sharpness, SHARPNESS);
2461 ENHANCEMENT(brightness, BRIGHTNESS);
2462 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2463 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2464 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2465 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2466 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2467
e044218a
CW		 2468 if (enhancements.dot_crawl) {
2469 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2470 return false;
2471
2472 intel_sdvo_connector->max_dot_crawl = 1;
2473 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2474 intel_sdvo_connector->dot_crawl =
2475 drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2);
2476 if (!intel_sdvo_connector->dot_crawl)
2477 return false;
2478
2479 intel_sdvo_connector->dot_crawl->values[0] = 0;
2480 intel_sdvo_connector->dot_crawl->values[1] = 1;
2481 drm_connector_attach_property(connector,
2482 intel_sdvo_connector->dot_crawl,
2483 intel_sdvo_connector->cur_dot_crawl);
2484 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2485 }
2486
c5521706
CW		 2487 return true;
2488}
32aad86f 2489
c5521706
CW		 2490static bool
2491intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2492 struct intel_sdvo_connector *intel_sdvo_connector,
2493 struct intel_sdvo_enhancements_reply enhancements)
2494{
4ef69c7a 2495 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2496 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2497 uint16_t response, data_value[2];
32aad86f 2498
c5521706 2499 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2500
c5521706
CW		 2501 return true;
2502}
2503#undef ENHANCEMENT
32aad86f 2504
c5521706
CW		 2505static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2506 struct intel_sdvo_connector *intel_sdvo_connector)
2507{
2508 union {
2509 struct intel_sdvo_enhancements_reply reply;
2510 uint16_t response;
2511 } enhancements;
32aad86f 2512
c5521706
CW		 2513 if (!intel_sdvo_get_value(intel_sdvo,
2514 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2515 &enhancements, sizeof(enhancements)))
2516 return false;
fcc8d672 2517
c5521706
CW		 2518 if (enhancements.response == 0) {
2519 DRM_DEBUG_KMS("No enhancement is supported\n");
2520 return true;
b9219c5e 2521 }
32aad86f 2522
c5521706
CW		 2523 if (IS_TV(intel_sdvo_connector))
2524 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2525 else if(IS_LVDS(intel_sdvo_connector))
2526 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2527 else
2528 return true;
fcc8d672 2529
b9219c5e
ZY		 2530}
2531
c751ce4f 2532bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
79e53945 2533{
b01f2c3a 2534 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2535 struct intel_encoder *intel_encoder;
ea5b213a 2536 struct intel_sdvo *intel_sdvo;
79e53945
JB		 2537 u8 ch[0x40];
2538 int i;
461ed3ca 2539 u32 i2c_reg, ddc_reg, analog_ddc_reg;
79e53945 2540
ea5b213a
CW		 2541 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2542 if (!intel_sdvo)
7d57382e 2543 return false;
79e53945 2544
ea5b213a 2545 intel_sdvo->sdvo_reg = sdvo_reg;
308cd3a2 2546
ea5b213a 2547 intel_encoder = &intel_sdvo->base;
21d40d37 2548 intel_encoder->type = INTEL_OUTPUT_SDVO;
79e53945 2549
461ed3ca
ZY		 2550 if (HAS_PCH_SPLIT(dev)) {
2551 i2c_reg = PCH_GPIOE;
2552 ddc_reg = PCH_GPIOE;
2553 analog_ddc_reg = PCH_GPIOA;
2554 } else {
2555 i2c_reg = GPIOE;
2556 ddc_reg = GPIOE;
2557 analog_ddc_reg = GPIOA;
2558 }
2559
79e53945 2560 /* setup the DDC bus. */
461ed3ca
ZY		 2561 if (IS_SDVOB(sdvo_reg))
2562 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOB");
308cd3a2 2563 else
461ed3ca 2564 intel_encoder->i2c_bus = intel_i2c_create(dev, i2c_reg, "SDVOCTRL_E for SDVOC");
308cd3a2 2565
21d40d37 2566 if (!intel_encoder->i2c_bus)
ad5b2a6d 2567 goto err_inteloutput;
79e53945 2568
ea5b213a 2569 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
79e53945 2570
308cd3a2 2571 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
21d40d37 2572 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
79e53945 2573
79e53945
JB		 2574 /* Read the regs to test if we can talk to the device */
2575 for (i = 0; i < 0x40; i++) {
ea5b213a 2576 if (!intel_sdvo_read_byte(intel_sdvo, i, &ch[i])) {
8a4c47f3 2577 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
461ed3ca 2578 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
79e53945
JB		 2579 goto err_i2c;
2580 }
2581 }
2582
619ac3b7 2583 /* setup the DDC bus. */
461ed3ca
ZY		 2584 if (IS_SDVOB(sdvo_reg)) {
2585 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOB DDC BUS");
ea5b213a 2586 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
57cdaf90 2587 "SDVOB/VGA DDC BUS");
b01f2c3a 2588 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
57cdaf90 2589 } else {
461ed3ca 2590 intel_encoder->ddc_bus = intel_i2c_create(dev, ddc_reg, "SDVOC DDC BUS");
ea5b213a 2591 intel_sdvo->analog_ddc_bus = intel_i2c_create(dev, analog_ddc_reg,
57cdaf90 2592 "SDVOC/VGA DDC BUS");
b01f2c3a 2593 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
57cdaf90 2594 }
32aad86f 2595 if (intel_encoder->ddc_bus == NULL || intel_sdvo->analog_ddc_bus == NULL)
619ac3b7
ML		 2596 goto err_i2c;
2597
308cd3a2 2598 /* Wrap with our custom algo which switches to DDC mode */
21d40d37 2599 intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
619ac3b7 2600
14571b4c 2601 /* encoder type will be decided later */
4ef69c7a
CW		 2602 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
2603 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2604
af901ca1 2605 /* In default case sdvo lvds is false */
32aad86f
CW		 2606 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
2607 goto err_enc;
79e53945 2608
ea5b213a
CW		 2609 if (intel_sdvo_output_setup(intel_sdvo,
2610 intel_sdvo->caps.output_flags) != true) {
51c8b407 2611 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
461ed3ca 2612 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
32aad86f 2613 goto err_enc;
79e53945
JB		 2614 }
2615
ea5b213a 2616 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2617
79e53945 2618 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 2619 if (!intel_sdvo_set_target_input(intel_sdvo))
2620 goto err_enc;
79e53945 2621
32aad86f
CW		 2622 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2623 &intel_sdvo->pixel_clock_min,
2624 &intel_sdvo->pixel_clock_max))
2625 goto err_enc;
79e53945 2626
8a4c47f3 2627 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2628 "clock range %dMHz - %dMHz, "
2629 "input 1: %c, input 2: %c, "
2630 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2631 SDVO_NAME(intel_sdvo),
2632 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2633 intel_sdvo->caps.device_rev_id,
2634 intel_sdvo->pixel_clock_min / 1000,
2635 intel_sdvo->pixel_clock_max / 1000,
2636 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2637 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2638 /* check currently supported outputs */
ea5b213a 2639 intel_sdvo->caps.output_flags &
79e53945 2640 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2641 intel_sdvo->caps.output_flags &
79e53945 2642 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2643 return true;
79e53945 2644
32aad86f 2645err_enc:
4ef69c7a 2646 drm_encoder_cleanup(&intel_encoder->base);
79e53945 2647err_i2c:
ea5b213a
CW		 2648 if (intel_sdvo->analog_ddc_bus != NULL)
2649 intel_i2c_destroy(intel_sdvo->analog_ddc_bus);
21d40d37
EA		 2650 if (intel_encoder->ddc_bus != NULL)
2651 intel_i2c_destroy(intel_encoder->ddc_bus);
2652 if (intel_encoder->i2c_bus != NULL)
2653 intel_i2c_destroy(intel_encoder->i2c_bus);
ad5b2a6d 2654err_inteloutput:
ea5b213a 2655 kfree(intel_sdvo);
79e53945 2656
7d57382e 2657 return false;
79e53945 2658}
ubuntu-zesty-kernel mirror