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drm/i915: rip out unnecessary calls to drm_mode_set_crtcinfo
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
79e53945
JB		 32#include "drmP.h"
33#include "drm.h"
34#include "drm_crtc.h"
2b8d33f7 35#include "drm_edid.h"
ea5b213a 36#include "intel_drv.h"
79e53945
JB		 37#include "i915_drm.h"
38#include "i915_drv.h"
39#include "intel_sdvo_regs.h"
40
14571b4c
ZW		 41#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 44#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 45
46#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 47 SDVO_TV_MASK)
14571b4c
ZW		 48
49#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 50#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 51#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 52#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 53#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 54
79e53945 55
2e88e40b 56static const char *tv_format_names[] = {
ce6feabd
ZY		 57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64};
65
66#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
67
ea5b213a
CW		 68struct intel_sdvo {
69 struct intel_encoder base;
70
f899fc64 71 struct i2c_adapter *i2c;
f9c10a9b 72 u8 slave_addr;
e2f0ba97 73
e957d772
CW		 74 struct i2c_adapter ddc;
75
e2f0ba97 76 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 77 uint32_t sdvo_reg;
79e53945 78
e2f0ba97
JB		 79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
79e53945 81
e2f0ba97
JB		 82 /*
83 * Capabilities of the SDVO device returned by
84 * i830_sdvo_get_capabilities()
85 */
79e53945 86 struct intel_sdvo_caps caps;
e2f0ba97
JB		 87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 89 int pixel_clock_min, pixel_clock_max;
90
fb7a46f3 91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
cc68c81a
SF		 97 /*
98 * Hotplug activation bits for this device
99 */
100 uint8_t hotplug_active[2];
101
e953fd7b
CW		 102 /**
103 * This is used to select the color range of RBG outputs in HDMI mode.
104 * It is only valid when using TMDS encoding and 8 bit per color mode.
105 */
106 uint32_t color_range;
107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
eef4eacb
DV		 117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
ce6feabd 120 /* This is for current tv format name */
40039750 121 int tv_format_index;
ce6feabd 122
e2f0ba97
JB		 123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
da79de97
CW		 127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
12682a97 129
7086c87f 130 /**
6c9547ff
CW		 131 * This is set if we detect output of sdvo device as LVDS and
132 * have a valid fixed mode to use with the panel.
7086c87f
ML		 133 */
134 bool is_lvds;
e2f0ba97 135
12682a97 136 /**
137 * This is sdvo fixed pannel mode pointer
138 */
139 struct drm_display_mode *sdvo_lvds_fixed_mode;
140
c751ce4f 141 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 142 uint8_t ddc_bus;
143
6c9547ff
CW		 144 /* Input timings for adjusted_mode */
145 struct intel_sdvo_dtd input_dtd;
14571b4c
ZW		 146};
147
148struct intel_sdvo_connector {
615fb93f
CW		 149 struct intel_connector base;
150
14571b4c
ZW		 151 /* Mark the type of connector */
152 uint16_t output_flag;
153
c3e5f67b 154 enum hdmi_force_audio force_audio;
7f36e7ed 155
14571b4c 156 /* This contains all current supported TV format */
40039750 157 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 158 int format_supported_num;
c5521706 159 struct drm_property *tv_format;
14571b4c 160
b9219c5e 161 /* add the property for the SDVO-TV */
c5521706
CW		 162 struct drm_property *left;
163 struct drm_property *right;
164 struct drm_property *top;
165 struct drm_property *bottom;
166 struct drm_property *hpos;
167 struct drm_property *vpos;
168 struct drm_property *contrast;
169 struct drm_property *saturation;
170 struct drm_property *hue;
171 struct drm_property *sharpness;
172 struct drm_property *flicker_filter;
173 struct drm_property *flicker_filter_adaptive;
174 struct drm_property *flicker_filter_2d;
175 struct drm_property *tv_chroma_filter;
176 struct drm_property *tv_luma_filter;
e044218a 177 struct drm_property *dot_crawl;
b9219c5e
ZY		 178
179 /* add the property for the SDVO-TV/LVDS */
c5521706 180 struct drm_property *brightness;
b9219c5e
ZY		 181
182 /* Add variable to record current setting for the above property */
183 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 184
b9219c5e
ZY		 185 /* this is to get the range of margin.*/
186 u32 max_hscan, max_vscan;
187 u32 max_hpos, cur_hpos;
188 u32 max_vpos, cur_vpos;
189 u32 cur_brightness, max_brightness;
190 u32 cur_contrast, max_contrast;
191 u32 cur_saturation, max_saturation;
192 u32 cur_hue, max_hue;
c5521706
CW		 193 u32 cur_sharpness, max_sharpness;
194 u32 cur_flicker_filter, max_flicker_filter;
195 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
196 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
197 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
198 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 199 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 200};
201
890f3359 202static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 203{
4ef69c7a 204 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 205}
206
df0e9248
CW		 207static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
208{
209 return container_of(intel_attached_encoder(connector),
210 struct intel_sdvo, base);
211}
212
615fb93f
CW		 213static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
214{
215 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
216}
217
fb7a46f3 218static bool
ea5b213a 219intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 220static bool
221intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
222 struct intel_sdvo_connector *intel_sdvo_connector,
223 int type);
224static bool
225intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
226 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 227
79e53945
JB		 228/**
229 * Writes the SDVOB or SDVOC with the given value, but always writes both
230 * SDVOB and SDVOC to work around apparent hardware issues (according to
231 * comments in the BIOS).
232 */
ea5b213a 233static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 234{
4ef69c7a 235 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 236 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 237 u32 bval = val, cval = val;
238 int i;
239
ea5b213a
CW		 240 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
241 I915_WRITE(intel_sdvo->sdvo_reg, val);
242 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 243 return;
244 }
245
ea5b213a 246 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 247 cval = I915_READ(SDVOC);
248 } else {
249 bval = I915_READ(SDVOB);
250 }
251 /*
252 * Write the registers twice for luck. Sometimes,
253 * writing them only once doesn't appear to 'stick'.
254 * The BIOS does this too. Yay, magic
255 */
256 for (i = 0; i < 2; i++)
257 {
258 I915_WRITE(SDVOB, bval);
259 I915_READ(SDVOB);
260 I915_WRITE(SDVOC, cval);
261 I915_READ(SDVOC);
262 }
263}
264
32aad86f 265static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 266{
79e53945
JB		 267 struct i2c_msg msgs[] = {
268 {
e957d772 269 .addr = intel_sdvo->slave_addr,
79e53945
JB		 270 .flags = 0,
271 .len = 1,
e957d772 272 .buf = &addr,
79e53945
JB		 273 },
274 {
e957d772 275 .addr = intel_sdvo->slave_addr,
79e53945
JB		 276 .flags = I2C_M_RD,
277 .len = 1,
e957d772 278 .buf = ch,
79e53945
JB		 279 }
280 };
32aad86f 281 int ret;
79e53945 282
f899fc64 283 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 284 return true;
79e53945 285
8a4c47f3 286 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 287 return false;
288}
289
79e53945
JB		 290#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
291/** Mapping of command numbers to names, for debug output */
005568be 292static const struct _sdvo_cmd_name {
e2f0ba97 293 u8 cmd;
2e88e40b 294 const char *name;
79e53945 295} sdvo_cmd_names[] = {
0206e353
AJ		 296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
339
340 /* Add the op code for SDVO enhancements */
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
385
386 /* HDMI op code */
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 407};
408
eef4eacb 409#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 410
ea5b213a 411static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 412 const void *args, int args_len)
79e53945 413{
79e53945
JB		 414 int i;
415
8a4c47f3 416 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 417 SDVO_NAME(intel_sdvo), cmd);
79e53945 418 for (i = 0; i < args_len; i++)
342dc382 419 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 420 for (; i < 8; i++)
342dc382 421 DRM_LOG_KMS(" ");
04ad327f 422 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 423 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 424 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 425 break;
426 }
427 }
04ad327f 428 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 429 DRM_LOG_KMS("(%02X)", cmd);
430 DRM_LOG_KMS("\n");
79e53945 431}
79e53945 432
e957d772
CW		 433static const char *cmd_status_names[] = {
434 "Power on",
435 "Success",
436 "Not supported",
437 "Invalid arg",
438 "Pending",
439 "Target not specified",
440 "Scaling not supported"
441};
442
32aad86f
CW		 443static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
444 const void *args, int args_len)
79e53945 445{
3bf3f452
BW		 446 u8 *buf, status;
447 struct i2c_msg *msgs;
448 int i, ret = true;
449
450 buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
451 if (!buf)
452 return false;
453
454 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
455 if (!msgs)
456 return false;
79e53945 457
ea5b213a 458 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 459
460 for (i = 0; i < args_len; i++) {
e957d772
CW		 461 msgs[i].addr = intel_sdvo->slave_addr;
462 msgs[i].flags = 0;
463 msgs[i].len = 2;
464 msgs[i].buf = buf + 2 *i;
465 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
466 buf[2*i + 1] = ((u8*)args)[i];
467 }
468 msgs[i].addr = intel_sdvo->slave_addr;
469 msgs[i].flags = 0;
470 msgs[i].len = 2;
471 msgs[i].buf = buf + 2*i;
472 buf[2*i + 0] = SDVO_I2C_OPCODE;
473 buf[2*i + 1] = cmd;
474
475 /* the following two are to read the response */
476 status = SDVO_I2C_CMD_STATUS;
477 msgs[i+1].addr = intel_sdvo->slave_addr;
478 msgs[i+1].flags = 0;
479 msgs[i+1].len = 1;
480 msgs[i+1].buf = &status;
481
482 msgs[i+2].addr = intel_sdvo->slave_addr;
483 msgs[i+2].flags = I2C_M_RD;
484 msgs[i+2].len = 1;
485 msgs[i+2].buf = &status;
486
487 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
488 if (ret < 0) {
489 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 490 ret = false;
491 goto out;
e957d772
CW		 492 }
493 if (ret != i+3) {
494 /* failure in I2C transfer */
495 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 496 ret = false;
e957d772
CW		 497 }
498
3bf3f452
BW		 499out:
500 kfree(msgs);
501 kfree(buf);
502 return ret;
79e53945
JB		 503}
504
b5c616a7
CW		 505static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
506 void *response, int response_len)
79e53945 507{
b5c616a7
CW		 508 u8 retry = 5;
509 u8 status;
33b52961 510 int i;
79e53945 511
d121a5d2
CW		 512 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
513
b5c616a7
CW		 514 /*
515 * The documentation states that all commands will be
516 * processed within 15µs, and that we need only poll
517 * the status byte a maximum of 3 times in order for the
518 * command to be complete.
519 *
520 * Check 5 times in case the hardware failed to read the docs.
521 */
d121a5d2
CW		 522 if (!intel_sdvo_read_byte(intel_sdvo,
523 SDVO_I2C_CMD_STATUS,
524 &status))
525 goto log_fail;
526
527 while (status == SDVO_CMD_STATUS_PENDING && retry--) {
528 udelay(15);
b5c616a7
CW		 529 if (!intel_sdvo_read_byte(intel_sdvo,
530 SDVO_I2C_CMD_STATUS,
531 &status))
d121a5d2
CW		 532 goto log_fail;
533 }
b5c616a7 534
79e53945 535 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 536 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 537 else
342dc382 538 DRM_LOG_KMS("(??? %d)", status);
79e53945 539
b5c616a7
CW		 540 if (status != SDVO_CMD_STATUS_SUCCESS)
541 goto log_fail;
79e53945 542
b5c616a7
CW		 543 /* Read the command response */
544 for (i = 0; i < response_len; i++) {
545 if (!intel_sdvo_read_byte(intel_sdvo,
546 SDVO_I2C_RETURN_0 + i,
547 &((u8 *)response)[i]))
548 goto log_fail;
e957d772 549 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 550 }
b5c616a7 551 DRM_LOG_KMS("\n");
b5c616a7 552 return true;
79e53945 553
b5c616a7 554log_fail:
d121a5d2 555 DRM_LOG_KMS("... failed\n");
b5c616a7 556 return false;
79e53945
JB		 557}
558
b358d0a6 559static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 560{
561 if (mode->clock >= 100000)
562 return 1;
563 else if (mode->clock >= 50000)
564 return 2;
565 else
566 return 4;
567}
568
e957d772
CW		 569static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
570 u8 ddc_bus)
79e53945 571{
d121a5d2 572 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 573 return intel_sdvo_write_cmd(intel_sdvo,
574 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
575 &ddc_bus, 1);
79e53945
JB		 576}
577
32aad86f 578static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 579{
d121a5d2
CW		 580 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
581 return false;
582
583 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 584}
79e53945 585
32aad86f
CW		 586static bool
587intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
588{
589 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
590 return false;
79e53945 591
32aad86f
CW		 592 return intel_sdvo_read_response(intel_sdvo, value, len);
593}
79e53945 594
32aad86f
CW		 595static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
596{
597 struct intel_sdvo_set_target_input_args targets = {0};
598 return intel_sdvo_set_value(intel_sdvo,
599 SDVO_CMD_SET_TARGET_INPUT,
600 &targets, sizeof(targets));
79e53945
JB		 601}
602
603/**
604 * Return whether each input is trained.
605 *
606 * This function is making an assumption about the layout of the response,
607 * which should be checked against the docs.
608 */
ea5b213a 609static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 610{
611 struct intel_sdvo_get_trained_inputs_response response;
79e53945 612
1a3665c8 613 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 614 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
615 &response, sizeof(response)))
79e53945
JB		 616 return false;
617
618 *input_1 = response.input0_trained;
619 *input_2 = response.input1_trained;
620 return true;
621}
622
ea5b213a 623static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 624 u16 outputs)
625{
32aad86f
CW		 626 return intel_sdvo_set_value(intel_sdvo,
627 SDVO_CMD_SET_ACTIVE_OUTPUTS,
628 &outputs, sizeof(outputs));
79e53945
JB		 629}
630
ea5b213a 631static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 632 int mode)
633{
32aad86f 634 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 635
636 switch (mode) {
637 case DRM_MODE_DPMS_ON:
638 state = SDVO_ENCODER_STATE_ON;
639 break;
640 case DRM_MODE_DPMS_STANDBY:
641 state = SDVO_ENCODER_STATE_STANDBY;
642 break;
643 case DRM_MODE_DPMS_SUSPEND:
644 state = SDVO_ENCODER_STATE_SUSPEND;
645 break;
646 case DRM_MODE_DPMS_OFF:
647 state = SDVO_ENCODER_STATE_OFF;
648 break;
649 }
650
32aad86f
CW		 651 return intel_sdvo_set_value(intel_sdvo,
652 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 653}
654
ea5b213a 655static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 656 int *clock_min,
657 int *clock_max)
658{
659 struct intel_sdvo_pixel_clock_range clocks;
79e53945 660
1a3665c8 661 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 662 if (!intel_sdvo_get_value(intel_sdvo,
663 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
664 &clocks, sizeof(clocks)))
79e53945
JB		 665 return false;
666
667 /* Convert the values from units of 10 kHz to kHz. */
668 *clock_min = clocks.min * 10;
669 *clock_max = clocks.max * 10;
79e53945
JB		 670 return true;
671}
672
ea5b213a 673static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 674 u16 outputs)
675{
32aad86f
CW		 676 return intel_sdvo_set_value(intel_sdvo,
677 SDVO_CMD_SET_TARGET_OUTPUT,
678 &outputs, sizeof(outputs));
79e53945
JB		 679}
680
ea5b213a 681static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 682 struct intel_sdvo_dtd *dtd)
683{
32aad86f
CW		 684 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
685 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 686}
687
ea5b213a 688static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 689 struct intel_sdvo_dtd *dtd)
690{
ea5b213a 691 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 692 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
693}
694
ea5b213a 695static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 696 struct intel_sdvo_dtd *dtd)
697{
ea5b213a 698 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 699 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
700}
701
e2f0ba97 702static bool
ea5b213a 703intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 704 uint16_t clock,
705 uint16_t width,
706 uint16_t height)
707{
708 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 709
e642c6f1 710 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 711 args.clock = clock;
712 args.width = width;
713 args.height = height;
e642c6f1 714 args.interlace = 0;
12682a97 715
ea5b213a
CW		 716 if (intel_sdvo->is_lvds &&
717 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
718 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 719 args.scaled = 1;
720
32aad86f
CW		 721 return intel_sdvo_set_value(intel_sdvo,
722 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
723 &args, sizeof(args));
e2f0ba97
JB		 724}
725
ea5b213a 726static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 727 struct intel_sdvo_dtd *dtd)
728{
1a3665c8
CW		 729 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
730 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 731 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
732 &dtd->part1, sizeof(dtd->part1)) &&
733 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
734 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 735}
79e53945 736
ea5b213a 737static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 738{
32aad86f 739 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 740}
741
e2f0ba97 742static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 743 const struct drm_display_mode *mode)
79e53945 744{
e2f0ba97
JB		 745 uint16_t width, height;
746 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
747 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 748
749 width = mode->crtc_hdisplay;
750 height = mode->crtc_vdisplay;
751
752 /* do some mode translations */
753 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
754 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
755
756 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
757 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
758
759 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
760 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
761
e2f0ba97
JB		 762 dtd->part1.clock = mode->clock / 10;
763 dtd->part1.h_active = width & 0xff;
764 dtd->part1.h_blank = h_blank_len & 0xff;
765 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 766 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 767 dtd->part1.v_active = height & 0xff;
768 dtd->part1.v_blank = v_blank_len & 0xff;
769 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 770 ((v_blank_len >> 8) & 0xf);
771
171a9e96 772 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 773 dtd->part2.h_sync_width = h_sync_len & 0xff;
774 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 775 (v_sync_len & 0xf);
e2f0ba97 776 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 777 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
778 ((v_sync_len & 0x30) >> 4);
779
e2f0ba97 780 dtd->part2.dtd_flags = 0x18;
79e53945 781 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 782 dtd->part2.dtd_flags |= 0x2;
79e53945 783 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 784 dtd->part2.dtd_flags |= 0x4;
785
786 dtd->part2.sdvo_flags = 0;
787 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
788 dtd->part2.reserved = 0;
789}
790
791static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 792 const struct intel_sdvo_dtd *dtd)
e2f0ba97 793{
e2f0ba97
JB		 794 mode->hdisplay = dtd->part1.h_active;
795 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
796 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 797 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 798 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
799 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
800 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
801 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
802
803 mode->vdisplay = dtd->part1.v_active;
804 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
805 mode->vsync_start = mode->vdisplay;
806 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 807 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 808 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
809 mode->vsync_end = mode->vsync_start +
810 (dtd->part2.v_sync_off_width & 0xf);
811 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
812 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
813 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
814
815 mode->clock = dtd->part1.clock * 10;
816
171a9e96 817 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 818 if (dtd->part2.dtd_flags & 0x2)
819 mode->flags |= DRM_MODE_FLAG_PHSYNC;
820 if (dtd->part2.dtd_flags & 0x4)
821 mode->flags |= DRM_MODE_FLAG_PVSYNC;
822}
823
e27d8538 824static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 825{
e27d8538 826 struct intel_sdvo_encode encode;
e2f0ba97 827
1a3665c8 828 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 829 return intel_sdvo_get_value(intel_sdvo,
830 SDVO_CMD_GET_SUPP_ENCODE,
831 &encode, sizeof(encode));
e2f0ba97
JB		 832}
833
ea5b213a 834static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 835 uint8_t mode)
e2f0ba97 836{
32aad86f 837 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 838}
839
ea5b213a 840static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 841 uint8_t mode)
842{
32aad86f 843 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 844}
845
846#if 0
ea5b213a 847static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 848{
849 int i, j;
850 uint8_t set_buf_index[2];
851 uint8_t av_split;
852 uint8_t buf_size;
853 uint8_t buf[48];
854 uint8_t *pos;
855
32aad86f 856 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 857
858 for (i = 0; i <= av_split; i++) {
859 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 860 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 861 set_buf_index, 2);
c751ce4f
EA		 862 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
863 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 864
865 pos = buf;
866 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 867 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 868 NULL, 0);
c751ce4f 869 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 870 pos += 8;
871 }
872 }
873}
874#endif
875
3c17fe4b 876static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 877{
878 struct dip_infoframe avi_if = {
879 .type = DIP_TYPE_AVI,
3c17fe4b 880 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 881 .len = DIP_LEN_AVI,
882 };
3c17fe4b
DH		 883 uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
884 uint8_t set_buf_index[2] = { 1, 0 };
885 uint64_t *data = (uint64_t *)&avi_if;
886 unsigned i;
887
888 intel_dip_infoframe_csum(&avi_if);
889
d121a5d2
CW		 890 if (!intel_sdvo_set_value(intel_sdvo,
891 SDVO_CMD_SET_HBUF_INDEX,
3c17fe4b
DH		 892 set_buf_index, 2))
893 return false;
894
895 for (i = 0; i < sizeof(avi_if); i += 8) {
d121a5d2
CW		 896 if (!intel_sdvo_set_value(intel_sdvo,
897 SDVO_CMD_SET_HBUF_DATA,
3c17fe4b
DH		 898 data, 8))
899 return false;
900 data++;
901 }
e2f0ba97 902
d121a5d2
CW		 903 return intel_sdvo_set_value(intel_sdvo,
904 SDVO_CMD_SET_HBUF_TXRATE,
3c17fe4b 905 &tx_rate, 1);
e2f0ba97
JB		 906}
907
32aad86f 908static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 909{
ce6feabd 910 struct intel_sdvo_tv_format format;
40039750 911 uint32_t format_map;
ce6feabd 912
40039750 913 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 914 memset(&format, 0, sizeof(format));
32aad86f 915 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 916
32aad86f
CW		 917 BUILD_BUG_ON(sizeof(format) != 6);
918 return intel_sdvo_set_value(intel_sdvo,
919 SDVO_CMD_SET_TV_FORMAT,
920 &format, sizeof(format));
7026d4ac
ZW		 921}
922
32aad86f
CW		 923static bool
924intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
925 struct drm_display_mode *mode)
e2f0ba97 926{
32aad86f 927 struct intel_sdvo_dtd output_dtd;
79e53945 928
32aad86f
CW		 929 if (!intel_sdvo_set_target_output(intel_sdvo,
930 intel_sdvo->attached_output))
931 return false;
e2f0ba97 932
32aad86f
CW		 933 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
934 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
935 return false;
e2f0ba97 936
32aad86f
CW		 937 return true;
938}
939
940static bool
941intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
942 struct drm_display_mode *mode,
943 struct drm_display_mode *adjusted_mode)
944{
32aad86f
CW		 945 /* Reset the input timing to the screen. Assume always input 0. */
946 if (!intel_sdvo_set_target_input(intel_sdvo))
947 return false;
e2f0ba97 948
32aad86f
CW		 949 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
950 mode->clock / 10,
951 mode->hdisplay,
952 mode->vdisplay))
953 return false;
e2f0ba97 954
32aad86f 955 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
6c9547ff 956 &intel_sdvo->input_dtd))
32aad86f 957 return false;
e2f0ba97 958
6c9547ff 959 intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
79e53945 960
32aad86f
CW		 961 return true;
962}
12682a97 963
32aad86f
CW		 964static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
965 struct drm_display_mode *mode,
966 struct drm_display_mode *adjusted_mode)
967{
890f3359 968 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 969 int multiplier;
12682a97 970
32aad86f
CW		 971 /* We need to construct preferred input timings based on our
972 * output timings. To do that, we have to set the output
973 * timings, even though this isn't really the right place in
974 * the sequence to do it. Oh well.
975 */
976 if (intel_sdvo->is_tv) {
977 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
978 return false;
12682a97 979
c74696b9
PR		 980 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
981 mode,
982 adjusted_mode);
ea5b213a 983 } else if (intel_sdvo->is_lvds) {
32aad86f 984 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 985 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 986 return false;
12682a97 987
c74696b9
PR		 988 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
989 mode,
990 adjusted_mode);
e2f0ba97 991 }
32aad86f
CW		 992
993 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 994 * SDVO device will factor out the multiplier during mode_set.
32aad86f 995 */
6c9547ff
CW		 996 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
997 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 998
e2f0ba97
JB		 999 return true;
1000}
1001
1002static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1003 struct drm_display_mode *mode,
1004 struct drm_display_mode *adjusted_mode)
1005{
1006 struct drm_device *dev = encoder->dev;
1007 struct drm_i915_private *dev_priv = dev->dev_private;
1008 struct drm_crtc *crtc = encoder->crtc;
1009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 1010 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1011 u32 sdvox;
e2f0ba97
JB		 1012 struct intel_sdvo_in_out_map in_out;
1013 struct intel_sdvo_dtd input_dtd;
6c9547ff
CW		 1014 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1015 int rate;
e2f0ba97
JB		 1016
1017 if (!mode)
1018 return;
1019
1020 /* First, set the input mapping for the first input to our controlled
1021 * output. This is only correct if we're a single-input device, in
1022 * which case the first input is the output from the appropriate SDVO
1023 * channel on the motherboard. In a two-input device, the first input
1024 * will be SDVOB and the second SDVOC.
1025 */
ea5b213a 1026 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1027 in_out.in1 = 0;
1028
c74696b9
PR		 1029 intel_sdvo_set_value(intel_sdvo,
1030 SDVO_CMD_SET_IN_OUT_MAP,
1031 &in_out, sizeof(in_out));
e2f0ba97 1032
6c9547ff
CW		 1033 /* Set the output timings to the screen */
1034 if (!intel_sdvo_set_target_output(intel_sdvo,
1035 intel_sdvo->attached_output))
1036 return;
e2f0ba97 1037
7026d4ac 1038 /* We have tried to get input timing in mode_fixup, and filled into
6c9547ff 1039 * adjusted_mode.
e2f0ba97 1040 */
6c9547ff
CW		 1041 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
1042 input_dtd = intel_sdvo->input_dtd;
1043 } else {
e2f0ba97 1044 /* Set the output timing to the screen */
32aad86f
CW		 1045 if (!intel_sdvo_set_target_output(intel_sdvo,
1046 intel_sdvo->attached_output))
1047 return;
1048
6c9547ff 1049 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c74696b9 1050 (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
e2f0ba97 1051 }
79e53945
JB		 1052
1053 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1054 if (!intel_sdvo_set_target_input(intel_sdvo))
1055 return;
79e53945 1056
97aaf910
CW		 1057 if (intel_sdvo->has_hdmi_monitor) {
1058 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1059 intel_sdvo_set_colorimetry(intel_sdvo,
1060 SDVO_COLORIMETRY_RGB256);
1061 intel_sdvo_set_avi_infoframe(intel_sdvo);
1062 } else
1063 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1064
6c9547ff
CW		 1065 if (intel_sdvo->is_tv &&
1066 !intel_sdvo_set_tv_format(intel_sdvo))
1067 return;
e2f0ba97 1068
c74696b9 1069 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
79e53945 1070
6c9547ff
CW		 1071 switch (pixel_multiplier) {
1072 default:
32aad86f
CW		 1073 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1074 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1075 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1076 }
32aad86f
CW		 1077 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1078 return;
79e53945
JB		 1079
1080 /* Set the SDVO control regs. */
a6c45cf0 1081 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1082 /* The real mode polarity is set by the SDVO commands, using
1083 * struct intel_sdvo_dtd. */
1084 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
e953fd7b
CW		 1085 if (intel_sdvo->is_hdmi)
1086 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1087 if (INTEL_INFO(dev)->gen < 5)
1088 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1089 } else {
6c9547ff 1090 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1091 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1092 case SDVOB:
1093 sdvox &= SDVOB_PRESERVE_MASK;
1094 break;
1095 case SDVOC:
1096 sdvox &= SDVOC_PRESERVE_MASK;
1097 break;
1098 }
1099 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1100 }
3573c410
PZ		 1101
1102 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1103 sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
1104 else
1105 sdvox |= TRANSCODER(intel_crtc->pipe);
1106
da79de97 1107 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1108 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1109
a6c45cf0 1110 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1111 /* done in crtc_mode_set as the dpll_md reg must be written early */
1112 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1113 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1114 } else {
6c9547ff 1115 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1116 }
1117
6714afb1
CW		 1118 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1119 INTEL_INFO(dev)->gen < 5)
12682a97 1120 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1121 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1122}
1123
1124static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1125{
1126 struct drm_device *dev = encoder->dev;
1127 struct drm_i915_private *dev_priv = dev->dev_private;
890f3359 1128 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
9d0498a2 1129 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1130 u32 temp;
1131
1132 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1133 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1134 if (0)
ea5b213a 1135 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1136
1137 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1138 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1139 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1140 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1141 }
1142 }
1143 } else {
1144 bool input1, input2;
1145 int i;
1146 u8 status;
1147
ea5b213a 1148 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1149 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1150 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1151 for (i = 0; i < 2; i++)
9d0498a2 1152 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1153
32aad86f 1154 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1155 /* Warn if the device reported failure to sync.
1156 * A lot of SDVO devices fail to notify of sync, but it's
1157 * a given it the status is a success, we succeeded.
1158 */
1159 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1160 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1161 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1162 }
1163
1164 if (0)
ea5b213a
CW		 1165 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1166 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1167 }
1168 return;
1169}
1170
79e53945
JB		 1171static int intel_sdvo_mode_valid(struct drm_connector *connector,
1172 struct drm_display_mode *mode)
1173{
df0e9248 1174 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1175
1176 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1177 return MODE_NO_DBLESCAN;
1178
ea5b213a 1179 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1180 return MODE_CLOCK_LOW;
1181
ea5b213a 1182 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1183 return MODE_CLOCK_HIGH;
1184
8545423a 1185 if (intel_sdvo->is_lvds) {
ea5b213a 1186 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1187 return MODE_PANEL;
1188
ea5b213a 1189 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1190 return MODE_PANEL;
1191 }
1192
79e53945
JB		 1193 return MODE_OK;
1194}
1195
ea5b213a 1196static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1197{
1a3665c8 1198 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1199 if (!intel_sdvo_get_value(intel_sdvo,
1200 SDVO_CMD_GET_DEVICE_CAPS,
1201 caps, sizeof(*caps)))
1202 return false;
1203
1204 DRM_DEBUG_KMS("SDVO capabilities:\n"
1205 " vendor_id: %d\n"
1206 " device_id: %d\n"
1207 " device_rev_id: %d\n"
1208 " sdvo_version_major: %d\n"
1209 " sdvo_version_minor: %d\n"
1210 " sdvo_inputs_mask: %d\n"
1211 " smooth_scaling: %d\n"
1212 " sharp_scaling: %d\n"
1213 " up_scaling: %d\n"
1214 " down_scaling: %d\n"
1215 " stall_support: %d\n"
1216 " output_flags: %d\n",
1217 caps->vendor_id,
1218 caps->device_id,
1219 caps->device_rev_id,
1220 caps->sdvo_version_major,
1221 caps->sdvo_version_minor,
1222 caps->sdvo_inputs_mask,
1223 caps->smooth_scaling,
1224 caps->sharp_scaling,
1225 caps->up_scaling,
1226 caps->down_scaling,
1227 caps->stall_support,
1228 caps->output_flags);
1229
1230 return true;
79e53945
JB		 1231}
1232
cc68c81a 1233static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
79e53945
JB		 1234{
1235 u8 response[2];
79e53945 1236
32aad86f
CW		 1237 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1238 &response, 2) && response[0];
79e53945
JB		 1239}
1240
cc68c81a 1241static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1242{
cc68c81a 1243 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1244
cc68c81a 1245 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1246}
1247
fb7a46f3 1248static bool
ea5b213a 1249intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1250{
bc65212c 1251 /* Is there more than one type of output? */
2294488d 1252 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1253}
1254
f899fc64 1255static struct edid *
e957d772 1256intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1257{
e957d772
CW		 1258 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1259 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1260}
1261
ff482d83
CW		 1262/* Mac mini hack -- use the same DDC as the analog connector */
1263static struct edid *
1264intel_sdvo_get_analog_edid(struct drm_connector *connector)
1265{
f899fc64 1266 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1267
0c1dab89 1268 return drm_get_edid(connector,
3bd7d909
DK		 1269 intel_gmbus_get_adapter(dev_priv,
1270 dev_priv->crt_ddc_pin));
ff482d83
CW		 1271}
1272
c43b5634 1273static enum drm_connector_status
8bf38485 1274intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1275{
df0e9248 1276 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1277 enum drm_connector_status status;
1278 struct edid *edid;
9dff6af8 1279
e957d772 1280 edid = intel_sdvo_get_edid(connector);
57cdaf90 1281
ea5b213a 1282 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1283 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1284
7c3f0a27
ZY		 1285 /*
1286 * Don't use the 1 as the argument of DDC bus switch to get
1287 * the EDID. It is used for SDVO SPD ROM.
1288 */
9d1a903d 1289 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1290 intel_sdvo->ddc_bus = ddc;
1291 edid = intel_sdvo_get_edid(connector);
1292 if (edid)
7c3f0a27 1293 break;
7c3f0a27 1294 }
e957d772
CW		 1295 /*
1296 * If we found the EDID on the other bus,
1297 * assume that is the correct DDC bus.
1298 */
1299 if (edid == NULL)
1300 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1301 }
9d1a903d
CW		 1302
1303 /*
1304 * When there is no edid and no monitor is connected with VGA
1305 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1306 */
ff482d83
CW		 1307 if (edid == NULL)
1308 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1309
2f551c84 1310 status = connector_status_unknown;
9dff6af8 1311 if (edid != NULL) {
149c36a3 1312 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1313 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1314 status = connector_status_connected;
da79de97
CW		 1315 if (intel_sdvo->is_hdmi) {
1316 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1317 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1318 }
13946743
CW		 1319 } else
1320 status = connector_status_disconnected;
149c36a3 1321 connector->display_info.raw_edid = NULL;
9d1a903d
CW		 1322 kfree(edid);
1323 }
7f36e7ed
CW		 1324
1325 if (status == connector_status_connected) {
1326 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1327 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1328 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1329 }
1330
2b8d33f7 1331 return status;
9dff6af8
ML		 1332}
1333
52220085
CW		 1334static bool
1335intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1336 struct edid *edid)
1337{
1338 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1339 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1340
1341 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1342 connector_is_digital, monitor_is_digital);
1343 return connector_is_digital == monitor_is_digital;
1344}
1345
7b334fcb 1346static enum drm_connector_status
930a9e28 1347intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1348{
fb7a46f3 1349 uint16_t response;
df0e9248 1350 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1351 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1352 enum drm_connector_status ret;
79e53945 1353
32aad86f 1354 if (!intel_sdvo_write_cmd(intel_sdvo,
e957d772 1355 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
32aad86f 1356 return connector_status_unknown;
ba84cd1f
CW		 1357
1358 /* add 30ms delay when the output type might be TV */
a0b1c7a5 1359 if (intel_sdvo->caps.output_flags & SDVO_TV_MASK)
d09c23de 1360 mdelay(30);
ba84cd1f 1361
32aad86f
CW		 1362 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1363 return connector_status_unknown;
79e53945 1364
e957d772
CW		 1365 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1366 response & 0xff, response >> 8,
1367 intel_sdvo_connector->output_flag);
e2f0ba97 1368
fb7a46f3 1369 if (response == 0)
79e53945 1370 return connector_status_disconnected;
fb7a46f3 1371
ea5b213a 1372 intel_sdvo->attached_output = response;
14571b4c 1373
97aaf910
CW		 1374 intel_sdvo->has_hdmi_monitor = false;
1375 intel_sdvo->has_hdmi_audio = false;
1376
615fb93f 1377 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1378 ret = connector_status_disconnected;
13946743 1379 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1380 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1381 else {
1382 struct edid *edid;
1383
1384 /* if we have an edid check it matches the connection */
1385 edid = intel_sdvo_get_edid(connector);
1386 if (edid == NULL)
1387 edid = intel_sdvo_get_analog_edid(connector);
1388 if (edid != NULL) {
52220085
CW		 1389 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1390 edid))
13946743 1391 ret = connector_status_connected;
52220085
CW		 1392 else
1393 ret = connector_status_disconnected;
1394
13946743
CW		 1395 connector->display_info.raw_edid = NULL;
1396 kfree(edid);
1397 } else
1398 ret = connector_status_connected;
1399 }
14571b4c
ZW		 1400
1401 /* May update encoder flag for like clock for SDVO TV, etc.*/
1402 if (ret == connector_status_connected) {
ea5b213a
CW		 1403 intel_sdvo->is_tv = false;
1404 intel_sdvo->is_lvds = false;
1405 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1406
1407 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1408 intel_sdvo->is_tv = true;
1409 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1410 }
1411 if (response & SDVO_LVDS_MASK)
8545423a 1412 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1413 }
14571b4c
ZW		 1414
1415 return ret;
79e53945
JB		 1416}
1417
e2f0ba97 1418static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1419{
ff482d83 1420 struct edid *edid;
79e53945
JB		 1421
1422 /* set the bus switch and get the modes */
e957d772 1423 edid = intel_sdvo_get_edid(connector);
79e53945 1424
57cdaf90
KP		 1425 /*
1426 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1427 * link between analog and digital outputs. So, if the regular SDVO
1428 * DDC fails, check to see if the analog output is disconnected, in
1429 * which case we'll look there for the digital DDC data.
e2f0ba97 1430 */
f899fc64
CW		 1431 if (edid == NULL)
1432 edid = intel_sdvo_get_analog_edid(connector);
1433
ff482d83 1434 if (edid != NULL) {
52220085
CW		 1435 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1436 edid)) {
0c1dab89
CW		 1437 drm_mode_connector_update_edid_property(connector, edid);
1438 drm_add_edid_modes(connector, edid);
1439 }
13946743 1440
ff482d83
CW		 1441 connector->display_info.raw_edid = NULL;
1442 kfree(edid);
e2f0ba97 1443 }
e2f0ba97
JB		 1444}
1445
1446/*
1447 * Set of SDVO TV modes.
1448 * Note! This is in reply order (see loop in get_tv_modes).
1449 * XXX: all 60Hz refresh?
1450 */
b1f559ec 1451static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1452 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1453 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1454 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1455 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1456 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1458 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1459 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1461 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1462 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1464 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1465 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1467 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1468 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1470 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1471 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1473 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1474 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1476 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1477 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1479 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1480 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1482 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1483 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1485 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1486 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1488 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1489 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1491 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1492 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1494 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1495 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1497 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1498 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1500 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1501 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1503 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1504 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1506 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1507 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1509};
1510
1511static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1512{
df0e9248 1513 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1514 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1515 uint32_t reply = 0, format_map = 0;
1516 int i;
e2f0ba97
JB		 1517
1518 /* Read the list of supported input resolutions for the selected TV
1519 * format.
1520 */
40039750 1521 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1522 memcpy(&tv_res, &format_map,
32aad86f 1523 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1524
32aad86f
CW		 1525 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1526 return;
ce6feabd 1527
32aad86f 1528 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1529 if (!intel_sdvo_write_cmd(intel_sdvo,
1530 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1531 &tv_res, sizeof(tv_res)))
1532 return;
1533 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1534 return;
1535
1536 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1537 if (reply & (1 << i)) {
1538 struct drm_display_mode *nmode;
1539 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1540 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1541 if (nmode)
1542 drm_mode_probed_add(connector, nmode);
1543 }
e2f0ba97
JB		 1544}
1545
7086c87f
ML		 1546static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1547{
df0e9248 1548 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1549 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1550 struct drm_display_mode *newmode;
7086c87f
ML		 1551
1552 /*
1553 * Attempt to get the mode list from DDC.
1554 * Assume that the preferred modes are
1555 * arranged in priority order.
1556 */
f899fc64 1557 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1558 if (list_empty(&connector->probed_modes) == false)
12682a97 1559 goto end;
7086c87f
ML		 1560
1561 /* Fetch modes from VBT */
1562 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1563 newmode = drm_mode_duplicate(connector->dev,
1564 dev_priv->sdvo_lvds_vbt_mode);
1565 if (newmode != NULL) {
1566 /* Guarantee the mode is preferred */
1567 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1568 DRM_MODE_TYPE_DRIVER);
1569 drm_mode_probed_add(connector, newmode);
1570 }
1571 }
12682a97 1572
1573end:
1574 list_for_each_entry(newmode, &connector->probed_modes, head) {
1575 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1576 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1577 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1578
8545423a 1579 intel_sdvo->is_lvds = true;
12682a97 1580 break;
1581 }
1582 }
1583
7086c87f
ML		 1584}
1585
e2f0ba97
JB		 1586static int intel_sdvo_get_modes(struct drm_connector *connector)
1587{
615fb93f 1588 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1589
615fb93f 1590 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1591 intel_sdvo_get_tv_modes(connector);
615fb93f 1592 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1593 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1594 else
1595 intel_sdvo_get_ddc_modes(connector);
1596
32aad86f 1597 return !list_empty(&connector->probed_modes);
79e53945
JB		 1598}
1599
fcc8d672
CW		 1600static void
1601intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1602{
615fb93f 1603 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1604 struct drm_device *dev = connector->dev;
1605
c5521706
CW		 1606 if (intel_sdvo_connector->left)
1607 drm_property_destroy(dev, intel_sdvo_connector->left);
1608 if (intel_sdvo_connector->right)
1609 drm_property_destroy(dev, intel_sdvo_connector->right);
1610 if (intel_sdvo_connector->top)
1611 drm_property_destroy(dev, intel_sdvo_connector->top);
1612 if (intel_sdvo_connector->bottom)
1613 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1614 if (intel_sdvo_connector->hpos)
1615 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1616 if (intel_sdvo_connector->vpos)
1617 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1618 if (intel_sdvo_connector->saturation)
1619 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1620 if (intel_sdvo_connector->contrast)
1621 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1622 if (intel_sdvo_connector->hue)
1623 drm_property_destroy(dev, intel_sdvo_connector->hue);
1624 if (intel_sdvo_connector->sharpness)
1625 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1626 if (intel_sdvo_connector->flicker_filter)
1627 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1628 if (intel_sdvo_connector->flicker_filter_2d)
1629 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1630 if (intel_sdvo_connector->flicker_filter_adaptive)
1631 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1632 if (intel_sdvo_connector->tv_luma_filter)
1633 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1634 if (intel_sdvo_connector->tv_chroma_filter)
1635 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1636 if (intel_sdvo_connector->dot_crawl)
1637 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1638 if (intel_sdvo_connector->brightness)
1639 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1640}
1641
79e53945
JB		 1642static void intel_sdvo_destroy(struct drm_connector *connector)
1643{
615fb93f 1644 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1645
c5521706 1646 if (intel_sdvo_connector->tv_format)
ce6feabd 1647 drm_property_destroy(connector->dev,
c5521706 1648 intel_sdvo_connector->tv_format);
b9219c5e 1649
d2a82a6f 1650 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1651 drm_sysfs_connector_remove(connector);
1652 drm_connector_cleanup(connector);
d2a82a6f 1653 kfree(connector);
79e53945
JB		 1654}
1655
1aad7ac0
CW		 1656static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1657{
1658 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1659 struct edid *edid;
1660 bool has_audio = false;
1661
1662 if (!intel_sdvo->is_hdmi)
1663 return false;
1664
1665 edid = intel_sdvo_get_edid(connector);
1666 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1667 has_audio = drm_detect_monitor_audio(edid);
1668
1669 return has_audio;
1670}
1671
ce6feabd
ZY		 1672static int
1673intel_sdvo_set_property(struct drm_connector *connector,
1674 struct drm_property *property,
1675 uint64_t val)
1676{
df0e9248 1677 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1678 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1679 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1680 uint16_t temp_value;
32aad86f
CW		 1681 uint8_t cmd;
1682 int ret;
ce6feabd
ZY		 1683
1684 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1685 if (ret)
1686 return ret;
ce6feabd 1687
3f43c48d 1688 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1689 int i = val;
1690 bool has_audio;
1691
1692 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1693 return 0;
1694
1aad7ac0 1695 intel_sdvo_connector->force_audio = i;
7f36e7ed 1696
c3e5f67b 1697 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 1698 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1699 else
c3e5f67b 1700 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 1701
1aad7ac0 1702 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1703 return 0;
7f36e7ed 1704
1aad7ac0 1705 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 1706 goto done;
1707 }
1708
e953fd7b
CW		 1709 if (property == dev_priv->broadcast_rgb_property) {
1710 if (val == !!intel_sdvo->color_range)
7f36e7ed
CW		 1711 return 0;
1712
e953fd7b 1713 intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
7f36e7ed
CW		 1714 goto done;
1715 }
1716
c5521706
CW		 1717#define CHECK_PROPERTY(name, NAME) \
1718 if (intel_sdvo_connector->name == property) { \
1719 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1720 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1721 cmd = SDVO_CMD_SET_##NAME; \
1722 intel_sdvo_connector->cur_##name = temp_value; \
1723 goto set_value; \
1724 }
1725
1726 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1727 if (val >= TV_FORMAT_NUM)
1728 return -EINVAL;
1729
40039750 1730 if (intel_sdvo->tv_format_index ==
615fb93f 1731 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1732 return 0;
ce6feabd 1733
40039750 1734 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1735 goto done;
32aad86f 1736 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1737 temp_value = val;
c5521706 1738 if (intel_sdvo_connector->left == property) {
b9219c5e 1739 drm_connector_property_set_value(connector,
c5521706 1740 intel_sdvo_connector->right, val);
615fb93f 1741 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1742 return 0;
b9219c5e 1743
615fb93f
CW		 1744 intel_sdvo_connector->left_margin = temp_value;
1745 intel_sdvo_connector->right_margin = temp_value;
1746 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1747 intel_sdvo_connector->left_margin;
b9219c5e 1748 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1749 goto set_value;
1750 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1751 drm_connector_property_set_value(connector,
c5521706 1752 intel_sdvo_connector->left, val);
615fb93f 1753 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1754 return 0;
b9219c5e 1755
615fb93f
CW		 1756 intel_sdvo_connector->left_margin = temp_value;
1757 intel_sdvo_connector->right_margin = temp_value;
1758 temp_value = intel_sdvo_connector->max_hscan -
1759 intel_sdvo_connector->left_margin;
b9219c5e 1760 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1761 goto set_value;
1762 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1763 drm_connector_property_set_value(connector,
c5521706 1764 intel_sdvo_connector->bottom, val);
615fb93f 1765 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1766 return 0;
b9219c5e 1767
615fb93f
CW		 1768 intel_sdvo_connector->top_margin = temp_value;
1769 intel_sdvo_connector->bottom_margin = temp_value;
1770 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1771 intel_sdvo_connector->top_margin;
b9219c5e 1772 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1773 goto set_value;
1774 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1775 drm_connector_property_set_value(connector,
c5521706 1776 intel_sdvo_connector->top, val);
615fb93f 1777 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1778 return 0;
1779
615fb93f
CW		 1780 intel_sdvo_connector->top_margin = temp_value;
1781 intel_sdvo_connector->bottom_margin = temp_value;
1782 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1783 intel_sdvo_connector->top_margin;
b9219c5e 1784 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1785 goto set_value;
1786 }
1787 CHECK_PROPERTY(hpos, HPOS)
1788 CHECK_PROPERTY(vpos, VPOS)
1789 CHECK_PROPERTY(saturation, SATURATION)
1790 CHECK_PROPERTY(contrast, CONTRAST)
1791 CHECK_PROPERTY(hue, HUE)
1792 CHECK_PROPERTY(brightness, BRIGHTNESS)
1793 CHECK_PROPERTY(sharpness, SHARPNESS)
1794 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1795 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1796 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1797 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1798 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1799 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1800 }
b9219c5e 1801
c5521706 1802 return -EINVAL; /* unknown property */
b9219c5e 1803
c5521706
CW		 1804set_value:
1805 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1806 return -EIO;
b9219c5e 1807
b9219c5e 1808
c5521706 1809done:
df0e9248
CW		 1810 if (intel_sdvo->base.base.crtc) {
1811 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
ce6feabd 1812 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1813 crtc->y, crtc->fb);
1814 }
1815
32aad86f 1816 return 0;
c5521706 1817#undef CHECK_PROPERTY
ce6feabd
ZY		 1818}
1819
79e53945
JB		 1820static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1821 .dpms = intel_sdvo_dpms,
1822 .mode_fixup = intel_sdvo_mode_fixup,
1823 .prepare = intel_encoder_prepare,
1824 .mode_set = intel_sdvo_mode_set,
1825 .commit = intel_encoder_commit,
1826};
1827
1828static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1829 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1830 .detect = intel_sdvo_detect,
1831 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1832 .set_property = intel_sdvo_set_property,
79e53945
JB		 1833 .destroy = intel_sdvo_destroy,
1834};
1835
1836static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1837 .get_modes = intel_sdvo_get_modes,
1838 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1839 .best_encoder = intel_best_encoder,
79e53945
JB		 1840};
1841
b358d0a6 1842static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1843{
890f3359 1844 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 1845
ea5b213a 1846 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1847 drm_mode_destroy(encoder->dev,
ea5b213a 1848 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1849
e957d772 1850 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 1851 intel_encoder_destroy(encoder);
79e53945
JB		 1852}
1853
1854static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1855 .destroy = intel_sdvo_enc_destroy,
1856};
1857
b66d8424
CW		 1858static void
1859intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1860{
1861 uint16_t mask = 0;
1862 unsigned int num_bits;
1863
1864 /* Make a mask of outputs less than or equal to our own priority in the
1865 * list.
1866 */
1867 switch (sdvo->controlled_output) {
1868 case SDVO_OUTPUT_LVDS1:
1869 mask |= SDVO_OUTPUT_LVDS1;
1870 case SDVO_OUTPUT_LVDS0:
1871 mask |= SDVO_OUTPUT_LVDS0;
1872 case SDVO_OUTPUT_TMDS1:
1873 mask |= SDVO_OUTPUT_TMDS1;
1874 case SDVO_OUTPUT_TMDS0:
1875 mask |= SDVO_OUTPUT_TMDS0;
1876 case SDVO_OUTPUT_RGB1:
1877 mask |= SDVO_OUTPUT_RGB1;
1878 case SDVO_OUTPUT_RGB0:
1879 mask |= SDVO_OUTPUT_RGB0;
1880 break;
1881 }
1882
1883 /* Count bits to find what number we are in the priority list. */
1884 mask &= sdvo->caps.output_flags;
1885 num_bits = hweight16(mask);
1886 /* If more than 3 outputs, default to DDC bus 3 for now. */
1887 if (num_bits > 3)
1888 num_bits = 3;
1889
1890 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1891 sdvo->ddc_bus = 1 << num_bits;
1892}
79e53945 1893
e2f0ba97
JB		 1894/**
1895 * Choose the appropriate DDC bus for control bus switch command for this
1896 * SDVO output based on the controlled output.
1897 *
1898 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1899 * outputs, then LVDS outputs.
1900 */
1901static void
b1083333 1902intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1903 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1904{
b1083333 1905 struct sdvo_device_mapping *mapping;
e2f0ba97 1906
eef4eacb 1907 if (sdvo->is_sdvob)
b1083333
AJ		 1908 mapping = &(dev_priv->sdvo_mappings[0]);
1909 else
1910 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1911
b66d8424
CW		 1912 if (mapping->initialized)
1913 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1914 else
1915 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1916}
1917
e957d772
CW		 1918static void
1919intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
1920 struct intel_sdvo *sdvo, u32 reg)
1921{
1922 struct sdvo_device_mapping *mapping;
46eb3036 1923 u8 pin;
e957d772 1924
eef4eacb 1925 if (sdvo->is_sdvob)
e957d772
CW		 1926 mapping = &dev_priv->sdvo_mappings[0];
1927 else
1928 mapping = &dev_priv->sdvo_mappings[1];
1929
1930 pin = GMBUS_PORT_DPB;
46eb3036 1931 if (mapping->initialized)
e957d772 1932 pin = mapping->i2c_pin;
e957d772 1933
3bd7d909
DK		 1934 if (intel_gmbus_is_port_valid(pin)) {
1935 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
d5090b96 1936 intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ);
63abf3ed 1937 intel_gmbus_force_bit(sdvo->i2c, true);
46eb3036 1938 } else {
3bd7d909 1939 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
46eb3036 1940 }
e957d772
CW		 1941}
1942
e2f0ba97 1943static bool
e27d8538 1944intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1945{
97aaf910 1946 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 1947}
1948
714605e4 1949static u8
eef4eacb 1950intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 1951{
1952 struct drm_i915_private *dev_priv = dev->dev_private;
1953 struct sdvo_device_mapping *my_mapping, *other_mapping;
1954
eef4eacb 1955 if (sdvo->is_sdvob) {
714605e4 1956 my_mapping = &dev_priv->sdvo_mappings[0];
1957 other_mapping = &dev_priv->sdvo_mappings[1];
1958 } else {
1959 my_mapping = &dev_priv->sdvo_mappings[1];
1960 other_mapping = &dev_priv->sdvo_mappings[0];
1961 }
1962
1963 /* If the BIOS described our SDVO device, take advantage of it. */
1964 if (my_mapping->slave_addr)
1965 return my_mapping->slave_addr;
1966
1967 /* If the BIOS only described a different SDVO device, use the
1968 * address that it isn't using.
1969 */
1970 if (other_mapping->slave_addr) {
1971 if (other_mapping->slave_addr == 0x70)
1972 return 0x72;
1973 else
1974 return 0x70;
1975 }
1976
1977 /* No SDVO device info is found for another DVO port,
1978 * so use mapping assumption we had before BIOS parsing.
1979 */
eef4eacb 1980 if (sdvo->is_sdvob)
714605e4 1981 return 0x70;
1982 else
1983 return 0x72;
1984}
1985
14571b4c 1986static void
df0e9248
CW		 1987intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
1988 struct intel_sdvo *encoder)
14571b4c 1989{
df0e9248
CW		 1990 drm_connector_init(encoder->base.base.dev,
1991 &connector->base.base,
1992 &intel_sdvo_connector_funcs,
1993 connector->base.base.connector_type);
6070a4a9 1994
df0e9248
CW		 1995 drm_connector_helper_add(&connector->base.base,
1996 &intel_sdvo_connector_helper_funcs);
14571b4c 1997
8f4839e2 1998 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 1999 connector->base.base.doublescan_allowed = 0;
2000 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
14571b4c 2001
df0e9248
CW		 2002 intel_connector_attach_encoder(&connector->base, &encoder->base);
2003 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2004}
6070a4a9 2005
7f36e7ed
CW		 2006static void
2007intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
2008{
2009 struct drm_device *dev = connector->base.base.dev;
2010
3f43c48d 2011 intel_attach_force_audio_property(&connector->base.base);
e953fd7b
CW		 2012 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
2013 intel_attach_broadcast_rgb_property(&connector->base.base);
7f36e7ed
CW		 2014}
2015
fb7a46f3 2016static bool
ea5b213a 2017intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2018{
4ef69c7a 2019 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2020 struct drm_connector *connector;
cc68c81a 2021 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2022 struct intel_connector *intel_connector;
615fb93f 2023 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2024
615fb93f
CW		 2025 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2026 if (!intel_sdvo_connector)
14571b4c
ZW		 2027 return false;
2028
14571b4c 2029 if (device == 0) {
ea5b213a 2030 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2031 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2032 } else if (device == 1) {
ea5b213a 2033 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2034 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2035 }
2036
615fb93f 2037 intel_connector = &intel_sdvo_connector->base;
14571b4c 2038 connector = &intel_connector->base;
cc68c81a
SF		 2039 if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
2040 connector->polled = DRM_CONNECTOR_POLL_HPD;
2041 intel_sdvo->hotplug_active[0] |= 1 << device;
2042 /* Some SDVO devices have one-shot hotplug interrupts.
2043 * Ensure that they get re-enabled when an interrupt happens.
2044 */
2045 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2046 intel_sdvo_enable_hotplug(intel_encoder);
2047 }
2048 else
2049 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2050 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2051 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2052
e27d8538 2053 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2054 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2055 intel_sdvo->is_hdmi = true;
14571b4c 2056 }
ea5b213a
CW		 2057 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2058 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2059
df0e9248 2060 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221
CW		 2061 if (intel_sdvo->is_hdmi)
2062 intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
14571b4c
ZW		 2063
2064 return true;
2065}
2066
2067static bool
ea5b213a 2068intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2069{
4ef69c7a
CW		 2070 struct drm_encoder *encoder = &intel_sdvo->base.base;
2071 struct drm_connector *connector;
2072 struct intel_connector *intel_connector;
2073 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2074
615fb93f
CW		 2075 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2076 if (!intel_sdvo_connector)
2077 return false;
14571b4c 2078
615fb93f 2079 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2080 connector = &intel_connector->base;
2081 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2082 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2083
4ef69c7a
CW		 2084 intel_sdvo->controlled_output |= type;
2085 intel_sdvo_connector->output_flag = type;
14571b4c 2086
4ef69c7a
CW		 2087 intel_sdvo->is_tv = true;
2088 intel_sdvo->base.needs_tv_clock = true;
2089 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2090
df0e9248 2091 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2092
4ef69c7a 2093 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2094 goto err;
14571b4c 2095
4ef69c7a 2096 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2097 goto err;
14571b4c 2098
4ef69c7a 2099 return true;
32aad86f
CW		 2100
2101err:
123d5c01 2102 intel_sdvo_destroy(connector);
32aad86f 2103 return false;
14571b4c
ZW		 2104}
2105
2106static bool
ea5b213a 2107intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2108{
4ef69c7a
CW		 2109 struct drm_encoder *encoder = &intel_sdvo->base.base;
2110 struct drm_connector *connector;
2111 struct intel_connector *intel_connector;
2112 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2113
615fb93f
CW		 2114 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2115 if (!intel_sdvo_connector)
2116 return false;
14571b4c 2117
615fb93f 2118 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2119 connector = &intel_connector->base;
eb1f8e4f 2120 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2121 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2122 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2123
2124 if (device == 0) {
2125 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2126 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2127 } else if (device == 1) {
2128 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2129 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2130 }
2131
2132 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
ea5b213a 2133 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2134
df0e9248
CW		 2135 intel_sdvo_connector_init(intel_sdvo_connector,
2136 intel_sdvo);
4ef69c7a 2137 return true;
14571b4c
ZW		 2138}
2139
2140static bool
ea5b213a 2141intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2142{
4ef69c7a
CW		 2143 struct drm_encoder *encoder = &intel_sdvo->base.base;
2144 struct drm_connector *connector;
2145 struct intel_connector *intel_connector;
2146 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2147
615fb93f
CW		 2148 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2149 if (!intel_sdvo_connector)
2150 return false;
14571b4c 2151
615fb93f
CW		 2152 intel_connector = &intel_sdvo_connector->base;
2153 connector = &intel_connector->base;
4ef69c7a
CW		 2154 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2155 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2156
2157 if (device == 0) {
2158 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2159 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2160 } else if (device == 1) {
2161 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2162 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2163 }
2164
2165 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
ea5b213a 2166 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2167
df0e9248 2168 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2169 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2170 goto err;
2171
2172 return true;
2173
2174err:
123d5c01 2175 intel_sdvo_destroy(connector);
32aad86f 2176 return false;
14571b4c
ZW		 2177}
2178
2179static bool
ea5b213a 2180intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2181{
ea5b213a
CW		 2182 intel_sdvo->is_tv = false;
2183 intel_sdvo->base.needs_tv_clock = false;
2184 intel_sdvo->is_lvds = false;
fb7a46f3 2185
14571b4c 2186 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2187
14571b4c 2188 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2189 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2190 return false;
2191
2192 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2193 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2194 return false;
2195
2196 /* TV has no XXX1 function block */
a1f4b7ff 2197 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2198 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2199 return false;
2200
2201 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2202 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2203 return false;
fb7a46f3 2204
a0b1c7a5
CW		 2205 if (flags & SDVO_OUTPUT_YPRPB0)
2206 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2207 return false;
2208
14571b4c 2209 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2210 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2211 return false;
2212
2213 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2214 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2215 return false;
2216
2217 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2218 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2219 return false;
2220
2221 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2222 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2223 return false;
fb7a46f3 2224
14571b4c 2225 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2226 unsigned char bytes[2];
2227
ea5b213a
CW		 2228 intel_sdvo->controlled_output = 0;
2229 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2230 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2231 SDVO_NAME(intel_sdvo),
51c8b407 2232 bytes[0], bytes[1]);
14571b4c 2233 return false;
fb7a46f3 2234 }
27f8227b 2235 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2236
14571b4c 2237 return true;
fb7a46f3 2238}
2239
32aad86f
CW		 2240static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2241 struct intel_sdvo_connector *intel_sdvo_connector,
2242 int type)
ce6feabd 2243{
4ef69c7a 2244 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2245 struct intel_sdvo_tv_format format;
2246 uint32_t format_map, i;
ce6feabd 2247
32aad86f
CW		 2248 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2249 return false;
ce6feabd 2250
1a3665c8 2251 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2252 if (!intel_sdvo_get_value(intel_sdvo,
2253 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2254 &format, sizeof(format)))
2255 return false;
ce6feabd 2256
32aad86f 2257 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2258
2259 if (format_map == 0)
32aad86f 2260 return false;
ce6feabd 2261
615fb93f 2262 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2263 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2264 if (format_map & (1 << i))
2265 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2266
2267
c5521706 2268 intel_sdvo_connector->tv_format =
32aad86f
CW		 2269 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2270 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2271 if (!intel_sdvo_connector->tv_format)
fcc8d672 2272 return false;
ce6feabd 2273
615fb93f 2274 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2275 drm_property_add_enum(
c5521706 2276 intel_sdvo_connector->tv_format, i,
40039750 2277 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2278
40039750 2279 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2280 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2281 intel_sdvo_connector->tv_format, 0);
32aad86f 2282 return true;
ce6feabd
ZY		 2283
2284}
2285
c5521706
CW		 2286#define ENHANCEMENT(name, NAME) do { \
2287 if (enhancements.name) { \
2288 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2289 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2290 return false; \
2291 intel_sdvo_connector->max_##name = data_value[0]; \
2292 intel_sdvo_connector->cur_##name = response; \
2293 intel_sdvo_connector->name = \
d9bc3c02 2294 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2295 if (!intel_sdvo_connector->name) return false; \
c5521706
CW		 2296 drm_connector_attach_property(connector, \
2297 intel_sdvo_connector->name, \
2298 intel_sdvo_connector->cur_##name); \
2299 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2300 data_value[0], data_value[1], response); \
2301 } \
0206e353 2302} while (0)
c5521706
CW		 2303
2304static bool
2305intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2306 struct intel_sdvo_connector *intel_sdvo_connector,
2307 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2308{
4ef69c7a 2309 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2310 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2311 uint16_t response, data_value[2];
2312
c5521706
CW		 2313 /* when horizontal overscan is supported, Add the left/right property */
2314 if (enhancements.overscan_h) {
2315 if (!intel_sdvo_get_value(intel_sdvo,
2316 SDVO_CMD_GET_MAX_OVERSCAN_H,
2317 &data_value, 4))
2318 return false;
32aad86f 2319
c5521706
CW		 2320 if (!intel_sdvo_get_value(intel_sdvo,
2321 SDVO_CMD_GET_OVERSCAN_H,
2322 &response, 2))
2323 return false;
fcc8d672 2324
c5521706
CW		 2325 intel_sdvo_connector->max_hscan = data_value[0];
2326 intel_sdvo_connector->left_margin = data_value[0] - response;
2327 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2328 intel_sdvo_connector->left =
d9bc3c02 2329 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2330 if (!intel_sdvo_connector->left)
2331 return false;
fcc8d672 2332
c5521706
CW		 2333 drm_connector_attach_property(connector,
2334 intel_sdvo_connector->left,
2335 intel_sdvo_connector->left_margin);
fcc8d672 2336
c5521706 2337 intel_sdvo_connector->right =
d9bc3c02 2338 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2339 if (!intel_sdvo_connector->right)
2340 return false;
32aad86f 2341
c5521706
CW		 2342 drm_connector_attach_property(connector,
2343 intel_sdvo_connector->right,
2344 intel_sdvo_connector->right_margin);
2345 DRM_DEBUG_KMS("h_overscan: max %d, "
2346 "default %d, current %d\n",
2347 data_value[0], data_value[1], response);
2348 }
32aad86f 2349
c5521706
CW		 2350 if (enhancements.overscan_v) {
2351 if (!intel_sdvo_get_value(intel_sdvo,
2352 SDVO_CMD_GET_MAX_OVERSCAN_V,
2353 &data_value, 4))
2354 return false;
fcc8d672 2355
c5521706
CW		 2356 if (!intel_sdvo_get_value(intel_sdvo,
2357 SDVO_CMD_GET_OVERSCAN_V,
2358 &response, 2))
2359 return false;
32aad86f 2360
c5521706
CW		 2361 intel_sdvo_connector->max_vscan = data_value[0];
2362 intel_sdvo_connector->top_margin = data_value[0] - response;
2363 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2364 intel_sdvo_connector->top =
d9bc3c02
SH		 2365 drm_property_create_range(dev, 0,
2366 "top_margin", 0, data_value[0]);
c5521706
CW		 2367 if (!intel_sdvo_connector->top)
2368 return false;
32aad86f 2369
c5521706
CW		 2370 drm_connector_attach_property(connector,
2371 intel_sdvo_connector->top,
2372 intel_sdvo_connector->top_margin);
fcc8d672 2373
c5521706 2374 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2375 drm_property_create_range(dev, 0,
2376 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2377 if (!intel_sdvo_connector->bottom)
2378 return false;
32aad86f 2379
c5521706
CW		 2380 drm_connector_attach_property(connector,
2381 intel_sdvo_connector->bottom,
2382 intel_sdvo_connector->bottom_margin);
2383 DRM_DEBUG_KMS("v_overscan: max %d, "
2384 "default %d, current %d\n",
2385 data_value[0], data_value[1], response);
2386 }
32aad86f 2387
c5521706
CW		 2388 ENHANCEMENT(hpos, HPOS);
2389 ENHANCEMENT(vpos, VPOS);
2390 ENHANCEMENT(saturation, SATURATION);
2391 ENHANCEMENT(contrast, CONTRAST);
2392 ENHANCEMENT(hue, HUE);
2393 ENHANCEMENT(sharpness, SHARPNESS);
2394 ENHANCEMENT(brightness, BRIGHTNESS);
2395 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2396 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2397 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2398 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2399 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2400
e044218a
CW		 2401 if (enhancements.dot_crawl) {
2402 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2403 return false;
2404
2405 intel_sdvo_connector->max_dot_crawl = 1;
2406 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2407 intel_sdvo_connector->dot_crawl =
d9bc3c02 2408 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2409 if (!intel_sdvo_connector->dot_crawl)
2410 return false;
2411
e044218a
CW		 2412 drm_connector_attach_property(connector,
2413 intel_sdvo_connector->dot_crawl,
2414 intel_sdvo_connector->cur_dot_crawl);
2415 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2416 }
2417
c5521706
CW		 2418 return true;
2419}
32aad86f 2420
c5521706
CW		 2421static bool
2422intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2423 struct intel_sdvo_connector *intel_sdvo_connector,
2424 struct intel_sdvo_enhancements_reply enhancements)
2425{
4ef69c7a 2426 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2427 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2428 uint16_t response, data_value[2];
32aad86f 2429
c5521706 2430 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2431
c5521706
CW		 2432 return true;
2433}
2434#undef ENHANCEMENT
32aad86f 2435
c5521706
CW		 2436static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2437 struct intel_sdvo_connector *intel_sdvo_connector)
2438{
2439 union {
2440 struct intel_sdvo_enhancements_reply reply;
2441 uint16_t response;
2442 } enhancements;
32aad86f 2443
1a3665c8
CW		 2444 BUILD_BUG_ON(sizeof(enhancements) != 2);
2445
cf9a2f3a
CW		 2446 enhancements.response = 0;
2447 intel_sdvo_get_value(intel_sdvo,
2448 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2449 &enhancements, sizeof(enhancements));
c5521706
CW		 2450 if (enhancements.response == 0) {
2451 DRM_DEBUG_KMS("No enhancement is supported\n");
2452 return true;
b9219c5e 2453 }
32aad86f 2454
c5521706
CW		 2455 if (IS_TV(intel_sdvo_connector))
2456 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2457 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2458 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2459 else
2460 return true;
e957d772
CW		 2461}
2462
2463static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2464 struct i2c_msg *msgs,
2465 int num)
2466{
2467 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2468
e957d772
CW		 2469 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2470 return -EIO;
2471
2472 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2473}
2474
2475static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2476{
2477 struct intel_sdvo *sdvo = adapter->algo_data;
2478 return sdvo->i2c->algo->functionality(sdvo->i2c);
2479}
2480
2481static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2482 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2483 .functionality = intel_sdvo_ddc_proxy_func
2484};
2485
2486static bool
2487intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2488 struct drm_device *dev)
2489{
2490 sdvo->ddc.owner = THIS_MODULE;
2491 sdvo->ddc.class = I2C_CLASS_DDC;
2492 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2493 sdvo->ddc.dev.parent = &dev->pdev->dev;
2494 sdvo->ddc.algo_data = sdvo;
2495 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2496
2497 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2498}
2499
eef4eacb 2500bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2501{
b01f2c3a 2502 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2503 struct intel_encoder *intel_encoder;
ea5b213a 2504 struct intel_sdvo *intel_sdvo;
79e53945 2505 int i;
79e53945 2506
ea5b213a
CW		 2507 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2508 if (!intel_sdvo)
7d57382e 2509 return false;
79e53945 2510
56184e3d 2511 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2512 intel_sdvo->is_sdvob = is_sdvob;
2513 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2514 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
e957d772
CW		 2515 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
2516 kfree(intel_sdvo);
2517 return false;
2518 }
2519
56184e3d 2520 /* encoder type will be decided later */
ea5b213a 2521 intel_encoder = &intel_sdvo->base;
21d40d37 2522 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2523 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2524
79e53945
JB		 2525 /* Read the regs to test if we can talk to the device */
2526 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2527 u8 byte;
2528
2529 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2530 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2531 SDVO_NAME(intel_sdvo));
f899fc64 2532 goto err;
79e53945
JB		 2533 }
2534 }
2535
eef4eacb 2536 if (intel_sdvo->is_sdvob)
b01f2c3a 2537 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
f899fc64 2538 else
b01f2c3a 2539 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
619ac3b7 2540
4ef69c7a 2541 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2542
af901ca1 2543 /* In default case sdvo lvds is false */
32aad86f 2544 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2545 goto err;
79e53945 2546
cc68c81a
SF		 2547 /* Set up hotplug command - note paranoia about contents of reply.
2548 * We assume that the hardware is in a sane state, and only touch
2549 * the bits we think we understand.
2550 */
2551 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
2552 &intel_sdvo->hotplug_active, 2);
2553 intel_sdvo->hotplug_active[0] &= ~0x3;
2554
ea5b213a
CW		 2555 if (intel_sdvo_output_setup(intel_sdvo,
2556 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 2557 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2558 SDVO_NAME(intel_sdvo));
f899fc64 2559 goto err;
79e53945
JB		 2560 }
2561
ea5b213a 2562 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2563
79e53945 2564 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2565 if (!intel_sdvo_set_target_input(intel_sdvo))
f899fc64 2566 goto err;
79e53945 2567
32aad86f
CW		 2568 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2569 &intel_sdvo->pixel_clock_min,
2570 &intel_sdvo->pixel_clock_max))
f899fc64 2571 goto err;
79e53945 2572
8a4c47f3 2573 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2574 "clock range %dMHz - %dMHz, "
2575 "input 1: %c, input 2: %c, "
2576 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2577 SDVO_NAME(intel_sdvo),
2578 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2579 intel_sdvo->caps.device_rev_id,
2580 intel_sdvo->pixel_clock_min / 1000,
2581 intel_sdvo->pixel_clock_max / 1000,
2582 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2583 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2584 /* check currently supported outputs */
ea5b213a 2585 intel_sdvo->caps.output_flags &
79e53945 2586 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2587 intel_sdvo->caps.output_flags &
79e53945 2588 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2589 return true;
79e53945 2590
f899fc64 2591err:
373a3cf7 2592 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2593 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2594 kfree(intel_sdvo);
79e53945 2595
7d57382e 2596 return false;
79e53945 2597}
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