]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/gpu/drm/i915/intel_sdvo.c
projects / mirror_ubuntu-zesty-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915/sdvo: Only create the analog encoder as required
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945
JB		 30#include <linux/delay.h>
31#include "drmP.h"
32#include "drm.h"
33#include "drm_crtc.h"
2b8d33f7 34#include "drm_edid.h"
ea5b213a 35#include "intel_drv.h"
79e53945
JB		 36#include "i915_drm.h"
37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0)
44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
46 SDVO_TV_MASK)
47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
49#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 50#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
14571b4c 51
79e53945 52
2e88e40b 53static const char *tv_format_names[] = {
ce6feabd
ZY		 54 "NTSC_M" , "NTSC_J" , "NTSC_443",
55 "PAL_B" , "PAL_D" , "PAL_G" ,
56 "PAL_H" , "PAL_I" , "PAL_M" ,
57 "PAL_N" , "PAL_NC" , "PAL_60" ,
58 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
59 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
60 "SECAM_60"
61};
62
63#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
64
ea5b213a
CW		 65struct intel_sdvo {
66 struct intel_encoder base;
67
f9c10a9b 68 u8 slave_addr;
e2f0ba97
JB		 69
70 /* Register for the SDVO device: SDVOB or SDVOC */
c751ce4f 71 int sdvo_reg;
79e53945 72
e2f0ba97
JB		 73 /* Active outputs controlled by this SDVO output */
74 uint16_t controlled_output;
79e53945 75
e2f0ba97
JB		 76 /*
77 * Capabilities of the SDVO device returned by
78 * i830_sdvo_get_capabilities()
79 */
79e53945 80 struct intel_sdvo_caps caps;
e2f0ba97
JB		 81
82 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 83 int pixel_clock_min, pixel_clock_max;
84
fb7a46f3 85 /*
86 * For multiple function SDVO device,
87 * this is for current attached outputs.
88 */
89 uint16_t attached_output;
90
e2f0ba97
JB		 91 /**
92 * This is set if we're going to treat the device as TV-out.
93 *
94 * While we have these nice friendly flags for output types that ought
95 * to decide this for us, the S-Video output on our HDMI+S-Video card
96 * shows up as RGB1 (VGA).
97 */
98 bool is_tv;
99
ce6feabd 100 /* This is for current tv format name */
40039750 101 int tv_format_index;
ce6feabd 102
e2f0ba97
JB		 103 /**
104 * This is set if we treat the device as HDMI, instead of DVI.
105 */
106 bool is_hdmi;
12682a97 107
7086c87f 108 /**
6c9547ff
CW		 109 * This is set if we detect output of sdvo device as LVDS and
110 * have a valid fixed mode to use with the panel.
7086c87f
ML		 111 */
112 bool is_lvds;
e2f0ba97 113
12682a97 114 /**
115 * This is sdvo fixed pannel mode pointer
116 */
117 struct drm_display_mode *sdvo_lvds_fixed_mode;
118
e2f0ba97
JB		 119 /*
120 * supported encoding mode, used to determine whether HDMI is
121 * supported
122 */
123 struct intel_sdvo_encode encode;
124
c751ce4f 125 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 126 uint8_t ddc_bus;
127
6c9547ff
CW		 128 /* Input timings for adjusted_mode */
129 struct intel_sdvo_dtd input_dtd;
14571b4c
ZW		 130};
131
132struct intel_sdvo_connector {
615fb93f
CW		 133 struct intel_connector base;
134
14571b4c
ZW		 135 /* Mark the type of connector */
136 uint16_t output_flag;
137
138 /* This contains all current supported TV format */
40039750 139 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 140 int format_supported_num;
c5521706 141 struct drm_property *tv_format;
14571b4c 142
b9219c5e 143 /* add the property for the SDVO-TV */
c5521706
CW		 144 struct drm_property *left;
145 struct drm_property *right;
146 struct drm_property *top;
147 struct drm_property *bottom;
148 struct drm_property *hpos;
149 struct drm_property *vpos;
150 struct drm_property *contrast;
151 struct drm_property *saturation;
152 struct drm_property *hue;
153 struct drm_property *sharpness;
154 struct drm_property *flicker_filter;
155 struct drm_property *flicker_filter_adaptive;
156 struct drm_property *flicker_filter_2d;
157 struct drm_property *tv_chroma_filter;
158 struct drm_property *tv_luma_filter;
e044218a 159 struct drm_property *dot_crawl;
b9219c5e
ZY		 160
161 /* add the property for the SDVO-TV/LVDS */
c5521706 162 struct drm_property *brightness;
b9219c5e
ZY		 163
164 /* Add variable to record current setting for the above property */
165 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 166
b9219c5e
ZY		 167 /* this is to get the range of margin.*/
168 u32 max_hscan, max_vscan;
169 u32 max_hpos, cur_hpos;
170 u32 max_vpos, cur_vpos;
171 u32 cur_brightness, max_brightness;
172 u32 cur_contrast, max_contrast;
173 u32 cur_saturation, max_saturation;
174 u32 cur_hue, max_hue;
c5521706
CW		 175 u32 cur_sharpness, max_sharpness;
176 u32 cur_flicker_filter, max_flicker_filter;
177 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
178 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
179 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
180 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 181 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 182};
183
890f3359 184static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 185{
4ef69c7a 186 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 187}
188
df0e9248
CW		 189static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
190{
191 return container_of(intel_attached_encoder(connector),
192 struct intel_sdvo, base);
193}
194
615fb93f
CW		 195static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
196{
197 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
198}
199
fb7a46f3 200static bool
ea5b213a 201intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 202static bool
203intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
204 struct intel_sdvo_connector *intel_sdvo_connector,
205 int type);
206static bool
207intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
208 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 209
79e53945
JB		 210/**
211 * Writes the SDVOB or SDVOC with the given value, but always writes both
212 * SDVOB and SDVOC to work around apparent hardware issues (according to
213 * comments in the BIOS).
214 */
ea5b213a 215static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 216{
4ef69c7a 217 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 218 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 219 u32 bval = val, cval = val;
220 int i;
221
ea5b213a
CW		 222 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
223 I915_WRITE(intel_sdvo->sdvo_reg, val);
224 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 225 return;
226 }
227
ea5b213a 228 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 229 cval = I915_READ(SDVOC);
230 } else {
231 bval = I915_READ(SDVOB);
232 }
233 /*
234 * Write the registers twice for luck. Sometimes,
235 * writing them only once doesn't appear to 'stick'.
236 * The BIOS does this too. Yay, magic
237 */
238 for (i = 0; i < 2; i++)
239 {
240 I915_WRITE(SDVOB, bval);
241 I915_READ(SDVOB);
242 I915_WRITE(SDVOC, cval);
243 I915_READ(SDVOC);
244 }
245}
246
32aad86f 247static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 248{
32aad86f 249 u8 out_buf[2] = { addr, 0 };
79e53945 250 u8 buf[2];
79e53945
JB		 251 struct i2c_msg msgs[] = {
252 {
ea5b213a 253 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 254 .flags = 0,
255 .len = 1,
256 .buf = out_buf,
257 },
258 {
ea5b213a 259 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 260 .flags = I2C_M_RD,
261 .len = 1,
262 .buf = buf,
263 }
264 };
32aad86f 265 int ret;
79e53945 266
ea5b213a 267 if ((ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 2)) == 2)
79e53945
JB		 268 {
269 *ch = buf[0];
270 return true;
271 }
272
8a4c47f3 273 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 274 return false;
275}
276
32aad86f 277static bool intel_sdvo_write_byte(struct intel_sdvo *intel_sdvo, int addr, u8 ch)
79e53945 278{
32aad86f 279 u8 out_buf[2] = { addr, ch };
79e53945
JB		 280 struct i2c_msg msgs[] = {
281 {
ea5b213a 282 .addr = intel_sdvo->slave_addr >> 1,
79e53945
JB		 283 .flags = 0,
284 .len = 2,
285 .buf = out_buf,
286 }
287 };
288
32aad86f 289 return i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 1) == 1;
79e53945
JB		 290}
291
292#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
293/** Mapping of command numbers to names, for debug output */
005568be 294static const struct _sdvo_cmd_name {
e2f0ba97 295 u8 cmd;
2e88e40b 296 const char *name;
79e53945
JB		 297} sdvo_cmd_names[] = {
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
e2f0ba97
JB		 333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
79e53945 337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
e2f0ba97
JB		 338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
c5521706 341
b9219c5e 342 /* Add the op code for SDVO enhancements */
c5521706
CW		 343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
b9219c5e
ZY		 349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
c5521706
CW		 367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
387
e2f0ba97
JB		 388 /* HDMI op code */
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
407 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
408 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 409};
410
461ed3ca 411#define IS_SDVOB(reg) (reg == SDVOB || reg == PCH_SDVOB)
ea5b213a 412#define SDVO_NAME(svdo) (IS_SDVOB((svdo)->sdvo_reg) ? "SDVOB" : "SDVOC")
79e53945 413
ea5b213a 414static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 415 const void *args, int args_len)
79e53945 416{
79e53945
JB		 417 int i;
418
8a4c47f3 419 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 420 SDVO_NAME(intel_sdvo), cmd);
79e53945 421 for (i = 0; i < args_len; i++)
342dc382 422 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 423 for (; i < 8; i++)
342dc382 424 DRM_LOG_KMS(" ");
04ad327f 425 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 426 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 427 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 428 break;
429 }
430 }
04ad327f 431 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 432 DRM_LOG_KMS("(%02X)", cmd);
433 DRM_LOG_KMS("\n");
79e53945 434}
79e53945 435
32aad86f
CW		 436static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
437 const void *args, int args_len)
79e53945
JB		 438{
439 int i;
440
ea5b213a 441 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 442
443 for (i = 0; i < args_len; i++) {
32aad86f
CW		 444 if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0 - i,
445 ((u8*)args)[i]))
446 return false;
79e53945
JB		 447 }
448
32aad86f 449 return intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_OPCODE, cmd);
79e53945
JB		 450}
451
79e53945
JB		 452static const char *cmd_status_names[] = {
453 "Power on",
454 "Success",
455 "Not supported",
456 "Invalid arg",
457 "Pending",
458 "Target not specified",
459 "Scaling not supported"
460};
461
b5c616a7
CW		 462static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
463 void *response, int response_len)
79e53945 464{
b5c616a7
CW		 465 u8 retry = 5;
466 u8 status;
33b52961 467 int i;
79e53945 468
b5c616a7
CW		 469 /*
470 * The documentation states that all commands will be
471 * processed within 15µs, and that we need only poll
472 * the status byte a maximum of 3 times in order for the
473 * command to be complete.
474 *
475 * Check 5 times in case the hardware failed to read the docs.
476 */
477 do {
478 if (!intel_sdvo_read_byte(intel_sdvo,
479 SDVO_I2C_CMD_STATUS,
480 &status))
481 return false;
482 } while (status == SDVO_CMD_STATUS_PENDING && --retry);
483
ea5b213a 484 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
79e53945 485 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 486 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 487 else
342dc382 488 DRM_LOG_KMS("(??? %d)", status);
79e53945 489
b5c616a7
CW		 490 if (status != SDVO_CMD_STATUS_SUCCESS)
491 goto log_fail;
79e53945 492
b5c616a7
CW		 493 /* Read the command response */
494 for (i = 0; i < response_len; i++) {
495 if (!intel_sdvo_read_byte(intel_sdvo,
496 SDVO_I2C_RETURN_0 + i,
497 &((u8 *)response)[i]))
498 goto log_fail;
499 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
500 }
79e53945 501
b5c616a7
CW		 502 for (; i < 8; i++)
503 DRM_LOG_KMS(" ");
504 DRM_LOG_KMS("\n");
79e53945 505
b5c616a7 506 return true;
79e53945 507
b5c616a7
CW		 508log_fail:
509 DRM_LOG_KMS("\n");
510 return false;
79e53945
JB		 511}
512
b358d0a6 513static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 514{
515 if (mode->clock >= 100000)
516 return 1;
517 else if (mode->clock >= 50000)
518 return 2;
519 else
520 return 4;
521}
522
523/**
6a304caf
ZY		 524 * Try to read the response after issuie the DDC switch command. But it
525 * is noted that we must do the action of reading response and issuing DDC
526 * switch command in one I2C transaction. Otherwise when we try to start
527 * another I2C transaction after issuing the DDC bus switch, it will be
528 * switched to the internal SDVO register.
79e53945 529 */
819f3fb7
CW		 530static int intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
531 u8 target)
79e53945 532{
6a304caf
ZY		 533 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
534 struct i2c_msg msgs[] = {
535 {
ea5b213a 536 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 537 .flags = 0,
538 .len = 2,
539 .buf = out_buf,
540 },
541 /* the following two are to read the response */
542 {
ea5b213a 543 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 544 .flags = 0,
545 .len = 1,
546 .buf = cmd_buf,
547 },
548 {
ea5b213a 549 .addr = intel_sdvo->slave_addr >> 1,
6a304caf
ZY		 550 .flags = I2C_M_RD,
551 .len = 1,
552 .buf = ret_value,
553 },
554 };
555
ea5b213a 556 intel_sdvo_debug_write(intel_sdvo, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
819f3fb7 557 &target, 1);
6a304caf 558 /* write the DDC switch command argument */
819f3fb7
CW		 559 if (!intel_sdvo_write_byte(intel_sdvo, SDVO_I2C_ARG_0, target))
560 return -EIO;
6a304caf
ZY		 561
562 out_buf[0] = SDVO_I2C_OPCODE;
563 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
564 cmd_buf[0] = SDVO_I2C_CMD_STATUS;
565 cmd_buf[1] = 0;
566 ret_value[0] = 0;
567 ret_value[1] = 0;
568
ea5b213a 569 ret = i2c_transfer(intel_sdvo->base.i2c_bus, msgs, 3);
819f3fb7
CW		 570 if (ret < 0)
571 return ret;
6a304caf
ZY		 572 if (ret != 3) {
573 /* failure in I2C transfer */
574 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
819f3fb7 575 return -EIO;
6a304caf
ZY		 576 }
577 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
578 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
819f3fb7
CW		 579 ret_value[0]);
580 return -EIO;
6a304caf 581 }
819f3fb7
CW		 582
583 return 0;
79e53945
JB		 584}
585
32aad86f 586static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 587{
32aad86f
CW		 588 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
589 return false;
79e53945 590
32aad86f
CW		 591 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
592}
79e53945 593
32aad86f
CW		 594static bool
595intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
596{
597 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
598 return false;
79e53945 599
32aad86f
CW		 600 return intel_sdvo_read_response(intel_sdvo, value, len);
601}
79e53945 602
32aad86f
CW		 603static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
604{
605 struct intel_sdvo_set_target_input_args targets = {0};
606 return intel_sdvo_set_value(intel_sdvo,
607 SDVO_CMD_SET_TARGET_INPUT,
608 &targets, sizeof(targets));
79e53945
JB		 609}
610
611/**
612 * Return whether each input is trained.
613 *
614 * This function is making an assumption about the layout of the response,
615 * which should be checked against the docs.
616 */
ea5b213a 617static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 618{
619 struct intel_sdvo_get_trained_inputs_response response;
79e53945 620
32aad86f
CW		 621 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
622 &response, sizeof(response)))
79e53945
JB		 623 return false;
624
625 *input_1 = response.input0_trained;
626 *input_2 = response.input1_trained;
627 return true;
628}
629
ea5b213a 630static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 631 u16 outputs)
632{
32aad86f
CW		 633 return intel_sdvo_set_value(intel_sdvo,
634 SDVO_CMD_SET_ACTIVE_OUTPUTS,
635 &outputs, sizeof(outputs));
79e53945
JB		 636}
637
ea5b213a 638static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 639 int mode)
640{
32aad86f 641 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 642
643 switch (mode) {
644 case DRM_MODE_DPMS_ON:
645 state = SDVO_ENCODER_STATE_ON;
646 break;
647 case DRM_MODE_DPMS_STANDBY:
648 state = SDVO_ENCODER_STATE_STANDBY;
649 break;
650 case DRM_MODE_DPMS_SUSPEND:
651 state = SDVO_ENCODER_STATE_SUSPEND;
652 break;
653 case DRM_MODE_DPMS_OFF:
654 state = SDVO_ENCODER_STATE_OFF;
655 break;
656 }
657
32aad86f
CW		 658 return intel_sdvo_set_value(intel_sdvo,
659 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 660}
661
ea5b213a 662static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 663 int *clock_min,
664 int *clock_max)
665{
666 struct intel_sdvo_pixel_clock_range clocks;
79e53945 667
32aad86f
CW		 668 if (!intel_sdvo_get_value(intel_sdvo,
669 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
670 &clocks, sizeof(clocks)))
79e53945
JB		 671 return false;
672
673 /* Convert the values from units of 10 kHz to kHz. */
674 *clock_min = clocks.min * 10;
675 *clock_max = clocks.max * 10;
79e53945
JB		 676 return true;
677}
678
ea5b213a 679static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 680 u16 outputs)
681{
32aad86f
CW		 682 return intel_sdvo_set_value(intel_sdvo,
683 SDVO_CMD_SET_TARGET_OUTPUT,
684 &outputs, sizeof(outputs));
79e53945
JB		 685}
686
ea5b213a 687static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 688 struct intel_sdvo_dtd *dtd)
689{
32aad86f
CW		 690 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
691 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 692}
693
ea5b213a 694static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 695 struct intel_sdvo_dtd *dtd)
696{
ea5b213a 697 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 698 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
699}
700
ea5b213a 701static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 702 struct intel_sdvo_dtd *dtd)
703{
ea5b213a 704 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 705 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
706}
707
e2f0ba97 708static bool
ea5b213a 709intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 710 uint16_t clock,
711 uint16_t width,
712 uint16_t height)
713{
714 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 715
e642c6f1 716 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 717 args.clock = clock;
718 args.width = width;
719 args.height = height;
e642c6f1 720 args.interlace = 0;
12682a97 721
ea5b213a
CW		 722 if (intel_sdvo->is_lvds &&
723 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
724 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 725 args.scaled = 1;
726
32aad86f
CW		 727 return intel_sdvo_set_value(intel_sdvo,
728 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
729 &args, sizeof(args));
e2f0ba97
JB		 730}
731
ea5b213a 732static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 733 struct intel_sdvo_dtd *dtd)
734{
32aad86f
CW		 735 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
736 &dtd->part1, sizeof(dtd->part1)) &&
737 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
738 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 739}
79e53945 740
ea5b213a 741static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 742{
32aad86f 743 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 744}
745
e2f0ba97 746static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 747 const struct drm_display_mode *mode)
79e53945 748{
e2f0ba97
JB		 749 uint16_t width, height;
750 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
751 uint16_t h_sync_offset, v_sync_offset;
79e53945
JB		 752
753 width = mode->crtc_hdisplay;
754 height = mode->crtc_vdisplay;
755
756 /* do some mode translations */
757 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
758 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
759
760 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
761 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
762
763 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
764 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
765
e2f0ba97
JB		 766 dtd->part1.clock = mode->clock / 10;
767 dtd->part1.h_active = width & 0xff;
768 dtd->part1.h_blank = h_blank_len & 0xff;
769 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 770 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 771 dtd->part1.v_active = height & 0xff;
772 dtd->part1.v_blank = v_blank_len & 0xff;
773 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 774 ((v_blank_len >> 8) & 0xf);
775
171a9e96 776 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 777 dtd->part2.h_sync_width = h_sync_len & 0xff;
778 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 779 (v_sync_len & 0xf);
e2f0ba97 780 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 781 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
782 ((v_sync_len & 0x30) >> 4);
783
e2f0ba97 784 dtd->part2.dtd_flags = 0x18;
79e53945 785 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 786 dtd->part2.dtd_flags |= 0x2;
79e53945 787 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 788 dtd->part2.dtd_flags |= 0x4;
789
790 dtd->part2.sdvo_flags = 0;
791 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
792 dtd->part2.reserved = 0;
793}
794
795static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 796 const struct intel_sdvo_dtd *dtd)
e2f0ba97 797{
e2f0ba97
JB		 798 mode->hdisplay = dtd->part1.h_active;
799 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
800 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 801 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 802 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
803 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
804 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
805 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
806
807 mode->vdisplay = dtd->part1.v_active;
808 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
809 mode->vsync_start = mode->vdisplay;
810 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 811 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 812 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
813 mode->vsync_end = mode->vsync_start +
814 (dtd->part2.v_sync_off_width & 0xf);
815 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
816 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
817 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
818
819 mode->clock = dtd->part1.clock * 10;
820
171a9e96 821 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 822 if (dtd->part2.dtd_flags & 0x2)
823 mode->flags |= DRM_MODE_FLAG_PHSYNC;
824 if (dtd->part2.dtd_flags & 0x4)
825 mode->flags |= DRM_MODE_FLAG_PVSYNC;
826}
827
ea5b213a 828static bool intel_sdvo_get_supp_encode(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 829 struct intel_sdvo_encode *encode)
830{
32aad86f
CW		 831 if (intel_sdvo_get_value(intel_sdvo,
832 SDVO_CMD_GET_SUPP_ENCODE,
833 encode, sizeof(*encode)))
834 return true;
e2f0ba97 835
32aad86f
CW		 836 /* non-support means DVI */
837 memset(encode, 0, sizeof(*encode));
838 return false;
e2f0ba97
JB		 839}
840
ea5b213a 841static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 842 uint8_t mode)
e2f0ba97 843{
32aad86f 844 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 845}
846
ea5b213a 847static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 848 uint8_t mode)
849{
32aad86f 850 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 851}
852
853#if 0
ea5b213a 854static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 855{
856 int i, j;
857 uint8_t set_buf_index[2];
858 uint8_t av_split;
859 uint8_t buf_size;
860 uint8_t buf[48];
861 uint8_t *pos;
862
32aad86f 863 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 864
865 for (i = 0; i <= av_split; i++) {
866 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 867 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 868 set_buf_index, 2);
c751ce4f
EA		 869 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
870 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 871
872 pos = buf;
873 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 874 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 875 NULL, 0);
c751ce4f 876 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 877 pos += 8;
878 }
879 }
880}
881#endif
882
32aad86f 883static bool intel_sdvo_set_hdmi_buf(struct intel_sdvo *intel_sdvo,
c751ce4f
EA		 884 int index,
885 uint8_t *data, int8_t size, uint8_t tx_rate)
e2f0ba97
JB		 886{
887 uint8_t set_buf_index[2];
888
889 set_buf_index[0] = index;
890 set_buf_index[1] = 0;
891
32aad86f
CW		 892 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_INDEX,
893 set_buf_index, 2))
894 return false;
e2f0ba97
JB		 895
896 for (; size > 0; size -= 8) {
32aad86f
CW		 897 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_DATA, data, 8))
898 return false;
899
e2f0ba97
JB		 900 data += 8;
901 }
902
32aad86f 903 return intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
e2f0ba97
JB		 904}
905
906static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
907{
908 uint8_t csum = 0;
909 int i;
910
911 for (i = 0; i < size; i++)
912 csum += data[i];
913
914 return 0x100 - csum;
915}
916
917#define DIP_TYPE_AVI 0x82
918#define DIP_VERSION_AVI 0x2
919#define DIP_LEN_AVI 13
920
921struct dip_infoframe {
922 uint8_t type;
923 uint8_t version;
924 uint8_t len;
925 uint8_t checksum;
926 union {
927 struct {
928 /* Packet Byte #1 */
929 uint8_t S:2;
930 uint8_t B:2;
931 uint8_t A:1;
932 uint8_t Y:2;
933 uint8_t rsvd1:1;
934 /* Packet Byte #2 */
935 uint8_t R:4;
936 uint8_t M:2;
937 uint8_t C:2;
938 /* Packet Byte #3 */
939 uint8_t SC:2;
940 uint8_t Q:2;
941 uint8_t EC:3;
942 uint8_t ITC:1;
943 /* Packet Byte #4 */
944 uint8_t VIC:7;
945 uint8_t rsvd2:1;
946 /* Packet Byte #5 */
947 uint8_t PR:4;
948 uint8_t rsvd3:4;
949 /* Packet Byte #6~13 */
950 uint16_t top_bar_end;
951 uint16_t bottom_bar_start;
952 uint16_t left_bar_end;
953 uint16_t right_bar_start;
954 } avi;
955 struct {
956 /* Packet Byte #1 */
957 uint8_t channel_count:3;
958 uint8_t rsvd1:1;
959 uint8_t coding_type:4;
960 /* Packet Byte #2 */
961 uint8_t sample_size:2; /* SS0, SS1 */
962 uint8_t sample_frequency:3;
963 uint8_t rsvd2:3;
964 /* Packet Byte #3 */
965 uint8_t coding_type_private:5;
966 uint8_t rsvd3:3;
967 /* Packet Byte #4 */
968 uint8_t channel_allocation;
969 /* Packet Byte #5 */
970 uint8_t rsvd4:3;
971 uint8_t level_shift:4;
972 uint8_t downmix_inhibit:1;
973 } audio;
974 uint8_t payload[28];
975 } __attribute__ ((packed)) u;
976} __attribute__((packed));
977
32aad86f 978static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 979 struct drm_display_mode * mode)
980{
981 struct dip_infoframe avi_if = {
982 .type = DIP_TYPE_AVI,
983 .version = DIP_VERSION_AVI,
984 .len = DIP_LEN_AVI,
985 };
986
987 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
988 4 + avi_if.len);
32aad86f
CW		 989 return intel_sdvo_set_hdmi_buf(intel_sdvo, 1, (uint8_t *)&avi_if,
990 4 + avi_if.len,
991 SDVO_HBUF_TX_VSYNC);
e2f0ba97
JB		 992}
993
32aad86f 994static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 995{
ce6feabd 996 struct intel_sdvo_tv_format format;
40039750 997 uint32_t format_map;
ce6feabd 998
40039750 999 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1000 memset(&format, 0, sizeof(format));
32aad86f 1001 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1002
32aad86f
CW		 1003 BUILD_BUG_ON(sizeof(format) != 6);
1004 return intel_sdvo_set_value(intel_sdvo,
1005 SDVO_CMD_SET_TV_FORMAT,
1006 &format, sizeof(format));
7026d4ac
ZW		 1007}
1008
32aad86f
CW		 1009static bool
1010intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
1011 struct drm_display_mode *mode)
e2f0ba97 1012{
32aad86f 1013 struct intel_sdvo_dtd output_dtd;
79e53945 1014
32aad86f
CW		 1015 if (!intel_sdvo_set_target_output(intel_sdvo,
1016 intel_sdvo->attached_output))
1017 return false;
e2f0ba97 1018
32aad86f
CW		 1019 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1020 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1021 return false;
e2f0ba97 1022
32aad86f
CW		 1023 return true;
1024}
1025
1026static bool
1027intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
1028 struct drm_display_mode *mode,
1029 struct drm_display_mode *adjusted_mode)
1030{
32aad86f
CW		 1031 /* Reset the input timing to the screen. Assume always input 0. */
1032 if (!intel_sdvo_set_target_input(intel_sdvo))
1033 return false;
e2f0ba97 1034
32aad86f
CW		 1035 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1036 mode->clock / 10,
1037 mode->hdisplay,
1038 mode->vdisplay))
1039 return false;
e2f0ba97 1040
32aad86f 1041 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
6c9547ff 1042 &intel_sdvo->input_dtd))
32aad86f 1043 return false;
e2f0ba97 1044
6c9547ff 1045 intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
79e53945 1046
32aad86f 1047 drm_mode_set_crtcinfo(adjusted_mode, 0);
32aad86f
CW		 1048 return true;
1049}
12682a97 1050
32aad86f
CW		 1051static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1052 struct drm_display_mode *mode,
1053 struct drm_display_mode *adjusted_mode)
1054{
890f3359 1055 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1056 int multiplier;
12682a97 1057
32aad86f
CW		 1058 /* We need to construct preferred input timings based on our
1059 * output timings. To do that, we have to set the output
1060 * timings, even though this isn't really the right place in
1061 * the sequence to do it. Oh well.
1062 */
1063 if (intel_sdvo->is_tv) {
1064 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1065 return false;
12682a97 1066
c74696b9
PR		 1067 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1068 mode,
1069 adjusted_mode);
ea5b213a 1070 } else if (intel_sdvo->is_lvds) {
32aad86f 1071 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1072 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1073 return false;
12682a97 1074
c74696b9
PR		 1075 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1076 mode,
1077 adjusted_mode);
e2f0ba97 1078 }
32aad86f
CW		 1079
1080 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1081 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1082 */
6c9547ff
CW		 1083 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
1084 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 1085
e2f0ba97
JB		 1086 return true;
1087}
1088
1089static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1090 struct drm_display_mode *mode,
1091 struct drm_display_mode *adjusted_mode)
1092{
1093 struct drm_device *dev = encoder->dev;
1094 struct drm_i915_private *dev_priv = dev->dev_private;
1095 struct drm_crtc *crtc = encoder->crtc;
1096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 1097 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1098 u32 sdvox;
e2f0ba97
JB		 1099 struct intel_sdvo_in_out_map in_out;
1100 struct intel_sdvo_dtd input_dtd;
6c9547ff
CW		 1101 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1102 int rate;
e2f0ba97
JB		 1103
1104 if (!mode)
1105 return;
1106
1107 /* First, set the input mapping for the first input to our controlled
1108 * output. This is only correct if we're a single-input device, in
1109 * which case the first input is the output from the appropriate SDVO
1110 * channel on the motherboard. In a two-input device, the first input
1111 * will be SDVOB and the second SDVOC.
1112 */
ea5b213a 1113 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1114 in_out.in1 = 0;
1115
c74696b9
PR		 1116 intel_sdvo_set_value(intel_sdvo,
1117 SDVO_CMD_SET_IN_OUT_MAP,
1118 &in_out, sizeof(in_out));
e2f0ba97 1119
6c9547ff
CW		 1120 /* Set the output timings to the screen */
1121 if (!intel_sdvo_set_target_output(intel_sdvo,
1122 intel_sdvo->attached_output))
1123 return;
e2f0ba97 1124
7026d4ac 1125 /* We have tried to get input timing in mode_fixup, and filled into
6c9547ff 1126 * adjusted_mode.
e2f0ba97 1127 */
6c9547ff
CW		 1128 if (intel_sdvo->is_tv || intel_sdvo->is_lvds) {
1129 input_dtd = intel_sdvo->input_dtd;
1130 } else {
e2f0ba97 1131 /* Set the output timing to the screen */
32aad86f
CW		 1132 if (!intel_sdvo_set_target_output(intel_sdvo,
1133 intel_sdvo->attached_output))
1134 return;
1135
6c9547ff 1136 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c74696b9 1137 (void) intel_sdvo_set_output_timing(intel_sdvo, &input_dtd);
e2f0ba97 1138 }
79e53945
JB		 1139
1140 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1141 if (!intel_sdvo_set_target_input(intel_sdvo))
1142 return;
79e53945 1143
6c9547ff
CW		 1144 if (intel_sdvo->is_hdmi &&
1145 !intel_sdvo_set_avi_infoframe(intel_sdvo, mode))
1146 return;
7026d4ac 1147
6c9547ff
CW		 1148 if (intel_sdvo->is_tv &&
1149 !intel_sdvo_set_tv_format(intel_sdvo))
1150 return;
e2f0ba97 1151
c74696b9 1152 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
79e53945 1153
6c9547ff
CW		 1154 switch (pixel_multiplier) {
1155 default:
32aad86f
CW		 1156 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1157 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1158 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1159 }
32aad86f
CW		 1160 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1161 return;
79e53945
JB		 1162
1163 /* Set the SDVO control regs. */
e2f0ba97 1164 if (IS_I965G(dev)) {
6c9547ff 1165 sdvox = SDVO_BORDER_ENABLE;
81a14b46
AJ		 1166 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1167 sdvox |= SDVO_VSYNC_ACTIVE_HIGH;
1168 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1169 sdvox |= SDVO_HSYNC_ACTIVE_HIGH;
e2f0ba97 1170 } else {
6c9547ff 1171 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1172 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1173 case SDVOB:
1174 sdvox &= SDVOB_PRESERVE_MASK;
1175 break;
1176 case SDVOC:
1177 sdvox &= SDVOC_PRESERVE_MASK;
1178 break;
1179 }
1180 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1181 }
79e53945
JB		 1182 if (intel_crtc->pipe == 1)
1183 sdvox |= SDVO_PIPE_B_SELECT;
6c9547ff
CW		 1184 if (intel_sdvo->is_hdmi)
1185 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1186
79e53945 1187 if (IS_I965G(dev)) {
e2f0ba97
JB		 1188 /* done in crtc_mode_set as the dpll_md reg must be written early */
1189 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1190 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1191 } else {
6c9547ff 1192 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1193 }
1194
6c9547ff 1195 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL)
12682a97 1196 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1197 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1198}
1199
1200static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1201{
1202 struct drm_device *dev = encoder->dev;
1203 struct drm_i915_private *dev_priv = dev->dev_private;
890f3359 1204 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
9d0498a2 1205 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1206 u32 temp;
1207
1208 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1209 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1210 if (0)
ea5b213a 1211 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1212
1213 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1214 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1215 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1216 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1217 }
1218 }
1219 } else {
1220 bool input1, input2;
1221 int i;
1222 u8 status;
1223
ea5b213a 1224 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1225 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1226 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1227 for (i = 0; i < 2; i++)
9d0498a2 1228 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1229
32aad86f 1230 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1231 /* Warn if the device reported failure to sync.
1232 * A lot of SDVO devices fail to notify of sync, but it's
1233 * a given it the status is a success, we succeeded.
1234 */
1235 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1236 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1237 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1238 }
1239
1240 if (0)
ea5b213a
CW		 1241 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1242 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1243 }
1244 return;
1245}
1246
79e53945
JB		 1247static int intel_sdvo_mode_valid(struct drm_connector *connector,
1248 struct drm_display_mode *mode)
1249{
df0e9248 1250 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1251
1252 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1253 return MODE_NO_DBLESCAN;
1254
ea5b213a 1255 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1256 return MODE_CLOCK_LOW;
1257
ea5b213a 1258 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1259 return MODE_CLOCK_HIGH;
1260
8545423a 1261 if (intel_sdvo->is_lvds) {
ea5b213a 1262 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1263 return MODE_PANEL;
1264
ea5b213a 1265 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1266 return MODE_PANEL;
1267 }
1268
79e53945
JB		 1269 return MODE_OK;
1270}
1271
ea5b213a 1272static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1273{
32aad86f 1274 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DEVICE_CAPS, caps, sizeof(*caps));
79e53945
JB		 1275}
1276
d2a82a6f
ZW		 1277/* No use! */
1278#if 0
79e53945
JB		 1279struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1280{
1281 struct drm_connector *connector = NULL;
ea5b213a
CW		 1282 struct intel_sdvo *iout = NULL;
1283 struct intel_sdvo *sdvo;
79e53945
JB		 1284
1285 /* find the sdvo connector */
1286 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
ea5b213a 1287 iout = to_intel_sdvo(connector);
79e53945
JB		 1288
1289 if (iout->type != INTEL_OUTPUT_SDVO)
1290 continue;
1291
1292 sdvo = iout->dev_priv;
1293
c751ce4f 1294 if (sdvo->sdvo_reg == SDVOB && sdvoB)
79e53945
JB		 1295 return connector;
1296
c751ce4f 1297 if (sdvo->sdvo_reg == SDVOC && !sdvoB)
79e53945
JB		 1298 return connector;
1299
1300 }
1301
1302 return NULL;
1303}
1304
1305int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1306{
1307 u8 response[2];
1308 u8 status;
ea5b213a 1309 struct intel_sdvo *intel_sdvo;
8a4c47f3 1310 DRM_DEBUG_KMS("\n");
79e53945
JB		 1311
1312 if (!connector)
1313 return 0;
1314
ea5b213a 1315 intel_sdvo = to_intel_sdvo(connector);
79e53945 1316
32aad86f
CW		 1317 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1318 &response, 2) && response[0];
79e53945
JB		 1319}
1320
1321void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1322{
1323 u8 response[2];
1324 u8 status;
ea5b213a 1325 struct intel_sdvo *intel_sdvo = to_intel_sdvo(connector);
79e53945 1326
ea5b213a
CW		 1327 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1328 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945
JB		 1329
1330 if (on) {
ea5b213a
CW		 1331 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1332 status = intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1333
ea5b213a 1334 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1335 } else {
1336 response[0] = 0;
1337 response[1] = 0;
ea5b213a 1338 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
79e53945
JB		 1339 }
1340
ea5b213a
CW		 1341 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1342 intel_sdvo_read_response(intel_sdvo, &response, 2);
79e53945 1343}
d2a82a6f 1344#endif
79e53945 1345
fb7a46f3 1346static bool
ea5b213a 1347intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1348{
fb7a46f3 1349 int caps = 0;
1350
ea5b213a 1351 if (intel_sdvo->caps.output_flags &
fb7a46f3 1352 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1353 caps++;
ea5b213a 1354 if (intel_sdvo->caps.output_flags &
fb7a46f3 1355 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1356 caps++;
ea5b213a 1357 if (intel_sdvo->caps.output_flags &
19e1f888 1358 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
fb7a46f3 1359 caps++;
ea5b213a 1360 if (intel_sdvo->caps.output_flags &
fb7a46f3 1361 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1362 caps++;
ea5b213a 1363 if (intel_sdvo->caps.output_flags &
fb7a46f3 1364 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1365 caps++;
1366
ea5b213a 1367 if (intel_sdvo->caps.output_flags &
fb7a46f3 1368 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1369 caps++;
1370
ea5b213a 1371 if (intel_sdvo->caps.output_flags &
fb7a46f3 1372 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1373 caps++;
1374
1375 return (caps > 1);
1376}
1377
57cdaf90
KP		 1378static struct drm_connector *
1379intel_find_analog_connector(struct drm_device *dev)
1380{
1381 struct drm_connector *connector;
df0e9248
CW		 1382 struct intel_sdvo *encoder;
1383
1384 list_for_each_entry(encoder,
1385 &dev->mode_config.encoder_list,
1386 base.base.head) {
1387 if (encoder->base.type == INTEL_OUTPUT_ANALOG) {
1388 list_for_each_entry(connector,
1389 &dev->mode_config.connector_list,
1390 head) {
1391 if (&encoder->base ==
1392 intel_attached_encoder(connector))
d2a82a6f
ZW		 1393 return connector;
1394 }
1395 }
57cdaf90 1396 }
df0e9248 1397
57cdaf90
KP		 1398 return NULL;
1399}
1400
1401static int
1402intel_analog_is_connected(struct drm_device *dev)
1403{
1404 struct drm_connector *analog_connector;
57cdaf90 1405
32aad86f 1406 analog_connector = intel_find_analog_connector(dev);
57cdaf90
KP		 1407 if (!analog_connector)
1408 return false;
1409
1410 if (analog_connector->funcs->detect(analog_connector) ==
1411 connector_status_disconnected)
1412 return false;
1413
1414 return true;
1415}
1416
ff482d83
CW		 1417/* Mac mini hack -- use the same DDC as the analog connector */
1418static struct edid *
1419intel_sdvo_get_analog_edid(struct drm_connector *connector)
1420{
1421 struct intel_encoder *encoder = intel_attached_encoder(connector);
1422 struct drm_device *dev = connector->dev;
1423 struct i2c_adapter *ddc;
1424 struct edid *edid;
1425 u32 ddc_reg;
1426
1427 if (!intel_analog_is_connected(dev))
1428 return NULL;
1429
1430 if (HAS_PCH_SPLIT(dev))
1431 ddc_reg = PCH_GPIOA;
1432 else
1433 ddc_reg = GPIOA;
1434
1435 ddc = intel_i2c_create(encoder, ddc_reg, "SDVO/VGA DDC BUS");
1436 if (ddc == NULL)
1437 return NULL;
1438
1439 edid = drm_get_edid(connector, ddc);
1440 intel_i2c_destroy(ddc);
1441
1442 return edid;
1443}
1444
2b8d33f7 1445enum drm_connector_status
149c36a3 1446intel_sdvo_hdmi_sink_detect(struct drm_connector *connector)
9dff6af8 1447{
df0e9248 1448 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1449 enum drm_connector_status status;
1450 struct edid *edid;
9dff6af8 1451
ea5b213a 1452 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
57cdaf90 1453
ea5b213a 1454 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
9d1a903d
CW		 1455 u8 saved_ddc = intel_sdvo->ddc_bus, ddc;
1456
7c3f0a27
ZY		 1457 /*
1458 * Don't use the 1 as the argument of DDC bus switch to get
1459 * the EDID. It is used for SDVO SPD ROM.
1460 */
9d1a903d
CW		 1461 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
1462 intel_sdvo->ddc_bus = ddc;
ea5b213a 1463 edid = drm_get_edid(connector, intel_sdvo->base.ddc_bus);
9d1a903d 1464 if (edid)
7c3f0a27 1465 break;
7c3f0a27 1466 }
9d1a903d
CW		 1467
1468 /*
1469 * If we found the EDID on the other bus, maybe that is the
1470 * correct DDC bus.
1471 */
7c3f0a27 1472 if (edid == NULL)
ea5b213a 1473 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1474 }
9d1a903d
CW		 1475
1476 /*
1477 * When there is no edid and no monitor is connected with VGA
1478 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1479 */
ff482d83
CW		 1480 if (edid == NULL)
1481 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1482
9d1a903d 1483 status = connector_status_disconnected;
9dff6af8 1484 if (edid != NULL) {
149c36a3 1485 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1486 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1487 status = connector_status_connected;
ea5b213a 1488 intel_sdvo->is_hdmi = drm_detect_hdmi_monitor(edid);
9d1a903d 1489 }
149c36a3 1490 connector->display_info.raw_edid = NULL;
9d1a903d
CW		 1491 kfree(edid);
1492 }
149c36a3 1493
2b8d33f7 1494 return status;
9dff6af8
ML		 1495}
1496
79e53945
JB		 1497static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1498{
fb7a46f3 1499 uint16_t response;
df0e9248 1500 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1501 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1502 enum drm_connector_status ret;
79e53945 1503
32aad86f
CW		 1504 if (!intel_sdvo_write_cmd(intel_sdvo,
1505 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
1506 return connector_status_unknown;
ea5b213a 1507 if (intel_sdvo->is_tv) {
d09c23de
ZY		 1508 /* add 30ms delay when the output type is SDVO-TV */
1509 mdelay(30);
1510 }
32aad86f
CW		 1511 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1512 return connector_status_unknown;
79e53945 1513
51c8b407 1514 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
e2f0ba97 1515
fb7a46f3 1516 if (response == 0)
79e53945 1517 return connector_status_disconnected;
fb7a46f3 1518
ea5b213a 1519 intel_sdvo->attached_output = response;
14571b4c 1520
615fb93f 1521 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1522 ret = connector_status_disconnected;
149c36a3
AJ		 1523 else if (response & SDVO_TMDS_MASK)
1524 ret = intel_sdvo_hdmi_sink_detect(connector);
14571b4c
ZW		 1525 else
1526 ret = connector_status_connected;
1527
1528 /* May update encoder flag for like clock for SDVO TV, etc.*/
1529 if (ret == connector_status_connected) {
ea5b213a
CW		 1530 intel_sdvo->is_tv = false;
1531 intel_sdvo->is_lvds = false;
1532 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1533
1534 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1535 intel_sdvo->is_tv = true;
1536 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1537 }
1538 if (response & SDVO_LVDS_MASK)
8545423a 1539 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1540 }
14571b4c
ZW		 1541
1542 return ret;
79e53945
JB		 1543}
1544
e2f0ba97 1545static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1546{
df0e9248 1547 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
ff482d83 1548 struct edid *edid;
57cdaf90 1549 int num_modes;
79e53945
JB		 1550
1551 /* set the bus switch and get the modes */
ea5b213a 1552 num_modes = intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
ff482d83
CW		 1553 if (num_modes)
1554 return;
79e53945 1555
57cdaf90
KP		 1556 /*
1557 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1558 * link between analog and digital outputs. So, if the regular SDVO
1559 * DDC fails, check to see if the analog output is disconnected, in
1560 * which case we'll look there for the digital DDC data.
e2f0ba97 1561 */
ff482d83
CW		 1562 edid = intel_sdvo_get_analog_edid(connector);
1563 if (edid != NULL) {
1564 drm_mode_connector_update_edid_property(connector, edid);
1565 drm_add_edid_modes(connector, edid);
1566 connector->display_info.raw_edid = NULL;
1567 kfree(edid);
e2f0ba97 1568 }
e2f0ba97
JB		 1569}
1570
1571/*
1572 * Set of SDVO TV modes.
1573 * Note! This is in reply order (see loop in get_tv_modes).
1574 * XXX: all 60Hz refresh?
1575 */
1576struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1577 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1578 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1579 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1580 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1581 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1582 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1583 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1584 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1585 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1586 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1587 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1588 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1589 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1590 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1591 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1592 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1593 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1594 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1595 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1596 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1597 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1598 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1599 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1601 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1602 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1603 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1604 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1605 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1606 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1607 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1608 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1609 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1610 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1611 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1612 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1613 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1614 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1615 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1616 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1617 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1618 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1619 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1620 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1621 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1622 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1623 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1624 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1625 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1626 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1627 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1628 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1629 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1630 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1631 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1632 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1633 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1634};
1635
1636static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1637{
df0e9248 1638 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1639 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1640 uint32_t reply = 0, format_map = 0;
1641 int i;
e2f0ba97
JB		 1642
1643 /* Read the list of supported input resolutions for the selected TV
1644 * format.
1645 */
40039750 1646 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1647 memcpy(&tv_res, &format_map,
32aad86f 1648 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1649
32aad86f
CW		 1650 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1651 return;
ce6feabd 1652
32aad86f
CW		 1653 BUILD_BUG_ON(sizeof(tv_res) != 3);
1654 if (!intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1655 &tv_res, sizeof(tv_res)))
1656 return;
1657 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1658 return;
1659
1660 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1661 if (reply & (1 << i)) {
1662 struct drm_display_mode *nmode;
1663 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1664 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1665 if (nmode)
1666 drm_mode_probed_add(connector, nmode);
1667 }
e2f0ba97
JB		 1668}
1669
7086c87f
ML		 1670static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1671{
df0e9248 1672 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1673 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1674 struct drm_display_mode *newmode;
7086c87f
ML		 1675
1676 /*
1677 * Attempt to get the mode list from DDC.
1678 * Assume that the preferred modes are
1679 * arranged in priority order.
1680 */
ea5b213a 1681 intel_ddc_get_modes(connector, intel_sdvo->base.ddc_bus);
7086c87f 1682 if (list_empty(&connector->probed_modes) == false)
12682a97 1683 goto end;
7086c87f
ML		 1684
1685 /* Fetch modes from VBT */
1686 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1687 newmode = drm_mode_duplicate(connector->dev,
1688 dev_priv->sdvo_lvds_vbt_mode);
1689 if (newmode != NULL) {
1690 /* Guarantee the mode is preferred */
1691 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1692 DRM_MODE_TYPE_DRIVER);
1693 drm_mode_probed_add(connector, newmode);
1694 }
1695 }
12682a97 1696
1697end:
1698 list_for_each_entry(newmode, &connector->probed_modes, head) {
1699 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1700 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1701 drm_mode_duplicate(connector->dev, newmode);
6c9547ff
CW		 1702
1703 drm_mode_set_crtcinfo(intel_sdvo->sdvo_lvds_fixed_mode,
1704 0);
1705
8545423a 1706 intel_sdvo->is_lvds = true;
12682a97 1707 break;
1708 }
1709 }
1710
7086c87f
ML		 1711}
1712
e2f0ba97
JB		 1713static int intel_sdvo_get_modes(struct drm_connector *connector)
1714{
615fb93f 1715 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1716
615fb93f 1717 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1718 intel_sdvo_get_tv_modes(connector);
615fb93f 1719 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1720 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1721 else
1722 intel_sdvo_get_ddc_modes(connector);
1723
32aad86f 1724 return !list_empty(&connector->probed_modes);
79e53945
JB		 1725}
1726
fcc8d672
CW		 1727static void
1728intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1729{
615fb93f 1730 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1731 struct drm_device *dev = connector->dev;
1732
c5521706
CW		 1733 if (intel_sdvo_connector->left)
1734 drm_property_destroy(dev, intel_sdvo_connector->left);
1735 if (intel_sdvo_connector->right)
1736 drm_property_destroy(dev, intel_sdvo_connector->right);
1737 if (intel_sdvo_connector->top)
1738 drm_property_destroy(dev, intel_sdvo_connector->top);
1739 if (intel_sdvo_connector->bottom)
1740 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1741 if (intel_sdvo_connector->hpos)
1742 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1743 if (intel_sdvo_connector->vpos)
1744 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1745 if (intel_sdvo_connector->saturation)
1746 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1747 if (intel_sdvo_connector->contrast)
1748 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1749 if (intel_sdvo_connector->hue)
1750 drm_property_destroy(dev, intel_sdvo_connector->hue);
1751 if (intel_sdvo_connector->sharpness)
1752 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1753 if (intel_sdvo_connector->flicker_filter)
1754 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1755 if (intel_sdvo_connector->flicker_filter_2d)
1756 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1757 if (intel_sdvo_connector->flicker_filter_adaptive)
1758 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1759 if (intel_sdvo_connector->tv_luma_filter)
1760 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1761 if (intel_sdvo_connector->tv_chroma_filter)
1762 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1763 if (intel_sdvo_connector->dot_crawl)
1764 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1765 if (intel_sdvo_connector->brightness)
1766 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1767}
1768
79e53945
JB		 1769static void intel_sdvo_destroy(struct drm_connector *connector)
1770{
615fb93f 1771 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1772
c5521706 1773 if (intel_sdvo_connector->tv_format)
ce6feabd 1774 drm_property_destroy(connector->dev,
c5521706 1775 intel_sdvo_connector->tv_format);
b9219c5e 1776
d2a82a6f 1777 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1778 drm_sysfs_connector_remove(connector);
1779 drm_connector_cleanup(connector);
d2a82a6f 1780 kfree(connector);
79e53945
JB		 1781}
1782
ce6feabd
ZY		 1783static int
1784intel_sdvo_set_property(struct drm_connector *connector,
1785 struct drm_property *property,
1786 uint64_t val)
1787{
df0e9248 1788 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1789 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e 1790 uint16_t temp_value;
32aad86f
CW		 1791 uint8_t cmd;
1792 int ret;
ce6feabd
ZY		 1793
1794 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1795 if (ret)
1796 return ret;
ce6feabd 1797
c5521706
CW		 1798#define CHECK_PROPERTY(name, NAME) \
1799 if (intel_sdvo_connector->name == property) { \
1800 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1801 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1802 cmd = SDVO_CMD_SET_##NAME; \
1803 intel_sdvo_connector->cur_##name = temp_value; \
1804 goto set_value; \
1805 }
1806
1807 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1808 if (val >= TV_FORMAT_NUM)
1809 return -EINVAL;
1810
40039750 1811 if (intel_sdvo->tv_format_index ==
615fb93f 1812 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1813 return 0;
ce6feabd 1814
40039750 1815 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1816 goto done;
32aad86f 1817 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1818 temp_value = val;
c5521706 1819 if (intel_sdvo_connector->left == property) {
b9219c5e 1820 drm_connector_property_set_value(connector,
c5521706 1821 intel_sdvo_connector->right, val);
615fb93f 1822 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1823 return 0;
b9219c5e 1824
615fb93f
CW		 1825 intel_sdvo_connector->left_margin = temp_value;
1826 intel_sdvo_connector->right_margin = temp_value;
1827 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1828 intel_sdvo_connector->left_margin;
b9219c5e 1829 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1830 goto set_value;
1831 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1832 drm_connector_property_set_value(connector,
c5521706 1833 intel_sdvo_connector->left, val);
615fb93f 1834 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1835 return 0;
b9219c5e 1836
615fb93f
CW		 1837 intel_sdvo_connector->left_margin = temp_value;
1838 intel_sdvo_connector->right_margin = temp_value;
1839 temp_value = intel_sdvo_connector->max_hscan -
1840 intel_sdvo_connector->left_margin;
b9219c5e 1841 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1842 goto set_value;
1843 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1844 drm_connector_property_set_value(connector,
c5521706 1845 intel_sdvo_connector->bottom, val);
615fb93f 1846 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1847 return 0;
b9219c5e 1848
615fb93f
CW		 1849 intel_sdvo_connector->top_margin = temp_value;
1850 intel_sdvo_connector->bottom_margin = temp_value;
1851 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1852 intel_sdvo_connector->top_margin;
b9219c5e 1853 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1854 goto set_value;
1855 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1856 drm_connector_property_set_value(connector,
c5521706 1857 intel_sdvo_connector->top, val);
615fb93f 1858 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1859 return 0;
1860
615fb93f
CW		 1861 intel_sdvo_connector->top_margin = temp_value;
1862 intel_sdvo_connector->bottom_margin = temp_value;
1863 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1864 intel_sdvo_connector->top_margin;
b9219c5e 1865 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1866 goto set_value;
1867 }
1868 CHECK_PROPERTY(hpos, HPOS)
1869 CHECK_PROPERTY(vpos, VPOS)
1870 CHECK_PROPERTY(saturation, SATURATION)
1871 CHECK_PROPERTY(contrast, CONTRAST)
1872 CHECK_PROPERTY(hue, HUE)
1873 CHECK_PROPERTY(brightness, BRIGHTNESS)
1874 CHECK_PROPERTY(sharpness, SHARPNESS)
1875 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1876 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1877 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1878 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1879 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1880 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1881 }
b9219c5e 1882
c5521706 1883 return -EINVAL; /* unknown property */
b9219c5e 1884
c5521706
CW		 1885set_value:
1886 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1887 return -EIO;
b9219c5e 1888
b9219c5e 1889
c5521706 1890done:
df0e9248
CW		 1891 if (intel_sdvo->base.base.crtc) {
1892 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
ce6feabd 1893 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1894 crtc->y, crtc->fb);
1895 }
1896
32aad86f 1897 return 0;
c5521706 1898#undef CHECK_PROPERTY
ce6feabd
ZY		 1899}
1900
79e53945
JB		 1901static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1902 .dpms = intel_sdvo_dpms,
1903 .mode_fixup = intel_sdvo_mode_fixup,
1904 .prepare = intel_encoder_prepare,
1905 .mode_set = intel_sdvo_mode_set,
1906 .commit = intel_encoder_commit,
1907};
1908
1909static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1910 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1911 .detect = intel_sdvo_detect,
1912 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1913 .set_property = intel_sdvo_set_property,
79e53945
JB		 1914 .destroy = intel_sdvo_destroy,
1915};
1916
1917static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1918 .get_modes = intel_sdvo_get_modes,
1919 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1920 .best_encoder = intel_best_encoder,
79e53945
JB		 1921};
1922
b358d0a6 1923static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1924{
890f3359 1925 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 1926
ea5b213a 1927 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1928 drm_mode_destroy(encoder->dev,
ea5b213a 1929 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1930
ea5b213a 1931 intel_encoder_destroy(encoder);
79e53945
JB		 1932}
1933
1934static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1935 .destroy = intel_sdvo_enc_destroy,
1936};
1937
b66d8424
CW		 1938static void
1939intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1940{
1941 uint16_t mask = 0;
1942 unsigned int num_bits;
1943
1944 /* Make a mask of outputs less than or equal to our own priority in the
1945 * list.
1946 */
1947 switch (sdvo->controlled_output) {
1948 case SDVO_OUTPUT_LVDS1:
1949 mask |= SDVO_OUTPUT_LVDS1;
1950 case SDVO_OUTPUT_LVDS0:
1951 mask |= SDVO_OUTPUT_LVDS0;
1952 case SDVO_OUTPUT_TMDS1:
1953 mask |= SDVO_OUTPUT_TMDS1;
1954 case SDVO_OUTPUT_TMDS0:
1955 mask |= SDVO_OUTPUT_TMDS0;
1956 case SDVO_OUTPUT_RGB1:
1957 mask |= SDVO_OUTPUT_RGB1;
1958 case SDVO_OUTPUT_RGB0:
1959 mask |= SDVO_OUTPUT_RGB0;
1960 break;
1961 }
1962
1963 /* Count bits to find what number we are in the priority list. */
1964 mask &= sdvo->caps.output_flags;
1965 num_bits = hweight16(mask);
1966 /* If more than 3 outputs, default to DDC bus 3 for now. */
1967 if (num_bits > 3)
1968 num_bits = 3;
1969
1970 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1971 sdvo->ddc_bus = 1 << num_bits;
1972}
79e53945 1973
e2f0ba97
JB		 1974/**
1975 * Choose the appropriate DDC bus for control bus switch command for this
1976 * SDVO output based on the controlled output.
1977 *
1978 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1979 * outputs, then LVDS outputs.
1980 */
1981static void
b1083333 1982intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1983 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1984{
b1083333 1985 struct sdvo_device_mapping *mapping;
e2f0ba97 1986
b1083333
AJ		 1987 if (IS_SDVOB(reg))
1988 mapping = &(dev_priv->sdvo_mappings[0]);
1989 else
1990 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1991
b66d8424
CW		 1992 if (mapping->initialized)
1993 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1994 else
1995 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1996}
1997
1998static bool
ea5b213a 1999intel_sdvo_get_digital_encoding_mode(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2000{
32aad86f
CW		 2001 return intel_sdvo_set_target_output(intel_sdvo,
2002 device == 0 ? SDVO_OUTPUT_TMDS0 : SDVO_OUTPUT_TMDS1) &&
2003 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
2004 &intel_sdvo->is_hdmi, 1);
e2f0ba97
JB		 2005}
2006
619ac3b7
ML		 2007static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
2008 struct i2c_msg msgs[], int num)
2009{
ea5b213a 2010 struct intel_sdvo *intel_sdvo;
f9c10a9b 2011 const struct i2c_algorithm *algo;
819f3fb7 2012 int ret;
619ac3b7 2013
890f3359
CW		 2014 intel_sdvo = container_of(i2c_adap->algo_data,
2015 struct intel_sdvo,
2016 base);
ea5b213a 2017 algo = intel_sdvo->base.i2c_bus->algo;
619ac3b7 2018
819f3fb7
CW		 2019 ret = intel_sdvo_set_control_bus_switch(intel_sdvo,
2020 intel_sdvo->ddc_bus);
2021 if (ret)
2022 return ret;
2023
619ac3b7
ML		 2024 return algo->master_xfer(i2c_adap, msgs, num);
2025}
2026
2027static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
2028 .master_xfer = intel_sdvo_master_xfer,
2029};
2030
714605e4 2031static u8
c751ce4f 2032intel_sdvo_get_slave_addr(struct drm_device *dev, int sdvo_reg)
714605e4 2033{
2034 struct drm_i915_private *dev_priv = dev->dev_private;
2035 struct sdvo_device_mapping *my_mapping, *other_mapping;
2036
461ed3ca 2037 if (IS_SDVOB(sdvo_reg)) {
714605e4 2038 my_mapping = &dev_priv->sdvo_mappings[0];
2039 other_mapping = &dev_priv->sdvo_mappings[1];
2040 } else {
2041 my_mapping = &dev_priv->sdvo_mappings[1];
2042 other_mapping = &dev_priv->sdvo_mappings[0];
2043 }
2044
2045 /* If the BIOS described our SDVO device, take advantage of it. */
2046 if (my_mapping->slave_addr)
2047 return my_mapping->slave_addr;
2048
2049 /* If the BIOS only described a different SDVO device, use the
2050 * address that it isn't using.
2051 */
2052 if (other_mapping->slave_addr) {
2053 if (other_mapping->slave_addr == 0x70)
2054 return 0x72;
2055 else
2056 return 0x70;
2057 }
2058
2059 /* No SDVO device info is found for another DVO port,
2060 * so use mapping assumption we had before BIOS parsing.
2061 */
461ed3ca 2062 if (IS_SDVOB(sdvo_reg))
714605e4 2063 return 0x70;
2064 else
2065 return 0x72;
2066}
2067
14571b4c 2068static void
df0e9248
CW		 2069intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2070 struct intel_sdvo *encoder)
14571b4c 2071{
df0e9248
CW		 2072 drm_connector_init(encoder->base.base.dev,
2073 &connector->base.base,
2074 &intel_sdvo_connector_funcs,
2075 connector->base.base.connector_type);
6070a4a9 2076
df0e9248
CW		 2077 drm_connector_helper_add(&connector->base.base,
2078 &intel_sdvo_connector_helper_funcs);
14571b4c 2079
df0e9248
CW		 2080 connector->base.base.interlace_allowed = 0;
2081 connector->base.base.doublescan_allowed = 0;
2082 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
14571b4c 2083
df0e9248
CW		 2084 intel_connector_attach_encoder(&connector->base, &encoder->base);
2085 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2086}
6070a4a9 2087
fb7a46f3 2088static bool
ea5b213a 2089intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2090{
4ef69c7a 2091 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c
ZW		 2092 struct drm_connector *connector;
2093 struct intel_connector *intel_connector;
615fb93f 2094 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2095
615fb93f
CW		 2096 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2097 if (!intel_sdvo_connector)
14571b4c
ZW		 2098 return false;
2099
14571b4c 2100 if (device == 0) {
ea5b213a 2101 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2102 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2103 } else if (device == 1) {
ea5b213a 2104 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2105 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2106 }
2107
615fb93f 2108 intel_connector = &intel_sdvo_connector->base;
14571b4c 2109 connector = &intel_connector->base;
eb1f8e4f 2110 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2111 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2112 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2113
ea5b213a
CW		 2114 if (intel_sdvo_get_supp_encode(intel_sdvo, &intel_sdvo->encode)
2115 && intel_sdvo_get_digital_encoding_mode(intel_sdvo, device)
2116 && intel_sdvo->is_hdmi) {
14571b4c 2117 /* enable hdmi encoding mode if supported */
ea5b213a
CW		 2118 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
2119 intel_sdvo_set_colorimetry(intel_sdvo,
14571b4c
ZW		 2120 SDVO_COLORIMETRY_RGB256);
2121 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2122 }
ea5b213a
CW		 2123 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2124 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2125
df0e9248 2126 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c
ZW		 2127
2128 return true;
2129}
2130
2131static bool
ea5b213a 2132intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2133{
4ef69c7a
CW		 2134 struct drm_encoder *encoder = &intel_sdvo->base.base;
2135 struct drm_connector *connector;
2136 struct intel_connector *intel_connector;
2137 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2138
615fb93f
CW		 2139 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2140 if (!intel_sdvo_connector)
2141 return false;
14571b4c 2142
615fb93f 2143 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2144 connector = &intel_connector->base;
2145 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2146 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2147
4ef69c7a
CW		 2148 intel_sdvo->controlled_output |= type;
2149 intel_sdvo_connector->output_flag = type;
14571b4c 2150
4ef69c7a
CW		 2151 intel_sdvo->is_tv = true;
2152 intel_sdvo->base.needs_tv_clock = true;
2153 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2154
df0e9248 2155 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2156
4ef69c7a 2157 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2158 goto err;
14571b4c 2159
4ef69c7a 2160 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2161 goto err;
14571b4c 2162
4ef69c7a 2163 return true;
32aad86f
CW		 2164
2165err:
fcc8d672 2166 intel_sdvo_destroy_enhance_property(connector);
32aad86f
CW		 2167 kfree(intel_sdvo_connector);
2168 return false;
14571b4c
ZW		 2169}
2170
2171static bool
ea5b213a 2172intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2173{
4ef69c7a
CW		 2174 struct drm_encoder *encoder = &intel_sdvo->base.base;
2175 struct drm_connector *connector;
2176 struct intel_connector *intel_connector;
2177 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2178
615fb93f
CW		 2179 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2180 if (!intel_sdvo_connector)
2181 return false;
14571b4c 2182
615fb93f 2183 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2184 connector = &intel_connector->base;
eb1f8e4f 2185 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2186 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2187 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2188
2189 if (device == 0) {
2190 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2191 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2192 } else if (device == 1) {
2193 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2194 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2195 }
2196
2197 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
ea5b213a 2198 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2199
df0e9248
CW		 2200 intel_sdvo_connector_init(intel_sdvo_connector,
2201 intel_sdvo);
4ef69c7a 2202 return true;
14571b4c
ZW		 2203}
2204
2205static bool
ea5b213a 2206intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2207{
4ef69c7a
CW		 2208 struct drm_encoder *encoder = &intel_sdvo->base.base;
2209 struct drm_connector *connector;
2210 struct intel_connector *intel_connector;
2211 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2212
615fb93f
CW		 2213 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2214 if (!intel_sdvo_connector)
2215 return false;
14571b4c 2216
615fb93f
CW		 2217 intel_connector = &intel_sdvo_connector->base;
2218 connector = &intel_connector->base;
4ef69c7a
CW		 2219 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2220 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2221
2222 if (device == 0) {
2223 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2224 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2225 } else if (device == 1) {
2226 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2227 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2228 }
2229
2230 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
ea5b213a 2231 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2232
df0e9248 2233 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2234 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2235 goto err;
2236
2237 return true;
2238
2239err:
fcc8d672 2240 intel_sdvo_destroy_enhance_property(connector);
32aad86f
CW		 2241 kfree(intel_sdvo_connector);
2242 return false;
14571b4c
ZW		 2243}
2244
2245static bool
ea5b213a 2246intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2247{
ea5b213a
CW		 2248 intel_sdvo->is_tv = false;
2249 intel_sdvo->base.needs_tv_clock = false;
2250 intel_sdvo->is_lvds = false;
fb7a46f3 2251
14571b4c 2252 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2253
14571b4c 2254 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2255 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2256 return false;
2257
2258 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2259 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2260 return false;
2261
2262 /* TV has no XXX1 function block */
a1f4b7ff 2263 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2264 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2265 return false;
2266
2267 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2268 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2269 return false;
fb7a46f3 2270
14571b4c 2271 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2272 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2273 return false;
2274
2275 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2276 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2277 return false;
2278
2279 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2280 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2281 return false;
2282
2283 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2284 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2285 return false;
fb7a46f3 2286
14571b4c 2287 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2288 unsigned char bytes[2];
2289
ea5b213a
CW		 2290 intel_sdvo->controlled_output = 0;
2291 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2292 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2293 SDVO_NAME(intel_sdvo),
51c8b407 2294 bytes[0], bytes[1]);
14571b4c 2295 return false;
fb7a46f3 2296 }
ea5b213a 2297 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1);
fb7a46f3 2298
14571b4c 2299 return true;
fb7a46f3 2300}
2301
32aad86f
CW		 2302static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2303 struct intel_sdvo_connector *intel_sdvo_connector,
2304 int type)
ce6feabd 2305{
4ef69c7a 2306 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2307 struct intel_sdvo_tv_format format;
2308 uint32_t format_map, i;
ce6feabd 2309
32aad86f
CW		 2310 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2311 return false;
ce6feabd 2312
32aad86f
CW		 2313 if (!intel_sdvo_get_value(intel_sdvo,
2314 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2315 &format, sizeof(format)))
2316 return false;
ce6feabd 2317
32aad86f 2318 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2319
2320 if (format_map == 0)
32aad86f 2321 return false;
ce6feabd 2322
615fb93f 2323 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2324 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2325 if (format_map & (1 << i))
2326 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2327
2328
c5521706 2329 intel_sdvo_connector->tv_format =
32aad86f
CW		 2330 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2331 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2332 if (!intel_sdvo_connector->tv_format)
fcc8d672 2333 return false;
ce6feabd 2334
615fb93f 2335 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2336 drm_property_add_enum(
c5521706 2337 intel_sdvo_connector->tv_format, i,
40039750 2338 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2339
40039750 2340 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2341 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2342 intel_sdvo_connector->tv_format, 0);
32aad86f 2343 return true;
ce6feabd
ZY		 2344
2345}
2346
c5521706
CW		 2347#define ENHANCEMENT(name, NAME) do { \
2348 if (enhancements.name) { \
2349 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2350 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2351 return false; \
2352 intel_sdvo_connector->max_##name = data_value[0]; \
2353 intel_sdvo_connector->cur_##name = response; \
2354 intel_sdvo_connector->name = \
2355 drm_property_create(dev, DRM_MODE_PROP_RANGE, #name, 2); \
2356 if (!intel_sdvo_connector->name) return false; \
2357 intel_sdvo_connector->name->values[0] = 0; \
2358 intel_sdvo_connector->name->values[1] = data_value[0]; \
2359 drm_connector_attach_property(connector, \
2360 intel_sdvo_connector->name, \
2361 intel_sdvo_connector->cur_##name); \
2362 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2363 data_value[0], data_value[1], response); \
2364 } \
2365} while(0)
2366
2367static bool
2368intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2369 struct intel_sdvo_connector *intel_sdvo_connector,
2370 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2371{
4ef69c7a 2372 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2373 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2374 uint16_t response, data_value[2];
2375
c5521706
CW		 2376 /* when horizontal overscan is supported, Add the left/right property */
2377 if (enhancements.overscan_h) {
2378 if (!intel_sdvo_get_value(intel_sdvo,
2379 SDVO_CMD_GET_MAX_OVERSCAN_H,
2380 &data_value, 4))
2381 return false;
32aad86f 2382
c5521706
CW		 2383 if (!intel_sdvo_get_value(intel_sdvo,
2384 SDVO_CMD_GET_OVERSCAN_H,
2385 &response, 2))
2386 return false;
fcc8d672 2387
c5521706
CW		 2388 intel_sdvo_connector->max_hscan = data_value[0];
2389 intel_sdvo_connector->left_margin = data_value[0] - response;
2390 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2391 intel_sdvo_connector->left =
2392 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2393 "left_margin", 2);
2394 if (!intel_sdvo_connector->left)
2395 return false;
fcc8d672 2396
c5521706
CW		 2397 intel_sdvo_connector->left->values[0] = 0;
2398 intel_sdvo_connector->left->values[1] = data_value[0];
2399 drm_connector_attach_property(connector,
2400 intel_sdvo_connector->left,
2401 intel_sdvo_connector->left_margin);
fcc8d672 2402
c5521706
CW		 2403 intel_sdvo_connector->right =
2404 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2405 "right_margin", 2);
2406 if (!intel_sdvo_connector->right)
2407 return false;
32aad86f 2408
c5521706
CW		 2409 intel_sdvo_connector->right->values[0] = 0;
2410 intel_sdvo_connector->right->values[1] = data_value[0];
2411 drm_connector_attach_property(connector,
2412 intel_sdvo_connector->right,
2413 intel_sdvo_connector->right_margin);
2414 DRM_DEBUG_KMS("h_overscan: max %d, "
2415 "default %d, current %d\n",
2416 data_value[0], data_value[1], response);
2417 }
32aad86f 2418
c5521706
CW		 2419 if (enhancements.overscan_v) {
2420 if (!intel_sdvo_get_value(intel_sdvo,
2421 SDVO_CMD_GET_MAX_OVERSCAN_V,
2422 &data_value, 4))
2423 return false;
fcc8d672 2424
c5521706
CW		 2425 if (!intel_sdvo_get_value(intel_sdvo,
2426 SDVO_CMD_GET_OVERSCAN_V,
2427 &response, 2))
2428 return false;
32aad86f 2429
c5521706
CW		 2430 intel_sdvo_connector->max_vscan = data_value[0];
2431 intel_sdvo_connector->top_margin = data_value[0] - response;
2432 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2433 intel_sdvo_connector->top =
2434 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2435 "top_margin", 2);
2436 if (!intel_sdvo_connector->top)
2437 return false;
32aad86f 2438
c5521706
CW		 2439 intel_sdvo_connector->top->values[0] = 0;
2440 intel_sdvo_connector->top->values[1] = data_value[0];
2441 drm_connector_attach_property(connector,
2442 intel_sdvo_connector->top,
2443 intel_sdvo_connector->top_margin);
fcc8d672 2444
c5521706
CW		 2445 intel_sdvo_connector->bottom =
2446 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2447 "bottom_margin", 2);
2448 if (!intel_sdvo_connector->bottom)
2449 return false;
32aad86f 2450
c5521706
CW		 2451 intel_sdvo_connector->bottom->values[0] = 0;
2452 intel_sdvo_connector->bottom->values[1] = data_value[0];
2453 drm_connector_attach_property(connector,
2454 intel_sdvo_connector->bottom,
2455 intel_sdvo_connector->bottom_margin);
2456 DRM_DEBUG_KMS("v_overscan: max %d, "
2457 "default %d, current %d\n",
2458 data_value[0], data_value[1], response);
2459 }
32aad86f 2460
c5521706
CW		 2461 ENHANCEMENT(hpos, HPOS);
2462 ENHANCEMENT(vpos, VPOS);
2463 ENHANCEMENT(saturation, SATURATION);
2464 ENHANCEMENT(contrast, CONTRAST);
2465 ENHANCEMENT(hue, HUE);
2466 ENHANCEMENT(sharpness, SHARPNESS);
2467 ENHANCEMENT(brightness, BRIGHTNESS);
2468 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2469 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2470 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2471 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2472 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2473
e044218a
CW		 2474 if (enhancements.dot_crawl) {
2475 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2476 return false;
2477
2478 intel_sdvo_connector->max_dot_crawl = 1;
2479 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2480 intel_sdvo_connector->dot_crawl =
2481 drm_property_create(dev, DRM_MODE_PROP_RANGE, "dot_crawl", 2);
2482 if (!intel_sdvo_connector->dot_crawl)
2483 return false;
2484
2485 intel_sdvo_connector->dot_crawl->values[0] = 0;
2486 intel_sdvo_connector->dot_crawl->values[1] = 1;
2487 drm_connector_attach_property(connector,
2488 intel_sdvo_connector->dot_crawl,
2489 intel_sdvo_connector->cur_dot_crawl);
2490 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2491 }
2492
c5521706
CW		 2493 return true;
2494}
32aad86f 2495
c5521706
CW		 2496static bool
2497intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2498 struct intel_sdvo_connector *intel_sdvo_connector,
2499 struct intel_sdvo_enhancements_reply enhancements)
2500{
4ef69c7a 2501 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2502 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2503 uint16_t response, data_value[2];
32aad86f 2504
c5521706 2505 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2506
c5521706
CW		 2507 return true;
2508}
2509#undef ENHANCEMENT
32aad86f 2510
c5521706
CW		 2511static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2512 struct intel_sdvo_connector *intel_sdvo_connector)
2513{
2514 union {
2515 struct intel_sdvo_enhancements_reply reply;
2516 uint16_t response;
2517 } enhancements;
32aad86f 2518
c5521706
CW		 2519 if (!intel_sdvo_get_value(intel_sdvo,
2520 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2521 &enhancements, sizeof(enhancements)))
2522 return false;
fcc8d672 2523
c5521706
CW		 2524 if (enhancements.response == 0) {
2525 DRM_DEBUG_KMS("No enhancement is supported\n");
2526 return true;
b9219c5e 2527 }
32aad86f 2528
c5521706
CW		 2529 if (IS_TV(intel_sdvo_connector))
2530 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2531 else if(IS_LVDS(intel_sdvo_connector))
2532 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2533 else
2534 return true;
fcc8d672 2535
b9219c5e
ZY		 2536}
2537
c751ce4f 2538bool intel_sdvo_init(struct drm_device *dev, int sdvo_reg)
79e53945 2539{
b01f2c3a 2540 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2541 struct intel_encoder *intel_encoder;
ea5b213a 2542 struct intel_sdvo *intel_sdvo;
79e53945
JB		 2543 u8 ch[0x40];
2544 int i;
ff482d83 2545 u32 i2c_reg, ddc_reg;
79e53945 2546
ea5b213a
CW		 2547 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2548 if (!intel_sdvo)
7d57382e 2549 return false;
79e53945 2550
ea5b213a 2551 intel_sdvo->sdvo_reg = sdvo_reg;
308cd3a2 2552
ea5b213a 2553 intel_encoder = &intel_sdvo->base;
21d40d37 2554 intel_encoder->type = INTEL_OUTPUT_SDVO;
79e53945 2555
461ed3ca
ZY		 2556 if (HAS_PCH_SPLIT(dev)) {
2557 i2c_reg = PCH_GPIOE;
2558 ddc_reg = PCH_GPIOE;
461ed3ca
ZY		 2559 } else {
2560 i2c_reg = GPIOE;
2561 ddc_reg = GPIOE;
461ed3ca
ZY		 2562 }
2563
79e53945 2564 /* setup the DDC bus. */
461ed3ca 2565 if (IS_SDVOB(sdvo_reg))
890f3359
CW		 2566 intel_encoder->i2c_bus =
2567 intel_i2c_create(intel_encoder,
2568 i2c_reg, "SDVOCTRL_E for SDVOB");
308cd3a2 2569 else
890f3359
CW		 2570 intel_encoder->i2c_bus =
2571 intel_i2c_create(intel_encoder,
2572 i2c_reg, "SDVOCTRL_E for SDVOC");
308cd3a2 2573
21d40d37 2574 if (!intel_encoder->i2c_bus)
ad5b2a6d 2575 goto err_inteloutput;
79e53945 2576
ea5b213a 2577 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg);
79e53945 2578
308cd3a2 2579 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
21d40d37 2580 intel_sdvo_i2c_bit_algo.functionality = intel_encoder->i2c_bus->algo->functionality;
79e53945 2581
79e53945
JB		 2582 /* Read the regs to test if we can talk to the device */
2583 for (i = 0; i < 0x40; i++) {
ea5b213a 2584 if (!intel_sdvo_read_byte(intel_sdvo, i, &ch[i])) {
8a4c47f3 2585 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
461ed3ca 2586 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
79e53945
JB		 2587 goto err_i2c;
2588 }
2589 }
2590
619ac3b7 2591 /* setup the DDC bus. */
461ed3ca 2592 if (IS_SDVOB(sdvo_reg)) {
890f3359
CW		 2593 intel_encoder->ddc_bus =
2594 intel_i2c_create(intel_encoder,
2595 ddc_reg, "SDVOB DDC BUS");
b01f2c3a 2596 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
57cdaf90 2597 } else {
890f3359
CW		 2598 intel_encoder->ddc_bus =
2599 intel_i2c_create(intel_encoder,
2600 ddc_reg, "SDVOC DDC BUS");
b01f2c3a 2601 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
57cdaf90 2602 }
ff482d83 2603 if (intel_encoder->ddc_bus == NULL)
619ac3b7
ML		 2604 goto err_i2c;
2605
308cd3a2 2606 /* Wrap with our custom algo which switches to DDC mode */
21d40d37 2607 intel_encoder->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
619ac3b7 2608
14571b4c 2609 /* encoder type will be decided later */
4ef69c7a
CW		 2610 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
2611 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2612
af901ca1 2613 /* In default case sdvo lvds is false */
32aad86f
CW		 2614 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
2615 goto err_enc;
79e53945 2616
ea5b213a
CW		 2617 if (intel_sdvo_output_setup(intel_sdvo,
2618 intel_sdvo->caps.output_flags) != true) {
51c8b407 2619 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
461ed3ca 2620 IS_SDVOB(sdvo_reg) ? 'B' : 'C');
32aad86f 2621 goto err_enc;
79e53945
JB		 2622 }
2623
ea5b213a 2624 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2625
79e53945 2626 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 2627 if (!intel_sdvo_set_target_input(intel_sdvo))
2628 goto err_enc;
79e53945 2629
32aad86f
CW		 2630 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2631 &intel_sdvo->pixel_clock_min,
2632 &intel_sdvo->pixel_clock_max))
2633 goto err_enc;
79e53945 2634
8a4c47f3 2635 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2636 "clock range %dMHz - %dMHz, "
2637 "input 1: %c, input 2: %c, "
2638 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2639 SDVO_NAME(intel_sdvo),
2640 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2641 intel_sdvo->caps.device_rev_id,
2642 intel_sdvo->pixel_clock_min / 1000,
2643 intel_sdvo->pixel_clock_max / 1000,
2644 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2645 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2646 /* check currently supported outputs */
ea5b213a 2647 intel_sdvo->caps.output_flags &
79e53945 2648 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2649 intel_sdvo->caps.output_flags &
79e53945 2650 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2651 return true;
79e53945 2652
32aad86f 2653err_enc:
4ef69c7a 2654 drm_encoder_cleanup(&intel_encoder->base);
79e53945 2655err_i2c:
21d40d37
EA		 2656 if (intel_encoder->ddc_bus != NULL)
2657 intel_i2c_destroy(intel_encoder->ddc_bus);
2658 if (intel_encoder->i2c_bus != NULL)
2659 intel_i2c_destroy(intel_encoder->i2c_bus);
ad5b2a6d 2660err_inteloutput:
ea5b213a 2661 kfree(intel_sdvo);
79e53945 2662
7d57382e 2663 return false;
79e53945 2664}
ubuntu-zesty-kernel mirror