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UBUNTU: Ubuntu-4.15.0-96.97
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7 32#include <drm/drmP.h>
c6f95f27 33#include <drm/drm_atomic_helper.h>
760285e7
DH		 34#include <drm/drm_crtc.h>
35#include <drm/drm_edid.h>
ea5b213a 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945
JB		 38#include "i915_drv.h"
39#include "intel_sdvo_regs.h"
40
14571b4c
ZW		 41#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 44#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 45
46#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 47 SDVO_TV_MASK)
14571b4c
ZW		 48
49#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 50#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 51#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 52#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 53#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 54
79e53945 55
4d9194de 56static const char * const tv_format_names[] = {
ce6feabd
ZY		 57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64};
65
53abb679 66#define TV_FORMAT_NUM ARRAY_SIZE(tv_format_names)
ce6feabd 67
ea5b213a
CW		 68struct intel_sdvo {
69 struct intel_encoder base;
70
f899fc64 71 struct i2c_adapter *i2c;
f9c10a9b 72 u8 slave_addr;
e2f0ba97 73
e957d772
CW		 74 struct i2c_adapter ddc;
75
e2f0ba97 76 /* Register for the SDVO device: SDVOB or SDVOC */
f0f59a00 77 i915_reg_t sdvo_reg;
79e53945 78
e2f0ba97
JB		 79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
79e53945 81
e2f0ba97
JB		 82 /*
83 * Capabilities of the SDVO device returned by
19d415a2 84 * intel_sdvo_get_capabilities()
e2f0ba97 85 */
79e53945 86 struct intel_sdvo_caps caps;
e2f0ba97
JB		 87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 89 int pixel_clock_min, pixel_clock_max;
90
fb7a46f3 91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
cc68c81a
SF		 97 /*
98 * Hotplug activation bits for this device
99 */
5fa7ac9c 100 uint16_t hotplug_active;
cc68c81a 101
e2f0ba97
JB		 102 /**
103 * This is set if we're going to treat the device as TV-out.
104 *
105 * While we have these nice friendly flags for output types that ought
106 * to decide this for us, the S-Video output on our HDMI+S-Video card
107 * shows up as RGB1 (VGA).
108 */
109 bool is_tv;
110
2a5c0832 111 enum port port;
eef4eacb 112
e2f0ba97
JB		 113 /**
114 * This is set if we treat the device as HDMI, instead of DVI.
115 */
116 bool is_hdmi;
da79de97
CW		 117 bool has_hdmi_monitor;
118 bool has_hdmi_audio;
abedc077 119 bool rgb_quant_range_selectable;
12682a97 120
7086c87f 121 /**
6c9547ff
CW		 122 * This is set if we detect output of sdvo device as LVDS and
123 * have a valid fixed mode to use with the panel.
7086c87f
ML		 124 */
125 bool is_lvds;
e2f0ba97 126
12682a97 127 /**
128 * This is sdvo fixed pannel mode pointer
129 */
130 struct drm_display_mode *sdvo_lvds_fixed_mode;
131
c751ce4f 132 /* DDC bus used by this SDVO encoder */
e2f0ba97 133 uint8_t ddc_bus;
e751823d
EE		 134
135 /*
136 * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
137 */
138 uint8_t dtd_sdvo_flags;
14571b4c
ZW		 139};
140
141struct intel_sdvo_connector {
615fb93f
CW		 142 struct intel_connector base;
143
14571b4c
ZW		 144 /* Mark the type of connector */
145 uint16_t output_flag;
146
147 /* This contains all current supported TV format */
40039750 148 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 149 int format_supported_num;
c5521706 150 struct drm_property *tv_format;
14571b4c 151
b9219c5e 152 /* add the property for the SDVO-TV */
c5521706
CW		 153 struct drm_property *left;
154 struct drm_property *right;
155 struct drm_property *top;
156 struct drm_property *bottom;
157 struct drm_property *hpos;
158 struct drm_property *vpos;
159 struct drm_property *contrast;
160 struct drm_property *saturation;
161 struct drm_property *hue;
162 struct drm_property *sharpness;
163 struct drm_property *flicker_filter;
164 struct drm_property *flicker_filter_adaptive;
165 struct drm_property *flicker_filter_2d;
166 struct drm_property *tv_chroma_filter;
167 struct drm_property *tv_luma_filter;
e044218a 168 struct drm_property *dot_crawl;
b9219c5e
ZY		 169
170 /* add the property for the SDVO-TV/LVDS */
c5521706 171 struct drm_property *brightness;
b9219c5e 172
b9219c5e 173 /* this is to get the range of margin.*/
630d30a4
ML		 174 u32 max_hscan, max_vscan;
175};
176
177struct intel_sdvo_connector_state {
178 /* base.base: tv.saturation/contrast/hue/brightness */
179 struct intel_digital_connector_state base;
180
181 struct {
182 unsigned overscan_h, overscan_v, hpos, vpos, sharpness;
183 unsigned flicker_filter, flicker_filter_2d, flicker_filter_adaptive;
184 unsigned chroma_filter, luma_filter, dot_crawl;
185 } tv;
79e53945
JB		 186};
187
8aca63aa 188static struct intel_sdvo *to_sdvo(struct intel_encoder *encoder)
ea5b213a 189{
8aca63aa 190 return container_of(encoder, struct intel_sdvo, base);
ea5b213a
CW		 191}
192
df0e9248
CW		 193static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
194{
8aca63aa 195 return to_sdvo(intel_attached_encoder(connector));
df0e9248
CW		 196}
197
630d30a4
ML		 198static struct intel_sdvo_connector *
199to_intel_sdvo_connector(struct drm_connector *connector)
200{
201 return container_of(connector, struct intel_sdvo_connector, base.base);
202}
203
5f88a9c6
VS		 204#define to_intel_sdvo_connector_state(conn_state) \
205 container_of((conn_state), struct intel_sdvo_connector_state, base.base)
615fb93f 206
fb7a46f3 207static bool
ea5b213a 208intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 209static bool
210intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
211 struct intel_sdvo_connector *intel_sdvo_connector,
212 int type);
213static bool
214intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
215 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 216
79e53945
JB		 217/**
218 * Writes the SDVOB or SDVOC with the given value, but always writes both
219 * SDVOB and SDVOC to work around apparent hardware issues (according to
220 * comments in the BIOS).
221 */
ea5b213a 222static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 223{
4ef69c7a 224 struct drm_device *dev = intel_sdvo->base.base.dev;
fac5e23e 225 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945
JB		 226 u32 bval = val, cval = val;
227 int i;
228
2a5c0832 229 if (HAS_PCH_SPLIT(dev_priv)) {
ea5b213a 230 I915_WRITE(intel_sdvo->sdvo_reg, val);
abab6311 231 POSTING_READ(intel_sdvo->sdvo_reg);
e8504ee2
VS		 232 /*
233 * HW workaround, need to write this twice for issue
234 * that may result in first write getting masked.
235 */
6e266956 236 if (HAS_PCH_IBX(dev_priv)) {
e8504ee2
VS		 237 I915_WRITE(intel_sdvo->sdvo_reg, val);
238 POSTING_READ(intel_sdvo->sdvo_reg);
239 }
461ed3ca
ZY		 240 return;
241 }
242
2a5c0832 243 if (intel_sdvo->port == PORT_B)
e2debe91
PZ		 244 cval = I915_READ(GEN3_SDVOC);
245 else
246 bval = I915_READ(GEN3_SDVOB);
247
79e53945
JB		 248 /*
249 * Write the registers twice for luck. Sometimes,
250 * writing them only once doesn't appear to 'stick'.
251 * The BIOS does this too. Yay, magic
252 */
253 for (i = 0; i < 2; i++)
254 {
e2debe91 255 I915_WRITE(GEN3_SDVOB, bval);
abab6311 256 POSTING_READ(GEN3_SDVOB);
e2debe91 257 I915_WRITE(GEN3_SDVOC, cval);
abab6311 258 POSTING_READ(GEN3_SDVOC);
79e53945
JB		 259 }
260}
261
32aad86f 262static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 263{
79e53945
JB		 264 struct i2c_msg msgs[] = {
265 {
e957d772 266 .addr = intel_sdvo->slave_addr,
79e53945
JB		 267 .flags = 0,
268 .len = 1,
e957d772 269 .buf = &addr,
79e53945
JB		 270 },
271 {
e957d772 272 .addr = intel_sdvo->slave_addr,
79e53945
JB		 273 .flags = I2C_M_RD,
274 .len = 1,
e957d772 275 .buf = ch,
79e53945
JB		 276 }
277 };
32aad86f 278 int ret;
79e53945 279
f899fc64 280 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 281 return true;
79e53945 282
8a4c47f3 283 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 284 return false;
285}
286
79e53945
JB		 287#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
288/** Mapping of command numbers to names, for debug output */
005568be 289static const struct _sdvo_cmd_name {
e2f0ba97 290 u8 cmd;
2e88e40b 291 const char *name;
579627ea 292} __attribute__ ((packed)) sdvo_cmd_names[] = {
0206e353
AJ		 293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
336
337 /* Add the op code for SDVO enhancements */
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
382
383 /* HDMI op code */
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 404};
405
2a5c0832 406#define SDVO_NAME(svdo) ((svdo)->port == PORT_B ? "SDVOB" : "SDVOC")
79e53945 407
ea5b213a 408static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 409 const void *args, int args_len)
79e53945 410{
84fcb469
DV		 411 int i, pos = 0;
412#define BUF_LEN 256
413 char buffer[BUF_LEN];
414
415#define BUF_PRINT(args...) \
416 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
417
79e53945 418
84fcb469
DV		 419 for (i = 0; i < args_len; i++) {
420 BUF_PRINT("%02X ", ((u8 *)args)[i]);
421 }
422 for (; i < 8; i++) {
423 BUF_PRINT(" ");
424 }
04ad327f 425 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 426 if (cmd == sdvo_cmd_names[i].cmd) {
84fcb469 427 BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 428 break;
429 }
430 }
84fcb469
DV		 431 if (i == ARRAY_SIZE(sdvo_cmd_names)) {
432 BUF_PRINT("(%02X)", cmd);
433 }
434 BUG_ON(pos >= BUF_LEN - 1);
435#undef BUF_PRINT
436#undef BUF_LEN
437
438 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
79e53945 439}
79e53945 440
4d9194de 441static const char * const cmd_status_names[] = {
e957d772
CW		 442 "Power on",
443 "Success",
444 "Not supported",
445 "Invalid arg",
446 "Pending",
447 "Target not specified",
448 "Scaling not supported"
449};
450
a8506684
DV		 451static bool __intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
452 const void *args, int args_len,
453 bool unlocked)
79e53945 454{
3bf3f452
BW		 455 u8 *buf, status;
456 struct i2c_msg *msgs;
457 int i, ret = true;
458
a8506684 459 /* Would be simpler to allocate both in one go ? */
5c67eeb6 460 buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
3bf3f452
BW		 461 if (!buf)
462 return false;
463
464 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e 465 if (!msgs) {
a8506684 466 kfree(buf);
3bf3f452 467 return false;
a8506684 468 }
79e53945 469
ea5b213a 470 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 471
472 for (i = 0; i < args_len; i++) {
e957d772
CW		 473 msgs[i].addr = intel_sdvo->slave_addr;
474 msgs[i].flags = 0;
475 msgs[i].len = 2;
476 msgs[i].buf = buf + 2 *i;
477 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
478 buf[2*i + 1] = ((u8*)args)[i];
479 }
480 msgs[i].addr = intel_sdvo->slave_addr;
481 msgs[i].flags = 0;
482 msgs[i].len = 2;
483 msgs[i].buf = buf + 2*i;
484 buf[2*i + 0] = SDVO_I2C_OPCODE;
485 buf[2*i + 1] = cmd;
486
487 /* the following two are to read the response */
488 status = SDVO_I2C_CMD_STATUS;
489 msgs[i+1].addr = intel_sdvo->slave_addr;
490 msgs[i+1].flags = 0;
491 msgs[i+1].len = 1;
492 msgs[i+1].buf = &status;
493
494 msgs[i+2].addr = intel_sdvo->slave_addr;
495 msgs[i+2].flags = I2C_M_RD;
496 msgs[i+2].len = 1;
497 msgs[i+2].buf = &status;
498
a8506684
DV		 499 if (unlocked)
500 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
501 else
502 ret = __i2c_transfer(intel_sdvo->i2c, msgs, i+3);
e957d772
CW		 503 if (ret < 0) {
504 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 505 ret = false;
506 goto out;
e957d772
CW		 507 }
508 if (ret != i+3) {
509 /* failure in I2C transfer */
510 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 511 ret = false;
e957d772
CW		 512 }
513
3bf3f452
BW		 514out:
515 kfree(msgs);
516 kfree(buf);
517 return ret;
79e53945
JB		 518}
519
a8506684
DV		 520static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
521 const void *args, int args_len)
522{
523 return __intel_sdvo_write_cmd(intel_sdvo, cmd, args, args_len, true);
524}
525
b5c616a7
CW		 526static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
527 void *response, int response_len)
79e53945 528{
fc37381c 529 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
b5c616a7 530 u8 status;
84fcb469
DV		 531 int i, pos = 0;
532#define BUF_LEN 256
533 char buffer[BUF_LEN];
79e53945 534
d121a5d2 535
b5c616a7
CW		 536 /*
537 * The documentation states that all commands will be
538 * processed within 15µs, and that we need only poll
539 * the status byte a maximum of 3 times in order for the
540 * command to be complete.
541 *
542 * Check 5 times in case the hardware failed to read the docs.
fc37381c
CW		 543 *
544 * Also beware that the first response by many devices is to
545 * reply PENDING and stall for time. TVs are notorious for
546 * requiring longer than specified to complete their replies.
547 * Originally (in the DDX long ago), the delay was only ever 15ms
548 * with an additional delay of 30ms applied for TVs added later after
549 * many experiments. To accommodate both sets of delays, we do a
550 * sequence of slow checks if the device is falling behind and fails
551 * to reply within 5*15µs.
b5c616a7 552 */
d121a5d2
CW		 553 if (!intel_sdvo_read_byte(intel_sdvo,
554 SDVO_I2C_CMD_STATUS,
555 &status))
556 goto log_fail;
557
1ad87e72 558 while ((status == SDVO_CMD_STATUS_PENDING ||
46a3f4a3 559 status == SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED) && --retry) {
fc37381c
CW		 560 if (retry < 10)
561 msleep(15);
562 else
563 udelay(15);
564
b5c616a7
CW		 565 if (!intel_sdvo_read_byte(intel_sdvo,
566 SDVO_I2C_CMD_STATUS,
567 &status))
d121a5d2
CW		 568 goto log_fail;
569 }
b5c616a7 570
84fcb469
DV		 571#define BUF_PRINT(args...) \
572 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
573
79e53945 574 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
84fcb469 575 BUF_PRINT("(%s)", cmd_status_names[status]);
79e53945 576 else
84fcb469 577 BUF_PRINT("(??? %d)", status);
79e53945 578
b5c616a7
CW		 579 if (status != SDVO_CMD_STATUS_SUCCESS)
580 goto log_fail;
79e53945 581
b5c616a7
CW		 582 /* Read the command response */
583 for (i = 0; i < response_len; i++) {
584 if (!intel_sdvo_read_byte(intel_sdvo,
585 SDVO_I2C_RETURN_0 + i,
586 &((u8 *)response)[i]))
587 goto log_fail;
84fcb469 588 BUF_PRINT(" %02X", ((u8 *)response)[i]);
b5c616a7 589 }
84fcb469
DV		 590 BUG_ON(pos >= BUF_LEN - 1);
591#undef BUF_PRINT
592#undef BUF_LEN
593
594 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
b5c616a7 595 return true;
79e53945 596
b5c616a7 597log_fail:
84fcb469 598 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
b5c616a7 599 return false;
79e53945
JB		 600}
601
5e7234c9 602static int intel_sdvo_get_pixel_multiplier(const struct drm_display_mode *adjusted_mode)
79e53945 603{
aad941d5 604 if (adjusted_mode->crtc_clock >= 100000)
79e53945 605 return 1;
aad941d5 606 else if (adjusted_mode->crtc_clock >= 50000)
79e53945
JB		 607 return 2;
608 else
609 return 4;
610}
611
a8506684
DV		 612static bool __intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
613 u8 ddc_bus)
79e53945 614{
d121a5d2 615 /* This must be the immediately preceding write before the i2c xfer */
a8506684
DV		 616 return __intel_sdvo_write_cmd(intel_sdvo,
617 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
618 &ddc_bus, 1, false);
79e53945
JB		 619}
620
32aad86f 621static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 622{
d121a5d2
CW		 623 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
624 return false;
625
626 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 627}
79e53945 628
32aad86f
CW		 629static bool
630intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
631{
632 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
633 return false;
79e53945 634
32aad86f
CW		 635 return intel_sdvo_read_response(intel_sdvo, value, len);
636}
79e53945 637
32aad86f
CW		 638static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
639{
640 struct intel_sdvo_set_target_input_args targets = {0};
641 return intel_sdvo_set_value(intel_sdvo,
642 SDVO_CMD_SET_TARGET_INPUT,
643 &targets, sizeof(targets));
79e53945
JB		 644}
645
646/**
647 * Return whether each input is trained.
648 *
649 * This function is making an assumption about the layout of the response,
650 * which should be checked against the docs.
651 */
ea5b213a 652static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 653{
654 struct intel_sdvo_get_trained_inputs_response response;
79e53945 655
1a3665c8 656 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 657 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
658 &response, sizeof(response)))
79e53945
JB		 659 return false;
660
661 *input_1 = response.input0_trained;
662 *input_2 = response.input1_trained;
663 return true;
664}
665
ea5b213a 666static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 667 u16 outputs)
668{
32aad86f
CW		 669 return intel_sdvo_set_value(intel_sdvo,
670 SDVO_CMD_SET_ACTIVE_OUTPUTS,
671 &outputs, sizeof(outputs));
79e53945
JB		 672}
673
4ac41f47
DV		 674static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
675 u16 *outputs)
676{
677 return intel_sdvo_get_value(intel_sdvo,
678 SDVO_CMD_GET_ACTIVE_OUTPUTS,
679 outputs, sizeof(*outputs));
680}
681
ea5b213a 682static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 683 int mode)
684{
32aad86f 685 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 686
687 switch (mode) {
688 case DRM_MODE_DPMS_ON:
689 state = SDVO_ENCODER_STATE_ON;
690 break;
691 case DRM_MODE_DPMS_STANDBY:
692 state = SDVO_ENCODER_STATE_STANDBY;
693 break;
694 case DRM_MODE_DPMS_SUSPEND:
695 state = SDVO_ENCODER_STATE_SUSPEND;
696 break;
697 case DRM_MODE_DPMS_OFF:
698 state = SDVO_ENCODER_STATE_OFF;
699 break;
700 }
701
32aad86f
CW		 702 return intel_sdvo_set_value(intel_sdvo,
703 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 704}
705
ea5b213a 706static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 707 int *clock_min,
708 int *clock_max)
709{
710 struct intel_sdvo_pixel_clock_range clocks;
79e53945 711
1a3665c8 712 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 713 if (!intel_sdvo_get_value(intel_sdvo,
714 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
715 &clocks, sizeof(clocks)))
79e53945
JB		 716 return false;
717
718 /* Convert the values from units of 10 kHz to kHz. */
719 *clock_min = clocks.min * 10;
720 *clock_max = clocks.max * 10;
79e53945
JB		 721 return true;
722}
723
ea5b213a 724static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 725 u16 outputs)
726{
32aad86f
CW		 727 return intel_sdvo_set_value(intel_sdvo,
728 SDVO_CMD_SET_TARGET_OUTPUT,
729 &outputs, sizeof(outputs));
79e53945
JB		 730}
731
ea5b213a 732static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 733 struct intel_sdvo_dtd *dtd)
734{
32aad86f
CW		 735 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
736 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 737}
738
045ac3b5
JB		 739static bool intel_sdvo_get_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
740 struct intel_sdvo_dtd *dtd)
741{
742 return intel_sdvo_get_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
743 intel_sdvo_get_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
744}
745
ea5b213a 746static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 747 struct intel_sdvo_dtd *dtd)
748{
ea5b213a 749 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 750 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
751}
752
ea5b213a 753static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 754 struct intel_sdvo_dtd *dtd)
755{
ea5b213a 756 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 757 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
758}
759
045ac3b5
JB		 760static bool intel_sdvo_get_input_timing(struct intel_sdvo *intel_sdvo,
761 struct intel_sdvo_dtd *dtd)
762{
763 return intel_sdvo_get_timing(intel_sdvo,
764 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
765}
766
e2f0ba97 767static bool
ea5b213a 768intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 769 uint16_t clock,
770 uint16_t width,
771 uint16_t height)
772{
773 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 774
e642c6f1 775 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 776 args.clock = clock;
777 args.width = width;
778 args.height = height;
e642c6f1 779 args.interlace = 0;
12682a97 780
ea5b213a
CW		 781 if (intel_sdvo->is_lvds &&
782 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
783 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 784 args.scaled = 1;
785
32aad86f
CW		 786 return intel_sdvo_set_value(intel_sdvo,
787 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
788 &args, sizeof(args));
e2f0ba97
JB		 789}
790
ea5b213a 791static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 792 struct intel_sdvo_dtd *dtd)
793{
1a3665c8
CW		 794 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
795 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 796 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
797 &dtd->part1, sizeof(dtd->part1)) &&
798 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
799 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 800}
79e53945 801
ea5b213a 802static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 803{
32aad86f 804 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 805}
806
e2f0ba97 807static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 808 const struct drm_display_mode *mode)
79e53945 809{
e2f0ba97
JB		 810 uint16_t width, height;
811 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
812 uint16_t h_sync_offset, v_sync_offset;
6651819b 813 int mode_clock;
79e53945 814
1c4a814e
DV		 815 memset(dtd, 0, sizeof(*dtd));
816
c6ebd4c0
DV		 817 width = mode->hdisplay;
818 height = mode->vdisplay;
79e53945
JB		 819
820 /* do some mode translations */
c6ebd4c0
DV		 821 h_blank_len = mode->htotal - mode->hdisplay;
822 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 823
c6ebd4c0
DV		 824 v_blank_len = mode->vtotal - mode->vdisplay;
825 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 826
c6ebd4c0
DV		 827 h_sync_offset = mode->hsync_start - mode->hdisplay;
828 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 829
6651819b 830 mode_clock = mode->clock;
6651819b
DV		 831 mode_clock /= 10;
832 dtd->part1.clock = mode_clock;
833
e2f0ba97
JB		 834 dtd->part1.h_active = width & 0xff;
835 dtd->part1.h_blank = h_blank_len & 0xff;
836 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 837 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 838 dtd->part1.v_active = height & 0xff;
839 dtd->part1.v_blank = v_blank_len & 0xff;
840 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 841 ((v_blank_len >> 8) & 0xf);
842
171a9e96 843 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 844 dtd->part2.h_sync_width = h_sync_len & 0xff;
845 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 846 (v_sync_len & 0xf);
e2f0ba97 847 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 848 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
849 ((v_sync_len & 0x30) >> 4);
850
e2f0ba97 851 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 852 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
853 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 854 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 855 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 856 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 857 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97 858
e2f0ba97 859 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
e2f0ba97
JB		 860}
861
1c4a814e 862static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode *pmode,
32aad86f 863 const struct intel_sdvo_dtd *dtd)
e2f0ba97 864{
1c4a814e
DV		 865 struct drm_display_mode mode = {};
866
867 mode.hdisplay = dtd->part1.h_active;
868 mode.hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
869 mode.hsync_start = mode.hdisplay + dtd->part2.h_sync_off;
870 mode.hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
871 mode.hsync_end = mode.hsync_start + dtd->part2.h_sync_width;
872 mode.hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
873 mode.htotal = mode.hdisplay + dtd->part1.h_blank;
874 mode.htotal += (dtd->part1.h_high & 0xf) << 8;
875
876 mode.vdisplay = dtd->part1.v_active;
877 mode.vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
878 mode.vsync_start = mode.vdisplay;
879 mode.vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
880 mode.vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
881 mode.vsync_start += dtd->part2.v_sync_off_high & 0xc0;
882 mode.vsync_end = mode.vsync_start +
e2f0ba97 883 (dtd->part2.v_sync_off_width & 0xf);
1c4a814e
DV		 884 mode.vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
885 mode.vtotal = mode.vdisplay + dtd->part1.v_blank;
886 mode.vtotal += (dtd->part1.v_high & 0xf) << 8;
e2f0ba97 887
1c4a814e 888 mode.clock = dtd->part1.clock * 10;
e2f0ba97 889
59d92bfa 890 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
1c4a814e 891 mode.flags |= DRM_MODE_FLAG_INTERLACE;
59d92bfa 892 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1c4a814e 893 mode.flags |= DRM_MODE_FLAG_PHSYNC;
3cea210f 894 else
1c4a814e 895 mode.flags |= DRM_MODE_FLAG_NHSYNC;
59d92bfa 896 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1c4a814e 897 mode.flags |= DRM_MODE_FLAG_PVSYNC;
3cea210f 898 else
1c4a814e
DV		 899 mode.flags |= DRM_MODE_FLAG_NVSYNC;
900
901 drm_mode_set_crtcinfo(&mode, 0);
902
903 drm_mode_copy(pmode, &mode);
e2f0ba97
JB		 904}
905
e27d8538 906static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 907{
e27d8538 908 struct intel_sdvo_encode encode;
e2f0ba97 909
1a3665c8 910 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 911 return intel_sdvo_get_value(intel_sdvo,
912 SDVO_CMD_GET_SUPP_ENCODE,
913 &encode, sizeof(encode));
e2f0ba97
JB		 914}
915
ea5b213a 916static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 917 uint8_t mode)
e2f0ba97 918{
32aad86f 919 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 920}
921
ea5b213a 922static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 923 uint8_t mode)
924{
32aad86f 925 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 926}
927
b106612f
VS		 928static bool intel_sdvo_set_audio_state(struct intel_sdvo *intel_sdvo,
929 u8 audio_state)
930{
931 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_AUDIO_STAT,
932 &audio_state, 1);
933}
934
e2f0ba97 935#if 0
ea5b213a 936static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 937{
938 int i, j;
939 uint8_t set_buf_index[2];
940 uint8_t av_split;
941 uint8_t buf_size;
942 uint8_t buf[48];
943 uint8_t *pos;
944
32aad86f 945 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 946
947 for (i = 0; i <= av_split; i++) {
948 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 949 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 950 set_buf_index, 2);
c751ce4f
EA		 951 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
952 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 953
954 pos = buf;
955 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 956 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 957 NULL, 0);
c751ce4f 958 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 959 pos += 8;
960 }
961 }
962}
963#endif
964
b6e0e543
DV		 965static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
966 unsigned if_index, uint8_t tx_rate,
fff63867 967 const uint8_t *data, unsigned length)
b6e0e543
DV		 968{
969 uint8_t set_buf_index[2] = { if_index, 0 };
970 uint8_t hbuf_size, tmp[8];
971 int i;
972
973 if (!intel_sdvo_set_value(intel_sdvo,
974 SDVO_CMD_SET_HBUF_INDEX,
975 set_buf_index, 2))
976 return false;
977
978 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
979 &hbuf_size, 1))
980 return false;
981
982 /* Buffer size is 0 based, hooray! */
983 hbuf_size++;
984
985 DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
986 if_index, length, hbuf_size);
987
988 for (i = 0; i < hbuf_size; i += 8) {
989 memset(tmp, 0, 8);
990 if (i < length)
991 memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
992
993 if (!intel_sdvo_set_value(intel_sdvo,
994 SDVO_CMD_SET_HBUF_DATA,
995 tmp, 8))
996 return false;
997 }
998
999 return intel_sdvo_set_value(intel_sdvo,
1000 SDVO_CMD_SET_HBUF_TXRATE,
1001 &tx_rate, 1);
1002}
1003
abedc077 1004static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
5f88a9c6 1005 const struct intel_crtc_state *pipe_config)
e2f0ba97 1006{
15dcd350 1007 uint8_t sdvo_data[HDMI_INFOFRAME_SIZE(AVI)];
15dcd350
DL		 1008 union hdmi_infoframe frame;
1009 int ret;
1010 ssize_t len;
1011
1012 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
0c1f528c
SS		 1013 &pipe_config->base.adjusted_mode,
1014 false);
15dcd350
DL		 1015 if (ret < 0) {
1016 DRM_ERROR("couldn't fill AVI infoframe\n");
1017 return false;
1018 }
3c17fe4b 1019
abedc077 1020 if (intel_sdvo->rgb_quant_range_selectable) {
f9fe0530 1021 if (pipe_config->limited_color_range)
15dcd350
DL		 1022 frame.avi.quantization_range =
1023 HDMI_QUANTIZATION_RANGE_LIMITED;
abedc077 1024 else
15dcd350
DL		 1025 frame.avi.quantization_range =
1026 HDMI_QUANTIZATION_RANGE_FULL;
abedc077
VS		 1027 }
1028
15dcd350
DL		 1029 len = hdmi_infoframe_pack(&frame, sdvo_data, sizeof(sdvo_data));
1030 if (len < 0)
1031 return false;
81014b9d 1032
b6e0e543
DV		 1033 return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
1034 SDVO_HBUF_TX_VSYNC,
1035 sdvo_data, sizeof(sdvo_data));
e2f0ba97
JB		 1036}
1037
630d30a4 1038static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo,
5f88a9c6 1039 const struct drm_connector_state *conn_state)
7026d4ac 1040{
ce6feabd 1041 struct intel_sdvo_tv_format format;
40039750 1042 uint32_t format_map;
ce6feabd 1043
630d30a4 1044 format_map = 1 << conn_state->tv.mode;
ce6feabd 1045 memset(&format, 0, sizeof(format));
32aad86f 1046 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 1047
32aad86f
CW		 1048 BUILD_BUG_ON(sizeof(format) != 6);
1049 return intel_sdvo_set_value(intel_sdvo,
1050 SDVO_CMD_SET_TV_FORMAT,
1051 &format, sizeof(format));
7026d4ac
ZW		 1052}
1053
32aad86f
CW		 1054static bool
1055intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1056 const struct drm_display_mode *mode)
e2f0ba97 1057{
32aad86f 1058 struct intel_sdvo_dtd output_dtd;
79e53945 1059
32aad86f
CW		 1060 if (!intel_sdvo_set_target_output(intel_sdvo,
1061 intel_sdvo->attached_output))
1062 return false;
e2f0ba97 1063
32aad86f
CW		 1064 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1065 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1066 return false;
e2f0ba97 1067
32aad86f
CW		 1068 return true;
1069}
1070
c9a29698
DV		 1071/* Asks the sdvo controller for the preferred input mode given the output mode.
1072 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 1073static bool
c9a29698 1074intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 1075 const struct drm_display_mode *mode,
c9a29698 1076 struct drm_display_mode *adjusted_mode)
32aad86f 1077{
c9a29698
DV		 1078 struct intel_sdvo_dtd input_dtd;
1079
32aad86f
CW		 1080 /* Reset the input timing to the screen. Assume always input 0. */
1081 if (!intel_sdvo_set_target_input(intel_sdvo))
1082 return false;
e2f0ba97 1083
32aad86f
CW		 1084 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
1085 mode->clock / 10,
1086 mode->hdisplay,
1087 mode->vdisplay))
1088 return false;
e2f0ba97 1089
32aad86f 1090 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 1091 &input_dtd))
32aad86f 1092 return false;
e2f0ba97 1093
c9a29698 1094 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
e751823d 1095 intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
79e53945 1096
32aad86f
CW		 1097 return true;
1098}
12682a97 1099
5cec258b 1100static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc_state *pipe_config)
70484559 1101{
3c52f4eb 1102 unsigned dotclock = pipe_config->port_clock;
70484559
DV		 1103 struct dpll *clock = &pipe_config->dpll;
1104
1105 /* SDVO TV has fixed PLL values depend on its clock range,
1106 this mirrors vbios setting. */
1107 if (dotclock >= 100000 && dotclock < 140500) {
1108 clock->p1 = 2;
1109 clock->p2 = 10;
1110 clock->n = 3;
1111 clock->m1 = 16;
1112 clock->m2 = 8;
1113 } else if (dotclock >= 140500 && dotclock <= 200000) {
1114 clock->p1 = 1;
1115 clock->p2 = 10;
1116 clock->n = 6;
1117 clock->m1 = 12;
1118 clock->m2 = 8;
1119 } else {
1120 WARN(1, "SDVO TV clock out of range: %i\n", dotclock);
1121 }
1122
1123 pipe_config->clock_set = true;
1124}
1125
6cc5f341 1126static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
0a478c27
ML		 1127 struct intel_crtc_state *pipe_config,
1128 struct drm_connector_state *conn_state)
32aad86f 1129{
8aca63aa 1130 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
630d30a4
ML		 1131 struct intel_sdvo_connector_state *intel_sdvo_state =
1132 to_intel_sdvo_connector_state(conn_state);
2d112de7
ACO		 1133 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1134 struct drm_display_mode *mode = &pipe_config->base.mode;
12682a97 1135
5d2d38dd
DV		 1136 DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
1137 pipe_config->pipe_bpp = 8*3;
1138
6e266956 1139 if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
5bfe2ac0
DV		 1140 pipe_config->has_pch_encoder = true;
1141
32aad86f
CW		 1142 /* We need to construct preferred input timings based on our
1143 * output timings. To do that, we have to set the output
1144 * timings, even though this isn't really the right place in
1145 * the sequence to do it. Oh well.
1146 */
1147 if (intel_sdvo->is_tv) {
1148 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
1149 return false;
12682a97 1150
c9a29698
DV		 1151 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1152 mode,
1153 adjusted_mode);
09ede541 1154 pipe_config->sdvo_tv_clock = true;
ea5b213a 1155 } else if (intel_sdvo->is_lvds) {
32aad86f 1156 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1157 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1158 return false;
12682a97 1159
c9a29698
DV		 1160 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1161 mode,
1162 adjusted_mode);
e2f0ba97 1163 }
32aad86f
CW		 1164
1165 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1166 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1167 */
6cc5f341
DV		 1168 pipe_config->pixel_multiplier =
1169 intel_sdvo_get_pixel_multiplier(adjusted_mode);
32aad86f 1170
630d30a4 1171 if (intel_sdvo_state->base.force_audio != HDMI_AUDIO_OFF_DVI)
b32962f8
ML		 1172 pipe_config->has_hdmi_sink = intel_sdvo->has_hdmi_monitor;
1173
630d30a4
ML		 1174 if (intel_sdvo_state->base.force_audio == HDMI_AUDIO_ON ||
1175 (intel_sdvo_state->base.force_audio == HDMI_AUDIO_AUTO && intel_sdvo->has_hdmi_audio))
b32962f8 1176 pipe_config->has_audio = true;
9f04003e 1177
630d30a4 1178 if (intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
55bc60db 1179 /* See CEA-861-E - 5.1 Default Encoding Parameters */
4f3a8bc7
PZ		 1180 /* FIXME: This bit is only valid when using TMDS encoding and 8
1181 * bit per color mode. */
9f04003e 1182 if (pipe_config->has_hdmi_sink &&
18316c8c 1183 drm_match_cea_mode(adjusted_mode) > 1)
69f5acc8
DV		 1184 pipe_config->limited_color_range = true;
1185 } else {
9f04003e 1186 if (pipe_config->has_hdmi_sink &&
630d30a4 1187 intel_sdvo_state->base.broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED)
69f5acc8 1188 pipe_config->limited_color_range = true;
55bc60db
VS		 1189 }
1190
70484559
DV		 1191 /* Clock computation needs to happen after pixel multiplier. */
1192 if (intel_sdvo->is_tv)
1193 i9xx_adjust_sdvo_tv_clock(pipe_config);
1194
7949dd47
VS		 1195 /* Set user selected PAR to incoming mode's member */
1196 if (intel_sdvo->is_hdmi)
0e9f25d0 1197 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
7949dd47 1198
e2f0ba97
JB		 1199 return true;
1200}
1201
630d30a4
ML		 1202#define UPDATE_PROPERTY(input, NAME) \
1203 do { \
1204 val = input; \
1205 intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_##NAME, &val, sizeof(val)); \
1206 } while (0)
1207
1208static void intel_sdvo_update_props(struct intel_sdvo *intel_sdvo,
5f88a9c6 1209 const struct intel_sdvo_connector_state *sdvo_state)
630d30a4 1210{
5f88a9c6 1211 const struct drm_connector_state *conn_state = &sdvo_state->base.base;
630d30a4
ML		 1212 struct intel_sdvo_connector *intel_sdvo_conn =
1213 to_intel_sdvo_connector(conn_state->connector);
1214 uint16_t val;
1215
1216 if (intel_sdvo_conn->left)
1217 UPDATE_PROPERTY(sdvo_state->tv.overscan_h, OVERSCAN_H);
1218
1219 if (intel_sdvo_conn->top)
1220 UPDATE_PROPERTY(sdvo_state->tv.overscan_v, OVERSCAN_V);
1221
1222 if (intel_sdvo_conn->hpos)
1223 UPDATE_PROPERTY(sdvo_state->tv.hpos, HPOS);
1224
1225 if (intel_sdvo_conn->vpos)
1226 UPDATE_PROPERTY(sdvo_state->tv.vpos, VPOS);
1227
1228 if (intel_sdvo_conn->saturation)
1229 UPDATE_PROPERTY(conn_state->tv.saturation, SATURATION);
1230
1231 if (intel_sdvo_conn->contrast)
1232 UPDATE_PROPERTY(conn_state->tv.contrast, CONTRAST);
1233
1234 if (intel_sdvo_conn->hue)
1235 UPDATE_PROPERTY(conn_state->tv.hue, HUE);
1236
1237 if (intel_sdvo_conn->brightness)
1238 UPDATE_PROPERTY(conn_state->tv.brightness, BRIGHTNESS);
1239
1240 if (intel_sdvo_conn->sharpness)
1241 UPDATE_PROPERTY(sdvo_state->tv.sharpness, SHARPNESS);
1242
1243 if (intel_sdvo_conn->flicker_filter)
1244 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter, FLICKER_FILTER);
1245
1246 if (intel_sdvo_conn->flicker_filter_2d)
1247 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_2d, FLICKER_FILTER_2D);
1248
1249 if (intel_sdvo_conn->flicker_filter_adaptive)
1250 UPDATE_PROPERTY(sdvo_state->tv.flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
1251
1252 if (intel_sdvo_conn->tv_chroma_filter)
1253 UPDATE_PROPERTY(sdvo_state->tv.chroma_filter, TV_CHROMA_FILTER);
1254
1255 if (intel_sdvo_conn->tv_luma_filter)
1256 UPDATE_PROPERTY(sdvo_state->tv.luma_filter, TV_LUMA_FILTER);
1257
1258 if (intel_sdvo_conn->dot_crawl)
1259 UPDATE_PROPERTY(sdvo_state->tv.dot_crawl, DOT_CRAWL);
1260
1261#undef UPDATE_PROPERTY
1262}
1263
fd6bbda9 1264static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
5f88a9c6
VS		 1265 const struct intel_crtc_state *crtc_state,
1266 const struct drm_connector_state *conn_state)
e2f0ba97 1267{
66478475 1268 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
f9fe0530
ML		 1269 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1270 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
5f88a9c6
VS		 1271 const struct intel_sdvo_connector_state *sdvo_state =
1272 to_intel_sdvo_connector_state(conn_state);
1273 const struct drm_display_mode *mode = &crtc_state->base.mode;
8aca63aa 1274 struct intel_sdvo *intel_sdvo = to_sdvo(intel_encoder);
6c9547ff 1275 u32 sdvox;
e2f0ba97 1276 struct intel_sdvo_in_out_map in_out;
6651819b 1277 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff 1278 int rate;
e2f0ba97 1279
630d30a4
ML		 1280 intel_sdvo_update_props(intel_sdvo, sdvo_state);
1281
e2f0ba97
JB		 1282 /* First, set the input mapping for the first input to our controlled
1283 * output. This is only correct if we're a single-input device, in
1284 * which case the first input is the output from the appropriate SDVO
1285 * channel on the motherboard. In a two-input device, the first input
1286 * will be SDVOB and the second SDVOC.
1287 */
ea5b213a 1288 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1289 in_out.in1 = 0;
1290
c74696b9
PR		 1291 intel_sdvo_set_value(intel_sdvo,
1292 SDVO_CMD_SET_IN_OUT_MAP,
1293 &in_out, sizeof(in_out));
e2f0ba97 1294
6c9547ff
CW		 1295 /* Set the output timings to the screen */
1296 if (!intel_sdvo_set_target_output(intel_sdvo,
1297 intel_sdvo->attached_output))
1298 return;
e2f0ba97 1299
6651819b
DV		 1300 /* lvds has a special fixed output timing. */
1301 if (intel_sdvo->is_lvds)
1302 intel_sdvo_get_dtd_from_mode(&output_dtd,
1303 intel_sdvo->sdvo_lvds_fixed_mode);
1304 else
1305 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1306 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1307 DRM_INFO("Setting output timings on %s failed\n",
1308 SDVO_NAME(intel_sdvo));
79e53945
JB		 1309
1310 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1311 if (!intel_sdvo_set_target_input(intel_sdvo))
1312 return;
79e53945 1313
f9fe0530 1314 if (crtc_state->has_hdmi_sink) {
97aaf910
CW		 1315 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1316 intel_sdvo_set_colorimetry(intel_sdvo,
1317 SDVO_COLORIMETRY_RGB256);
f9fe0530 1318 intel_sdvo_set_avi_infoframe(intel_sdvo, crtc_state);
97aaf910
CW		 1319 } else
1320 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1321
6c9547ff 1322 if (intel_sdvo->is_tv &&
630d30a4 1323 !intel_sdvo_set_tv_format(intel_sdvo, conn_state))
6c9547ff 1324 return;
e2f0ba97 1325
6651819b 1326 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
eeb47937 1327
e751823d
EE		 1328 if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
1329 input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
c8d4bb54
DV		 1330 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1331 DRM_INFO("Setting input timings on %s failed\n",
1332 SDVO_NAME(intel_sdvo));
79e53945 1333
f9fe0530 1334 switch (crtc_state->pixel_multiplier) {
6c9547ff 1335 default:
fd0753cf 1336 WARN(1, "unknown pixel multiplier specified\n");
32aad86f
CW		 1337 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1338 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1339 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1340 }
32aad86f
CW		 1341 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1342 return;
79e53945
JB		 1343
1344 /* Set the SDVO control regs. */
66478475 1345 if (INTEL_GEN(dev_priv) >= 4) {
ba68e086
PZ		 1346 /* The real mode polarity is set by the SDVO commands, using
1347 * struct intel_sdvo_dtd. */
1348 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
6e266956 1349 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
69f5acc8 1350 sdvox |= HDMI_COLOR_RANGE_16_235;
66478475 1351 if (INTEL_GEN(dev_priv) < 5)
6714afb1 1352 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1353 } else {
6c9547ff 1354 sdvox = I915_READ(intel_sdvo->sdvo_reg);
2a5c0832 1355 if (intel_sdvo->port == PORT_B)
e2f0ba97 1356 sdvox &= SDVOB_PRESERVE_MASK;
2a5c0832 1357 else
e2f0ba97 1358 sdvox &= SDVOC_PRESERVE_MASK;
e2f0ba97
JB		 1359 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1360 }
3573c410 1361
b9eb89b2 1362 if (HAS_PCH_CPT(dev_priv))
eeb47937 1363 sdvox |= SDVO_PIPE_SEL_CPT(crtc->pipe);
3573c410 1364 else
eeb47937 1365 sdvox |= SDVO_PIPE_SEL(crtc->pipe);
3573c410 1366
66478475 1367 if (INTEL_GEN(dev_priv) >= 4) {
e2f0ba97 1368 /* done in crtc_mode_set as the dpll_md reg must be written early */
50a0bc90 1369 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
73f67aa8 1370 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
e2f0ba97 1371 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1372 } else {
f9fe0530 1373 sdvox |= (crtc_state->pixel_multiplier - 1)
6cc5f341 1374 << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1375 }
1376
6714afb1 1377 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
66478475 1378 INTEL_GEN(dev_priv) < 5)
12682a97 1379 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1380 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1381}
1382
4ac41f47 1383static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
79e53945 1384{
4ac41f47
DV		 1385 struct intel_sdvo_connector *intel_sdvo_connector =
1386 to_intel_sdvo_connector(&connector->base);
1387 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
2f28c50b 1388 u16 active_outputs = 0;
4ac41f47
DV		 1389
1390 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
1391
1392 if (active_outputs & intel_sdvo_connector->output_flag)
1393 return true;
1394 else
1395 return false;
1396}
1397
1398static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
1399 enum pipe *pipe)
1400{
1401 struct drm_device *dev = encoder->base.dev;
fac5e23e 1402 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1403 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
2f28c50b 1404 u16 active_outputs = 0;
4ac41f47
DV		 1405 u32 tmp;
1406
1407 tmp = I915_READ(intel_sdvo->sdvo_reg);
7a7d1fb7 1408 intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
4ac41f47 1409
7a7d1fb7 1410 if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
4ac41f47
DV		 1411 return false;
1412
6e266956 1413 if (HAS_PCH_CPT(dev_priv))
4ac41f47
DV		 1414 *pipe = PORT_TO_PIPE_CPT(tmp);
1415 else
1416 *pipe = PORT_TO_PIPE(tmp);
1417
1418 return true;
1419}
1420
045ac3b5 1421static void intel_sdvo_get_config(struct intel_encoder *encoder,
5cec258b 1422 struct intel_crtc_state *pipe_config)
045ac3b5 1423{
6c49f241 1424 struct drm_device *dev = encoder->base.dev;
fac5e23e 1425 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1426 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
045ac3b5 1427 struct intel_sdvo_dtd dtd;
6c49f241 1428 int encoder_pixel_multiplier = 0;
18442d08 1429 int dotclock;
6c49f241
DV		 1430 u32 flags = 0, sdvox;
1431 u8 val;
045ac3b5
JB		 1432 bool ret;
1433
b5a9fa09
DV		 1434 sdvox = I915_READ(intel_sdvo->sdvo_reg);
1435
045ac3b5
JB		 1436 ret = intel_sdvo_get_input_timing(intel_sdvo, &dtd);
1437 if (!ret) {
bb760063
DV		 1438 /* Some sdvo encoders are not spec compliant and don't
1439 * implement the mandatory get_timings function. */
045ac3b5 1440 DRM_DEBUG_DRIVER("failed to retrieve SDVO DTD\n");
bb760063
DV		 1441 pipe_config->quirks |= PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS;
1442 } else {
1443 if (dtd.part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
1444 flags |= DRM_MODE_FLAG_PHSYNC;
1445 else
1446 flags |= DRM_MODE_FLAG_NHSYNC;
045ac3b5 1447
bb760063
DV		 1448 if (dtd.part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
1449 flags |= DRM_MODE_FLAG_PVSYNC;
1450 else
1451 flags |= DRM_MODE_FLAG_NVSYNC;
045ac3b5
JB		 1452 }
1453
2d112de7 1454 pipe_config->base.adjusted_mode.flags |= flags;
045ac3b5 1455
fdafa9e2
DV		 1456 /*
1457 * pixel multiplier readout is tricky: Only on i915g/gm it is stored in
1458 * the sdvo port register, on all other platforms it is part of the dpll
1459 * state. Since the general pipe state readout happens before the
1460 * encoder->get_config we so already have a valid pixel multplier on all
1461 * other platfroms.
1462 */
50a0bc90 1463 if (IS_I915G(dev_priv) || IS_I915GM(dev_priv)) {
6c49f241
DV		 1464 pipe_config->pixel_multiplier =
1465 ((sdvox & SDVO_PORT_MULTIPLY_MASK)
1466 >> SDVO_PORT_MULTIPLY_SHIFT) + 1;
1467 }
045ac3b5 1468
2b85886a 1469 dotclock = pipe_config->port_clock;
e3b247da 1470
2b85886a
VS		 1471 if (pipe_config->pixel_multiplier)
1472 dotclock /= pipe_config->pixel_multiplier;
18442d08 1473
2d112de7 1474 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
18442d08 1475
6c49f241 1476 /* Cross check the port pixel multiplier with the sdvo encoder state. */
53b91408
DL		 1477 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_CLOCK_RATE_MULT,
1478 &val, 1)) {
1479 switch (val) {
1480 case SDVO_CLOCK_RATE_MULT_1X:
1481 encoder_pixel_multiplier = 1;
1482 break;
1483 case SDVO_CLOCK_RATE_MULT_2X:
1484 encoder_pixel_multiplier = 2;
1485 break;
1486 case SDVO_CLOCK_RATE_MULT_4X:
1487 encoder_pixel_multiplier = 4;
1488 break;
1489 }
6c49f241 1490 }
fdafa9e2 1491
b5a9fa09
DV		 1492 if (sdvox & HDMI_COLOR_RANGE_16_235)
1493 pipe_config->limited_color_range = true;
1494
b106612f
VS		 1495 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_AUDIO_STAT,
1496 &val, 1)) {
1497 u8 mask = SDVO_AUDIO_ELD_VALID | SDVO_AUDIO_PRESENCE_DETECT;
1498
1499 if ((val & mask) == mask)
1500 pipe_config->has_audio = true;
1501 }
de44e256 1502
9f04003e
DV		 1503 if (intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ENCODE,
1504 &val, 1)) {
1505 if (val == SDVO_ENCODE_HDMI)
1506 pipe_config->has_hdmi_sink = true;
1507 }
1508
6c49f241
DV		 1509 WARN(encoder_pixel_multiplier != pipe_config->pixel_multiplier,
1510 "SDVO pixel multiplier mismatch, port: %i, encoder: %i\n",
1511 pipe_config->pixel_multiplier, encoder_pixel_multiplier);
045ac3b5
JB		 1512}
1513
b106612f
VS		 1514static void intel_sdvo_disable_audio(struct intel_sdvo *intel_sdvo)
1515{
1516 intel_sdvo_set_audio_state(intel_sdvo, 0);
1517}
1518
1519static void intel_sdvo_enable_audio(struct intel_sdvo *intel_sdvo,
1520 const struct intel_crtc_state *crtc_state,
1521 const struct drm_connector_state *conn_state)
1522{
1523 const struct drm_display_mode *adjusted_mode =
1524 &crtc_state->base.adjusted_mode;
1525 struct drm_connector *connector = conn_state->connector;
1526 u8 *eld = connector->eld;
1527
1528 eld[6] = drm_av_sync_delay(connector, adjusted_mode) / 2;
1529
1530 intel_sdvo_set_audio_state(intel_sdvo, 0);
1531
1532 intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_ELD,
1533 SDVO_HBUF_TX_DISABLED,
1534 eld, drm_eld_size(eld));
1535
1536 intel_sdvo_set_audio_state(intel_sdvo, SDVO_AUDIO_ELD_VALID |
1537 SDVO_AUDIO_PRESENCE_DETECT);
1538}
1539
fd6bbda9 1540static void intel_disable_sdvo(struct intel_encoder *encoder,
5f88a9c6
VS		 1541 const struct intel_crtc_state *old_crtc_state,
1542 const struct drm_connector_state *conn_state)
ce22c320 1543{
fac5e23e 1544 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
8aca63aa 1545 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
1612c8bd 1546 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
ce22c320
DV		 1547 u32 temp;
1548
b106612f
VS		 1549 if (old_crtc_state->has_audio)
1550 intel_sdvo_disable_audio(intel_sdvo);
1551
ce22c320
DV		 1552 intel_sdvo_set_active_outputs(intel_sdvo, 0);
1553 if (0)
1554 intel_sdvo_set_encoder_power_state(intel_sdvo,
1555 DRM_MODE_DPMS_OFF);
1556
1557 temp = I915_READ(intel_sdvo->sdvo_reg);
776ca7cf 1558
1612c8bd
VS		 1559 temp &= ~SDVO_ENABLE;
1560 intel_sdvo_write_sdvox(intel_sdvo, temp);
1561
1562 /*
1563 * HW workaround for IBX, we need to move the port
1564 * to transcoder A after disabling it to allow the
1565 * matching DP port to be enabled on transcoder A.
1566 */
1567 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
0c241d5b
VS		 1568 /*
1569 * We get CPU/PCH FIFO underruns on the other pipe when
1570 * doing the workaround. Sweep them under the rug.
1571 */
1572 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1573 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1574
1612c8bd
VS		 1575 temp &= ~SDVO_PIPE_B_SELECT;
1576 temp |= SDVO_ENABLE;
1577 intel_sdvo_write_sdvox(intel_sdvo, temp);
1578
1579 temp &= ~SDVO_ENABLE;
1580 intel_sdvo_write_sdvox(intel_sdvo, temp);
0c241d5b 1581
0f0f74bc 1582 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
0c241d5b
VS		 1583 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1584 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
ce22c320
DV		 1585 }
1586}
1587
fd6bbda9 1588static void pch_disable_sdvo(struct intel_encoder *encoder,
5f88a9c6
VS		 1589 const struct intel_crtc_state *old_crtc_state,
1590 const struct drm_connector_state *old_conn_state)
3c65d1d1
VS		 1591{
1592}
1593
fd6bbda9 1594static void pch_post_disable_sdvo(struct intel_encoder *encoder,
5f88a9c6
VS		 1595 const struct intel_crtc_state *old_crtc_state,
1596 const struct drm_connector_state *old_conn_state)
3c65d1d1 1597{
fd6bbda9 1598 intel_disable_sdvo(encoder, old_crtc_state, old_conn_state);
3c65d1d1
VS		 1599}
1600
fd6bbda9 1601static void intel_enable_sdvo(struct intel_encoder *encoder,
5f88a9c6
VS		 1602 const struct intel_crtc_state *pipe_config,
1603 const struct drm_connector_state *conn_state)
ce22c320
DV		 1604{
1605 struct drm_device *dev = encoder->base.dev;
fac5e23e 1606 struct drm_i915_private *dev_priv = to_i915(dev);
8aca63aa 1607 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
ce22c320 1608 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 1609 u32 temp;
ce22c320
DV		 1610 bool input1, input2;
1611 int i;
d0a7b6de 1612 bool success;
ce22c320
DV		 1613
1614 temp = I915_READ(intel_sdvo->sdvo_reg);
3c65d1d1
VS		 1615 temp |= SDVO_ENABLE;
1616 intel_sdvo_write_sdvox(intel_sdvo, temp);
776ca7cf 1617
ce22c320 1618 for (i = 0; i < 2; i++)
0f0f74bc 1619 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
ce22c320 1620
d0a7b6de 1621 success = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
ce22c320
DV		 1622 /* Warn if the device reported failure to sync.
1623 * A lot of SDVO devices fail to notify of sync, but it's
1624 * a given it the status is a success, we succeeded.
1625 */
d0a7b6de 1626 if (success && !input1) {
ce22c320
DV		 1627 DRM_DEBUG_KMS("First %s output reported failure to "
1628 "sync\n", SDVO_NAME(intel_sdvo));
1629 }
1630
1631 if (0)
1632 intel_sdvo_set_encoder_power_state(intel_sdvo,
1633 DRM_MODE_DPMS_ON);
1634 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
b106612f
VS		 1635
1636 if (pipe_config->has_audio)
1637 intel_sdvo_enable_audio(intel_sdvo, pipe_config, conn_state);
ce22c320
DV		 1638}
1639
c19de8eb
DL		 1640static enum drm_mode_status
1641intel_sdvo_mode_valid(struct drm_connector *connector,
1642 struct drm_display_mode *mode)
79e53945 1643{
df0e9248 1644 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
24b23882 1645 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
79e53945
JB		 1646
1647 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1648 return MODE_NO_DBLESCAN;
1649
ea5b213a 1650 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1651 return MODE_CLOCK_LOW;
1652
ea5b213a 1653 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1654 return MODE_CLOCK_HIGH;
1655
24b23882
MK		 1656 if (mode->clock > max_dotclk)
1657 return MODE_CLOCK_HIGH;
1658
8545423a 1659 if (intel_sdvo->is_lvds) {
ea5b213a 1660 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1661 return MODE_PANEL;
1662
ea5b213a 1663 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1664 return MODE_PANEL;
1665 }
1666
79e53945
JB		 1667 return MODE_OK;
1668}
1669
ea5b213a 1670static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1671{
1a3665c8 1672 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1673 if (!intel_sdvo_get_value(intel_sdvo,
1674 SDVO_CMD_GET_DEVICE_CAPS,
1675 caps, sizeof(*caps)))
1676 return false;
1677
1678 DRM_DEBUG_KMS("SDVO capabilities:\n"
1679 " vendor_id: %d\n"
1680 " device_id: %d\n"
1681 " device_rev_id: %d\n"
1682 " sdvo_version_major: %d\n"
1683 " sdvo_version_minor: %d\n"
1684 " sdvo_inputs_mask: %d\n"
1685 " smooth_scaling: %d\n"
1686 " sharp_scaling: %d\n"
1687 " up_scaling: %d\n"
1688 " down_scaling: %d\n"
1689 " stall_support: %d\n"
1690 " output_flags: %d\n",
1691 caps->vendor_id,
1692 caps->device_id,
1693 caps->device_rev_id,
1694 caps->sdvo_version_major,
1695 caps->sdvo_version_minor,
1696 caps->sdvo_inputs_mask,
1697 caps->smooth_scaling,
1698 caps->sharp_scaling,
1699 caps->up_scaling,
1700 caps->down_scaling,
1701 caps->stall_support,
1702 caps->output_flags);
1703
1704 return true;
79e53945
JB		 1705}
1706
5fa7ac9c 1707static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
79e53945 1708{
50a0bc90 1709 struct drm_i915_private *dev_priv = to_i915(intel_sdvo->base.base.dev);
5fa7ac9c 1710 uint16_t hotplug;
79e53945 1711
50a0bc90 1712 if (!I915_HAS_HOTPLUG(dev_priv))
1d83d957
VS		 1713 return 0;
1714
768b107e
DV		 1715 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1716 * on the line. */
50a0bc90 1717 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
5fa7ac9c 1718 return 0;
768b107e 1719
5fa7ac9c
JN		 1720 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1721 &hotplug, sizeof(hotplug)))
1722 return 0;
768b107e 1723
5fa7ac9c 1724 return hotplug;
79e53945
JB		 1725}
1726
cc68c81a 1727static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1728{
8aca63aa 1729 struct intel_sdvo *intel_sdvo = to_sdvo(encoder);
79e53945 1730
5fa7ac9c
JN		 1731 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
1732 &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1733}
1734
fb7a46f3 1735static bool
ea5b213a 1736intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1737{
bc65212c 1738 /* Is there more than one type of output? */
2294488d 1739 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1740}
1741
f899fc64 1742static struct edid *
e957d772 1743intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1744{
e957d772
CW		 1745 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1746 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1747}
1748
ff482d83
CW		 1749/* Mac mini hack -- use the same DDC as the analog connector */
1750static struct edid *
1751intel_sdvo_get_analog_edid(struct drm_connector *connector)
1752{
fac5e23e 1753 struct drm_i915_private *dev_priv = to_i915(connector->dev);
ff482d83 1754
0c1dab89 1755 return drm_get_edid(connector,
3bd7d909 1756 intel_gmbus_get_adapter(dev_priv,
41aa3448 1757 dev_priv->vbt.crt_ddc_pin));
ff482d83
CW		 1758}
1759
c43b5634 1760static enum drm_connector_status
8bf38485 1761intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1762{
df0e9248 1763 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1764 enum drm_connector_status status;
1765 struct edid *edid;
9dff6af8 1766
e957d772 1767 edid = intel_sdvo_get_edid(connector);
57cdaf90 1768
ea5b213a 1769 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1770 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1771
7c3f0a27
ZY		 1772 /*
1773 * Don't use the 1 as the argument of DDC bus switch to get
1774 * the EDID. It is used for SDVO SPD ROM.
1775 */
9d1a903d 1776 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1777 intel_sdvo->ddc_bus = ddc;
1778 edid = intel_sdvo_get_edid(connector);
1779 if (edid)
7c3f0a27 1780 break;
7c3f0a27 1781 }
e957d772
CW		 1782 /*
1783 * If we found the EDID on the other bus,
1784 * assume that is the correct DDC bus.
1785 */
1786 if (edid == NULL)
1787 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1788 }
9d1a903d
CW		 1789
1790 /*
1791 * When there is no edid and no monitor is connected with VGA
1792 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1793 */
ff482d83
CW		 1794 if (edid == NULL)
1795 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1796
2f551c84 1797 status = connector_status_unknown;
9dff6af8 1798 if (edid != NULL) {
149c36a3 1799 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1800 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1801 status = connector_status_connected;
da79de97
CW		 1802 if (intel_sdvo->is_hdmi) {
1803 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1804 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
abedc077
VS		 1805 intel_sdvo->rgb_quant_range_selectable =
1806 drm_rgb_quant_range_selectable(edid);
da79de97 1807 }
13946743
CW		 1808 } else
1809 status = connector_status_disconnected;
9d1a903d
CW		 1810 kfree(edid);
1811 }
7f36e7ed 1812
2b8d33f7 1813 return status;
9dff6af8
ML		 1814}
1815
52220085
CW		 1816static bool
1817intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1818 struct edid *edid)
1819{
1820 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1821 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1822
1823 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1824 connector_is_digital, monitor_is_digital);
1825 return connector_is_digital == monitor_is_digital;
1826}
1827
7b334fcb 1828static enum drm_connector_status
930a9e28 1829intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1830{
fb7a46f3 1831 uint16_t response;
df0e9248 1832 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1833 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1834 enum drm_connector_status ret;
79e53945 1835
164c8598 1836 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1837 connector->base.id, connector->name);
164c8598 1838
fc37381c
CW		 1839 if (!intel_sdvo_get_value(intel_sdvo,
1840 SDVO_CMD_GET_ATTACHED_DISPLAYS,
1841 &response, 2))
32aad86f 1842 return connector_status_unknown;
79e53945 1843
e957d772
CW		 1844 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1845 response & 0xff, response >> 8,
1846 intel_sdvo_connector->output_flag);
e2f0ba97 1847
fb7a46f3 1848 if (response == 0)
79e53945 1849 return connector_status_disconnected;
fb7a46f3 1850
ea5b213a 1851 intel_sdvo->attached_output = response;
14571b4c 1852
97aaf910
CW		 1853 intel_sdvo->has_hdmi_monitor = false;
1854 intel_sdvo->has_hdmi_audio = false;
abedc077 1855 intel_sdvo->rgb_quant_range_selectable = false;
97aaf910 1856
615fb93f 1857 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1858 ret = connector_status_disconnected;
13946743 1859 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1860 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1861 else {
1862 struct edid *edid;
1863
1864 /* if we have an edid check it matches the connection */
1865 edid = intel_sdvo_get_edid(connector);
1866 if (edid == NULL)
1867 edid = intel_sdvo_get_analog_edid(connector);
1868 if (edid != NULL) {
52220085
CW		 1869 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1870 edid))
13946743 1871 ret = connector_status_connected;
52220085
CW		 1872 else
1873 ret = connector_status_disconnected;
1874
13946743
CW		 1875 kfree(edid);
1876 } else
1877 ret = connector_status_connected;
1878 }
14571b4c
ZW		 1879
1880 /* May update encoder flag for like clock for SDVO TV, etc.*/
1881 if (ret == connector_status_connected) {
ea5b213a
CW		 1882 intel_sdvo->is_tv = false;
1883 intel_sdvo->is_lvds = false;
14571b4c 1884
09ede541 1885 if (response & SDVO_TV_MASK)
ea5b213a 1886 intel_sdvo->is_tv = true;
14571b4c 1887 if (response & SDVO_LVDS_MASK)
8545423a 1888 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1889 }
14571b4c
ZW		 1890
1891 return ret;
79e53945
JB		 1892}
1893
e2f0ba97 1894static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1895{
ff482d83 1896 struct edid *edid;
79e53945 1897
46a3f4a3 1898 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1899 connector->base.id, connector->name);
46a3f4a3 1900
79e53945 1901 /* set the bus switch and get the modes */
e957d772 1902 edid = intel_sdvo_get_edid(connector);
79e53945 1903
57cdaf90
KP		 1904 /*
1905 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1906 * link between analog and digital outputs. So, if the regular SDVO
1907 * DDC fails, check to see if the analog output is disconnected, in
1908 * which case we'll look there for the digital DDC data.
e2f0ba97 1909 */
f899fc64
CW		 1910 if (edid == NULL)
1911 edid = intel_sdvo_get_analog_edid(connector);
1912
ff482d83 1913 if (edid != NULL) {
52220085
CW		 1914 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1915 edid)) {
0c1dab89
CW		 1916 drm_mode_connector_update_edid_property(connector, edid);
1917 drm_add_edid_modes(connector, edid);
1918 }
13946743 1919
ff482d83 1920 kfree(edid);
e2f0ba97 1921 }
e2f0ba97
JB		 1922}
1923
1924/*
1925 * Set of SDVO TV modes.
1926 * Note! This is in reply order (see loop in get_tv_modes).
1927 * XXX: all 60Hz refresh?
1928 */
b1f559ec 1929static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1930 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1931 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1933 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1934 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1935 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1936 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1937 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1938 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1939 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1940 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1941 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1942 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1943 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1944 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1945 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1946 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1947 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1948 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1949 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1950 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1951 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1952 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1953 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1954 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1955 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1956 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1957 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1958 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1959 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1960 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1961 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1962 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1963 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1964 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1965 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1966 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1967 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1968 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1969 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1970 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1971 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1972 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1973 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1974 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1975 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1976 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1977 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1978 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1979 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1980 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1981 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1982 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1983 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1984 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1985 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1986 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1987};
1988
1989static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1990{
df0e9248 1991 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
630d30a4 1992 const struct drm_connector_state *conn_state = connector->state;
7026d4ac 1993 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1994 uint32_t reply = 0, format_map = 0;
1995 int i;
e2f0ba97 1996
46a3f4a3 1997 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 1998 connector->base.id, connector->name);
46a3f4a3 1999
e2f0ba97
JB		 2000 /* Read the list of supported input resolutions for the selected TV
2001 * format.
2002 */
630d30a4 2003 format_map = 1 << conn_state->tv.mode;
ce6feabd 2004 memcpy(&tv_res, &format_map,
32aad86f 2005 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 2006
32aad86f
CW		 2007 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
2008 return;
ce6feabd 2009
32aad86f 2010 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 2011 if (!intel_sdvo_write_cmd(intel_sdvo,
2012 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 2013 &tv_res, sizeof(tv_res)))
2014 return;
2015 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 2016 return;
2017
2018 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 2019 if (reply & (1 << i)) {
2020 struct drm_display_mode *nmode;
2021 nmode = drm_mode_duplicate(connector->dev,
32aad86f 2022 &sdvo_tv_modes[i]);
7026d4ac
ZW		 2023 if (nmode)
2024 drm_mode_probed_add(connector, nmode);
2025 }
e2f0ba97
JB		 2026}
2027
7086c87f
ML		 2028static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
2029{
df0e9248 2030 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
fac5e23e 2031 struct drm_i915_private *dev_priv = to_i915(connector->dev);
12682a97 2032 struct drm_display_mode *newmode;
7086c87f 2033
46a3f4a3 2034 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 2035 connector->base.id, connector->name);
46a3f4a3 2036
7086c87f 2037 /*
c3456fb3 2038 * Fetch modes from VBT. For SDVO prefer the VBT mode since some
4300a0f8 2039 * SDVO->LVDS transcoders can't cope with the EDID mode.
7086c87f 2040 */
41aa3448 2041 if (dev_priv->vbt.sdvo_lvds_vbt_mode != NULL) {
7086c87f 2042 newmode = drm_mode_duplicate(connector->dev,
41aa3448 2043 dev_priv->vbt.sdvo_lvds_vbt_mode);
7086c87f
ML		 2044 if (newmode != NULL) {
2045 /* Guarantee the mode is preferred */
2046 newmode->type = (DRM_MODE_TYPE_PREFERRED |
2047 DRM_MODE_TYPE_DRIVER);
2048 drm_mode_probed_add(connector, newmode);
2049 }
2050 }
12682a97 2051
4300a0f8
DA		 2052 /*
2053 * Attempt to get the mode list from DDC.
2054 * Assume that the preferred modes are
2055 * arranged in priority order.
2056 */
2057 intel_ddc_get_modes(connector, &intel_sdvo->ddc);
2058
12682a97 2059 list_for_each_entry(newmode, &connector->probed_modes, head) {
2060 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 2061 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 2062 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 2063
8545423a 2064 intel_sdvo->is_lvds = true;
12682a97 2065 break;
2066 }
2067 }
7086c87f
ML		 2068}
2069
e2f0ba97
JB		 2070static int intel_sdvo_get_modes(struct drm_connector *connector)
2071{
615fb93f 2072 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 2073
615fb93f 2074 if (IS_TV(intel_sdvo_connector))
e2f0ba97 2075 intel_sdvo_get_tv_modes(connector);
615fb93f 2076 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 2077 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 2078 else
2079 intel_sdvo_get_ddc_modes(connector);
2080
32aad86f 2081 return !list_empty(&connector->probed_modes);
79e53945
JB		 2082}
2083
2084static void intel_sdvo_destroy(struct drm_connector *connector)
2085{
615fb93f 2086 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 2087
79e53945 2088 drm_connector_cleanup(connector);
4b745b1e 2089 kfree(intel_sdvo_connector);
79e53945
JB		 2090}
2091
ce6feabd 2092static int
630d30a4
ML		 2093intel_sdvo_connector_atomic_get_property(struct drm_connector *connector,
2094 const struct drm_connector_state *state,
2095 struct drm_property *property,
2096 uint64_t *val)
ce6feabd 2097{
615fb93f 2098 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
630d30a4 2099 const struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state((void *)state);
c5521706
CW		 2100
2101 if (property == intel_sdvo_connector->tv_format) {
630d30a4 2102 int i;
b9219c5e 2103
630d30a4
ML		 2104 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
2105 if (state->tv.mode == intel_sdvo_connector->tv_format_supported[i]) {
2106 *val = i;
b9219c5e 2107
32aad86f 2108 return 0;
630d30a4 2109 }
b9219c5e 2110
630d30a4
ML		 2111 WARN_ON(1);
2112 *val = 0;
2113 } else if (property == intel_sdvo_connector->top ||
2114 property == intel_sdvo_connector->bottom)
2115 *val = intel_sdvo_connector->max_vscan - sdvo_state->tv.overscan_v;
2116 else if (property == intel_sdvo_connector->left ||
2117 property == intel_sdvo_connector->right)
2118 *val = intel_sdvo_connector->max_hscan - sdvo_state->tv.overscan_h;
2119 else if (property == intel_sdvo_connector->hpos)
2120 *val = sdvo_state->tv.hpos;
2121 else if (property == intel_sdvo_connector->vpos)
2122 *val = sdvo_state->tv.vpos;
2123 else if (property == intel_sdvo_connector->saturation)
2124 *val = state->tv.saturation;
2125 else if (property == intel_sdvo_connector->contrast)
2126 *val = state->tv.contrast;
2127 else if (property == intel_sdvo_connector->hue)
2128 *val = state->tv.hue;
2129 else if (property == intel_sdvo_connector->brightness)
2130 *val = state->tv.brightness;
2131 else if (property == intel_sdvo_connector->sharpness)
2132 *val = sdvo_state->tv.sharpness;
2133 else if (property == intel_sdvo_connector->flicker_filter)
2134 *val = sdvo_state->tv.flicker_filter;
2135 else if (property == intel_sdvo_connector->flicker_filter_2d)
2136 *val = sdvo_state->tv.flicker_filter_2d;
2137 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2138 *val = sdvo_state->tv.flicker_filter_adaptive;
2139 else if (property == intel_sdvo_connector->tv_chroma_filter)
2140 *val = sdvo_state->tv.chroma_filter;
2141 else if (property == intel_sdvo_connector->tv_luma_filter)
2142 *val = sdvo_state->tv.luma_filter;
2143 else if (property == intel_sdvo_connector->dot_crawl)
2144 *val = sdvo_state->tv.dot_crawl;
2145 else
2146 return intel_digital_connector_atomic_get_property(connector, state, property, val);
32aad86f 2147
630d30a4
ML		 2148 return 0;
2149}
b9219c5e 2150
630d30a4
ML		 2151static int
2152intel_sdvo_connector_atomic_set_property(struct drm_connector *connector,
2153 struct drm_connector_state *state,
2154 struct drm_property *property,
2155 uint64_t val)
2156{
2157 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
2158 struct intel_sdvo_connector_state *sdvo_state = to_intel_sdvo_connector_state(state);
b9219c5e 2159
630d30a4
ML		 2160 if (property == intel_sdvo_connector->tv_format) {
2161 state->tv.mode = intel_sdvo_connector->tv_format_supported[val];
b9219c5e 2162
630d30a4
ML		 2163 if (state->crtc) {
2164 struct drm_crtc_state *crtc_state =
2165 drm_atomic_get_new_crtc_state(state->state, state->crtc);
b9219c5e 2166
630d30a4
ML		 2167 crtc_state->connectors_changed = true;
2168 }
2169 } else if (property == intel_sdvo_connector->top ||
2170 property == intel_sdvo_connector->bottom)
2171 /* Cannot set these independent from each other */
2172 sdvo_state->tv.overscan_v = intel_sdvo_connector->max_vscan - val;
2173 else if (property == intel_sdvo_connector->left ||
2174 property == intel_sdvo_connector->right)
2175 /* Cannot set these independent from each other */
2176 sdvo_state->tv.overscan_h = intel_sdvo_connector->max_hscan - val;
2177 else if (property == intel_sdvo_connector->hpos)
2178 sdvo_state->tv.hpos = val;
2179 else if (property == intel_sdvo_connector->vpos)
2180 sdvo_state->tv.vpos = val;
2181 else if (property == intel_sdvo_connector->saturation)
2182 state->tv.saturation = val;
2183 else if (property == intel_sdvo_connector->contrast)
2184 state->tv.contrast = val;
2185 else if (property == intel_sdvo_connector->hue)
2186 state->tv.hue = val;
2187 else if (property == intel_sdvo_connector->brightness)
2188 state->tv.brightness = val;
2189 else if (property == intel_sdvo_connector->sharpness)
2190 sdvo_state->tv.sharpness = val;
2191 else if (property == intel_sdvo_connector->flicker_filter)
2192 sdvo_state->tv.flicker_filter = val;
2193 else if (property == intel_sdvo_connector->flicker_filter_2d)
2194 sdvo_state->tv.flicker_filter_2d = val;
2195 else if (property == intel_sdvo_connector->flicker_filter_adaptive)
2196 sdvo_state->tv.flicker_filter_adaptive = val;
2197 else if (property == intel_sdvo_connector->tv_chroma_filter)
2198 sdvo_state->tv.chroma_filter = val;
2199 else if (property == intel_sdvo_connector->tv_luma_filter)
2200 sdvo_state->tv.luma_filter = val;
2201 else if (property == intel_sdvo_connector->dot_crawl)
2202 sdvo_state->tv.dot_crawl = val;
2203 else
2204 return intel_digital_connector_atomic_set_property(connector, state, property, val);
c5521706 2205
32aad86f 2206 return 0;
ce6feabd
ZY		 2207}
2208
7a418e34
CW		 2209static int
2210intel_sdvo_connector_register(struct drm_connector *connector)
2211{
2212 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1ebaa0b9
CW		 2213 int ret;
2214
2215 ret = intel_connector_register(connector);
2216 if (ret)
2217 return ret;
7a418e34
CW		 2218
2219 return sysfs_create_link(&connector->kdev->kobj,
2220 &sdvo->ddc.dev.kobj,
2221 sdvo->ddc.dev.kobj.name);
2222}
2223
c191eca1
CW		 2224static void
2225intel_sdvo_connector_unregister(struct drm_connector *connector)
2226{
2227 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
2228
2229 sysfs_remove_link(&connector->kdev->kobj,
2230 sdvo->ddc.dev.kobj.name);
2231 intel_connector_unregister(connector);
2232}
2233
630d30a4
ML		 2234static struct drm_connector_state *
2235intel_sdvo_connector_duplicate_state(struct drm_connector *connector)
2236{
2237 struct intel_sdvo_connector_state *state;
2238
2239 state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
2240 if (!state)
2241 return NULL;
2242
2243 __drm_atomic_helper_connector_duplicate_state(connector, &state->base.base);
2244 return &state->base.base;
2245}
2246
79e53945 2247static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
79e53945
JB		 2248 .detect = intel_sdvo_detect,
2249 .fill_modes = drm_helper_probe_single_connector_modes,
630d30a4
ML		 2250 .atomic_get_property = intel_sdvo_connector_atomic_get_property,
2251 .atomic_set_property = intel_sdvo_connector_atomic_set_property,
7a418e34 2252 .late_register = intel_sdvo_connector_register,
c191eca1 2253 .early_unregister = intel_sdvo_connector_unregister,
79e53945 2254 .destroy = intel_sdvo_destroy,
c6f95f27 2255 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
630d30a4 2256 .atomic_duplicate_state = intel_sdvo_connector_duplicate_state,
79e53945
JB		 2257};
2258
630d30a4
ML		 2259static int intel_sdvo_atomic_check(struct drm_connector *conn,
2260 struct drm_connector_state *new_conn_state)
2261{
2262 struct drm_atomic_state *state = new_conn_state->state;
2263 struct drm_connector_state *old_conn_state =
2264 drm_atomic_get_old_connector_state(state, conn);
2265 struct intel_sdvo_connector_state *old_state =
2266 to_intel_sdvo_connector_state(old_conn_state);
2267 struct intel_sdvo_connector_state *new_state =
2268 to_intel_sdvo_connector_state(new_conn_state);
2269
2270 if (new_conn_state->crtc &&
2271 (memcmp(&old_state->tv, &new_state->tv, sizeof(old_state->tv)) ||
2272 memcmp(&old_conn_state->tv, &new_conn_state->tv, sizeof(old_conn_state->tv)))) {
2273 struct drm_crtc_state *crtc_state =
2274 drm_atomic_get_new_crtc_state(new_conn_state->state,
2275 new_conn_state->crtc);
2276
2277 crtc_state->connectors_changed = true;
2278 }
2279
2280 return intel_digital_connector_atomic_check(conn, new_conn_state);
2281}
2282
79e53945
JB		 2283static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2284 .get_modes = intel_sdvo_get_modes,
2285 .mode_valid = intel_sdvo_mode_valid,
630d30a4 2286 .atomic_check = intel_sdvo_atomic_check,
79e53945
JB		 2287};
2288
b358d0a6 2289static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 2290{
8aca63aa 2291 struct intel_sdvo *intel_sdvo = to_sdvo(to_intel_encoder(encoder));
d2a82a6f 2292
ea5b213a 2293 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 2294 drm_mode_destroy(encoder->dev,
ea5b213a 2295 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 2296
e957d772 2297 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2298 intel_encoder_destroy(encoder);
79e53945
JB		 2299}
2300
2301static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2302 .destroy = intel_sdvo_enc_destroy,
2303};
2304
b66d8424
CW		 2305static void
2306intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
2307{
2308 uint16_t mask = 0;
2309 unsigned int num_bits;
2310
2311 /* Make a mask of outputs less than or equal to our own priority in the
2312 * list.
2313 */
2314 switch (sdvo->controlled_output) {
2315 case SDVO_OUTPUT_LVDS1:
2316 mask |= SDVO_OUTPUT_LVDS1;
2317 case SDVO_OUTPUT_LVDS0:
2318 mask |= SDVO_OUTPUT_LVDS0;
2319 case SDVO_OUTPUT_TMDS1:
2320 mask |= SDVO_OUTPUT_TMDS1;
2321 case SDVO_OUTPUT_TMDS0:
2322 mask |= SDVO_OUTPUT_TMDS0;
2323 case SDVO_OUTPUT_RGB1:
2324 mask |= SDVO_OUTPUT_RGB1;
2325 case SDVO_OUTPUT_RGB0:
2326 mask |= SDVO_OUTPUT_RGB0;
2327 break;
2328 }
2329
2330 /* Count bits to find what number we are in the priority list. */
2331 mask &= sdvo->caps.output_flags;
2332 num_bits = hweight16(mask);
2333 /* If more than 3 outputs, default to DDC bus 3 for now. */
2334 if (num_bits > 3)
2335 num_bits = 3;
2336
2337 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2338 sdvo->ddc_bus = 1 << num_bits;
2339}
79e53945 2340
e2f0ba97
JB		 2341/**
2342 * Choose the appropriate DDC bus for control bus switch command for this
2343 * SDVO output based on the controlled output.
2344 *
2345 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2346 * outputs, then LVDS outputs.
2347 */
2348static void
b1083333 2349intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
8bd864b8 2350 struct intel_sdvo *sdvo)
e2f0ba97 2351{
b1083333 2352 struct sdvo_device_mapping *mapping;
e2f0ba97 2353
2a5c0832 2354 if (sdvo->port == PORT_B)
9d6c875d 2355 mapping = &dev_priv->vbt.sdvo_mappings[0];
b1083333 2356 else
9d6c875d 2357 mapping = &dev_priv->vbt.sdvo_mappings[1];
e2f0ba97 2358
b66d8424
CW		 2359 if (mapping->initialized)
2360 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
2361 else
2362 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 2363}
2364
e957d772
CW		 2365static void
2366intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
8bd864b8 2367 struct intel_sdvo *sdvo)
e957d772
CW		 2368{
2369 struct sdvo_device_mapping *mapping;
46eb3036 2370 u8 pin;
e957d772 2371
2a5c0832 2372 if (sdvo->port == PORT_B)
9d6c875d 2373 mapping = &dev_priv->vbt.sdvo_mappings[0];
e957d772 2374 else
9d6c875d 2375 mapping = &dev_priv->vbt.sdvo_mappings[1];
e957d772 2376
88ac7939
JN		 2377 if (mapping->initialized &&
2378 intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
e957d772 2379 pin = mapping->i2c_pin;
6cb1612a 2380 else
988c7015 2381 pin = GMBUS_PIN_DPB;
e957d772 2382
6cb1612a
JN		 2383 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
2384
2385 /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
2386 * our code totally fails once we start using gmbus. Hence fall back to
2387 * bit banging for now. */
2388 intel_gmbus_force_bit(sdvo->i2c, true);
e957d772
CW		 2389}
2390
fbfcc4f3
JN		 2391/* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
2392static void
2393intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
2394{
2395 intel_gmbus_force_bit(sdvo->i2c, false);
e957d772
CW		 2396}
2397
e2f0ba97 2398static bool
e27d8538 2399intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 2400{
97aaf910 2401 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 2402}
2403
714605e4 2404static u8
c39055b0
ACO		 2405intel_sdvo_get_slave_addr(struct drm_i915_private *dev_priv,
2406 struct intel_sdvo *sdvo)
714605e4 2407{
714605e4 2408 struct sdvo_device_mapping *my_mapping, *other_mapping;
2409
2a5c0832 2410 if (sdvo->port == PORT_B) {
9d6c875d
JN		 2411 my_mapping = &dev_priv->vbt.sdvo_mappings[0];
2412 other_mapping = &dev_priv->vbt.sdvo_mappings[1];
714605e4 2413 } else {
9d6c875d
JN		 2414 my_mapping = &dev_priv->vbt.sdvo_mappings[1];
2415 other_mapping = &dev_priv->vbt.sdvo_mappings[0];
714605e4 2416 }
2417
2418 /* If the BIOS described our SDVO device, take advantage of it. */
2419 if (my_mapping->slave_addr)
2420 return my_mapping->slave_addr;
2421
2422 /* If the BIOS only described a different SDVO device, use the
2423 * address that it isn't using.
2424 */
2425 if (other_mapping->slave_addr) {
2426 if (other_mapping->slave_addr == 0x70)
2427 return 0x72;
2428 else
2429 return 0x70;
2430 }
2431
2432 /* No SDVO device info is found for another DVO port,
2433 * so use mapping assumption we had before BIOS parsing.
2434 */
2a5c0832 2435 if (sdvo->port == PORT_B)
714605e4 2436 return 0x70;
2437 else
2438 return 0x72;
2439}
2440
c393454d 2441static int
df0e9248
CW		 2442intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2443 struct intel_sdvo *encoder)
14571b4c 2444{
c393454d
ID		 2445 struct drm_connector *drm_connector;
2446 int ret;
2447
2448 drm_connector = &connector->base.base;
2449 ret = drm_connector_init(encoder->base.base.dev,
2450 drm_connector,
df0e9248
CW		 2451 &intel_sdvo_connector_funcs,
2452 connector->base.base.connector_type);
c393454d
ID		 2453 if (ret < 0)
2454 return ret;
6070a4a9 2455
c393454d 2456 drm_connector_helper_add(drm_connector,
df0e9248 2457 &intel_sdvo_connector_helper_funcs);
14571b4c 2458
8f4839e2 2459 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2460 connector->base.base.doublescan_allowed = 0;
2461 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
4ac41f47 2462 connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
14571b4c 2463
df0e9248 2464 intel_connector_attach_encoder(&connector->base, &encoder->base);
c393454d
ID		 2465
2466 return 0;
14571b4c 2467}
6070a4a9 2468
7f36e7ed 2469static void
55bc60db
VS		 2470intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
2471 struct intel_sdvo_connector *connector)
7f36e7ed 2472{
646d5772 2473 struct drm_i915_private *dev_priv = to_i915(connector->base.base.dev);
7f36e7ed 2474
3f43c48d 2475 intel_attach_force_audio_property(&connector->base.base);
646d5772 2476 if (INTEL_GEN(dev_priv) >= 4 && IS_MOBILE(dev_priv)) {
e953fd7b 2477 intel_attach_broadcast_rgb_property(&connector->base.base);
55bc60db 2478 }
7949dd47 2479 intel_attach_aspect_ratio_property(&connector->base.base);
0e9f25d0 2480 connector->base.base.state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
7f36e7ed
CW		 2481}
2482
08d9bc92
ACO		 2483static struct intel_sdvo_connector *intel_sdvo_connector_alloc(void)
2484{
2485 struct intel_sdvo_connector *sdvo_connector;
630d30a4 2486 struct intel_sdvo_connector_state *conn_state;
08d9bc92
ACO		 2487
2488 sdvo_connector = kzalloc(sizeof(*sdvo_connector), GFP_KERNEL);
2489 if (!sdvo_connector)
2490 return NULL;
2491
630d30a4
ML		 2492 conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL);
2493 if (!conn_state) {
08d9bc92
ACO		 2494 kfree(sdvo_connector);
2495 return NULL;
2496 }
2497
630d30a4
ML		 2498 __drm_atomic_helper_connector_reset(&sdvo_connector->base.base,
2499 &conn_state->base.base);
2500
08d9bc92
ACO		 2501 return sdvo_connector;
2502}
2503
fb7a46f3 2504static bool
ea5b213a 2505intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2506{
4ef69c7a 2507 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2508 struct drm_connector *connector;
cc68c81a 2509 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2510 struct intel_connector *intel_connector;
615fb93f 2511 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2512
46a3f4a3
CW		 2513 DRM_DEBUG_KMS("initialising DVI device %d\n", device);
2514
08d9bc92 2515 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f 2516 if (!intel_sdvo_connector)
14571b4c
ZW		 2517 return false;
2518
14571b4c 2519 if (device == 0) {
ea5b213a 2520 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2521 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2522 } else if (device == 1) {
ea5b213a 2523 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2524 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2525 }
2526
615fb93f 2527 intel_connector = &intel_sdvo_connector->base;
14571b4c 2528 connector = &intel_connector->base;
5fa7ac9c
JN		 2529 if (intel_sdvo_get_hotplug_support(intel_sdvo) &
2530 intel_sdvo_connector->output_flag) {
5fa7ac9c 2531 intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
cc68c81a
SF		 2532 /* Some SDVO devices have one-shot hotplug interrupts.
2533 * Ensure that they get re-enabled when an interrupt happens.
2534 */
2535 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
3a2fb2c3 2536 intel_sdvo_enable_hotplug(intel_encoder);
5fa7ac9c 2537 } else {
821450c6 2538 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
5fa7ac9c 2539 }
14571b4c
ZW		 2540 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2541 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2542
b106612f 2543 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2544 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2545 intel_sdvo->is_hdmi = true;
14571b4c 2546 }
14571b4c 2547
c393454d
ID		 2548 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2549 kfree(intel_sdvo_connector);
2550 return false;
2551 }
2552
f797d221 2553 if (intel_sdvo->is_hdmi)
55bc60db 2554 intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
14571b4c
ZW		 2555
2556 return true;
2557}
2558
2559static bool
ea5b213a 2560intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2561{
4ef69c7a
CW		 2562 struct drm_encoder *encoder = &intel_sdvo->base.base;
2563 struct drm_connector *connector;
2564 struct intel_connector *intel_connector;
2565 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2566
46a3f4a3
CW		 2567 DRM_DEBUG_KMS("initialising TV type %d\n", type);
2568
08d9bc92 2569 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2570 if (!intel_sdvo_connector)
2571 return false;
14571b4c 2572
615fb93f 2573 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2574 connector = &intel_connector->base;
2575 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2576 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2577
4ef69c7a
CW		 2578 intel_sdvo->controlled_output |= type;
2579 intel_sdvo_connector->output_flag = type;
14571b4c 2580
4ef69c7a 2581 intel_sdvo->is_tv = true;
14571b4c 2582
c393454d
ID		 2583 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2584 kfree(intel_sdvo_connector);
2585 return false;
2586 }
14571b4c 2587
4ef69c7a 2588 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2589 goto err;
14571b4c 2590
4ef69c7a 2591 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2592 goto err;
14571b4c 2593
4ef69c7a 2594 return true;
32aad86f
CW		 2595
2596err:
123d5c01 2597 intel_sdvo_destroy(connector);
32aad86f 2598 return false;
14571b4c
ZW		 2599}
2600
2601static bool
ea5b213a 2602intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2603{
4ef69c7a
CW		 2604 struct drm_encoder *encoder = &intel_sdvo->base.base;
2605 struct drm_connector *connector;
2606 struct intel_connector *intel_connector;
2607 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2608
46a3f4a3
CW		 2609 DRM_DEBUG_KMS("initialising analog device %d\n", device);
2610
8ce7da47 2611 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2612 if (!intel_sdvo_connector)
2613 return false;
14571b4c 2614
615fb93f 2615 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2616 connector = &intel_connector->base;
821450c6 2617 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2618 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2619 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2620
2621 if (device == 0) {
2622 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2623 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2624 } else if (device == 1) {
2625 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2626 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2627 }
2628
c393454d
ID		 2629 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2630 kfree(intel_sdvo_connector);
2631 return false;
2632 }
2633
4ef69c7a 2634 return true;
14571b4c
ZW		 2635}
2636
2637static bool
ea5b213a 2638intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2639{
4ef69c7a
CW		 2640 struct drm_encoder *encoder = &intel_sdvo->base.base;
2641 struct drm_connector *connector;
2642 struct intel_connector *intel_connector;
2643 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2644
46a3f4a3
CW		 2645 DRM_DEBUG_KMS("initialising LVDS device %d\n", device);
2646
08d9bc92 2647 intel_sdvo_connector = intel_sdvo_connector_alloc();
615fb93f
CW		 2648 if (!intel_sdvo_connector)
2649 return false;
14571b4c 2650
615fb93f
CW		 2651 intel_connector = &intel_sdvo_connector->base;
2652 connector = &intel_connector->base;
4ef69c7a
CW		 2653 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2654 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2655
2656 if (device == 0) {
2657 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2658 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2659 } else if (device == 1) {
2660 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2661 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2662 }
2663
c393454d
ID		 2664 if (intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo) < 0) {
2665 kfree(intel_sdvo_connector);
2666 return false;
2667 }
2668
4ef69c7a 2669 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2670 goto err;
2671
2672 return true;
2673
2674err:
123d5c01 2675 intel_sdvo_destroy(connector);
32aad86f 2676 return false;
14571b4c
ZW		 2677}
2678
2679static bool
ea5b213a 2680intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2681{
ea5b213a 2682 intel_sdvo->is_tv = false;
ea5b213a 2683 intel_sdvo->is_lvds = false;
fb7a46f3 2684
14571b4c 2685 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2686
14571b4c 2687 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2688 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2689 return false;
2690
2691 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2692 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2693 return false;
2694
2695 /* TV has no XXX1 function block */
a1f4b7ff 2696 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2697 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2698 return false;
2699
2700 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2701 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2702 return false;
fb7a46f3 2703
a0b1c7a5
CW		 2704 if (flags & SDVO_OUTPUT_YPRPB0)
2705 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2706 return false;
2707
14571b4c 2708 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2709 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2710 return false;
2711
2712 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2713 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2714 return false;
2715
2716 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2717 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2718 return false;
2719
2720 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2721 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2722 return false;
fb7a46f3 2723
14571b4c 2724 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2725 unsigned char bytes[2];
2726
ea5b213a
CW		 2727 intel_sdvo->controlled_output = 0;
2728 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2729 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2730 SDVO_NAME(intel_sdvo),
51c8b407 2731 bytes[0], bytes[1]);
14571b4c 2732 return false;
fb7a46f3 2733 }
27f8227b 2734 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2735
14571b4c 2736 return true;
fb7a46f3 2737}
2738
d0ddfbd3
JN		 2739static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
2740{
2741 struct drm_device *dev = intel_sdvo->base.base.dev;
2742 struct drm_connector *connector, *tmp;
2743
2744 list_for_each_entry_safe(connector, tmp,
2745 &dev->mode_config.connector_list, head) {
d9255d57 2746 if (intel_attached_encoder(connector) == &intel_sdvo->base) {
34ea3d38 2747 drm_connector_unregister(connector);
d0ddfbd3 2748 intel_sdvo_destroy(connector);
d9255d57 2749 }
d0ddfbd3
JN		 2750 }
2751}
2752
32aad86f
CW		 2753static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2754 struct intel_sdvo_connector *intel_sdvo_connector,
2755 int type)
ce6feabd 2756{
4ef69c7a 2757 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2758 struct intel_sdvo_tv_format format;
2759 uint32_t format_map, i;
ce6feabd 2760
32aad86f
CW		 2761 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2762 return false;
ce6feabd 2763
1a3665c8 2764 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2765 if (!intel_sdvo_get_value(intel_sdvo,
2766 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2767 &format, sizeof(format)))
2768 return false;
ce6feabd 2769
32aad86f 2770 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2771
2772 if (format_map == 0)
32aad86f 2773 return false;
ce6feabd 2774
615fb93f 2775 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2776 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2777 if (format_map & (1 << i))
2778 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2779
2780
c5521706 2781 intel_sdvo_connector->tv_format =
32aad86f
CW		 2782 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2783 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2784 if (!intel_sdvo_connector->tv_format)
fcc8d672 2785 return false;
ce6feabd 2786
615fb93f 2787 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2788 drm_property_add_enum(
c5521706 2789 intel_sdvo_connector->tv_format, i,
40039750 2790 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2791
630d30a4 2792 intel_sdvo_connector->base.base.state->tv.mode = intel_sdvo_connector->tv_format_supported[0];
10223df2
VS		 2793 drm_object_attach_property(&intel_sdvo_connector->base.base.base,
2794 intel_sdvo_connector->tv_format, 0);
32aad86f 2795 return true;
ce6feabd
ZY		 2796
2797}
2798
630d30a4 2799#define _ENHANCEMENT(state_assignment, name, NAME) do { \
c5521706
CW		 2800 if (enhancements.name) { \
2801 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2802 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2803 return false; \
c5521706 2804 intel_sdvo_connector->name = \
d9bc3c02 2805 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2806 if (!intel_sdvo_connector->name) return false; \
630d30a4 2807 state_assignment = response; \
662595df 2808 drm_object_attach_property(&connector->base, \
630d30a4 2809 intel_sdvo_connector->name, 0); \
c5521706
CW		 2810 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2811 data_value[0], data_value[1], response); \
2812 } \
0206e353 2813} while (0)
c5521706 2814
630d30a4
ML		 2815#define ENHANCEMENT(state, name, NAME) _ENHANCEMENT((state)->name, name, NAME)
2816
c5521706
CW		 2817static bool
2818intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2819 struct intel_sdvo_connector *intel_sdvo_connector,
2820 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2821{
4ef69c7a 2822 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2823 struct drm_connector *connector = &intel_sdvo_connector->base.base;
630d30a4
ML		 2824 struct drm_connector_state *conn_state = connector->state;
2825 struct intel_sdvo_connector_state *sdvo_state =
2826 to_intel_sdvo_connector_state(conn_state);
b9219c5e
ZY		 2827 uint16_t response, data_value[2];
2828
c5521706
CW		 2829 /* when horizontal overscan is supported, Add the left/right property */
2830 if (enhancements.overscan_h) {
2831 if (!intel_sdvo_get_value(intel_sdvo,
2832 SDVO_CMD_GET_MAX_OVERSCAN_H,
2833 &data_value, 4))
2834 return false;
32aad86f 2835
c5521706
CW		 2836 if (!intel_sdvo_get_value(intel_sdvo,
2837 SDVO_CMD_GET_OVERSCAN_H,
2838 &response, 2))
2839 return false;
fcc8d672 2840
630d30a4
ML		 2841 sdvo_state->tv.overscan_h = response;
2842
c5521706 2843 intel_sdvo_connector->max_hscan = data_value[0];
c5521706 2844 intel_sdvo_connector->left =
d9bc3c02 2845 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2846 if (!intel_sdvo_connector->left)
2847 return false;
fcc8d672 2848
662595df 2849 drm_object_attach_property(&connector->base,
630d30a4 2850 intel_sdvo_connector->left, 0);
fcc8d672 2851
c5521706 2852 intel_sdvo_connector->right =
d9bc3c02 2853 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2854 if (!intel_sdvo_connector->right)
2855 return false;
32aad86f 2856
662595df 2857 drm_object_attach_property(&connector->base,
630d30a4 2858 intel_sdvo_connector->right, 0);
c5521706
CW		 2859 DRM_DEBUG_KMS("h_overscan: max %d, "
2860 "default %d, current %d\n",
2861 data_value[0], data_value[1], response);
2862 }
32aad86f 2863
c5521706
CW		 2864 if (enhancements.overscan_v) {
2865 if (!intel_sdvo_get_value(intel_sdvo,
2866 SDVO_CMD_GET_MAX_OVERSCAN_V,
2867 &data_value, 4))
2868 return false;
fcc8d672 2869
c5521706
CW		 2870 if (!intel_sdvo_get_value(intel_sdvo,
2871 SDVO_CMD_GET_OVERSCAN_V,
2872 &response, 2))
2873 return false;
32aad86f 2874
630d30a4
ML		 2875 sdvo_state->tv.overscan_v = response;
2876
c5521706 2877 intel_sdvo_connector->max_vscan = data_value[0];
c5521706 2878 intel_sdvo_connector->top =
d9bc3c02
SH		 2879 drm_property_create_range(dev, 0,
2880 "top_margin", 0, data_value[0]);
c5521706
CW		 2881 if (!intel_sdvo_connector->top)
2882 return false;
32aad86f 2883
662595df 2884 drm_object_attach_property(&connector->base,
630d30a4 2885 intel_sdvo_connector->top, 0);
fcc8d672 2886
c5521706 2887 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2888 drm_property_create_range(dev, 0,
2889 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2890 if (!intel_sdvo_connector->bottom)
2891 return false;
32aad86f 2892
662595df 2893 drm_object_attach_property(&connector->base,
630d30a4 2894 intel_sdvo_connector->bottom, 0);
c5521706
CW		 2895 DRM_DEBUG_KMS("v_overscan: max %d, "
2896 "default %d, current %d\n",
2897 data_value[0], data_value[1], response);
2898 }
32aad86f 2899
630d30a4
ML		 2900 ENHANCEMENT(&sdvo_state->tv, hpos, HPOS);
2901 ENHANCEMENT(&sdvo_state->tv, vpos, VPOS);
2902 ENHANCEMENT(&conn_state->tv, saturation, SATURATION);
2903 ENHANCEMENT(&conn_state->tv, contrast, CONTRAST);
2904 ENHANCEMENT(&conn_state->tv, hue, HUE);
2905 ENHANCEMENT(&conn_state->tv, brightness, BRIGHTNESS);
2906 ENHANCEMENT(&sdvo_state->tv, sharpness, SHARPNESS);
2907 ENHANCEMENT(&sdvo_state->tv, flicker_filter, FLICKER_FILTER);
2908 ENHANCEMENT(&sdvo_state->tv, flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2909 ENHANCEMENT(&sdvo_state->tv, flicker_filter_2d, FLICKER_FILTER_2D);
2910 _ENHANCEMENT(sdvo_state->tv.chroma_filter, tv_chroma_filter, TV_CHROMA_FILTER);
2911 _ENHANCEMENT(sdvo_state->tv.luma_filter, tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2912
e044218a
CW		 2913 if (enhancements.dot_crawl) {
2914 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2915 return false;
2916
630d30a4 2917 sdvo_state->tv.dot_crawl = response & 0x1;
e044218a 2918 intel_sdvo_connector->dot_crawl =
d9bc3c02 2919 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2920 if (!intel_sdvo_connector->dot_crawl)
2921 return false;
2922
662595df 2923 drm_object_attach_property(&connector->base,
630d30a4 2924 intel_sdvo_connector->dot_crawl, 0);
e044218a
CW		 2925 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2926 }
2927
c5521706
CW		 2928 return true;
2929}
32aad86f 2930
c5521706
CW		 2931static bool
2932intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2933 struct intel_sdvo_connector *intel_sdvo_connector,
2934 struct intel_sdvo_enhancements_reply enhancements)
2935{
4ef69c7a 2936 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2937 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2938 uint16_t response, data_value[2];
32aad86f 2939
630d30a4 2940 ENHANCEMENT(&connector->state->tv, brightness, BRIGHTNESS);
fcc8d672 2941
c5521706
CW		 2942 return true;
2943}
2944#undef ENHANCEMENT
630d30a4 2945#undef _ENHANCEMENT
32aad86f 2946
c5521706
CW		 2947static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2948 struct intel_sdvo_connector *intel_sdvo_connector)
2949{
2950 union {
2951 struct intel_sdvo_enhancements_reply reply;
2952 uint16_t response;
2953 } enhancements;
32aad86f 2954
1a3665c8
CW		 2955 BUILD_BUG_ON(sizeof(enhancements) != 2);
2956
99016646
ID		 2957 if (!intel_sdvo_get_value(intel_sdvo,
2958 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2959 &enhancements, sizeof(enhancements)) ||
2960 enhancements.response == 0) {
c5521706
CW		 2961 DRM_DEBUG_KMS("No enhancement is supported\n");
2962 return true;
b9219c5e 2963 }
32aad86f 2964
c5521706
CW		 2965 if (IS_TV(intel_sdvo_connector))
2966 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2967 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2968 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2969 else
2970 return true;
e957d772
CW		 2971}
2972
2973static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2974 struct i2c_msg *msgs,
2975 int num)
2976{
2977 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2978
a8506684 2979 if (!__intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
e957d772
CW		 2980 return -EIO;
2981
2982 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2983}
2984
2985static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2986{
2987 struct intel_sdvo *sdvo = adapter->algo_data;
2988 return sdvo->i2c->algo->functionality(sdvo->i2c);
2989}
2990
2991static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2992 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2993 .functionality = intel_sdvo_ddc_proxy_func
2994};
2995
a8506684
DV		 2996static void proxy_lock_bus(struct i2c_adapter *adapter,
2997 unsigned int flags)
2998{
2999 struct intel_sdvo *sdvo = adapter->algo_data;
3000 sdvo->i2c->lock_ops->lock_bus(sdvo->i2c, flags);
3001}
3002
3003static int proxy_trylock_bus(struct i2c_adapter *adapter,
3004 unsigned int flags)
3005{
3006 struct intel_sdvo *sdvo = adapter->algo_data;
3007 return sdvo->i2c->lock_ops->trylock_bus(sdvo->i2c, flags);
3008}
3009
3010static void proxy_unlock_bus(struct i2c_adapter *adapter,
3011 unsigned int flags)
3012{
3013 struct intel_sdvo *sdvo = adapter->algo_data;
3014 sdvo->i2c->lock_ops->unlock_bus(sdvo->i2c, flags);
3015}
3016
0db1aa42 3017static const struct i2c_lock_operations proxy_lock_ops = {
a8506684
DV		 3018 .lock_bus = proxy_lock_bus,
3019 .trylock_bus = proxy_trylock_bus,
3020 .unlock_bus = proxy_unlock_bus,
3021};
3022
e957d772
CW		 3023static bool
3024intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
c39055b0 3025 struct drm_i915_private *dev_priv)
e957d772 3026{
c39055b0 3027 struct pci_dev *pdev = dev_priv->drm.pdev;
52a05c30 3028
e957d772
CW		 3029 sdvo->ddc.owner = THIS_MODULE;
3030 sdvo->ddc.class = I2C_CLASS_DDC;
3031 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
52a05c30 3032 sdvo->ddc.dev.parent = &pdev->dev;
e957d772
CW		 3033 sdvo->ddc.algo_data = sdvo;
3034 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
a8506684 3035 sdvo->ddc.lock_ops = &proxy_lock_ops;
e957d772
CW		 3036
3037 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 3038}
3039
2a5c0832
VS		 3040static void assert_sdvo_port_valid(const struct drm_i915_private *dev_priv,
3041 enum port port)
3042{
3043 if (HAS_PCH_SPLIT(dev_priv))
3044 WARN_ON(port != PORT_B);
3045 else
3046 WARN_ON(port != PORT_B && port != PORT_C);
3047}
3048
c39055b0 3049bool intel_sdvo_init(struct drm_i915_private *dev_priv,
f0f59a00 3050 i915_reg_t sdvo_reg, enum port port)
79e53945 3051{
21d40d37 3052 struct intel_encoder *intel_encoder;
ea5b213a 3053 struct intel_sdvo *intel_sdvo;
79e53945 3054 int i;
2a5c0832
VS		 3055
3056 assert_sdvo_port_valid(dev_priv, port);
3057
b14c5679 3058 intel_sdvo = kzalloc(sizeof(*intel_sdvo), GFP_KERNEL);
ea5b213a 3059 if (!intel_sdvo)
7d57382e 3060 return false;
79e53945 3061
56184e3d 3062 intel_sdvo->sdvo_reg = sdvo_reg;
2a5c0832 3063 intel_sdvo->port = port;
c39055b0
ACO		 3064 intel_sdvo->slave_addr =
3065 intel_sdvo_get_slave_addr(dev_priv, intel_sdvo) >> 1;
8bd864b8 3066 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo);
c39055b0 3067 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev_priv))
fbfcc4f3 3068 goto err_i2c_bus;
e957d772 3069
56184e3d 3070 /* encoder type will be decided later */
ea5b213a 3071 intel_encoder = &intel_sdvo->base;
21d40d37 3072 intel_encoder->type = INTEL_OUTPUT_SDVO;
79f255a0 3073 intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
03cdc1d4 3074 intel_encoder->port = port;
c39055b0
ACO		 3075 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
3076 &intel_sdvo_enc_funcs, 0,
580d8ed5 3077 "SDVO %c", port_name(port));
79e53945 3078
79e53945
JB		 3079 /* Read the regs to test if we can talk to the device */
3080 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 3081 u8 byte;
3082
3083 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 3084 DRM_DEBUG_KMS("No SDVO device found on %s\n",
3085 SDVO_NAME(intel_sdvo));
f899fc64 3086 goto err;
79e53945
JB		 3087 }
3088 }
3089
6cc5f341 3090 intel_encoder->compute_config = intel_sdvo_compute_config;
6e266956 3091 if (HAS_PCH_SPLIT(dev_priv)) {
3c65d1d1
VS		 3092 intel_encoder->disable = pch_disable_sdvo;
3093 intel_encoder->post_disable = pch_post_disable_sdvo;
3094 } else {
3095 intel_encoder->disable = intel_disable_sdvo;
3096 }
192d47a6 3097 intel_encoder->pre_enable = intel_sdvo_pre_enable;
ce22c320 3098 intel_encoder->enable = intel_enable_sdvo;
4ac41f47 3099 intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
045ac3b5 3100 intel_encoder->get_config = intel_sdvo_get_config;
ce22c320 3101
af901ca1 3102 /* In default case sdvo lvds is false */
32aad86f 3103 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 3104 goto err;
79e53945 3105
ea5b213a
CW		 3106 if (intel_sdvo_output_setup(intel_sdvo,
3107 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 3108 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
3109 SDVO_NAME(intel_sdvo));
d0ddfbd3
JN		 3110 /* Output_setup can leave behind connectors! */
3111 goto err_output;
79e53945
JB		 3112 }
3113
7ba220ce
CW		 3114 /* Only enable the hotplug irq if we need it, to work around noisy
3115 * hotplug lines.
3116 */
3117 if (intel_sdvo->hotplug_active) {
2a5c0832
VS		 3118 if (intel_sdvo->port == PORT_B)
3119 intel_encoder->hpd_pin = HPD_SDVO_B;
3120 else
3121 intel_encoder->hpd_pin = HPD_SDVO_C;
7ba220ce
CW		 3122 }
3123
e506d6fd
DV		 3124 /*
3125 * Cloning SDVO with anything is often impossible, since the SDVO
3126 * encoder can request a special input timing mode. And even if that's
3127 * not the case we have evidence that cloning a plain unscaled mode with
3128 * VGA doesn't really work. Furthermore the cloning flags are way too
3129 * simplistic anyway to express such constraints, so just give up on
3130 * cloning for SDVO encoders.
3131 */
bc079e8b 3132 intel_sdvo->base.cloneable = 0;
e506d6fd 3133
8bd864b8 3134 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo);
e2f0ba97 3135
79e53945 3136 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 3137 if (!intel_sdvo_set_target_input(intel_sdvo))
d0ddfbd3 3138 goto err_output;
79e53945 3139
32aad86f
CW		 3140 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
3141 &intel_sdvo->pixel_clock_min,
3142 &intel_sdvo->pixel_clock_max))
d0ddfbd3 3143 goto err_output;
79e53945 3144
8a4c47f3 3145 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 3146 "clock range %dMHz - %dMHz, "
3147 "input 1: %c, input 2: %c, "
3148 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 3149 SDVO_NAME(intel_sdvo),
3150 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
3151 intel_sdvo->caps.device_rev_id,
3152 intel_sdvo->pixel_clock_min / 1000,
3153 intel_sdvo->pixel_clock_max / 1000,
3154 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
3155 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 3156 /* check currently supported outputs */
ea5b213a 3157 intel_sdvo->caps.output_flags &
79e53945 3158 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 3159 intel_sdvo->caps.output_flags &
79e53945 3160 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 3161 return true;
79e53945 3162
d0ddfbd3
JN		 3163err_output:
3164 intel_sdvo_output_cleanup(intel_sdvo);
3165
f899fc64 3166err:
373a3cf7 3167 drm_encoder_cleanup(&intel_encoder->base);
e957d772 3168 i2c_del_adapter(&intel_sdvo->ddc);
fbfcc4f3
JN		 3169err_i2c_bus:
3170 intel_sdvo_unselect_i2c_bus(intel_sdvo);
ea5b213a 3171 kfree(intel_sdvo);
79e53945 3172
7d57382e 3173 return false;
79e53945 3174}
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