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drm/i915: Add support for CHV pipe B sprite CSC
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_sprite.c
CommitLineData
b840d907
JB		 1/*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 *
26 * New plane/sprite handling.
27 *
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
30 * support.
31 */
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_fourcc.h>
1731693a 35#include <drm/drm_rect.h>
b840d907 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
b840d907
JB		 38#include "i915_drv.h"
39
6ca2aeb2
VS		 40static bool
41format_is_yuv(uint32_t format)
42{
43 switch (format) {
44 case DRM_FORMAT_YUYV:
45 case DRM_FORMAT_UYVY:
46 case DRM_FORMAT_VYUY:
47 case DRM_FORMAT_YVYU:
48 return true;
49 default:
50 return false;
51 }
52}
53
8d7849db
VS		 54static int usecs_to_scanlines(const struct drm_display_mode *mode, int usecs)
55{
56 /* paranoia */
57 if (!mode->crtc_htotal)
58 return 1;
59
60 return DIV_ROUND_UP(usecs * mode->crtc_clock, 1000 * mode->crtc_htotal);
61}
62
63static bool intel_pipe_update_start(struct intel_crtc *crtc, uint32_t *start_vbl_count)
64{
65 struct drm_device *dev = crtc->base.dev;
66 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
67 enum pipe pipe = crtc->pipe;
68 long timeout = msecs_to_jiffies_timeout(1);
69 int scanline, min, max, vblank_start;
210871b6 70 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
8d7849db
VS		 71 DEFINE_WAIT(wait);
72
51fd371b 73 WARN_ON(!drm_modeset_is_locked(&crtc->base.mutex));
8d7849db
VS		 74
75 vblank_start = mode->crtc_vblank_start;
76 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
77 vblank_start = DIV_ROUND_UP(vblank_start, 2);
78
79 /* FIXME needs to be calibrated sensibly */
80 min = vblank_start - usecs_to_scanlines(mode, 100);
81 max = vblank_start - 1;
82
83 if (min <= 0 || max <= 0)
84 return false;
85
86 if (WARN_ON(drm_vblank_get(dev, pipe)))
87 return false;
88
89 local_irq_disable();
90
25ef284a
VS		 91 trace_i915_pipe_update_start(crtc, min, max);
92
8d7849db
VS		 93 for (;;) {
94 /*
95 * prepare_to_wait() has a memory barrier, which guarantees
96 * other CPUs can see the task state update by the time we
97 * read the scanline.
98 */
210871b6 99 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
8d7849db
VS		 100
101 scanline = intel_get_crtc_scanline(crtc);
102 if (scanline < min || scanline > max)
103 break;
104
105 if (timeout <= 0) {
106 DRM_ERROR("Potential atomic update failure on pipe %c\n",
107 pipe_name(crtc->pipe));
108 break;
109 }
110
111 local_irq_enable();
112
113 timeout = schedule_timeout(timeout);
114
115 local_irq_disable();
116 }
117
210871b6 118 finish_wait(wq, &wait);
8d7849db
VS		 119
120 drm_vblank_put(dev, pipe);
121
122 *start_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
123
25ef284a
VS		 124 trace_i915_pipe_update_vblank_evaded(crtc, min, max, *start_vbl_count);
125
8d7849db
VS		 126 return true;
127}
128
129static void intel_pipe_update_end(struct intel_crtc *crtc, u32 start_vbl_count)
130{
131 struct drm_device *dev = crtc->base.dev;
132 enum pipe pipe = crtc->pipe;
133 u32 end_vbl_count = dev->driver->get_vblank_counter(dev, pipe);
134
25ef284a
VS		 135 trace_i915_pipe_update_end(crtc, end_vbl_count);
136
8d7849db
VS		 137 local_irq_enable();
138
139 if (start_vbl_count != end_vbl_count)
140 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u)\n",
141 pipe_name(pipe), start_vbl_count, end_vbl_count);
142}
143
5b633d6b
VS		 144static void intel_update_primary_plane(struct intel_crtc *crtc)
145{
146 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
147 int reg = DSPCNTR(crtc->plane);
148
149 if (crtc->primary_enabled)
150 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE);
151 else
152 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE);
153}
154
dc2a41b4
DL		 155static void
156skl_update_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc,
157 struct drm_framebuffer *fb,
158 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
159 unsigned int crtc_w, unsigned int crtc_h,
160 uint32_t x, uint32_t y,
161 uint32_t src_w, uint32_t src_h)
162{
163 struct drm_device *dev = drm_plane->dev;
164 struct drm_i915_private *dev_priv = dev->dev_private;
165 struct intel_plane *intel_plane = to_intel_plane(drm_plane);
166 const int pipe = intel_plane->pipe;
167 const int plane = intel_plane->plane + 1;
168 u32 plane_ctl, stride;
169 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
170
171 plane_ctl = I915_READ(PLANE_CTL(pipe, plane));
172
173 /* Mask out pixel format bits in case we change it */
174 plane_ctl &= ~PLANE_CTL_FORMAT_MASK;
175 plane_ctl &= ~PLANE_CTL_ORDER_RGBX;
176 plane_ctl &= ~PLANE_CTL_YUV422_ORDER_MASK;
177 plane_ctl &= ~PLANE_CTL_TILED_MASK;
178 plane_ctl &= ~PLANE_CTL_ALPHA_MASK;
1447dde0 179 plane_ctl &= ~PLANE_CTL_ROTATE_MASK;
dc2a41b4
DL		 180
181 /* Trickle feed has to be enabled */
182 plane_ctl &= ~PLANE_CTL_TRICKLE_FEED_DISABLE;
183
184 switch (fb->pixel_format) {
185 case DRM_FORMAT_RGB565:
186 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
187 break;
188 case DRM_FORMAT_XBGR8888:
189 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
190 break;
191 case DRM_FORMAT_XRGB8888:
192 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
193 break;
194 /*
195 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
196 * to be already pre-multiplied. We need to add a knob (or a different
197 * DRM_FORMAT) for user-space to configure that.
198 */
199 case DRM_FORMAT_ABGR8888:
200 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 |
201 PLANE_CTL_ORDER_RGBX |
202 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
203 break;
204 case DRM_FORMAT_ARGB8888:
205 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888 |
206 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
207 break;
208 case DRM_FORMAT_YUYV:
209 plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
210 break;
211 case DRM_FORMAT_YVYU:
212 plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
213 break;
214 case DRM_FORMAT_UYVY:
215 plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
216 break;
217 case DRM_FORMAT_VYUY:
218 plane_ctl |= PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
219 break;
220 default:
221 BUG();
222 }
223
224 switch (obj->tiling_mode) {
225 case I915_TILING_NONE:
226 stride = fb->pitches[0] >> 6;
227 break;
228 case I915_TILING_X:
229 plane_ctl |= PLANE_CTL_TILED_X;
230 stride = fb->pitches[0] >> 9;
231 break;
232 default:
233 BUG();
234 }
1447dde0
SJ		 235 if (intel_plane->rotation == BIT(DRM_ROTATE_180))
236 plane_ctl |= PLANE_CTL_ROTATE_180;
dc2a41b4
DL		 237
238 plane_ctl |= PLANE_CTL_ENABLE;
239 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
240
241 intel_update_sprite_watermarks(drm_plane, crtc, src_w, src_h,
242 pixel_size, true,
243 src_w != crtc_w || src_h != crtc_h);
244
245 /* Sizes are 0 based */
246 src_w--;
247 src_h--;
248 crtc_w--;
249 crtc_h--;
250
251 I915_WRITE(PLANE_OFFSET(pipe, plane), (y << 16) | x);
252 I915_WRITE(PLANE_STRIDE(pipe, plane), stride);
253 I915_WRITE(PLANE_POS(pipe, plane), (crtc_y << 16) | crtc_x);
254 I915_WRITE(PLANE_SIZE(pipe, plane), (crtc_h << 16) | crtc_w);
255 I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
256 I915_WRITE(PLANE_SURF(pipe, plane), i915_gem_obj_ggtt_offset(obj));
257 POSTING_READ(PLANE_SURF(pipe, plane));
258}
259
260static void
261skl_disable_plane(struct drm_plane *drm_plane, struct drm_crtc *crtc)
262{
263 struct drm_device *dev = drm_plane->dev;
264 struct drm_i915_private *dev_priv = dev->dev_private;
265 struct intel_plane *intel_plane = to_intel_plane(drm_plane);
266 const int pipe = intel_plane->pipe;
267 const int plane = intel_plane->plane + 1;
268
269 I915_WRITE(PLANE_CTL(pipe, plane),
270 I915_READ(PLANE_CTL(pipe, plane)) & ~PLANE_CTL_ENABLE);
271
272 /* Activate double buffered register update */
273 I915_WRITE(PLANE_CTL(pipe, plane), 0);
274 POSTING_READ(PLANE_CTL(pipe, plane));
275
276 intel_update_sprite_watermarks(drm_plane, crtc, 0, 0, 0, false, false);
277}
278
279static int
280skl_update_colorkey(struct drm_plane *drm_plane,
281 struct drm_intel_sprite_colorkey *key)
282{
283 struct drm_device *dev = drm_plane->dev;
284 struct drm_i915_private *dev_priv = dev->dev_private;
285 struct intel_plane *intel_plane = to_intel_plane(drm_plane);
286 const int pipe = intel_plane->pipe;
287 const int plane = intel_plane->plane;
288 u32 plane_ctl;
289
290 I915_WRITE(PLANE_KEYVAL(pipe, plane), key->min_value);
291 I915_WRITE(PLANE_KEYMAX(pipe, plane), key->max_value);
292 I915_WRITE(PLANE_KEYMSK(pipe, plane), key->channel_mask);
293
294 plane_ctl = I915_READ(PLANE_CTL(pipe, plane));
295 plane_ctl &= ~PLANE_CTL_KEY_ENABLE_MASK;
296 if (key->flags & I915_SET_COLORKEY_DESTINATION)
297 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
298 else if (key->flags & I915_SET_COLORKEY_SOURCE)
299 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
300 I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
301
302 POSTING_READ(PLANE_CTL(pipe, plane));
303
304 return 0;
305}
306
307static void
308skl_get_colorkey(struct drm_plane *drm_plane,
309 struct drm_intel_sprite_colorkey *key)
310{
311 struct drm_device *dev = drm_plane->dev;
312 struct drm_i915_private *dev_priv = dev->dev_private;
313 struct intel_plane *intel_plane = to_intel_plane(drm_plane);
314 const int pipe = intel_plane->pipe;
315 const int plane = intel_plane->plane;
316 u32 plane_ctl;
317
318 key->min_value = I915_READ(PLANE_KEYVAL(pipe, plane));
319 key->max_value = I915_READ(PLANE_KEYMAX(pipe, plane));
320 key->channel_mask = I915_READ(PLANE_KEYMSK(pipe, plane));
321
322 plane_ctl = I915_READ(PLANE_CTL(pipe, plane));
323
324 switch (plane_ctl & PLANE_CTL_KEY_ENABLE_MASK) {
325 case PLANE_CTL_KEY_ENABLE_DESTINATION:
326 key->flags = I915_SET_COLORKEY_DESTINATION;
327 break;
328 case PLANE_CTL_KEY_ENABLE_SOURCE:
329 key->flags = I915_SET_COLORKEY_SOURCE;
330 break;
331 default:
332 key->flags = I915_SET_COLORKEY_NONE;
333 }
334}
335
6ca2aeb2
VS		 336static void
337chv_update_csc(struct intel_plane *intel_plane, uint32_t format)
338{
339 struct drm_i915_private *dev_priv = intel_plane->base.dev->dev_private;
340 int plane = intel_plane->plane;
341
342 /* Seems RGB data bypasses the CSC always */
343 if (!format_is_yuv(format))
344 return;
345
346 /*
347 * BT.601 limited range YCbCr -> full range RGB
348 *
349 * |r| | 6537 4769 0| |cr |
350 * |g| = |-3330 4769 -1605| x |y-64|
351 * |b| | 0 4769 8263| |cb |
352 *
353 * Cb and Cr apparently come in as signed already, so no
354 * need for any offset. For Y we need to remove the offset.
355 */
356 I915_WRITE(SPCSCYGOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
357 I915_WRITE(SPCSCCBOFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
358 I915_WRITE(SPCSCCROFF(plane), SPCSC_OOFF(0) | SPCSC_IOFF(0));
359
360 I915_WRITE(SPCSCC01(plane), SPCSC_C1(4769) | SPCSC_C0(6537));
361 I915_WRITE(SPCSCC23(plane), SPCSC_C1(-3330) | SPCSC_C0(0));
362 I915_WRITE(SPCSCC45(plane), SPCSC_C1(-1605) | SPCSC_C0(4769));
363 I915_WRITE(SPCSCC67(plane), SPCSC_C1(4769) | SPCSC_C0(0));
364 I915_WRITE(SPCSCC8(plane), SPCSC_C0(8263));
365
366 I915_WRITE(SPCSCYGICLAMP(plane), SPCSC_IMAX(940) | SPCSC_IMIN(64));
367 I915_WRITE(SPCSCCBICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
368 I915_WRITE(SPCSCCRICLAMP(plane), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
369
370 I915_WRITE(SPCSCYGOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
371 I915_WRITE(SPCSCCBOCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
372 I915_WRITE(SPCSCCROCLAMP(plane), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
373}
374
7f1f3851 375static void
b39d53f6
VS		 376vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
377 struct drm_framebuffer *fb,
7f1f3851
JB		 378 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
379 unsigned int crtc_w, unsigned int crtc_h,
380 uint32_t x, uint32_t y,
381 uint32_t src_w, uint32_t src_h)
382{
383 struct drm_device *dev = dplane->dev;
384 struct drm_i915_private *dev_priv = dev->dev_private;
385 struct intel_plane *intel_plane = to_intel_plane(dplane);
8d7849db 386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7f1f3851
JB		 387 int pipe = intel_plane->pipe;
388 int plane = intel_plane->plane;
389 u32 sprctl;
390 unsigned long sprsurf_offset, linear_offset;
391 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
8d7849db
VS		 392 u32 start_vbl_count;
393 bool atomic_update;
7f1f3851
JB		 394
395 sprctl = I915_READ(SPCNTR(pipe, plane));
396
397 /* Mask out pixel format bits in case we change it */
398 sprctl &= ~SP_PIXFORMAT_MASK;
399 sprctl &= ~SP_YUV_BYTE_ORDER_MASK;
400 sprctl &= ~SP_TILED;
76eebda7 401 sprctl &= ~SP_ROTATE_180;
7f1f3851
JB		 402
403 switch (fb->pixel_format) {
404 case DRM_FORMAT_YUYV:
405 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
406 break;
407 case DRM_FORMAT_YVYU:
408 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
409 break;
410 case DRM_FORMAT_UYVY:
411 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
412 break;
413 case DRM_FORMAT_VYUY:
414 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
415 break;
416 case DRM_FORMAT_RGB565:
417 sprctl |= SP_FORMAT_BGR565;
418 break;
419 case DRM_FORMAT_XRGB8888:
420 sprctl |= SP_FORMAT_BGRX8888;
421 break;
422 case DRM_FORMAT_ARGB8888:
423 sprctl |= SP_FORMAT_BGRA8888;
424 break;
425 case DRM_FORMAT_XBGR2101010:
426 sprctl |= SP_FORMAT_RGBX1010102;
427 break;
428 case DRM_FORMAT_ABGR2101010:
429 sprctl |= SP_FORMAT_RGBA1010102;
430 break;
431 case DRM_FORMAT_XBGR8888:
432 sprctl |= SP_FORMAT_RGBX8888;
433 break;
434 case DRM_FORMAT_ABGR8888:
435 sprctl |= SP_FORMAT_RGBA8888;
436 break;
437 default:
438 /*
439 * If we get here one of the upper layers failed to filter
440 * out the unsupported plane formats
441 */
442 BUG();
443 break;
444 }
445
4ea67bc7
VS		 446 /*
447 * Enable gamma to match primary/cursor plane behaviour.
448 * FIXME should be user controllable via propertiesa.
449 */
450 sprctl |= SP_GAMMA_ENABLE;
451
7f1f3851
JB		 452 if (obj->tiling_mode != I915_TILING_NONE)
453 sprctl |= SP_TILED;
454
455 sprctl |= SP_ENABLE;
456
ed57cb8a
DL		 457 intel_update_sprite_watermarks(dplane, crtc, src_w, src_h,
458 pixel_size, true,
67ca28f3
VS		 459 src_w != crtc_w || src_h != crtc_h);
460
7f1f3851
JB		 461 /* Sizes are 0 based */
462 src_w--;
463 src_h--;
464 crtc_w--;
465 crtc_h--;
466
7f1f3851
JB		 467 linear_offset = y * fb->pitches[0] + x * pixel_size;
468 sprsurf_offset = intel_gen4_compute_page_offset(&x, &y,
469 obj->tiling_mode,
470 pixel_size,
471 fb->pitches[0]);
472 linear_offset -= sprsurf_offset;
473
76eebda7
VS		 474 if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
475 sprctl |= SP_ROTATE_180;
476
477 x += src_w;
478 y += src_h;
479 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
480 }
481
8d7849db
VS		 482 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
483
5b633d6b
VS		 484 intel_update_primary_plane(intel_crtc);
485
6ca2aeb2
VS		 486 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B)
487 chv_update_csc(intel_plane, fb->pixel_format);
488
ca6ad025
VS		 489 I915_WRITE(SPSTRIDE(pipe, plane), fb->pitches[0]);
490 I915_WRITE(SPPOS(pipe, plane), (crtc_y << 16) | crtc_x);
491
7f1f3851
JB		 492 if (obj->tiling_mode != I915_TILING_NONE)
493 I915_WRITE(SPTILEOFF(pipe, plane), (y << 16) | x);
494 else
495 I915_WRITE(SPLINOFF(pipe, plane), linear_offset);
496
c14b0485
VS		 497 I915_WRITE(SPCONSTALPHA(pipe, plane), 0);
498
7f1f3851
JB		 499 I915_WRITE(SPSIZE(pipe, plane), (crtc_h << 16) | crtc_w);
500 I915_WRITE(SPCNTR(pipe, plane), sprctl);
85ba7b7d
DV		 501 I915_WRITE(SPSURF(pipe, plane), i915_gem_obj_ggtt_offset(obj) +
502 sprsurf_offset);
5b633d6b
VS		 503
504 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
8d7849db
VS		 505
506 if (atomic_update)
507 intel_pipe_update_end(intel_crtc, start_vbl_count);
7f1f3851
JB		 508}
509
510static void
b39d53f6 511vlv_disable_plane(struct drm_plane *dplane, struct drm_crtc *crtc)
7f1f3851
JB		 512{
513 struct drm_device *dev = dplane->dev;
514 struct drm_i915_private *dev_priv = dev->dev_private;
515 struct intel_plane *intel_plane = to_intel_plane(dplane);
8d7849db 516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7f1f3851
JB		 517 int pipe = intel_plane->pipe;
518 int plane = intel_plane->plane;
8d7849db
VS		 519 u32 start_vbl_count;
520 bool atomic_update;
521
522 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
7f1f3851 523
5b633d6b
VS		 524 intel_update_primary_plane(intel_crtc);
525
7f1f3851
JB		 526 I915_WRITE(SPCNTR(pipe, plane), I915_READ(SPCNTR(pipe, plane)) &
527 ~SP_ENABLE);
528 /* Activate double buffered register update */
85ba7b7d 529 I915_WRITE(SPSURF(pipe, plane), 0);
5b633d6b
VS		 530
531 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
a95fd8ca 532
8d7849db
VS		 533 if (atomic_update)
534 intel_pipe_update_end(intel_crtc, start_vbl_count);
535
ed57cb8a 536 intel_update_sprite_watermarks(dplane, crtc, 0, 0, 0, false, false);
7f1f3851
JB		 537}
538
539static int
540vlv_update_colorkey(struct drm_plane *dplane,
541 struct drm_intel_sprite_colorkey *key)
542{
543 struct drm_device *dev = dplane->dev;
544 struct drm_i915_private *dev_priv = dev->dev_private;
545 struct intel_plane *intel_plane = to_intel_plane(dplane);
546 int pipe = intel_plane->pipe;
547 int plane = intel_plane->plane;
548 u32 sprctl;
549
550 if (key->flags & I915_SET_COLORKEY_DESTINATION)
551 return -EINVAL;
552
553 I915_WRITE(SPKEYMINVAL(pipe, plane), key->min_value);
554 I915_WRITE(SPKEYMAXVAL(pipe, plane), key->max_value);
555 I915_WRITE(SPKEYMSK(pipe, plane), key->channel_mask);
556
557 sprctl = I915_READ(SPCNTR(pipe, plane));
558 sprctl &= ~SP_SOURCE_KEY;
559 if (key->flags & I915_SET_COLORKEY_SOURCE)
560 sprctl |= SP_SOURCE_KEY;
561 I915_WRITE(SPCNTR(pipe, plane), sprctl);
562
563 POSTING_READ(SPKEYMSK(pipe, plane));
564
565 return 0;
566}
567
568static void
569vlv_get_colorkey(struct drm_plane *dplane,
570 struct drm_intel_sprite_colorkey *key)
571{
572 struct drm_device *dev = dplane->dev;
573 struct drm_i915_private *dev_priv = dev->dev_private;
574 struct intel_plane *intel_plane = to_intel_plane(dplane);
575 int pipe = intel_plane->pipe;
576 int plane = intel_plane->plane;
577 u32 sprctl;
578
579 key->min_value = I915_READ(SPKEYMINVAL(pipe, plane));
580 key->max_value = I915_READ(SPKEYMAXVAL(pipe, plane));
581 key->channel_mask = I915_READ(SPKEYMSK(pipe, plane));
582
583 sprctl = I915_READ(SPCNTR(pipe, plane));
584 if (sprctl & SP_SOURCE_KEY)
585 key->flags = I915_SET_COLORKEY_SOURCE;
586 else
587 key->flags = I915_SET_COLORKEY_NONE;
588}
589
b840d907 590static void
b39d53f6
VS		 591ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
592 struct drm_framebuffer *fb,
b840d907
JB		 593 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
594 unsigned int crtc_w, unsigned int crtc_h,
595 uint32_t x, uint32_t y,
596 uint32_t src_w, uint32_t src_h)
597{
598 struct drm_device *dev = plane->dev;
599 struct drm_i915_private *dev_priv = dev->dev_private;
600 struct intel_plane *intel_plane = to_intel_plane(plane);
8d7849db 601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b840d907
JB		 602 int pipe = intel_plane->pipe;
603 u32 sprctl, sprscale = 0;
5a35e99e 604 unsigned long sprsurf_offset, linear_offset;
2bd3c3cb 605 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
8d7849db
VS		 606 u32 start_vbl_count;
607 bool atomic_update;
b840d907
JB		 608
609 sprctl = I915_READ(SPRCTL(pipe));
610
611 /* Mask out pixel format bits in case we change it */
612 sprctl &= ~SPRITE_PIXFORMAT_MASK;
613 sprctl &= ~SPRITE_RGB_ORDER_RGBX;
614 sprctl &= ~SPRITE_YUV_BYTE_ORDER_MASK;
e86fe0d3 615 sprctl &= ~SPRITE_TILED;
76eebda7 616 sprctl &= ~SPRITE_ROTATE_180;
b840d907
JB		 617
618 switch (fb->pixel_format) {
619 case DRM_FORMAT_XBGR8888:
5ee36913 620 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
b840d907
JB		 621 break;
622 case DRM_FORMAT_XRGB8888:
5ee36913 623 sprctl |= SPRITE_FORMAT_RGBX888;
b840d907
JB		 624 break;
625 case DRM_FORMAT_YUYV:
626 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
b840d907
JB		 627 break;
628 case DRM_FORMAT_YVYU:
629 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
b840d907
JB		 630 break;
631 case DRM_FORMAT_UYVY:
632 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
b840d907
JB		 633 break;
634 case DRM_FORMAT_VYUY:
635 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
b840d907
JB		 636 break;
637 default:
28d491df 638 BUG();
b840d907
JB		 639 }
640
4ea67bc7
VS		 641 /*
642 * Enable gamma to match primary/cursor plane behaviour.
643 * FIXME should be user controllable via propertiesa.
644 */
645 sprctl |= SPRITE_GAMMA_ENABLE;
646
b840d907
JB		 647 if (obj->tiling_mode != I915_TILING_NONE)
648 sprctl |= SPRITE_TILED;
649
b42c6009 650 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1f5d76db
PZ		 651 sprctl &= ~SPRITE_TRICKLE_FEED_DISABLE;
652 else
653 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
654
b840d907
JB		 655 sprctl |= SPRITE_ENABLE;
656
6bbfa1c5 657 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
86d3efce
VS		 658 sprctl |= SPRITE_PIPE_CSC_ENABLE;
659
ed57cb8a
DL		 660 intel_update_sprite_watermarks(plane, crtc, src_w, src_h, pixel_size,
661 true,
67ca28f3
VS		 662 src_w != crtc_w || src_h != crtc_h);
663
b840d907
JB		 664 /* Sizes are 0 based */
665 src_w--;
666 src_h--;
667 crtc_w--;
668 crtc_h--;
669
8553c18e 670 if (crtc_w != src_w || crtc_h != src_h)
b840d907 671 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
b840d907 672
ca320ac4 673 linear_offset = y * fb->pitches[0] + x * pixel_size;
5a35e99e 674 sprsurf_offset =
bc752862
CW		 675 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
676 pixel_size, fb->pitches[0]);
5a35e99e
DL		 677 linear_offset -= sprsurf_offset;
678
76eebda7
VS		 679 if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
680 sprctl |= SPRITE_ROTATE_180;
681
682 /* HSW and BDW does this automagically in hardware */
683 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
684 x += src_w;
685 y += src_h;
686 linear_offset += src_h * fb->pitches[0] +
687 src_w * pixel_size;
688 }
689 }
690
8d7849db
VS		 691 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
692
5b633d6b
VS		 693 intel_update_primary_plane(intel_crtc);
694
ca6ad025
VS		 695 I915_WRITE(SPRSTRIDE(pipe), fb->pitches[0]);
696 I915_WRITE(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
697
5a35e99e
DL		 698 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
699 * register */
b3dc685e 700 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
c54173a8 701 I915_WRITE(SPROFFSET(pipe), (y << 16) | x);
5a35e99e 702 else if (obj->tiling_mode != I915_TILING_NONE)
b840d907 703 I915_WRITE(SPRTILEOFF(pipe), (y << 16) | x);
5a35e99e
DL		 704 else
705 I915_WRITE(SPRLINOFF(pipe), linear_offset);
c54173a8 706
b840d907 707 I915_WRITE(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
2d354c34
DL		 708 if (intel_plane->can_scale)
709 I915_WRITE(SPRSCALE(pipe), sprscale);
b840d907 710 I915_WRITE(SPRCTL(pipe), sprctl);
85ba7b7d
DV		 711 I915_WRITE(SPRSURF(pipe),
712 i915_gem_obj_ggtt_offset(obj) + sprsurf_offset);
5b633d6b
VS		 713
714 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
8d7849db
VS		 715
716 if (atomic_update)
717 intel_pipe_update_end(intel_crtc, start_vbl_count);
b840d907
JB		 718}
719
720static void
b39d53f6 721ivb_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
b840d907
JB		 722{
723 struct drm_device *dev = plane->dev;
724 struct drm_i915_private *dev_priv = dev->dev_private;
725 struct intel_plane *intel_plane = to_intel_plane(plane);
8d7849db 726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b840d907 727 int pipe = intel_plane->pipe;
8d7849db
VS		 728 u32 start_vbl_count;
729 bool atomic_update;
730
731 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
b840d907 732
5b633d6b
VS		 733 intel_update_primary_plane(intel_crtc);
734
b840d907
JB		 735 I915_WRITE(SPRCTL(pipe), I915_READ(SPRCTL(pipe)) & ~SPRITE_ENABLE);
736 /* Can't leave the scaler enabled... */
2d354c34
DL		 737 if (intel_plane->can_scale)
738 I915_WRITE(SPRSCALE(pipe), 0);
b840d907 739 /* Activate double buffered register update */
85ba7b7d 740 I915_WRITE(SPRSURF(pipe), 0);
5b633d6b
VS		 741
742 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
828ed3e1 743
8d7849db
VS		 744 if (atomic_update)
745 intel_pipe_update_end(intel_crtc, start_vbl_count);
746
1bd09ec7
VS		 747 /*
748 * Avoid underruns when disabling the sprite.
749 * FIXME remove once watermark updates are done properly.
750 */
751 intel_wait_for_vblank(dev, pipe);
752
ed57cb8a 753 intel_update_sprite_watermarks(plane, crtc, 0, 0, 0, false, false);
b840d907
JB		 754}
755
8ea30864
JB		 756static int
757ivb_update_colorkey(struct drm_plane *plane,
758 struct drm_intel_sprite_colorkey *key)
759{
760 struct drm_device *dev = plane->dev;
761 struct drm_i915_private *dev_priv = dev->dev_private;
762 struct intel_plane *intel_plane;
763 u32 sprctl;
764 int ret = 0;
765
766 intel_plane = to_intel_plane(plane);
767
768 I915_WRITE(SPRKEYVAL(intel_plane->pipe), key->min_value);
769 I915_WRITE(SPRKEYMAX(intel_plane->pipe), key->max_value);
770 I915_WRITE(SPRKEYMSK(intel_plane->pipe), key->channel_mask);
771
772 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
773 sprctl &= ~(SPRITE_SOURCE_KEY | SPRITE_DEST_KEY);
774 if (key->flags & I915_SET_COLORKEY_DESTINATION)
775 sprctl |= SPRITE_DEST_KEY;
776 else if (key->flags & I915_SET_COLORKEY_SOURCE)
777 sprctl |= SPRITE_SOURCE_KEY;
778 I915_WRITE(SPRCTL(intel_plane->pipe), sprctl);
779
780 POSTING_READ(SPRKEYMSK(intel_plane->pipe));
781
782 return ret;
783}
784
785static void
786ivb_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
787{
788 struct drm_device *dev = plane->dev;
789 struct drm_i915_private *dev_priv = dev->dev_private;
790 struct intel_plane *intel_plane;
791 u32 sprctl;
792
793 intel_plane = to_intel_plane(plane);
794
795 key->min_value = I915_READ(SPRKEYVAL(intel_plane->pipe));
796 key->max_value = I915_READ(SPRKEYMAX(intel_plane->pipe));
797 key->channel_mask = I915_READ(SPRKEYMSK(intel_plane->pipe));
798 key->flags = 0;
799
800 sprctl = I915_READ(SPRCTL(intel_plane->pipe));
801
802 if (sprctl & SPRITE_DEST_KEY)
803 key->flags = I915_SET_COLORKEY_DESTINATION;
804 else if (sprctl & SPRITE_SOURCE_KEY)
805 key->flags = I915_SET_COLORKEY_SOURCE;
806 else
807 key->flags = I915_SET_COLORKEY_NONE;
808}
809
b840d907 810static void
b39d53f6
VS		 811ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
812 struct drm_framebuffer *fb,
b840d907
JB		 813 struct drm_i915_gem_object *obj, int crtc_x, int crtc_y,
814 unsigned int crtc_w, unsigned int crtc_h,
815 uint32_t x, uint32_t y,
816 uint32_t src_w, uint32_t src_h)
817{
818 struct drm_device *dev = plane->dev;
819 struct drm_i915_private *dev_priv = dev->dev_private;
820 struct intel_plane *intel_plane = to_intel_plane(plane);
8d7849db 821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2bd3c3cb 822 int pipe = intel_plane->pipe;
5a35e99e 823 unsigned long dvssurf_offset, linear_offset;
8aaa81a1 824 u32 dvscntr, dvsscale;
2bd3c3cb 825 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
8d7849db
VS		 826 u32 start_vbl_count;
827 bool atomic_update;
b840d907
JB		 828
829 dvscntr = I915_READ(DVSCNTR(pipe));
830
831 /* Mask out pixel format bits in case we change it */
832 dvscntr &= ~DVS_PIXFORMAT_MASK;
ab2f9df1 833 dvscntr &= ~DVS_RGB_ORDER_XBGR;
b840d907 834 dvscntr &= ~DVS_YUV_BYTE_ORDER_MASK;
79626523 835 dvscntr &= ~DVS_TILED;
76eebda7 836 dvscntr &= ~DVS_ROTATE_180;
b840d907
JB		 837
838 switch (fb->pixel_format) {
839 case DRM_FORMAT_XBGR8888:
ab2f9df1 840 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
b840d907
JB		 841 break;
842 case DRM_FORMAT_XRGB8888:
ab2f9df1 843 dvscntr |= DVS_FORMAT_RGBX888;
b840d907
JB		 844 break;
845 case DRM_FORMAT_YUYV:
846 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
b840d907
JB		 847 break;
848 case DRM_FORMAT_YVYU:
849 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
b840d907
JB		 850 break;
851 case DRM_FORMAT_UYVY:
852 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
b840d907
JB		 853 break;
854 case DRM_FORMAT_VYUY:
855 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
b840d907
JB		 856 break;
857 default:
28d491df 858 BUG();
b840d907
JB		 859 }
860
4ea67bc7
VS		 861 /*
862 * Enable gamma to match primary/cursor plane behaviour.
863 * FIXME should be user controllable via propertiesa.
864 */
865 dvscntr |= DVS_GAMMA_ENABLE;
866
b840d907
JB		 867 if (obj->tiling_mode != I915_TILING_NONE)
868 dvscntr |= DVS_TILED;
869
d1686ae3
CW		 870 if (IS_GEN6(dev))
871 dvscntr |= DVS_TRICKLE_FEED_DISABLE; /* must disable */
b840d907
JB		 872 dvscntr |= DVS_ENABLE;
873
ed57cb8a
DL		 874 intel_update_sprite_watermarks(plane, crtc, src_w, src_h,
875 pixel_size, true,
67ca28f3
VS		 876 src_w != crtc_w || src_h != crtc_h);
877
b840d907
JB		 878 /* Sizes are 0 based */
879 src_w--;
880 src_h--;
881 crtc_w--;
882 crtc_h--;
883
8aaa81a1 884 dvsscale = 0;
8368f014 885 if (crtc_w != src_w || crtc_h != src_h)
b840d907
JB		 886 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
887
ca320ac4 888 linear_offset = y * fb->pitches[0] + x * pixel_size;
5a35e99e 889 dvssurf_offset =
bc752862
CW		 890 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
891 pixel_size, fb->pitches[0]);
5a35e99e
DL		 892 linear_offset -= dvssurf_offset;
893
76eebda7
VS		 894 if (intel_plane->rotation == BIT(DRM_ROTATE_180)) {
895 dvscntr |= DVS_ROTATE_180;
896
897 x += src_w;
898 y += src_h;
899 linear_offset += src_h * fb->pitches[0] + src_w * pixel_size;
900 }
901
8d7849db
VS		 902 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
903
5b633d6b
VS		 904 intel_update_primary_plane(intel_crtc);
905
ca6ad025
VS		 906 I915_WRITE(DVSSTRIDE(pipe), fb->pitches[0]);
907 I915_WRITE(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
908
5a35e99e 909 if (obj->tiling_mode != I915_TILING_NONE)
b840d907 910 I915_WRITE(DVSTILEOFF(pipe), (y << 16) | x);
5a35e99e
DL		 911 else
912 I915_WRITE(DVSLINOFF(pipe), linear_offset);
b840d907 913
b840d907
JB		 914 I915_WRITE(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
915 I915_WRITE(DVSSCALE(pipe), dvsscale);
916 I915_WRITE(DVSCNTR(pipe), dvscntr);
85ba7b7d
DV		 917 I915_WRITE(DVSSURF(pipe),
918 i915_gem_obj_ggtt_offset(obj) + dvssurf_offset);
5b633d6b
VS		 919
920 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
8d7849db
VS		 921
922 if (atomic_update)
923 intel_pipe_update_end(intel_crtc, start_vbl_count);
b840d907
JB		 924}
925
926static void
b39d53f6 927ilk_disable_plane(struct drm_plane *plane, struct drm_crtc *crtc)
b840d907
JB		 928{
929 struct drm_device *dev = plane->dev;
930 struct drm_i915_private *dev_priv = dev->dev_private;
931 struct intel_plane *intel_plane = to_intel_plane(plane);
8d7849db 932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b840d907 933 int pipe = intel_plane->pipe;
8d7849db
VS		 934 u32 start_vbl_count;
935 bool atomic_update;
936
937 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
b840d907 938
5b633d6b
VS		 939 intel_update_primary_plane(intel_crtc);
940
b840d907
JB		 941 I915_WRITE(DVSCNTR(pipe), I915_READ(DVSCNTR(pipe)) & ~DVS_ENABLE);
942 /* Disable the scaler */
943 I915_WRITE(DVSSCALE(pipe), 0);
944 /* Flush double buffered register updates */
85ba7b7d 945 I915_WRITE(DVSSURF(pipe), 0);
5b633d6b
VS		 946
947 intel_flush_primary_plane(dev_priv, intel_crtc->plane);
a95fd8ca 948
8d7849db
VS		 949 if (atomic_update)
950 intel_pipe_update_end(intel_crtc, start_vbl_count);
951
1bd09ec7
VS		 952 /*
953 * Avoid underruns when disabling the sprite.
954 * FIXME remove once watermark updates are done properly.
955 */
956 intel_wait_for_vblank(dev, pipe);
957
ed57cb8a 958 intel_update_sprite_watermarks(plane, crtc, 0, 0, 0, false, false);
b840d907
JB		 959}
960
175bd420 961static void
5b633d6b 962intel_post_enable_primary(struct drm_crtc *crtc)
175bd420
JB		 963{
964 struct drm_device *dev = crtc->dev;
175bd420 965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
abae50ed 966
33c3b0d1
VS		 967 /*
968 * BDW signals flip done immediately if the plane
969 * is disabled, even if the plane enable is already
970 * armed to occur at the next vblank :(
971 */
972 if (IS_BROADWELL(dev))
973 intel_wait_for_vblank(dev, intel_crtc->pipe);
974
20bc8673
VS		 975 /*
976 * FIXME IPS should be fine as long as one plane is
977 * enabled, but in practice it seems to have problems
978 * when going from primary only to sprite only and vice
979 * versa.
980 */
cea165c3 981 hsw_enable_ips(intel_crtc);
20bc8673 982
82284b6b 983 mutex_lock(&dev->struct_mutex);
93314b5b 984 intel_update_fbc(dev);
82284b6b 985 mutex_unlock(&dev->struct_mutex);
175bd420
JB		 986}
987
988static void
5b633d6b 989intel_pre_disable_primary(struct drm_crtc *crtc)
175bd420
JB		 990{
991 struct drm_device *dev = crtc->dev;
992 struct drm_i915_private *dev_priv = dev->dev_private;
993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
82284b6b
VS		 994
995 mutex_lock(&dev->struct_mutex);
abae50ed
VS		 996 if (dev_priv->fbc.plane == intel_crtc->plane)
997 intel_disable_fbc(dev);
82284b6b 998 mutex_unlock(&dev->struct_mutex);
abae50ed 999
20bc8673
VS		 1000 /*
1001 * FIXME IPS should be fine as long as one plane is
1002 * enabled, but in practice it seems to have problems
1003 * when going from primary only to sprite only and vice
1004 * versa.
1005 */
1006 hsw_disable_ips(intel_crtc);
175bd420
JB		 1007}
1008
8ea30864 1009static int
d1686ae3 1010ilk_update_colorkey(struct drm_plane *plane,
8ea30864
JB		 1011 struct drm_intel_sprite_colorkey *key)
1012{
1013 struct drm_device *dev = plane->dev;
1014 struct drm_i915_private *dev_priv = dev->dev_private;
1015 struct intel_plane *intel_plane;
1016 u32 dvscntr;
1017 int ret = 0;
1018
1019 intel_plane = to_intel_plane(plane);
1020
1021 I915_WRITE(DVSKEYVAL(intel_plane->pipe), key->min_value);
1022 I915_WRITE(DVSKEYMAX(intel_plane->pipe), key->max_value);
1023 I915_WRITE(DVSKEYMSK(intel_plane->pipe), key->channel_mask);
1024
1025 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
1026 dvscntr &= ~(DVS_SOURCE_KEY | DVS_DEST_KEY);
1027 if (key->flags & I915_SET_COLORKEY_DESTINATION)
1028 dvscntr |= DVS_DEST_KEY;
1029 else if (key->flags & I915_SET_COLORKEY_SOURCE)
1030 dvscntr |= DVS_SOURCE_KEY;
1031 I915_WRITE(DVSCNTR(intel_plane->pipe), dvscntr);
1032
1033 POSTING_READ(DVSKEYMSK(intel_plane->pipe));
1034
1035 return ret;
1036}
1037
1038static void
d1686ae3 1039ilk_get_colorkey(struct drm_plane *plane, struct drm_intel_sprite_colorkey *key)
8ea30864
JB		 1040{
1041 struct drm_device *dev = plane->dev;
1042 struct drm_i915_private *dev_priv = dev->dev_private;
1043 struct intel_plane *intel_plane;
1044 u32 dvscntr;
1045
1046 intel_plane = to_intel_plane(plane);
1047
1048 key->min_value = I915_READ(DVSKEYVAL(intel_plane->pipe));
1049 key->max_value = I915_READ(DVSKEYMAX(intel_plane->pipe));
1050 key->channel_mask = I915_READ(DVSKEYMSK(intel_plane->pipe));
1051 key->flags = 0;
1052
1053 dvscntr = I915_READ(DVSCNTR(intel_plane->pipe));
1054
1055 if (dvscntr & DVS_DEST_KEY)
1056 key->flags = I915_SET_COLORKEY_DESTINATION;
1057 else if (dvscntr & DVS_SOURCE_KEY)
1058 key->flags = I915_SET_COLORKEY_SOURCE;
1059 else
1060 key->flags = I915_SET_COLORKEY_NONE;
1061}
1062
efb31d15
VS		 1063static bool colorkey_enabled(struct intel_plane *intel_plane)
1064{
1065 struct drm_intel_sprite_colorkey key;
1066
1067 intel_plane->get_colorkey(&intel_plane->base, &key);
1068
1069 return key.flags != I915_SET_COLORKEY_NONE;
1070}
1071
b840d907 1072static int
96d61a7f
GP		 1073intel_check_sprite_plane(struct drm_plane *plane,
1074 struct intel_plane_state *state)
b840d907 1075{
96d61a7f 1076 struct intel_crtc *intel_crtc = to_intel_crtc(state->crtc);
b840d907 1077 struct intel_plane *intel_plane = to_intel_plane(plane);
96d61a7f 1078 struct drm_framebuffer *fb = state->fb;
77cde952 1079 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
96d61a7f
GP		 1080 int crtc_x, crtc_y;
1081 unsigned int crtc_w, crtc_h;
1082 uint32_t src_x, src_y, src_w, src_h;
1083 struct drm_rect *src = &state->src;
1084 struct drm_rect *dst = &state->dst;
1085 struct drm_rect *orig_src = &state->orig_src;
1086 const struct drm_rect *clip = &state->clip;
1731693a
VS		 1087 int hscale, vscale;
1088 int max_scale, min_scale;
1089 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
5e1bac2f 1090
1731693a
VS		 1091 /* Don't modify another pipe's plane */
1092 if (intel_plane->pipe != intel_crtc->pipe) {
1093 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
b840d907 1094 return -EINVAL;
1731693a 1095 }
b840d907 1096
1731693a
VS		 1097 /* FIXME check all gen limits */
1098 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
1099 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
b840d907 1100 return -EINVAL;
1731693a 1101 }
b840d907 1102
94c6419e
DL		 1103 /* Sprite planes can be linear or x-tiled surfaces */
1104 switch (obj->tiling_mode) {
1105 case I915_TILING_NONE:
1106 case I915_TILING_X:
1107 break;
1108 default:
1731693a 1109 DRM_DEBUG_KMS("Unsupported tiling mode\n");
94c6419e
DL		 1110 return -EINVAL;
1111 }
1112
3c3686cd
VS		 1113 /*
1114 * FIXME the following code does a bunch of fuzzy adjustments to the
1115 * coordinates and sizes. We probably need some way to decide whether
1116 * more strict checking should be done instead.
1117 */
1731693a
VS		 1118 max_scale = intel_plane->max_downscale << 16;
1119 min_scale = intel_plane->can_scale ? 1 : (1 << 16);
1120
96d61a7f 1121 drm_rect_rotate(src, fb->width << 16, fb->height << 16,
76eebda7
VS		 1122 intel_plane->rotation);
1123
96d61a7f 1124 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
3c3686cd 1125 BUG_ON(hscale < 0);
1731693a 1126
96d61a7f 1127 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
3c3686cd 1128 BUG_ON(vscale < 0);
b840d907 1129
96d61a7f 1130 state->visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
b840d907 1131
96d61a7f
GP		 1132 crtc_x = dst->x1;
1133 crtc_y = dst->y1;
1134 crtc_w = drm_rect_width(dst);
1135 crtc_h = drm_rect_height(dst);
2d354c34 1136
96d61a7f 1137 if (state->visible) {
3c3686cd 1138 /* check again in case clipping clamped the results */
96d61a7f 1139 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
3c3686cd
VS		 1140 if (hscale < 0) {
1141 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
96d61a7f
GP		 1142 drm_rect_debug_print(src, true);
1143 drm_rect_debug_print(dst, false);
3c3686cd
VS		 1144
1145 return hscale;
1146 }
1147
96d61a7f 1148 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
3c3686cd
VS		 1149 if (vscale < 0) {
1150 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
96d61a7f
GP		 1151 drm_rect_debug_print(src, true);
1152 drm_rect_debug_print(dst, false);
3c3686cd
VS		 1153
1154 return vscale;
1155 }
1156
1731693a 1157 /* Make the source viewport size an exact multiple of the scaling factors. */
96d61a7f
GP		 1158 drm_rect_adjust_size(src,
1159 drm_rect_width(dst) * hscale - drm_rect_width(src),
1160 drm_rect_height(dst) * vscale - drm_rect_height(src));
1731693a 1161
96d61a7f 1162 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
76eebda7
VS		 1163 intel_plane->rotation);
1164
1731693a 1165 /* sanity check to make sure the src viewport wasn't enlarged */
96d61a7f
GP		 1166 WARN_ON(src->x1 < (int) orig_src->x1 ||
1167 src->y1 < (int) orig_src->y1 ||
1168 src->x2 > (int) orig_src->x2 ||
1169 src->y2 > (int) orig_src->y2);
1731693a
VS		 1170
1171 /*
1172 * Hardware doesn't handle subpixel coordinates.
1173 * Adjust to (macro)pixel boundary, but be careful not to
1174 * increase the source viewport size, because that could
1175 * push the downscaling factor out of bounds.
1731693a 1176 */
96d61a7f
GP		 1177 src_x = src->x1 >> 16;
1178 src_w = drm_rect_width(src) >> 16;
1179 src_y = src->y1 >> 16;
1180 src_h = drm_rect_height(src) >> 16;
1731693a
VS		 1181
1182 if (format_is_yuv(fb->pixel_format)) {
1183 src_x &= ~1;
1184 src_w &= ~1;
1185
1186 /*
1187 * Must keep src and dst the
1188 * same if we can't scale.
1189 */
1190 if (!intel_plane->can_scale)
1191 crtc_w &= ~1;
1192
1193 if (crtc_w == 0)
96d61a7f 1194 state->visible = false;
1731693a
VS		 1195 }
1196 }
1197
1198 /* Check size restrictions when scaling */
96d61a7f 1199 if (state->visible && (src_w != crtc_w || src_h != crtc_h)) {
1731693a
VS		 1200 unsigned int width_bytes;
1201
1202 WARN_ON(!intel_plane->can_scale);
1203
1204 /* FIXME interlacing min height is 6 */
1205
1206 if (crtc_w < 3 || crtc_h < 3)
96d61a7f 1207 state->visible = false;
1731693a
VS		 1208
1209 if (src_w < 3 || src_h < 3)
96d61a7f 1210 state->visible = false;
1731693a 1211
96d61a7f
GP		 1212 width_bytes = ((src_x * pixel_size) & 63) +
1213 src_w * pixel_size;
1731693a
VS		 1214
1215 if (src_w > 2048 || src_h > 2048 ||
1216 width_bytes > 4096 || fb->pitches[0] > 4096) {
1217 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
1218 return -EINVAL;
1219 }
1220 }
1221
96d61a7f
GP		 1222 if (state->visible) {
1223 src->x1 = src_x;
1224 src->x2 = src_x + src_w;
1225 src->y1 = src_y;
1226 src->y2 = src_y + src_h;
1227 }
1228
1229 dst->x1 = crtc_x;
1230 dst->x2 = crtc_x + crtc_w;
1231 dst->y1 = crtc_y;
1232 dst->y2 = crtc_y + crtc_h;
1233
1234 return 0;
1235}
1236
1237static int
34aa50a9
GP		 1238intel_prepare_sprite_plane(struct drm_plane *plane,
1239 struct intel_plane_state *state)
96d61a7f
GP		 1240{
1241 struct drm_device *dev = plane->dev;
1242 struct drm_crtc *crtc = state->crtc;
1243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
96d61a7f
GP		 1244 enum pipe pipe = intel_crtc->pipe;
1245 struct drm_framebuffer *fb = state->fb;
34aa50a9
GP		 1246 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1247 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
96d61a7f 1248 int ret;
b840d907 1249
25067bfc
GP		 1250 if (old_obj != obj) {
1251 mutex_lock(&dev->struct_mutex);
82284b6b 1252
25067bfc
GP		 1253 /* Note that this will apply the VT-d workaround for scanouts,
1254 * which is more restrictive than required for sprites. (The
1255 * primary plane requires 256KiB alignment with 64 PTE padding,
1256 * the sprite planes only require 128KiB alignment and 32 PTE
1257 * padding.
1258 */
1259 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
1260 if (ret == 0)
1261 i915_gem_track_fb(old_obj, obj,
1262 INTEL_FRONTBUFFER_SPRITE(pipe));
1263 mutex_unlock(&dev->struct_mutex);
1264 if (ret)
1265 return ret;
1266 }
b840d907 1267
34aa50a9
GP		 1268 return 0;
1269}
1270
1271static void
1272intel_commit_sprite_plane(struct drm_plane *plane,
1273 struct intel_plane_state *state)
1274{
1275 struct drm_device *dev = plane->dev;
1276 struct drm_crtc *crtc = state->crtc;
1277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1278 struct intel_plane *intel_plane = to_intel_plane(plane);
1279 enum pipe pipe = intel_crtc->pipe;
1280 struct drm_framebuffer *fb = state->fb;
77cde952
GP		 1281 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1282 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
34aa50a9
GP		 1283 int crtc_x, crtc_y;
1284 unsigned int crtc_w, crtc_h;
1285 uint32_t src_x, src_y, src_w, src_h;
1286 struct drm_rect *dst = &state->dst;
1287 const struct drm_rect *clip = &state->clip;
1288 bool primary_enabled;
1289
1290 /*
1291 * If the sprite is completely covering the primary plane,
1292 * we can disable the primary and save power.
1293 */
1294 primary_enabled = !drm_rect_equals(dst, clip) || colorkey_enabled(intel_plane);
1295 WARN_ON(!primary_enabled && !state->visible && intel_crtc->active);
1296
96d61a7f
GP		 1297 intel_plane->crtc_x = state->orig_dst.x1;
1298 intel_plane->crtc_y = state->orig_dst.y1;
1299 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
1300 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
1301 intel_plane->src_x = state->orig_src.x1;
1302 intel_plane->src_y = state->orig_src.y1;
1303 intel_plane->src_w = drm_rect_width(&state->orig_src);
1304 intel_plane->src_h = drm_rect_height(&state->orig_src);
b840d907
JB		 1305 intel_plane->obj = obj;
1306
03c5b25f 1307 if (intel_crtc->active) {
5b633d6b
VS		 1308 bool primary_was_enabled = intel_crtc->primary_enabled;
1309
1310 intel_crtc->primary_enabled = primary_enabled;
1311
46a55d30
VS		 1312 if (primary_was_enabled != primary_enabled)
1313 intel_crtc_wait_for_pending_flips(crtc);
1314
5b633d6b
VS		 1315 if (primary_was_enabled && !primary_enabled)
1316 intel_pre_disable_primary(crtc);
03c5b25f 1317
96d61a7f
GP		 1318 if (state->visible) {
1319 crtc_x = state->dst.x1;
e259f172 1320 crtc_y = state->dst.y1;
96d61a7f
GP		 1321 crtc_w = drm_rect_width(&state->dst);
1322 crtc_h = drm_rect_height(&state->dst);
1323 src_x = state->src.x1;
1324 src_y = state->src.y1;
1325 src_w = drm_rect_width(&state->src);
1326 src_h = drm_rect_height(&state->src);
03c5b25f
VS		 1327 intel_plane->update_plane(plane, crtc, fb, obj,
1328 crtc_x, crtc_y, crtc_w, crtc_h,
1329 src_x, src_y, src_w, src_h);
96d61a7f 1330 } else {
03c5b25f 1331 intel_plane->disable_plane(plane, crtc);
96d61a7f
GP		 1332 }
1333
03c5b25f 1334
f99d7069
DV		 1335 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_SPRITE(pipe));
1336
5b633d6b
VS		 1337 if (!primary_was_enabled && primary_enabled)
1338 intel_post_enable_primary(crtc);
03c5b25f 1339 }
175bd420 1340
b840d907 1341 /* Unpin old obj after new one is active to avoid ugliness */
25067bfc
GP		 1342 if (old_obj && old_obj != obj) {
1343
b840d907
JB		 1344 /*
1345 * It's fairly common to simply update the position of
1346 * an existing object. In that case, we don't need to
1347 * wait for vblank to avoid ugliness, we only need to
1348 * do the pin & ref bookkeeping.
1349 */
25067bfc 1350 if (intel_crtc->active)
2afd9efd 1351 intel_wait_for_vblank(dev, intel_crtc->pipe);
82284b6b
VS		 1352
1353 mutex_lock(&dev->struct_mutex);
1690e1eb 1354 intel_unpin_fb_obj(old_obj);
82284b6b 1355 mutex_unlock(&dev->struct_mutex);
b840d907 1356 }
b840d907
JB		 1357}
1358
96d61a7f
GP		 1359static int
1360intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
1361 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
1362 unsigned int crtc_w, unsigned int crtc_h,
1363 uint32_t src_x, uint32_t src_y,
1364 uint32_t src_w, uint32_t src_h)
1365{
1366 struct intel_plane_state state;
1367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1368 int ret;
1369
1370 state.crtc = crtc;
1371 state.fb = fb;
1372
1373 /* sample coordinates in 16.16 fixed point */
1374 state.src.x1 = src_x;
1375 state.src.x2 = src_x + src_w;
1376 state.src.y1 = src_y;
1377 state.src.y2 = src_y + src_h;
1378
1379 /* integer pixels */
1380 state.dst.x1 = crtc_x;
1381 state.dst.x2 = crtc_x + crtc_w;
1382 state.dst.y1 = crtc_y;
1383 state.dst.y2 = crtc_y + crtc_h;
1384
1385 state.clip.x1 = 0;
1386 state.clip.y1 = 0;
1387 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
1388 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
1389 state.orig_src = state.src;
1390 state.orig_dst = state.dst;
1391
1392 ret = intel_check_sprite_plane(plane, &state);
1393 if (ret)
1394 return ret;
1395
34aa50a9
GP		 1396 ret = intel_prepare_sprite_plane(plane, &state);
1397 if (ret)
1398 return ret;
1399
1400 intel_commit_sprite_plane(plane, &state);
1401 return 0;
96d61a7f
GP		 1402}
1403
b840d907
JB		 1404static int
1405intel_disable_plane(struct drm_plane *plane)
1406{
1407 struct drm_device *dev = plane->dev;
1408 struct intel_plane *intel_plane = to_intel_plane(plane);
03c5b25f 1409 struct intel_crtc *intel_crtc;
a071fa00 1410 enum pipe pipe;
b840d907 1411
88a94a58
VS		 1412 if (!plane->fb)
1413 return 0;
1414
1415 if (WARN_ON(!plane->crtc))
1416 return -EINVAL;
1417
03c5b25f 1418 intel_crtc = to_intel_crtc(plane->crtc);
a071fa00 1419 pipe = intel_crtc->pipe;
03c5b25f
VS		 1420
1421 if (intel_crtc->active) {
5b633d6b
VS		 1422 bool primary_was_enabled = intel_crtc->primary_enabled;
1423
1424 intel_crtc->primary_enabled = true;
1425
03c5b25f 1426 intel_plane->disable_plane(plane, plane->crtc);
5b633d6b
VS		 1427
1428 if (!primary_was_enabled && intel_crtc->primary_enabled)
1429 intel_post_enable_primary(plane->crtc);
03c5b25f 1430 }
b840d907 1431
5f3fb46b
VS		 1432 if (intel_plane->obj) {
1433 if (intel_crtc->active)
1434 intel_wait_for_vblank(dev, intel_plane->pipe);
c626d317 1435
5f3fb46b
VS		 1436 mutex_lock(&dev->struct_mutex);
1437 intel_unpin_fb_obj(intel_plane->obj);
a071fa00
DV		 1438 i915_gem_track_fb(intel_plane->obj, NULL,
1439 INTEL_FRONTBUFFER_SPRITE(pipe));
5f3fb46b 1440 mutex_unlock(&dev->struct_mutex);
82284b6b 1441
5f3fb46b
VS		 1442 intel_plane->obj = NULL;
1443 }
b840d907 1444
5f3fb46b 1445 return 0;
b840d907
JB		 1446}
1447
1448static void intel_destroy_plane(struct drm_plane *plane)
1449{
1450 struct intel_plane *intel_plane = to_intel_plane(plane);
1451 intel_disable_plane(plane);
1452 drm_plane_cleanup(plane);
1453 kfree(intel_plane);
1454}
1455
8ea30864
JB		 1456int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
1457 struct drm_file *file_priv)
1458{
1459 struct drm_intel_sprite_colorkey *set = data;
8ea30864
JB		 1460 struct drm_plane *plane;
1461 struct intel_plane *intel_plane;
1462 int ret = 0;
1463
1cff8f6b
DV		 1464 if (!drm_core_check_feature(dev, DRIVER_MODESET))
1465 return -ENODEV;
8ea30864
JB		 1466
1467 /* Make sure we don't try to enable both src & dest simultaneously */
1468 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
1469 return -EINVAL;
1470
a0e99e68 1471 drm_modeset_lock_all(dev);
8ea30864 1472
7707e653
RC		 1473 plane = drm_plane_find(dev, set->plane_id);
1474 if (!plane) {
3f2c2057 1475 ret = -ENOENT;
8ea30864
JB		 1476 goto out_unlock;
1477 }
1478
8ea30864
JB		 1479 intel_plane = to_intel_plane(plane);
1480 ret = intel_plane->update_colorkey(plane, set);
1481
1482out_unlock:
a0e99e68 1483 drm_modeset_unlock_all(dev);
8ea30864
JB		 1484 return ret;
1485}
1486
1487int intel_sprite_get_colorkey(struct drm_device *dev, void *data,
1488 struct drm_file *file_priv)
1489{
1490 struct drm_intel_sprite_colorkey *get = data;
8ea30864
JB		 1491 struct drm_plane *plane;
1492 struct intel_plane *intel_plane;
1493 int ret = 0;
1494
1cff8f6b
DV		 1495 if (!drm_core_check_feature(dev, DRIVER_MODESET))
1496 return -ENODEV;
8ea30864 1497
a0e99e68 1498 drm_modeset_lock_all(dev);
8ea30864 1499
7707e653
RC		 1500 plane = drm_plane_find(dev, get->plane_id);
1501 if (!plane) {
3f2c2057 1502 ret = -ENOENT;
8ea30864
JB		 1503 goto out_unlock;
1504 }
1505
8ea30864
JB		 1506 intel_plane = to_intel_plane(plane);
1507 intel_plane->get_colorkey(plane, get);
1508
1509out_unlock:
a0e99e68 1510 drm_modeset_unlock_all(dev);
8ea30864
JB		 1511 return ret;
1512}
1513
48404c1e
SJ		 1514int intel_plane_set_property(struct drm_plane *plane,
1515 struct drm_property *prop,
1516 uint64_t val)
7ed6eeee
VS		 1517{
1518 struct drm_device *dev = plane->dev;
1519 struct intel_plane *intel_plane = to_intel_plane(plane);
1520 uint64_t old_val;
1521 int ret = -ENOENT;
1522
1523 if (prop == dev->mode_config.rotation_property) {
1524 /* exactly one rotation angle please */
1525 if (hweight32(val & 0xf) != 1)
1526 return -EINVAL;
1527
09dba00c
VS		 1528 if (intel_plane->rotation == val)
1529 return 0;
1530
7ed6eeee
VS		 1531 old_val = intel_plane->rotation;
1532 intel_plane->rotation = val;
1533 ret = intel_plane_restore(plane);
1534 if (ret)
1535 intel_plane->rotation = old_val;
1536 }
1537
1538 return ret;
1539}
1540
e57465f3 1541int intel_plane_restore(struct drm_plane *plane)
5e1bac2f
JB		 1542{
1543 struct intel_plane *intel_plane = to_intel_plane(plane);
1544
1545 if (!plane->crtc || !plane->fb)
e57465f3 1546 return 0;
5e1bac2f 1547
48404c1e 1548 return plane->funcs->update_plane(plane, plane->crtc, plane->fb,
e57465f3
VS		 1549 intel_plane->crtc_x, intel_plane->crtc_y,
1550 intel_plane->crtc_w, intel_plane->crtc_h,
1551 intel_plane->src_x, intel_plane->src_y,
1552 intel_plane->src_w, intel_plane->src_h);
5e1bac2f
JB		 1553}
1554
bb53d4ae
VS		 1555void intel_plane_disable(struct drm_plane *plane)
1556{
1557 if (!plane->crtc || !plane->fb)
1558 return;
1559
1560 intel_disable_plane(plane);
1561}
1562
b840d907
JB		 1563static const struct drm_plane_funcs intel_plane_funcs = {
1564 .update_plane = intel_update_plane,
1565 .disable_plane = intel_disable_plane,
1566 .destroy = intel_destroy_plane,
7ed6eeee 1567 .set_property = intel_plane_set_property,
b840d907
JB		 1568};
1569
d1686ae3
CW		 1570static uint32_t ilk_plane_formats[] = {
1571 DRM_FORMAT_XRGB8888,
1572 DRM_FORMAT_YUYV,
1573 DRM_FORMAT_YVYU,
1574 DRM_FORMAT_UYVY,
1575 DRM_FORMAT_VYUY,
1576};
1577
b840d907
JB		 1578static uint32_t snb_plane_formats[] = {
1579 DRM_FORMAT_XBGR8888,
1580 DRM_FORMAT_XRGB8888,
1581 DRM_FORMAT_YUYV,
1582 DRM_FORMAT_YVYU,
1583 DRM_FORMAT_UYVY,
1584 DRM_FORMAT_VYUY,
1585};
1586
7f1f3851
JB		 1587static uint32_t vlv_plane_formats[] = {
1588 DRM_FORMAT_RGB565,
1589 DRM_FORMAT_ABGR8888,
1590 DRM_FORMAT_ARGB8888,
1591 DRM_FORMAT_XBGR8888,
1592 DRM_FORMAT_XRGB8888,
1593 DRM_FORMAT_XBGR2101010,
1594 DRM_FORMAT_ABGR2101010,
1595 DRM_FORMAT_YUYV,
1596 DRM_FORMAT_YVYU,
1597 DRM_FORMAT_UYVY,
1598 DRM_FORMAT_VYUY,
1599};
1600
dc2a41b4
DL		 1601static uint32_t skl_plane_formats[] = {
1602 DRM_FORMAT_RGB565,
1603 DRM_FORMAT_ABGR8888,
1604 DRM_FORMAT_ARGB8888,
1605 DRM_FORMAT_XBGR8888,
1606 DRM_FORMAT_XRGB8888,
1607 DRM_FORMAT_YUYV,
1608 DRM_FORMAT_YVYU,
1609 DRM_FORMAT_UYVY,
1610 DRM_FORMAT_VYUY,
1611};
1612
b840d907 1613int
7f1f3851 1614intel_plane_init(struct drm_device *dev, enum pipe pipe, int plane)
b840d907
JB		 1615{
1616 struct intel_plane *intel_plane;
1617 unsigned long possible_crtcs;
d1686ae3
CW		 1618 const uint32_t *plane_formats;
1619 int num_plane_formats;
b840d907
JB		 1620 int ret;
1621
d1686ae3 1622 if (INTEL_INFO(dev)->gen < 5)
b840d907 1623 return -ENODEV;
b840d907 1624
b14c5679 1625 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
b840d907
JB		 1626 if (!intel_plane)
1627 return -ENOMEM;
1628
d1686ae3
CW		 1629 switch (INTEL_INFO(dev)->gen) {
1630 case 5:
1631 case 6:
2d354c34 1632 intel_plane->can_scale = true;
b840d907 1633 intel_plane->max_downscale = 16;
d1686ae3
CW		 1634 intel_plane->update_plane = ilk_update_plane;
1635 intel_plane->disable_plane = ilk_disable_plane;
1636 intel_plane->update_colorkey = ilk_update_colorkey;
1637 intel_plane->get_colorkey = ilk_get_colorkey;
1638
1639 if (IS_GEN6(dev)) {
1640 plane_formats = snb_plane_formats;
1641 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1642 } else {
1643 plane_formats = ilk_plane_formats;
1644 num_plane_formats = ARRAY_SIZE(ilk_plane_formats);
1645 }
1646 break;
1647
1648 case 7:
4e0bbc31 1649 case 8:
d49f7091 1650 if (IS_IVYBRIDGE(dev)) {
2d354c34 1651 intel_plane->can_scale = true;
d49f7091
DL		 1652 intel_plane->max_downscale = 2;
1653 } else {
1654 intel_plane->can_scale = false;
1655 intel_plane->max_downscale = 1;
1656 }
7f1f3851
JB		 1657
1658 if (IS_VALLEYVIEW(dev)) {
7f1f3851
JB		 1659 intel_plane->update_plane = vlv_update_plane;
1660 intel_plane->disable_plane = vlv_disable_plane;
1661 intel_plane->update_colorkey = vlv_update_colorkey;
1662 intel_plane->get_colorkey = vlv_get_colorkey;
1663
1664 plane_formats = vlv_plane_formats;
1665 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
1666 } else {
7f1f3851
JB		 1667 intel_plane->update_plane = ivb_update_plane;
1668 intel_plane->disable_plane = ivb_disable_plane;
1669 intel_plane->update_colorkey = ivb_update_colorkey;
1670 intel_plane->get_colorkey = ivb_get_colorkey;
1671
1672 plane_formats = snb_plane_formats;
1673 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1674 }
d1686ae3 1675 break;
dc2a41b4
DL		 1676 case 9:
1677 /*
1678 * FIXME: Skylake planes can be scaled (with some restrictions),
1679 * but this is for another time.
1680 */
1681 intel_plane->can_scale = false;
1682 intel_plane->max_downscale = 1;
1683 intel_plane->update_plane = skl_update_plane;
1684 intel_plane->disable_plane = skl_disable_plane;
1685 intel_plane->update_colorkey = skl_update_colorkey;
1686 intel_plane->get_colorkey = skl_get_colorkey;
1687
1688 plane_formats = skl_plane_formats;
1689 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1690 break;
d1686ae3 1691 default:
a8b0bbab 1692 kfree(intel_plane);
d1686ae3 1693 return -ENODEV;
b840d907
JB		 1694 }
1695
1696 intel_plane->pipe = pipe;
7f1f3851 1697 intel_plane->plane = plane;
76eebda7 1698 intel_plane->rotation = BIT(DRM_ROTATE_0);
b840d907 1699 possible_crtcs = (1 << pipe);
8fe8a3fe
DF		 1700 ret = drm_universal_plane_init(dev, &intel_plane->base, possible_crtcs,
1701 &intel_plane_funcs,
1702 plane_formats, num_plane_formats,
1703 DRM_PLANE_TYPE_OVERLAY);
7ed6eeee 1704 if (ret) {
b840d907 1705 kfree(intel_plane);
7ed6eeee
VS		 1706 goto out;
1707 }
1708
1709 if (!dev->mode_config.rotation_property)
1710 dev->mode_config.rotation_property =
1711 drm_mode_create_rotation_property(dev,
1712 BIT(DRM_ROTATE_0) |
1713 BIT(DRM_ROTATE_180));
1714
1715 if (dev->mode_config.rotation_property)
1716 drm_object_attach_property(&intel_plane->base.base,
1717 dev->mode_config.rotation_property,
1718 intel_plane->rotation);
b840d907 1719
7ed6eeee 1720 out:
b840d907
JB		 1721 return ret;
1722}
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