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33a732f4 AD |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | */ | |
8c4f24f9 AH |
24 | #ifndef _INTEL_UC_H_ |
25 | #define _INTEL_UC_H_ | |
33a732f4 AD |
26 | |
27 | #include "intel_guc_fwif.h" | |
28 | #include "i915_guc_reg.h" | |
0b63bb14 | 29 | #include "intel_ringbuffer.h" |
33a732f4 | 30 | |
4741da92 CW |
31 | #include "i915_vma.h" |
32 | ||
e73bdd20 CW |
33 | struct drm_i915_gem_request; |
34 | ||
86e06cc0 DG |
35 | /* |
36 | * This structure primarily describes the GEM object shared with the GuC. | |
37 | * The GEM object is held for the entire lifetime of our interaction with | |
38 | * the GuC, being allocated before the GuC is loaded with its firmware. | |
39 | * Because there's no way to update the address used by the GuC after | |
40 | * initialisation, the shared object must stay pinned into the GGTT as | |
41 | * long as the GuC is in use. We also keep the first page (only) mapped | |
42 | * into kernel address space, as it includes shared data that must be | |
43 | * updated on every request submission. | |
44 | * | |
45 | * The single GEM object described here is actually made up of several | |
46 | * separate areas, as far as the GuC is concerned. The first page (kept | |
47 | * kmap'd) includes the "process decriptor" which holds sequence data for | |
48 | * the doorbell, and one cacheline which actually *is* the doorbell; a | |
49 | * write to this will "ring the doorbell" (i.e. send an interrupt to the | |
50 | * GuC). The subsequent pages of the client object constitute the work | |
51 | * queue (a circular array of work items), again described in the process | |
52 | * descriptor. Work queue pages are mapped momentarily as required. | |
53 | * | |
551aaecd DG |
54 | * We also keep a few statistics on failures. Ideally, these should all |
55 | * be zero! | |
56 | * no_wq_space: times that the submission pre-check found no space was | |
57 | * available in the work queue (note, the queue is shared, | |
58 | * not per-engine). It is OK for this to be nonzero, but | |
59 | * it should not be huge! | |
60 | * q_fail: failed to enqueue a work item. This should never happen, | |
61 | * because we check for space beforehand. | |
62 | * b_fail: failed to ring the doorbell. This should never happen, unless | |
63 | * somehow the hardware misbehaves, or maybe if the GuC firmware | |
64 | * crashes? We probably need to reset the GPU to recover. | |
65 | * retcode: errno from last guc_submit() | |
86e06cc0 | 66 | */ |
44a28b1d | 67 | struct i915_guc_client { |
8b797af1 | 68 | struct i915_vma *vma; |
72aa0d89 | 69 | void *vaddr; |
e2efd130 | 70 | struct i915_gem_context *owner; |
44a28b1d | 71 | struct intel_guc *guc; |
e02757d9 DG |
72 | |
73 | uint32_t engines; /* bitmap of (host) engine ids */ | |
44a28b1d DG |
74 | uint32_t priority; |
75 | uint32_t ctx_index; | |
44a28b1d | 76 | uint32_t proc_desc_offset; |
774439e1 | 77 | |
44a28b1d | 78 | uint32_t doorbell_offset; |
357248bf | 79 | uint32_t doorbell_cookie; |
44a28b1d | 80 | uint16_t doorbell_id; |
774439e1 | 81 | uint16_t padding[3]; /* Maintain alignment */ |
44a28b1d | 82 | |
dadd481b | 83 | spinlock_t wq_lock; |
44a28b1d DG |
84 | uint32_t wq_offset; |
85 | uint32_t wq_size; | |
44a28b1d | 86 | uint32_t wq_tail; |
dadd481b | 87 | uint32_t wq_rsvd; |
551aaecd | 88 | uint32_t no_wq_space; |
44a28b1d DG |
89 | uint32_t b_fail; |
90 | int retcode; | |
551aaecd DG |
91 | |
92 | /* Per-engine counts of GuC submissions */ | |
0b63bb14 | 93 | uint64_t submissions[I915_NUM_ENGINES]; |
44a28b1d DG |
94 | }; |
95 | ||
33a732f4 AD |
96 | enum intel_guc_fw_status { |
97 | GUC_FIRMWARE_FAIL = -1, | |
98 | GUC_FIRMWARE_NONE = 0, | |
99 | GUC_FIRMWARE_PENDING, | |
100 | GUC_FIRMWARE_SUCCESS | |
101 | }; | |
102 | ||
103 | /* | |
104 | * This structure encapsulates all the data needed during the process | |
105 | * of fetching, caching, and loading the firmware image into the GuC. | |
106 | */ | |
107 | struct intel_guc_fw { | |
33a732f4 AD |
108 | const char * guc_fw_path; |
109 | size_t guc_fw_size; | |
110 | struct drm_i915_gem_object * guc_fw_obj; | |
111 | enum intel_guc_fw_status guc_fw_fetch_status; | |
112 | enum intel_guc_fw_status guc_fw_load_status; | |
113 | ||
114 | uint16_t guc_fw_major_wanted; | |
115 | uint16_t guc_fw_minor_wanted; | |
116 | uint16_t guc_fw_major_found; | |
117 | uint16_t guc_fw_minor_found; | |
feda33ef AD |
118 | |
119 | uint32_t header_size; | |
120 | uint32_t header_offset; | |
121 | uint32_t rsa_size; | |
122 | uint32_t rsa_offset; | |
123 | uint32_t ucode_size; | |
124 | uint32_t ucode_offset; | |
33a732f4 AD |
125 | }; |
126 | ||
d6b40b4b AG |
127 | struct intel_guc_log { |
128 | uint32_t flags; | |
129 | struct i915_vma *vma; | |
4100b2ab SAK |
130 | void *buf_addr; |
131 | struct workqueue_struct *flush_wq; | |
132 | struct work_struct flush_work; | |
f8240835 | 133 | struct rchan *relay_chan; |
5aa1ee4b AG |
134 | |
135 | /* logging related stats */ | |
136 | u32 capture_miss_count; | |
137 | u32 flush_interrupt_count; | |
138 | u32 prev_overflow_count[GUC_MAX_LOG_BUFFER]; | |
139 | u32 total_overflow_count[GUC_MAX_LOG_BUFFER]; | |
140 | u32 flush_count[GUC_MAX_LOG_BUFFER]; | |
d6b40b4b AG |
141 | }; |
142 | ||
33a732f4 AD |
143 | struct intel_guc { |
144 | struct intel_guc_fw guc_fw; | |
d6b40b4b | 145 | struct intel_guc_log log; |
bac427f8 | 146 | |
a80bc45f | 147 | /* intel_guc_recv interrupt related state */ |
26705e20 SAK |
148 | bool interrupts_enabled; |
149 | ||
8b797af1 CW |
150 | struct i915_vma *ads_vma; |
151 | struct i915_vma *ctx_pool_vma; | |
bac427f8 | 152 | struct ida ctx_ids; |
44a28b1d DG |
153 | |
154 | struct i915_guc_client *execbuf_client; | |
155 | ||
44a28b1d DG |
156 | DECLARE_BITMAP(doorbell_bitmap, GUC_MAX_DOORBELLS); |
157 | uint32_t db_cacheline; /* Cyclic counter mod pagesize */ | |
158 | ||
159 | /* Action status & statistics */ | |
160 | uint64_t action_count; /* Total commands issued */ | |
161 | uint32_t action_cmd; /* Last command word */ | |
162 | uint32_t action_status; /* Last return status */ | |
163 | uint32_t action_fail; /* Total number of failures */ | |
164 | int32_t action_err; /* Last error code */ | |
165 | ||
0b63bb14 DG |
166 | uint64_t submissions[I915_NUM_ENGINES]; |
167 | uint32_t last_seqno[I915_NUM_ENGINES]; | |
5dd7989b | 168 | |
a80bc45f AH |
169 | /* To serialize the intel_guc_send actions */ |
170 | struct mutex send_mutex; | |
33a732f4 AD |
171 | }; |
172 | ||
2d803c2d | 173 | /* intel_uc.c */ |
413e8fdb | 174 | void intel_uc_init_early(struct drm_i915_private *dev_priv); |
2d803c2d AH |
175 | int intel_guc_send(struct intel_guc *guc, const u32 *action, u32 len); |
176 | int intel_guc_sample_forcewake(struct intel_guc *guc); | |
177 | int intel_guc_log_flush_complete(struct intel_guc *guc); | |
178 | int intel_guc_log_flush(struct intel_guc *guc); | |
179 | int intel_guc_log_control(struct intel_guc *guc, u32 control_val); | |
180 | ||
33a732f4 | 181 | /* intel_guc_loader.c */ |
bf9e8429 TU |
182 | extern void intel_guc_init(struct drm_i915_private *dev_priv); |
183 | extern int intel_guc_setup(struct drm_i915_private *dev_priv); | |
184 | extern void intel_guc_fini(struct drm_i915_private *dev_priv); | |
33a732f4 | 185 | extern const char *intel_guc_fw_status_repr(enum intel_guc_fw_status status); |
bf9e8429 TU |
186 | extern int intel_guc_suspend(struct drm_i915_private *dev_priv); |
187 | extern int intel_guc_resume(struct drm_i915_private *dev_priv); | |
33a732f4 | 188 | |
bac427f8 | 189 | /* i915_guc_submission.c */ |
beffa517 DG |
190 | int i915_guc_submission_init(struct drm_i915_private *dev_priv); |
191 | int i915_guc_submission_enable(struct drm_i915_private *dev_priv); | |
7a9347f9 | 192 | int i915_guc_wq_reserve(struct drm_i915_gem_request *rq); |
5ba89908 | 193 | void i915_guc_wq_unreserve(struct drm_i915_gem_request *request); |
beffa517 DG |
194 | void i915_guc_submission_disable(struct drm_i915_private *dev_priv); |
195 | void i915_guc_submission_fini(struct drm_i915_private *dev_priv); | |
4100b2ab | 196 | void i915_guc_capture_logs(struct drm_i915_private *dev_priv); |
896a0cb0 | 197 | void i915_guc_flush_logs(struct drm_i915_private *dev_priv); |
f8240835 AG |
198 | void i915_guc_register(struct drm_i915_private *dev_priv); |
199 | void i915_guc_unregister(struct drm_i915_private *dev_priv); | |
685534ef | 200 | int i915_guc_log_control(struct drm_i915_private *dev_priv, u64 control_val); |
bac427f8 | 201 | |
4741da92 CW |
202 | static inline u32 guc_ggtt_offset(struct i915_vma *vma) |
203 | { | |
204 | u32 offset = i915_ggtt_offset(vma); | |
205 | GEM_BUG_ON(offset < GUC_WOPCM_TOP); | |
206 | return offset; | |
207 | } | |
208 | ||
33a732f4 | 209 | #endif |