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1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | */ | |
23 | ||
24 | #include "i915_drv.h" | |
25 | #include "intel_drv.h" | |
26 | ||
27 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 | |
28 | ||
29 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) | |
30 | { | |
31 | u32 gt_thread_status_mask; | |
32 | ||
33 | if (IS_HASWELL(dev_priv->dev)) | |
34 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; | |
35 | else | |
36 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; | |
37 | ||
38 | /* w/a for a sporadic read returning 0 by waiting for the GT | |
39 | * thread to wake up. | |
40 | */ | |
41 | if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) | |
42 | DRM_ERROR("GT thread status wait timed out\n"); | |
43 | } | |
44 | ||
45 | static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) | |
46 | { | |
47 | I915_WRITE_NOTRACE(FORCEWAKE, 0); | |
48 | POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ | |
49 | } | |
50 | ||
51 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) | |
52 | { | |
53 | if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0, | |
54 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
55 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); | |
56 | ||
57 | I915_WRITE_NOTRACE(FORCEWAKE, 1); | |
58 | POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ | |
59 | ||
60 | if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1), | |
61 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
62 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); | |
63 | ||
64 | /* WaRsForcewakeWaitTC0:snb */ | |
65 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
66 | } | |
67 | ||
68 | static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) | |
69 | { | |
70 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); | |
71 | /* something from same cacheline, but !FORCEWAKE_MT */ | |
72 | POSTING_READ(ECOBUS); | |
73 | } | |
74 | ||
75 | static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) | |
76 | { | |
77 | u32 forcewake_ack; | |
78 | ||
79 | if (IS_HASWELL(dev_priv->dev)) | |
80 | forcewake_ack = FORCEWAKE_ACK_HSW; | |
81 | else | |
82 | forcewake_ack = FORCEWAKE_MT_ACK; | |
83 | ||
84 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0, | |
85 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
86 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); | |
87 | ||
88 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
89 | /* something from same cacheline, but !FORCEWAKE_MT */ | |
90 | POSTING_READ(ECOBUS); | |
91 | ||
92 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL), | |
93 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
94 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); | |
95 | ||
96 | /* WaRsForcewakeWaitTC0:ivb,hsw */ | |
97 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
98 | } | |
99 | ||
100 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) | |
101 | { | |
102 | u32 gtfifodbg; | |
103 | gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); | |
104 | if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, | |
105 | "MMIO read or write has been dropped %x\n", gtfifodbg)) | |
106 | I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); | |
107 | } | |
108 | ||
109 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) | |
110 | { | |
111 | I915_WRITE_NOTRACE(FORCEWAKE, 0); | |
112 | /* something from same cacheline, but !FORCEWAKE */ | |
113 | POSTING_READ(ECOBUS); | |
114 | gen6_gt_check_fifodbg(dev_priv); | |
115 | } | |
116 | ||
117 | static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) | |
118 | { | |
119 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
120 | /* something from same cacheline, but !FORCEWAKE_MT */ | |
121 | POSTING_READ(ECOBUS); | |
122 | gen6_gt_check_fifodbg(dev_priv); | |
123 | } | |
124 | ||
125 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) | |
126 | { | |
127 | int ret = 0; | |
128 | ||
129 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { | |
130 | int loop = 500; | |
131 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
132 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { | |
133 | udelay(10); | |
134 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
135 | } | |
136 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) | |
137 | ++ret; | |
138 | dev_priv->uncore.fifo_count = fifo; | |
139 | } | |
140 | dev_priv->uncore.fifo_count--; | |
141 | ||
142 | return ret; | |
143 | } | |
144 | ||
145 | static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) | |
146 | { | |
147 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff)); | |
148 | /* something from same cacheline, but !FORCEWAKE_VLV */ | |
149 | POSTING_READ(FORCEWAKE_ACK_VLV); | |
150 | } | |
151 | ||
152 | static void vlv_force_wake_get(struct drm_i915_private *dev_priv) | |
153 | { | |
154 | if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0, | |
155 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
156 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); | |
157 | ||
158 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
159 | I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV, | |
160 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
161 | ||
162 | if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL), | |
163 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
164 | DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n"); | |
165 | ||
166 | if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) & | |
167 | FORCEWAKE_KERNEL), | |
168 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
169 | DRM_ERROR("Timed out waiting for media to ack forcewake request.\n"); | |
170 | ||
171 | /* WaRsForcewakeWaitTC0:vlv */ | |
172 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
173 | } | |
174 | ||
175 | static void vlv_force_wake_put(struct drm_i915_private *dev_priv) | |
176 | { | |
177 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
178 | I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV, | |
179 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
180 | /* The below doubles as a POSTING_READ */ | |
181 | gen6_gt_check_fifodbg(dev_priv); | |
182 | } | |
183 | ||
184 | void intel_uncore_early_sanitize(struct drm_device *dev) | |
185 | { | |
186 | struct drm_i915_private *dev_priv = dev->dev_private; | |
187 | ||
188 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) | |
189 | I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); | |
190 | } | |
191 | ||
192 | void intel_uncore_init(struct drm_device *dev) | |
193 | { | |
194 | struct drm_i915_private *dev_priv = dev->dev_private; | |
195 | ||
196 | if (IS_VALLEYVIEW(dev)) { | |
197 | dev_priv->uncore.funcs.force_wake_get = vlv_force_wake_get; | |
198 | dev_priv->uncore.funcs.force_wake_put = vlv_force_wake_put; | |
199 | } else if (IS_HASWELL(dev)) { | |
200 | dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get; | |
201 | dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put; | |
202 | } else if (IS_IVYBRIDGE(dev)) { | |
203 | u32 ecobus; | |
204 | ||
205 | /* IVB configs may use multi-threaded forcewake */ | |
206 | ||
207 | /* A small trick here - if the bios hasn't configured | |
208 | * MT forcewake, and if the device is in RC6, then | |
209 | * force_wake_mt_get will not wake the device and the | |
210 | * ECOBUS read will return zero. Which will be | |
211 | * (correctly) interpreted by the test below as MT | |
212 | * forcewake being disabled. | |
213 | */ | |
214 | mutex_lock(&dev->struct_mutex); | |
215 | __gen6_gt_force_wake_mt_get(dev_priv); | |
216 | ecobus = I915_READ_NOTRACE(ECOBUS); | |
217 | __gen6_gt_force_wake_mt_put(dev_priv); | |
218 | mutex_unlock(&dev->struct_mutex); | |
219 | ||
220 | if (ecobus & FORCEWAKE_MT_ENABLE) { | |
221 | dev_priv->uncore.funcs.force_wake_get = | |
222 | __gen6_gt_force_wake_mt_get; | |
223 | dev_priv->uncore.funcs.force_wake_put = | |
224 | __gen6_gt_force_wake_mt_put; | |
225 | } else { | |
226 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); | |
227 | DRM_INFO("when using vblank-synced partial screen updates.\n"); | |
228 | dev_priv->uncore.funcs.force_wake_get = | |
229 | __gen6_gt_force_wake_get; | |
230 | dev_priv->uncore.funcs.force_wake_put = | |
231 | __gen6_gt_force_wake_put; | |
232 | } | |
233 | } else if (IS_GEN6(dev)) { | |
234 | dev_priv->uncore.funcs.force_wake_get = | |
235 | __gen6_gt_force_wake_get; | |
236 | dev_priv->uncore.funcs.force_wake_put = | |
237 | __gen6_gt_force_wake_put; | |
238 | } | |
239 | } | |
240 | ||
241 | void intel_uncore_sanitize(struct drm_device *dev) | |
242 | { | |
243 | struct drm_i915_private *dev_priv = dev->dev_private; | |
244 | ||
245 | if (IS_VALLEYVIEW(dev)) { | |
246 | vlv_force_wake_reset(dev_priv); | |
247 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
248 | __gen6_gt_force_wake_reset(dev_priv); | |
249 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
250 | __gen6_gt_force_wake_mt_reset(dev_priv); | |
251 | } | |
252 | ||
253 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ | |
254 | intel_disable_gt_powersave(dev); | |
255 | } | |
256 | ||
257 | /* | |
258 | * Generally this is called implicitly by the register read function. However, | |
259 | * if some sequence requires the GT to not power down then this function should | |
260 | * be called at the beginning of the sequence followed by a call to | |
261 | * gen6_gt_force_wake_put() at the end of the sequence. | |
262 | */ | |
263 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) | |
264 | { | |
265 | unsigned long irqflags; | |
266 | ||
267 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
268 | if (dev_priv->uncore.forcewake_count++ == 0) | |
269 | dev_priv->uncore.funcs.force_wake_get(dev_priv); | |
270 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
271 | } | |
272 | ||
273 | /* | |
274 | * see gen6_gt_force_wake_get() | |
275 | */ | |
276 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) | |
277 | { | |
278 | unsigned long irqflags; | |
279 | ||
280 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
281 | if (--dev_priv->uncore.forcewake_count == 0) | |
282 | dev_priv->uncore.funcs.force_wake_put(dev_priv); | |
283 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
284 | } | |
285 | ||
286 | /* We give fast paths for the really cool registers */ | |
287 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ | |
288 | ((HAS_FORCE_WAKE((dev_priv)->dev)) && \ | |
289 | ((reg) < 0x40000) && \ | |
290 | ((reg) != FORCEWAKE)) | |
291 | ||
292 | static void | |
293 | ilk_dummy_write(struct drm_i915_private *dev_priv) | |
294 | { | |
295 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up | |
296 | * the chip from rc6 before touching it for real. MI_MODE is masked, | |
297 | * hence harmless to write 0 into. */ | |
298 | I915_WRITE_NOTRACE(MI_MODE, 0); | |
299 | } | |
300 | ||
301 | static void | |
302 | hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) | |
303 | { | |
304 | if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) && | |
305 | (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { | |
306 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", | |
307 | reg); | |
308 | I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); | |
309 | } | |
310 | } | |
311 | ||
312 | static void | |
313 | hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) | |
314 | { | |
315 | if (HAS_FPGA_DBG_UNCLAIMED(dev_priv->dev) && | |
316 | (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { | |
317 | DRM_ERROR("Unclaimed write to %x\n", reg); | |
318 | I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); | |
319 | } | |
320 | } | |
321 | ||
322 | #define __i915_read(x, y) \ | |
323 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | |
324 | unsigned long irqflags; \ | |
325 | u##x val = 0; \ | |
326 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ | |
327 | if (IS_GEN5(dev_priv->dev)) \ | |
328 | ilk_dummy_write(dev_priv); \ | |
329 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
330 | if (dev_priv->uncore.forcewake_count == 0) \ | |
331 | dev_priv->uncore.funcs.force_wake_get(dev_priv); \ | |
332 | val = read##y(dev_priv->regs + reg); \ | |
333 | if (dev_priv->uncore.forcewake_count == 0) \ | |
334 | dev_priv->uncore.funcs.force_wake_put(dev_priv); \ | |
335 | } else { \ | |
336 | val = read##y(dev_priv->regs + reg); \ | |
337 | } \ | |
338 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
339 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ | |
340 | return val; \ | |
341 | } | |
342 | ||
343 | __i915_read(8, b) | |
344 | __i915_read(16, w) | |
345 | __i915_read(32, l) | |
346 | __i915_read(64, q) | |
347 | #undef __i915_read | |
348 | ||
349 | #define __i915_write(x, y) \ | |
350 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | |
351 | unsigned long irqflags; \ | |
352 | u32 __fifo_ret = 0; \ | |
353 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ | |
354 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); \ | |
355 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
356 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ | |
357 | } \ | |
358 | if (IS_GEN5(dev_priv->dev)) \ | |
359 | ilk_dummy_write(dev_priv); \ | |
360 | hsw_unclaimed_reg_clear(dev_priv, reg); \ | |
361 | write##y(val, dev_priv->regs + reg); \ | |
362 | if (unlikely(__fifo_ret)) { \ | |
363 | gen6_gt_check_fifodbg(dev_priv); \ | |
364 | } \ | |
365 | hsw_unclaimed_reg_check(dev_priv, reg); \ | |
366 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ | |
367 | } | |
368 | __i915_write(8, b) | |
369 | __i915_write(16, w) | |
370 | __i915_write(32, l) | |
371 | __i915_write(64, q) | |
372 | #undef __i915_write | |
373 | ||
374 | static const struct register_whitelist { | |
375 | uint64_t offset; | |
376 | uint32_t size; | |
377 | uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ | |
378 | } whitelist[] = { | |
379 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 }, | |
380 | }; | |
381 | ||
382 | int i915_reg_read_ioctl(struct drm_device *dev, | |
383 | void *data, struct drm_file *file) | |
384 | { | |
385 | struct drm_i915_private *dev_priv = dev->dev_private; | |
386 | struct drm_i915_reg_read *reg = data; | |
387 | struct register_whitelist const *entry = whitelist; | |
388 | int i; | |
389 | ||
390 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { | |
391 | if (entry->offset == reg->offset && | |
392 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) | |
393 | break; | |
394 | } | |
395 | ||
396 | if (i == ARRAY_SIZE(whitelist)) | |
397 | return -EINVAL; | |
398 | ||
399 | switch (entry->size) { | |
400 | case 8: | |
401 | reg->val = I915_READ64(reg->offset); | |
402 | break; | |
403 | case 4: | |
404 | reg->val = I915_READ(reg->offset); | |
405 | break; | |
406 | case 2: | |
407 | reg->val = I915_READ16(reg->offset); | |
408 | break; | |
409 | case 1: | |
410 | reg->val = I915_READ8(reg->offset); | |
411 | break; | |
412 | default: | |
413 | WARN_ON(1); | |
414 | return -EINVAL; | |
415 | } | |
416 | ||
417 | return 0; | |
418 | } | |
419 | ||
420 | static int i8xx_do_reset(struct drm_device *dev) | |
421 | { | |
422 | struct drm_i915_private *dev_priv = dev->dev_private; | |
423 | ||
424 | if (IS_I85X(dev)) | |
425 | return -ENODEV; | |
426 | ||
427 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); | |
428 | POSTING_READ(D_STATE); | |
429 | ||
430 | if (IS_I830(dev) || IS_845G(dev)) { | |
431 | I915_WRITE(DEBUG_RESET_I830, | |
432 | DEBUG_RESET_DISPLAY | | |
433 | DEBUG_RESET_RENDER | | |
434 | DEBUG_RESET_FULL); | |
435 | POSTING_READ(DEBUG_RESET_I830); | |
436 | msleep(1); | |
437 | ||
438 | I915_WRITE(DEBUG_RESET_I830, 0); | |
439 | POSTING_READ(DEBUG_RESET_I830); | |
440 | } | |
441 | ||
442 | msleep(1); | |
443 | ||
444 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); | |
445 | POSTING_READ(D_STATE); | |
446 | ||
447 | return 0; | |
448 | } | |
449 | ||
450 | static int i965_reset_complete(struct drm_device *dev) | |
451 | { | |
452 | u8 gdrst; | |
453 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); | |
454 | return (gdrst & GRDOM_RESET_ENABLE) == 0; | |
455 | } | |
456 | ||
457 | static int i965_do_reset(struct drm_device *dev) | |
458 | { | |
459 | int ret; | |
460 | ||
461 | /* | |
462 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | |
463 | * well as the reset bit (GR/bit 0). Setting the GR bit | |
464 | * triggers the reset; when done, the hardware will clear it. | |
465 | */ | |
466 | pci_write_config_byte(dev->pdev, I965_GDRST, | |
467 | GRDOM_RENDER | GRDOM_RESET_ENABLE); | |
468 | ret = wait_for(i965_reset_complete(dev), 500); | |
469 | if (ret) | |
470 | return ret; | |
471 | ||
472 | /* We can't reset render&media without also resetting display ... */ | |
473 | pci_write_config_byte(dev->pdev, I965_GDRST, | |
474 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); | |
475 | ||
476 | ret = wait_for(i965_reset_complete(dev), 500); | |
477 | if (ret) | |
478 | return ret; | |
479 | ||
480 | pci_write_config_byte(dev->pdev, I965_GDRST, 0); | |
481 | ||
482 | return 0; | |
483 | } | |
484 | ||
485 | static int ironlake_do_reset(struct drm_device *dev) | |
486 | { | |
487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
488 | u32 gdrst; | |
489 | int ret; | |
490 | ||
491 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
492 | gdrst &= ~GRDOM_MASK; | |
493 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, | |
494 | gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); | |
495 | ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
496 | if (ret) | |
497 | return ret; | |
498 | ||
499 | /* We can't reset render&media without also resetting display ... */ | |
500 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
501 | gdrst &= ~GRDOM_MASK; | |
502 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, | |
503 | gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); | |
504 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
505 | } | |
506 | ||
507 | static int gen6_do_reset(struct drm_device *dev) | |
508 | { | |
509 | struct drm_i915_private *dev_priv = dev->dev_private; | |
510 | int ret; | |
511 | unsigned long irqflags; | |
512 | ||
513 | /* Hold uncore.lock across reset to prevent any register access | |
514 | * with forcewake not set correctly | |
515 | */ | |
516 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
517 | ||
518 | /* Reset the chip */ | |
519 | ||
520 | /* GEN6_GDRST is not in the gt power well, no need to check | |
521 | * for fifo space for the write or forcewake the chip for | |
522 | * the read | |
523 | */ | |
524 | I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL); | |
525 | ||
526 | /* Spin waiting for the device to ack the reset request */ | |
527 | ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); | |
528 | ||
529 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ | |
530 | if (dev_priv->uncore.forcewake_count) | |
531 | dev_priv->uncore.funcs.force_wake_get(dev_priv); | |
532 | else | |
533 | dev_priv->uncore.funcs.force_wake_put(dev_priv); | |
534 | ||
535 | /* Restore fifo count */ | |
536 | dev_priv->uncore.fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
537 | ||
538 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
539 | return ret; | |
540 | } | |
541 | ||
542 | int intel_gpu_reset(struct drm_device *dev) | |
543 | { | |
544 | switch (INTEL_INFO(dev)->gen) { | |
545 | case 7: | |
546 | case 6: return gen6_do_reset(dev); | |
547 | case 5: return ironlake_do_reset(dev); | |
548 | case 4: return i965_do_reset(dev); | |
549 | case 2: return i8xx_do_reset(dev); | |
550 | default: return -ENODEV; | |
551 | } | |
552 | } | |
553 | ||
554 | void intel_uncore_clear_errors(struct drm_device *dev) | |
555 | { | |
556 | struct drm_i915_private *dev_priv = dev->dev_private; | |
557 | ||
558 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) | |
559 | I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); | |
560 | } | |
561 | ||
562 | void intel_uncore_check_errors(struct drm_device *dev) | |
563 | { | |
564 | struct drm_i915_private *dev_priv = dev->dev_private; | |
565 | ||
566 | if (HAS_FPGA_DBG_UNCLAIMED(dev) && | |
567 | (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { | |
568 | DRM_ERROR("Unclaimed register before interrupt\n"); | |
569 | I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM); | |
570 | } | |
571 | } |