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drm/i915: Rebalance runtime pm vs forcewake
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / i915 / intel_uncore.c
CommitLineData
907b28c5
CW		 1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#include "i915_drv.h"
25#include "intel_drv.h"
26
27#define FORCEWAKE_ACK_TIMEOUT_MS 2
28
6af5d92f
CW		 29#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
30#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
31
32#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
33#define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
34
35#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
36#define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
37
38#define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
39#define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
40
41#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
42
b2ec142c
PZ		 43static void
44assert_device_not_suspended(struct drm_i915_private *dev_priv)
45{
2b387059
CW		 46 WARN_ONCE(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
47 "Device suspended\n");
b2ec142c 48}
6af5d92f 49
907b28c5
CW		 50static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
51{
907b28c5
CW		 52 /* w/a for a sporadic read returning 0 by waiting for the GT
53 * thread to wake up.
54 */
eb88bd1b
VS		 55 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) &
56 GEN6_GT_THREAD_STATUS_CORE_MASK) == 0, 500))
907b28c5
CW		 57 DRM_ERROR("GT thread status wait timed out\n");
58}
59
60static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
61{
6af5d92f
CW		 62 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
63 /* something from same cacheline, but !FORCEWAKE */
64 __raw_posting_read(dev_priv, ECOBUS);
907b28c5
CW		 65}
66
c8d9a590
D		 67static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
68 int fw_engine)
907b28c5 69{
6af5d92f 70 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
907b28c5
CW		 71 FORCEWAKE_ACK_TIMEOUT_MS))
72 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
73
6af5d92f
CW		 74 __raw_i915_write32(dev_priv, FORCEWAKE, 1);
75 /* something from same cacheline, but !FORCEWAKE */
76 __raw_posting_read(dev_priv, ECOBUS);
907b28c5 77
6af5d92f 78 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
907b28c5
CW		 79 FORCEWAKE_ACK_TIMEOUT_MS))
80 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
81
82 /* WaRsForcewakeWaitTC0:snb */
83 __gen6_gt_wait_for_thread_c0(dev_priv);
84}
85
6a68735a 86static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
907b28c5 87{
6af5d92f 88 __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
907b28c5 89 /* something from same cacheline, but !FORCEWAKE_MT */
6af5d92f 90 __raw_posting_read(dev_priv, ECOBUS);
907b28c5
CW		 91}
92
6a68735a 93static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
c8d9a590 94 int fw_engine)
907b28c5
CW		 95{
96 u32 forcewake_ack;
97
f98cd096 98 if (IS_HASWELL(dev_priv->dev) || IS_BROADWELL(dev_priv->dev))
907b28c5
CW		 99 forcewake_ack = FORCEWAKE_ACK_HSW;
100 else
101 forcewake_ack = FORCEWAKE_MT_ACK;
102
6af5d92f 103 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
907b28c5
CW		 104 FORCEWAKE_ACK_TIMEOUT_MS))
105 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
106
6af5d92f
CW		 107 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
108 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
907b28c5 109 /* something from same cacheline, but !FORCEWAKE_MT */
6af5d92f 110 __raw_posting_read(dev_priv, ECOBUS);
907b28c5 111
6af5d92f 112 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),
907b28c5
CW		 113 FORCEWAKE_ACK_TIMEOUT_MS))
114 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
115
116 /* WaRsForcewakeWaitTC0:ivb,hsw */
c549f738 117 __gen6_gt_wait_for_thread_c0(dev_priv);
907b28c5
CW		 118}
119
120static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
121{
122 u32 gtfifodbg;
6af5d92f
CW		 123
124 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
90f256b5
VS		 125 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
126 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
907b28c5
CW		 127}
128
c8d9a590
D		 129static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
130 int fw_engine)
907b28c5 131{
6af5d92f 132 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
907b28c5 133 /* something from same cacheline, but !FORCEWAKE */
6af5d92f 134 __raw_posting_read(dev_priv, ECOBUS);
907b28c5
CW		 135 gen6_gt_check_fifodbg(dev_priv);
136}
137
6a68735a 138static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
c8d9a590 139 int fw_engine)
907b28c5 140{
6af5d92f
CW		 141 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
142 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
907b28c5 143 /* something from same cacheline, but !FORCEWAKE_MT */
6af5d92f 144 __raw_posting_read(dev_priv, ECOBUS);
6a68735a
MK		 145
146 if (IS_GEN7(dev_priv->dev))
147 gen6_gt_check_fifodbg(dev_priv);
907b28c5
CW		 148}
149
150static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
151{
152 int ret = 0;
153
5135d64b
D		 154 /* On VLV, FIFO will be shared by both SW and HW.
155 * So, we need to read the FREE_ENTRIES everytime */
156 if (IS_VALLEYVIEW(dev_priv->dev))
157 dev_priv->uncore.fifo_count =
158 __raw_i915_read32(dev_priv, GTFIFOCTL) &
159 GT_FIFO_FREE_ENTRIES_MASK;
160
907b28c5
CW		 161 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
162 int loop = 500;
46520e2b 163 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
907b28c5
CW		 164 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
165 udelay(10);
46520e2b 166 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
907b28c5
CW		 167 }
168 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
169 ++ret;
170 dev_priv->uncore.fifo_count = fifo;
171 }
172 dev_priv->uncore.fifo_count--;
173
174 return ret;
175}
176
177static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
178{
6af5d92f
CW		 179 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
180 _MASKED_BIT_DISABLE(0xffff));
05adaf1f
JN		 181 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
182 _MASKED_BIT_DISABLE(0xffff));
907b28c5 183 /* something from same cacheline, but !FORCEWAKE_VLV */
6af5d92f 184 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
907b28c5
CW		 185}
186
940aece4
D		 187static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
188 int fw_engine)
907b28c5 189{
940aece4
D		 190 /* Check for Render Engine */
191 if (FORCEWAKE_RENDER & fw_engine) {
95009861
MK		 192 if (wait_for_atomic((__raw_i915_read32(dev_priv,
193 FORCEWAKE_ACK_VLV) &
194 FORCEWAKE_KERNEL) == 0,
195 FORCEWAKE_ACK_TIMEOUT_MS))
196 DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
940aece4
D		 197
198 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
199 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
200
201 if (wait_for_atomic((__raw_i915_read32(dev_priv,
202 FORCEWAKE_ACK_VLV) &
203 FORCEWAKE_KERNEL),
204 FORCEWAKE_ACK_TIMEOUT_MS))
205 DRM_ERROR("Timed out: waiting for Render to ack.\n");
206 }
907b28c5 207
940aece4
D		 208 /* Check for Media Engine */
209 if (FORCEWAKE_MEDIA & fw_engine) {
95009861
MK		 210 if (wait_for_atomic((__raw_i915_read32(dev_priv,
211 FORCEWAKE_ACK_MEDIA_VLV) &
212 FORCEWAKE_KERNEL) == 0,
213 FORCEWAKE_ACK_TIMEOUT_MS))
214 DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
940aece4
D		 215
216 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
217 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
218
219 if (wait_for_atomic((__raw_i915_read32(dev_priv,
220 FORCEWAKE_ACK_MEDIA_VLV) &
221 FORCEWAKE_KERNEL),
222 FORCEWAKE_ACK_TIMEOUT_MS))
223 DRM_ERROR("Timed out: waiting for media to ack.\n");
224 }
907b28c5
CW		 225}
226
940aece4
D		 227static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
228 int fw_engine)
907b28c5 229{
940aece4
D		 230
231 /* Check for Render Engine */
232 if (FORCEWAKE_RENDER & fw_engine)
233 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
234 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
235
236
237 /* Check for Media Engine */
238 if (FORCEWAKE_MEDIA & fw_engine)
239 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
240 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
241
ab53c267
VS		 242 /* something from same cacheline, but !FORCEWAKE_VLV */
243 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
244 if (!IS_CHERRYVIEW(dev_priv->dev))
245 gen6_gt_check_fifodbg(dev_priv);
940aece4
D		 246}
247
b88b23d9 248static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
940aece4
D		 249{
250 unsigned long irqflags;
251
252 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
6fe72865
VS		 253
254 if (fw_engine & FORCEWAKE_RENDER &&
255 dev_priv->uncore.fw_rendercount++ != 0)
256 fw_engine &= ~FORCEWAKE_RENDER;
257 if (fw_engine & FORCEWAKE_MEDIA &&
258 dev_priv->uncore.fw_mediacount++ != 0)
259 fw_engine &= ~FORCEWAKE_MEDIA;
260
261 if (fw_engine)
262 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine);
940aece4
D		 263
264 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
265}
266
b88b23d9 267static void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
940aece4
D		 268{
269 unsigned long irqflags;
270
271 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
272
3123fcaf
DV		 273 if (fw_engine & FORCEWAKE_RENDER) {
274 WARN_ON(!dev_priv->uncore.fw_rendercount);
275 if (--dev_priv->uncore.fw_rendercount != 0)
276 fw_engine &= ~FORCEWAKE_RENDER;
277 }
278
279 if (fw_engine & FORCEWAKE_MEDIA) {
280 WARN_ON(!dev_priv->uncore.fw_mediacount);
281 if (--dev_priv->uncore.fw_mediacount != 0)
282 fw_engine &= ~FORCEWAKE_MEDIA;
283 }
940aece4 284
6fe72865
VS		 285 if (fw_engine)
286 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine);
940aece4
D		 287
288 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
907b28c5
CW		 289}
290
38cff0b1
ZW		 291static void __gen9_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
292{
293 __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
294 _MASKED_BIT_DISABLE(0xffff));
295
296 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
297 _MASKED_BIT_DISABLE(0xffff));
298
299 __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
300 _MASKED_BIT_DISABLE(0xffff));
301}
302
303static void
304__gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
305{
306 /* Check for Render Engine */
307 if (FORCEWAKE_RENDER & fw_engine) {
308 if (wait_for_atomic((__raw_i915_read32(dev_priv,
309 FORCEWAKE_ACK_RENDER_GEN9) &
310 FORCEWAKE_KERNEL) == 0,
311 FORCEWAKE_ACK_TIMEOUT_MS))
312 DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
313
314 __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
315 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
316
317 if (wait_for_atomic((__raw_i915_read32(dev_priv,
318 FORCEWAKE_ACK_RENDER_GEN9) &
319 FORCEWAKE_KERNEL),
320 FORCEWAKE_ACK_TIMEOUT_MS))
321 DRM_ERROR("Timed out: waiting for Render to ack.\n");
322 }
323
324 /* Check for Media Engine */
325 if (FORCEWAKE_MEDIA & fw_engine) {
326 if (wait_for_atomic((__raw_i915_read32(dev_priv,
327 FORCEWAKE_ACK_MEDIA_GEN9) &
328 FORCEWAKE_KERNEL) == 0,
329 FORCEWAKE_ACK_TIMEOUT_MS))
330 DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
331
332 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
333 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
334
335 if (wait_for_atomic((__raw_i915_read32(dev_priv,
336 FORCEWAKE_ACK_MEDIA_GEN9) &
337 FORCEWAKE_KERNEL),
338 FORCEWAKE_ACK_TIMEOUT_MS))
339 DRM_ERROR("Timed out: waiting for Media to ack.\n");
340 }
341
342 /* Check for Blitter Engine */
343 if (FORCEWAKE_BLITTER & fw_engine) {
344 if (wait_for_atomic((__raw_i915_read32(dev_priv,
345 FORCEWAKE_ACK_BLITTER_GEN9) &
346 FORCEWAKE_KERNEL) == 0,
347 FORCEWAKE_ACK_TIMEOUT_MS))
348 DRM_ERROR("Timed out: Blitter forcewake old ack to clear.\n");
349
350 __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
351 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
352
353 if (wait_for_atomic((__raw_i915_read32(dev_priv,
354 FORCEWAKE_ACK_BLITTER_GEN9) &
355 FORCEWAKE_KERNEL),
356 FORCEWAKE_ACK_TIMEOUT_MS))
357 DRM_ERROR("Timed out: waiting for Blitter to ack.\n");
358 }
359}
360
361static void
362__gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
363{
364 /* Check for Render Engine */
365 if (FORCEWAKE_RENDER & fw_engine)
366 __raw_i915_write32(dev_priv, FORCEWAKE_RENDER_GEN9,
367 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
368
369 /* Check for Media Engine */
370 if (FORCEWAKE_MEDIA & fw_engine)
371 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_GEN9,
372 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
373
374 /* Check for Blitter Engine */
375 if (FORCEWAKE_BLITTER & fw_engine)
376 __raw_i915_write32(dev_priv, FORCEWAKE_BLITTER_GEN9,
377 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
378}
379
380static void
381gen9_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
382{
383 unsigned long irqflags;
384
385 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
386
387 if (FORCEWAKE_RENDER & fw_engine) {
388 if (dev_priv->uncore.fw_rendercount++ == 0)
389 dev_priv->uncore.funcs.force_wake_get(dev_priv,
390 FORCEWAKE_RENDER);
391 }
392
393 if (FORCEWAKE_MEDIA & fw_engine) {
394 if (dev_priv->uncore.fw_mediacount++ == 0)
395 dev_priv->uncore.funcs.force_wake_get(dev_priv,
396 FORCEWAKE_MEDIA);
397 }
398
399 if (FORCEWAKE_BLITTER & fw_engine) {
400 if (dev_priv->uncore.fw_blittercount++ == 0)
401 dev_priv->uncore.funcs.force_wake_get(dev_priv,
402 FORCEWAKE_BLITTER);
403 }
404
405 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
406}
407
408static void
409gen9_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
410{
411 unsigned long irqflags;
412
413 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
414
415 if (FORCEWAKE_RENDER & fw_engine) {
416 WARN_ON(dev_priv->uncore.fw_rendercount == 0);
417 if (--dev_priv->uncore.fw_rendercount == 0)
418 dev_priv->uncore.funcs.force_wake_put(dev_priv,
419 FORCEWAKE_RENDER);
420 }
421
422 if (FORCEWAKE_MEDIA & fw_engine) {
423 WARN_ON(dev_priv->uncore.fw_mediacount == 0);
424 if (--dev_priv->uncore.fw_mediacount == 0)
425 dev_priv->uncore.funcs.force_wake_put(dev_priv,
426 FORCEWAKE_MEDIA);
427 }
428
429 if (FORCEWAKE_BLITTER & fw_engine) {
430 WARN_ON(dev_priv->uncore.fw_blittercount == 0);
431 if (--dev_priv->uncore.fw_blittercount == 0)
432 dev_priv->uncore.funcs.force_wake_put(dev_priv,
433 FORCEWAKE_BLITTER);
434 }
435
436 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
437}
438
8232644c 439static void gen6_force_wake_timer(unsigned long arg)
aec347ab 440{
8232644c 441 struct drm_i915_private *dev_priv = (void *)arg;
aec347ab
CW		 442 unsigned long irqflags;
443
b2ec142c
PZ		 444 assert_device_not_suspended(dev_priv);
445
aec347ab 446 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3123fcaf
DV		 447 WARN_ON(!dev_priv->uncore.forcewake_count);
448
aec347ab 449 if (--dev_priv->uncore.forcewake_count == 0)
c8d9a590 450 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
aec347ab
CW		 451 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
452}
453
156c7ca0 454void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
ef46e0d2
DV		 455{
456 struct drm_i915_private *dev_priv = dev->dev_private;
0294ae7b
CW		 457 unsigned long irqflags;
458
9e31c2a5
ID		 459 if (del_timer_sync(&dev_priv->uncore.force_wake_timer))
460 gen6_force_wake_timer((unsigned long)dev_priv);
0294ae7b
CW		 461
462 /* Hold uncore.lock across reset to prevent any register access
463 * with forcewake not set correctly
464 */
465 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
ef46e0d2 466
0a089e33 467 if (IS_VALLEYVIEW(dev))
ef46e0d2 468 vlv_force_wake_reset(dev_priv);
0a089e33 469 else if (IS_GEN6(dev) || IS_GEN7(dev))
ef46e0d2 470 __gen6_gt_force_wake_reset(dev_priv);
0a089e33 471
f98cd096 472 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
6a68735a 473 __gen7_gt_force_wake_mt_reset(dev_priv);
0294ae7b 474
38cff0b1
ZW		 475 if (IS_GEN9(dev))
476 __gen9_gt_force_wake_mt_reset(dev_priv);
477
0294ae7b
CW		 478 if (restore) { /* If reset with a user forcewake, try to restore */
479 unsigned fw = 0;
480
481 if (IS_VALLEYVIEW(dev)) {
482 if (dev_priv->uncore.fw_rendercount)
483 fw |= FORCEWAKE_RENDER;
484
485 if (dev_priv->uncore.fw_mediacount)
486 fw |= FORCEWAKE_MEDIA;
38cff0b1
ZW		 487 } else if (IS_GEN9(dev)) {
488 if (dev_priv->uncore.fw_rendercount)
489 fw |= FORCEWAKE_RENDER;
490
491 if (dev_priv->uncore.fw_mediacount)
492 fw |= FORCEWAKE_MEDIA;
493
494 if (dev_priv->uncore.fw_blittercount)
495 fw |= FORCEWAKE_BLITTER;
0294ae7b
CW		 496 } else {
497 if (dev_priv->uncore.forcewake_count)
498 fw = FORCEWAKE_ALL;
499 }
500
501 if (fw)
502 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
503
504 if (IS_GEN6(dev) || IS_GEN7(dev))
505 dev_priv->uncore.fifo_count =
506 __raw_i915_read32(dev_priv, GTFIFOCTL) &
507 GT_FIFO_FREE_ENTRIES_MASK;
0294ae7b
CW		 508 }
509
510 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
ef46e0d2
DV		 511}
512
ed493883
ID		 513static void __intel_uncore_early_sanitize(struct drm_device *dev,
514 bool restore_forcewake)
907b28c5
CW		 515{
516 struct drm_i915_private *dev_priv = dev->dev_private;
517
518 if (HAS_FPGA_DBG_UNCLAIMED(dev))
6af5d92f 519 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
18ce3994 520
1d2866ba 521 if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
18ce3994
BW		 522 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
523 /* The docs do not explain exactly how the calculation can be
524 * made. It is somewhat guessable, but for now, it's always
525 * 128MB.
526 * NB: We can't write IDICR yet because we do not have gt funcs
527 * set up */
528 dev_priv->ellc_size = 128;
529 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
530 }
907b28c5 531
97058870
VS		 532 /* clear out old GT FIFO errors */
533 if (IS_GEN6(dev) || IS_GEN7(dev))
534 __raw_i915_write32(dev_priv, GTFIFODBG,
535 __raw_i915_read32(dev_priv, GTFIFODBG));
536
10018603 537 intel_uncore_forcewake_reset(dev, restore_forcewake);
521198a2
MK		 538}
539
ed493883
ID		 540void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake)
541{
542 __intel_uncore_early_sanitize(dev, restore_forcewake);
543 i915_check_and_clear_faults(dev);
544}
545
521198a2
MK		 546void intel_uncore_sanitize(struct drm_device *dev)
547{
907b28c5
CW		 548 /* BIOS often leaves RC6 enabled, but disable it for hw init */
549 intel_disable_gt_powersave(dev);
550}
551
552/*
553 * Generally this is called implicitly by the register read function. However,
554 * if some sequence requires the GT to not power down then this function should
555 * be called at the beginning of the sequence followed by a call to
556 * gen6_gt_force_wake_put() at the end of the sequence.
557 */
c8d9a590 558void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
907b28c5
CW		 559{
560 unsigned long irqflags;
561
ab484f8f
BW		 562 if (!dev_priv->uncore.funcs.force_wake_get)
563 return;
564
c8c8fb33
PZ		 565 intel_runtime_pm_get(dev_priv);
566
38cff0b1
ZW		 567 /* Redirect to Gen9 specific routine */
568 if (IS_GEN9(dev_priv->dev))
569 return gen9_force_wake_get(dev_priv, fw_engine);
570
940aece4
D		 571 /* Redirect to VLV specific routine */
572 if (IS_VALLEYVIEW(dev_priv->dev))
573 return vlv_force_wake_get(dev_priv, fw_engine);
574
907b28c5
CW		 575 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
576 if (dev_priv->uncore.forcewake_count++ == 0)
c8d9a590 577 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
907b28c5
CW		 578 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
579}
580
581/*
582 * see gen6_gt_force_wake_get()
583 */
c8d9a590 584void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
907b28c5
CW		 585{
586 unsigned long irqflags;
587
ab484f8f
BW		 588 if (!dev_priv->uncore.funcs.force_wake_put)
589 return;
590
38cff0b1
ZW		 591 /* Redirect to Gen9 specific routine */
592 if (IS_GEN9(dev_priv->dev)) {
593 gen9_force_wake_put(dev_priv, fw_engine);
594 goto out;
595 }
596
940aece4 597 /* Redirect to VLV specific routine */
6d88064e
PZ		 598 if (IS_VALLEYVIEW(dev_priv->dev)) {
599 vlv_force_wake_put(dev_priv, fw_engine);
600 goto out;
601 }
940aece4 602
907b28c5 603 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3123fcaf
DV		 604 WARN_ON(!dev_priv->uncore.forcewake_count);
605
aec347ab
CW		 606 if (--dev_priv->uncore.forcewake_count == 0) {
607 dev_priv->uncore.forcewake_count++;
8232644c
CW		 608 mod_timer_pinned(&dev_priv->uncore.force_wake_timer,
609 jiffies + 1);
aec347ab 610 }
dc9fb09c 611
907b28c5 612 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
c8c8fb33 613
6d88064e 614out:
dc9fb09c 615 intel_runtime_pm_put(dev_priv);
907b28c5
CW		 616}
617
e998c40f
PZ		 618void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
619{
620 if (!dev_priv->uncore.funcs.force_wake_get)
621 return;
622
623 WARN_ON(dev_priv->uncore.forcewake_count > 0);
624}
625
907b28c5
CW		 626/* We give fast paths for the really cool registers */
627#define NEEDS_FORCE_WAKE(dev_priv, reg) \
ab484f8f 628 ((reg) < 0x40000 && (reg) != FORCEWAKE)
907b28c5 629
1938e59a 630#define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end))
38fb6a40 631
1938e59a
D		 632#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
633 (REG_RANGE((reg), 0x2000, 0x4000) || \
634 REG_RANGE((reg), 0x5000, 0x8000) || \
635 REG_RANGE((reg), 0xB000, 0x12000) || \
636 REG_RANGE((reg), 0x2E000, 0x30000))
637
638#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \
639 (REG_RANGE((reg), 0x12000, 0x14000) || \
640 REG_RANGE((reg), 0x22000, 0x24000) || \
641 REG_RANGE((reg), 0x30000, 0x40000))
642
643#define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \
644 (REG_RANGE((reg), 0x2000, 0x4000) || \
db5ff4ac 645 REG_RANGE((reg), 0x5200, 0x8000) || \
1938e59a 646 REG_RANGE((reg), 0x8300, 0x8500) || \
db5ff4ac 647 REG_RANGE((reg), 0xB000, 0xB480) || \
1938e59a
D		 648 REG_RANGE((reg), 0xE000, 0xE800))
649
650#define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \
651 (REG_RANGE((reg), 0x8800, 0x8900) || \
652 REG_RANGE((reg), 0xD000, 0xD800) || \
653 REG_RANGE((reg), 0x12000, 0x14000) || \
654 REG_RANGE((reg), 0x1A000, 0x1C000) || \
655 REG_RANGE((reg), 0x1E800, 0x1EA00) || \
db5ff4ac 656 REG_RANGE((reg), 0x30000, 0x38000))
1938e59a
D		 657
658#define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \
659 (REG_RANGE((reg), 0x4000, 0x5000) || \
660 REG_RANGE((reg), 0x8000, 0x8300) || \
661 REG_RANGE((reg), 0x8500, 0x8600) || \
662 REG_RANGE((reg), 0x9000, 0xB000) || \
db5ff4ac 663 REG_RANGE((reg), 0xF000, 0x10000))
38fb6a40 664
4597a88a 665#define FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) \
8ee558d8 666 REG_RANGE((reg), 0xB00, 0x2000)
4597a88a
ZW		 667
668#define FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) \
8ee558d8
AG		 669 (REG_RANGE((reg), 0x2000, 0x2700) || \
670 REG_RANGE((reg), 0x3000, 0x4000) || \
4597a88a 671 REG_RANGE((reg), 0x5200, 0x8000) || \
8ee558d8 672 REG_RANGE((reg), 0x8140, 0x8160) || \
4597a88a
ZW		 673 REG_RANGE((reg), 0x8300, 0x8500) || \
674 REG_RANGE((reg), 0x8C00, 0x8D00) || \
675 REG_RANGE((reg), 0xB000, 0xB480) || \
8ee558d8
AG		 676 REG_RANGE((reg), 0xE000, 0xE900) || \
677 REG_RANGE((reg), 0x24400, 0x24800))
4597a88a
ZW		 678
679#define FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) \
8ee558d8
AG		 680 (REG_RANGE((reg), 0x8130, 0x8140) || \
681 REG_RANGE((reg), 0x8800, 0x8A00) || \
4597a88a
ZW		 682 REG_RANGE((reg), 0xD000, 0xD800) || \
683 REG_RANGE((reg), 0x12000, 0x14000) || \
684 REG_RANGE((reg), 0x1A000, 0x1EA00) || \
685 REG_RANGE((reg), 0x30000, 0x40000))
686
687#define FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg) \
688 REG_RANGE((reg), 0x9400, 0x9800)
689
690#define FORCEWAKE_GEN9_BLITTER_RANGE_OFFSET(reg) \
691 ((reg) < 0x40000 &&\
692 !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg) && \
693 !FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg) && \
694 !FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg) && \
695 !FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg))
696
907b28c5
CW		 697static void
698ilk_dummy_write(struct drm_i915_private *dev_priv)
699{
700 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
701 * the chip from rc6 before touching it for real. MI_MODE is masked,
702 * hence harmless to write 0 into. */
6af5d92f 703 __raw_i915_write32(dev_priv, MI_MODE, 0);
907b28c5
CW		 704}
705
706static void
5978118c
PZ		 707hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read,
708 bool before)
907b28c5 709{
5978118c
PZ		 710 const char *op = read ? "reading" : "writing to";
711 const char *when = before ? "before" : "after";
712
713 if (!i915.mmio_debug)
714 return;
715
ab484f8f 716 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
5978118c
PZ		 717 WARN(1, "Unclaimed register detected %s %s register 0x%x\n",
718 when, op, reg);
6af5d92f 719 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
907b28c5
CW		 720 }
721}
722
723static void
5978118c 724hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv)
907b28c5 725{
5978118c
PZ		 726 if (i915.mmio_debug)
727 return;
728
ab484f8f 729 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
5978118c 730 DRM_ERROR("Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem.");
6af5d92f 731 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
907b28c5
CW		 732 }
733}
734
5d738795
BW		 735#define REG_READ_HEADER(x) \
736 unsigned long irqflags; \
737 u##x val = 0; \
6f0ea9e2 738 assert_device_not_suspended(dev_priv); \
5d738795
BW		 739 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
740
741#define REG_READ_FOOTER \
742 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
743 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
744 return val
745
3967018e 746#define __gen4_read(x) \
0b274481 747static u##x \
3967018e
BW		 748gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
749 REG_READ_HEADER(x); \
750 val = __raw_i915_read##x(dev_priv, reg); \
751 REG_READ_FOOTER; \
752}
753
754#define __gen5_read(x) \
755static u##x \
756gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
757 REG_READ_HEADER(x); \
758 ilk_dummy_write(dev_priv); \
759 val = __raw_i915_read##x(dev_priv, reg); \
760 REG_READ_FOOTER; \
761}
762
763#define __gen6_read(x) \
764static u##x \
765gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
5d738795 766 REG_READ_HEADER(x); \
5978118c 767 hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \
8232644c
CW		 768 if (dev_priv->uncore.forcewake_count == 0 && \
769 NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
770 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
771 FORCEWAKE_ALL); \
dc9fb09c
CW		 772 dev_priv->uncore.forcewake_count++; \
773 mod_timer_pinned(&dev_priv->uncore.force_wake_timer, \
774 jiffies + 1); \
907b28c5 775 } \
dc9fb09c 776 val = __raw_i915_read##x(dev_priv, reg); \
5978118c 777 hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \
5d738795 778 REG_READ_FOOTER; \
907b28c5
CW		 779}
780
940aece4
D		 781#define __vlv_read(x) \
782static u##x \
783vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
784 unsigned fwengine = 0; \
940aece4 785 REG_READ_HEADER(x); \
6fe72865
VS		 786 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
787 if (dev_priv->uncore.fw_rendercount == 0) \
788 fwengine = FORCEWAKE_RENDER; \
789 } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
790 if (dev_priv->uncore.fw_mediacount == 0) \
791 fwengine = FORCEWAKE_MEDIA; \
940aece4 792 } \
6fe72865
VS		 793 if (fwengine) \
794 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
795 val = __raw_i915_read##x(dev_priv, reg); \
796 if (fwengine) \
797 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
940aece4
D		 798 REG_READ_FOOTER; \
799}
800
1938e59a
D		 801#define __chv_read(x) \
802static u##x \
803chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
804 unsigned fwengine = 0; \
805 REG_READ_HEADER(x); \
806 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
807 if (dev_priv->uncore.fw_rendercount == 0) \
808 fwengine = FORCEWAKE_RENDER; \
809 } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
810 if (dev_priv->uncore.fw_mediacount == 0) \
811 fwengine = FORCEWAKE_MEDIA; \
812 } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
813 if (dev_priv->uncore.fw_rendercount == 0) \
814 fwengine |= FORCEWAKE_RENDER; \
815 if (dev_priv->uncore.fw_mediacount == 0) \
816 fwengine |= FORCEWAKE_MEDIA; \
817 } \
818 if (fwengine) \
819 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
820 val = __raw_i915_read##x(dev_priv, reg); \
821 if (fwengine) \
822 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
823 REG_READ_FOOTER; \
824}
940aece4 825
4597a88a
ZW		 826#define SKL_NEEDS_FORCE_WAKE(dev_priv, reg) \
827 ((reg) < 0x40000 && !FORCEWAKE_GEN9_UNCORE_RANGE_OFFSET(reg))
828
829#define __gen9_read(x) \
830static u##x \
831gen9_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
832 REG_READ_HEADER(x); \
833 if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
834 val = __raw_i915_read##x(dev_priv, reg); \
835 } else { \
836 unsigned fwengine = 0; \
837 if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \
838 if (dev_priv->uncore.fw_rendercount == 0) \
839 fwengine = FORCEWAKE_RENDER; \
840 } else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \
841 if (dev_priv->uncore.fw_mediacount == 0) \
842 fwengine = FORCEWAKE_MEDIA; \
843 } else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \
844 if (dev_priv->uncore.fw_rendercount == 0) \
845 fwengine |= FORCEWAKE_RENDER; \
846 if (dev_priv->uncore.fw_mediacount == 0) \
847 fwengine |= FORCEWAKE_MEDIA; \
848 } else { \
849 if (dev_priv->uncore.fw_blittercount == 0) \
850 fwengine = FORCEWAKE_BLITTER; \
851 } \
852 if (fwengine) \
853 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
854 val = __raw_i915_read##x(dev_priv, reg); \
855 if (fwengine) \
856 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
857 } \
858 REG_READ_FOOTER; \
859}
860
861__gen9_read(8)
862__gen9_read(16)
863__gen9_read(32)
864__gen9_read(64)
1938e59a
D		 865__chv_read(8)
866__chv_read(16)
867__chv_read(32)
868__chv_read(64)
940aece4
D		 869__vlv_read(8)
870__vlv_read(16)
871__vlv_read(32)
872__vlv_read(64)
3967018e
BW		 873__gen6_read(8)
874__gen6_read(16)
875__gen6_read(32)
876__gen6_read(64)
877__gen5_read(8)
878__gen5_read(16)
879__gen5_read(32)
880__gen5_read(64)
881__gen4_read(8)
882__gen4_read(16)
883__gen4_read(32)
884__gen4_read(64)
885
4597a88a 886#undef __gen9_read
1938e59a 887#undef __chv_read
940aece4 888#undef __vlv_read
3967018e
BW		 889#undef __gen6_read
890#undef __gen5_read
891#undef __gen4_read
5d738795
BW		 892#undef REG_READ_FOOTER
893#undef REG_READ_HEADER
894
895#define REG_WRITE_HEADER \
896 unsigned long irqflags; \
897 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
6f0ea9e2 898 assert_device_not_suspended(dev_priv); \
5d738795 899 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
907b28c5 900
0d965301
VS		 901#define REG_WRITE_FOOTER \
902 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
903
4032ef43 904#define __gen4_write(x) \
0b274481 905static void \
4032ef43
BW		 906gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
907 REG_WRITE_HEADER; \
908 __raw_i915_write##x(dev_priv, reg, val); \
0d965301 909 REG_WRITE_FOOTER; \
4032ef43
BW		 910}
911
912#define __gen5_write(x) \
913static void \
914gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
915 REG_WRITE_HEADER; \
916 ilk_dummy_write(dev_priv); \
917 __raw_i915_write##x(dev_priv, reg, val); \
0d965301 918 REG_WRITE_FOOTER; \
4032ef43
BW		 919}
920
921#define __gen6_write(x) \
922static void \
923gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
924 u32 __fifo_ret = 0; \
925 REG_WRITE_HEADER; \
926 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
927 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
928 } \
929 __raw_i915_write##x(dev_priv, reg, val); \
930 if (unlikely(__fifo_ret)) { \
931 gen6_gt_check_fifodbg(dev_priv); \
932 } \
0d965301 933 REG_WRITE_FOOTER; \
4032ef43
BW		 934}
935
936#define __hsw_write(x) \
937static void \
938hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
907b28c5 939 u32 __fifo_ret = 0; \
5d738795 940 REG_WRITE_HEADER; \
907b28c5
CW		 941 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
942 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
943 } \
5978118c 944 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
6af5d92f 945 __raw_i915_write##x(dev_priv, reg, val); \
907b28c5
CW		 946 if (unlikely(__fifo_ret)) { \
947 gen6_gt_check_fifodbg(dev_priv); \
948 } \
5978118c
PZ		 949 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
950 hsw_unclaimed_reg_detect(dev_priv); \
0d965301 951 REG_WRITE_FOOTER; \
907b28c5 952}
3967018e 953
ab2aa47e
BW		 954static const u32 gen8_shadowed_regs[] = {
955 FORCEWAKE_MT,
956 GEN6_RPNSWREQ,
957 GEN6_RC_VIDEO_FREQ,
958 RING_TAIL(RENDER_RING_BASE),
959 RING_TAIL(GEN6_BSD_RING_BASE),
960 RING_TAIL(VEBOX_RING_BASE),
961 RING_TAIL(BLT_RING_BASE),
962 /* TODO: Other registers are not yet used */
963};
964
965static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
966{
967 int i;
968 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
969 if (reg == gen8_shadowed_regs[i])
970 return true;
971
972 return false;
973}
974
975#define __gen8_write(x) \
976static void \
977gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
ab2aa47e 978 REG_WRITE_HEADER; \
66bc2cab 979 hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \
e9dbd2b2
MK		 980 if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \
981 if (dev_priv->uncore.forcewake_count == 0) \
982 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
983 FORCEWAKE_ALL); \
984 __raw_i915_write##x(dev_priv, reg, val); \
985 if (dev_priv->uncore.forcewake_count == 0) \
986 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
987 FORCEWAKE_ALL); \
988 } else { \
989 __raw_i915_write##x(dev_priv, reg, val); \
ab2aa47e 990 } \
66bc2cab
PZ		 991 hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \
992 hsw_unclaimed_reg_detect(dev_priv); \
0d965301 993 REG_WRITE_FOOTER; \
ab2aa47e
BW		 994}
995
1938e59a
D		 996#define __chv_write(x) \
997static void \
998chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
999 unsigned fwengine = 0; \
1000 bool shadowed = is_gen8_shadowed(dev_priv, reg); \
1001 REG_WRITE_HEADER; \
1002 if (!shadowed) { \
1003 if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \
1004 if (dev_priv->uncore.fw_rendercount == 0) \
1005 fwengine = FORCEWAKE_RENDER; \
1006 } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \
1007 if (dev_priv->uncore.fw_mediacount == 0) \
1008 fwengine = FORCEWAKE_MEDIA; \
1009 } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \
1010 if (dev_priv->uncore.fw_rendercount == 0) \
1011 fwengine |= FORCEWAKE_RENDER; \
1012 if (dev_priv->uncore.fw_mediacount == 0) \
1013 fwengine |= FORCEWAKE_MEDIA; \
1014 } \
1015 } \
1016 if (fwengine) \
1017 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
1018 __raw_i915_write##x(dev_priv, reg, val); \
1019 if (fwengine) \
1020 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
1021 REG_WRITE_FOOTER; \
1022}
1023
7c859007
ZW		 1024static const u32 gen9_shadowed_regs[] = {
1025 RING_TAIL(RENDER_RING_BASE),
1026 RING_TAIL(GEN6_BSD_RING_BASE),
1027 RING_TAIL(VEBOX_RING_BASE),
1028 RING_TAIL(BLT_RING_BASE),
1029 FORCEWAKE_BLITTER_GEN9,
1030 FORCEWAKE_RENDER_GEN9,
1031 FORCEWAKE_MEDIA_GEN9,
1032 GEN6_RPNSWREQ,
1033 GEN6_RC_VIDEO_FREQ,
1034 /* TODO: Other registers are not yet used */
1035};
1036
1037static bool is_gen9_shadowed(struct drm_i915_private *dev_priv, u32 reg)
1038{
1039 int i;
1040 for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
1041 if (reg == gen9_shadowed_regs[i])
1042 return true;
1043
1044 return false;
1045}
1046
4597a88a
ZW		 1047#define __gen9_write(x) \
1048static void \
1049gen9_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, \
1050 bool trace) { \
1051 REG_WRITE_HEADER; \
7c859007
ZW		 1052 if (!SKL_NEEDS_FORCE_WAKE((dev_priv), (reg)) || \
1053 is_gen9_shadowed(dev_priv, reg)) { \
4597a88a
ZW		 1054 __raw_i915_write##x(dev_priv, reg, val); \
1055 } else { \
1056 unsigned fwengine = 0; \
1057 if (FORCEWAKE_GEN9_RENDER_RANGE_OFFSET(reg)) { \
1058 if (dev_priv->uncore.fw_rendercount == 0) \
1059 fwengine = FORCEWAKE_RENDER; \
1060 } else if (FORCEWAKE_GEN9_MEDIA_RANGE_OFFSET(reg)) { \
1061 if (dev_priv->uncore.fw_mediacount == 0) \
1062 fwengine = FORCEWAKE_MEDIA; \
1063 } else if (FORCEWAKE_GEN9_COMMON_RANGE_OFFSET(reg)) { \
1064 if (dev_priv->uncore.fw_rendercount == 0) \
1065 fwengine |= FORCEWAKE_RENDER; \
1066 if (dev_priv->uncore.fw_mediacount == 0) \
1067 fwengine |= FORCEWAKE_MEDIA; \
1068 } else { \
1069 if (dev_priv->uncore.fw_blittercount == 0) \
1070 fwengine = FORCEWAKE_BLITTER; \
1071 } \
1072 if (fwengine) \
1073 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
1074 fwengine); \
1075 __raw_i915_write##x(dev_priv, reg, val); \
1076 if (fwengine) \
1077 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
1078 fwengine); \
1079 } \
1080 REG_WRITE_FOOTER; \
1081}
1082
1083__gen9_write(8)
1084__gen9_write(16)
1085__gen9_write(32)
1086__gen9_write(64)
1938e59a
D		 1087__chv_write(8)
1088__chv_write(16)
1089__chv_write(32)
1090__chv_write(64)
ab2aa47e
BW		 1091__gen8_write(8)
1092__gen8_write(16)
1093__gen8_write(32)
1094__gen8_write(64)
4032ef43
BW		 1095__hsw_write(8)
1096__hsw_write(16)
1097__hsw_write(32)
1098__hsw_write(64)
1099__gen6_write(8)
1100__gen6_write(16)
1101__gen6_write(32)
1102__gen6_write(64)
1103__gen5_write(8)
1104__gen5_write(16)
1105__gen5_write(32)
1106__gen5_write(64)
1107__gen4_write(8)
1108__gen4_write(16)
1109__gen4_write(32)
1110__gen4_write(64)
1111
4597a88a 1112#undef __gen9_write
1938e59a 1113#undef __chv_write
ab2aa47e 1114#undef __gen8_write
4032ef43
BW		 1115#undef __hsw_write
1116#undef __gen6_write
1117#undef __gen5_write
1118#undef __gen4_write
0d965301 1119#undef REG_WRITE_FOOTER
5d738795 1120#undef REG_WRITE_HEADER
907b28c5 1121
43d942a7
YZ		 1122#define ASSIGN_WRITE_MMIO_VFUNCS(x) \
1123do { \
1124 dev_priv->uncore.funcs.mmio_writeb = x##_write8; \
1125 dev_priv->uncore.funcs.mmio_writew = x##_write16; \
1126 dev_priv->uncore.funcs.mmio_writel = x##_write32; \
1127 dev_priv->uncore.funcs.mmio_writeq = x##_write64; \
1128} while (0)
1129
1130#define ASSIGN_READ_MMIO_VFUNCS(x) \
1131do { \
1132 dev_priv->uncore.funcs.mmio_readb = x##_read8; \
1133 dev_priv->uncore.funcs.mmio_readw = x##_read16; \
1134 dev_priv->uncore.funcs.mmio_readl = x##_read32; \
1135 dev_priv->uncore.funcs.mmio_readq = x##_read64; \
1136} while (0)
1137
0b274481
BW		 1138void intel_uncore_init(struct drm_device *dev)
1139{
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1141
8232644c
CW		 1142 setup_timer(&dev_priv->uncore.force_wake_timer,
1143 gen6_force_wake_timer, (unsigned long)dev_priv);
0b274481 1144
ed493883 1145 __intel_uncore_early_sanitize(dev, false);
05efeebd 1146
38cff0b1
ZW		 1147 if (IS_GEN9(dev)) {
1148 dev_priv->uncore.funcs.force_wake_get = __gen9_force_wake_get;
1149 dev_priv->uncore.funcs.force_wake_put = __gen9_force_wake_put;
1150 } else if (IS_VALLEYVIEW(dev)) {
940aece4
D		 1151 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
1152 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
f98cd096 1153 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6a68735a
MK		 1154 dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get;
1155 dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put;
0b274481
BW		 1156 } else if (IS_IVYBRIDGE(dev)) {
1157 u32 ecobus;
1158
1159 /* IVB configs may use multi-threaded forcewake */
1160
1161 /* A small trick here - if the bios hasn't configured
1162 * MT forcewake, and if the device is in RC6, then
1163 * force_wake_mt_get will not wake the device and the
1164 * ECOBUS read will return zero. Which will be
1165 * (correctly) interpreted by the test below as MT
1166 * forcewake being disabled.
1167 */
1168 mutex_lock(&dev->struct_mutex);
6a68735a 1169 __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
0b274481 1170 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
6a68735a 1171 __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
0b274481
BW		 1172 mutex_unlock(&dev->struct_mutex);
1173
1174 if (ecobus & FORCEWAKE_MT_ENABLE) {
1175 dev_priv->uncore.funcs.force_wake_get =
6a68735a 1176 __gen7_gt_force_wake_mt_get;
0b274481 1177 dev_priv->uncore.funcs.force_wake_put =
6a68735a 1178 __gen7_gt_force_wake_mt_put;
0b274481
BW		 1179 } else {
1180 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
1181 DRM_INFO("when using vblank-synced partial screen updates.\n");
1182 dev_priv->uncore.funcs.force_wake_get =
1183 __gen6_gt_force_wake_get;
1184 dev_priv->uncore.funcs.force_wake_put =
1185 __gen6_gt_force_wake_put;
1186 }
1187 } else if (IS_GEN6(dev)) {
1188 dev_priv->uncore.funcs.force_wake_get =
1189 __gen6_gt_force_wake_get;
1190 dev_priv->uncore.funcs.force_wake_put =
1191 __gen6_gt_force_wake_put;
1192 }
1193
3967018e 1194 switch (INTEL_INFO(dev)->gen) {
ab2aa47e 1195 default:
5f77eeb0 1196 MISSING_CASE(INTEL_INFO(dev)->gen);
4597a88a
ZW		 1197 return;
1198 case 9:
1199 ASSIGN_WRITE_MMIO_VFUNCS(gen9);
1200 ASSIGN_READ_MMIO_VFUNCS(gen9);
1201 break;
1202 case 8:
1938e59a 1203 if (IS_CHERRYVIEW(dev)) {
43d942a7
YZ		 1204 ASSIGN_WRITE_MMIO_VFUNCS(chv);
1205 ASSIGN_READ_MMIO_VFUNCS(chv);
1938e59a
D		 1206
1207 } else {
43d942a7
YZ		 1208 ASSIGN_WRITE_MMIO_VFUNCS(gen8);
1209 ASSIGN_READ_MMIO_VFUNCS(gen6);
1938e59a 1210 }
ab2aa47e 1211 break;
3967018e
BW		 1212 case 7:
1213 case 6:
4032ef43 1214 if (IS_HASWELL(dev)) {
43d942a7 1215 ASSIGN_WRITE_MMIO_VFUNCS(hsw);
4032ef43 1216 } else {
43d942a7 1217 ASSIGN_WRITE_MMIO_VFUNCS(gen6);
4032ef43 1218 }
940aece4
D		 1219
1220 if (IS_VALLEYVIEW(dev)) {
43d942a7 1221 ASSIGN_READ_MMIO_VFUNCS(vlv);
940aece4 1222 } else {
43d942a7 1223 ASSIGN_READ_MMIO_VFUNCS(gen6);
940aece4 1224 }
3967018e
BW		 1225 break;
1226 case 5:
43d942a7
YZ		 1227 ASSIGN_WRITE_MMIO_VFUNCS(gen5);
1228 ASSIGN_READ_MMIO_VFUNCS(gen5);
3967018e
BW		 1229 break;
1230 case 4:
1231 case 3:
1232 case 2:
43d942a7
YZ		 1233 ASSIGN_WRITE_MMIO_VFUNCS(gen4);
1234 ASSIGN_READ_MMIO_VFUNCS(gen4);
3967018e
BW		 1235 break;
1236 }
ed493883
ID		 1237
1238 i915_check_and_clear_faults(dev);
0b274481 1239}
43d942a7
YZ		 1240#undef ASSIGN_WRITE_MMIO_VFUNCS
1241#undef ASSIGN_READ_MMIO_VFUNCS
0b274481
BW		 1242
1243void intel_uncore_fini(struct drm_device *dev)
1244{
0b274481
BW		 1245 /* Paranoia: make sure we have disabled everything before we exit. */
1246 intel_uncore_sanitize(dev);
0294ae7b 1247 intel_uncore_forcewake_reset(dev, false);
0b274481
BW		 1248}
1249
af76ae44
DL		 1250#define GEN_RANGE(l, h) GENMASK(h, l)
1251
907b28c5
CW		 1252static const struct register_whitelist {
1253 uint64_t offset;
1254 uint32_t size;
af76ae44
DL		 1255 /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1256 uint32_t gen_bitmask;
907b28c5 1257} whitelist[] = {
c3f59a67 1258 { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 9) },
907b28c5
CW		 1259};
1260
1261int i915_reg_read_ioctl(struct drm_device *dev,
1262 void *data, struct drm_file *file)
1263{
1264 struct drm_i915_private *dev_priv = dev->dev_private;
1265 struct drm_i915_reg_read *reg = data;
1266 struct register_whitelist const *entry = whitelist;
cf67c70f 1267 int i, ret = 0;
907b28c5
CW		 1268
1269 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1270 if (entry->offset == reg->offset &&
1271 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1272 break;
1273 }
1274
1275 if (i == ARRAY_SIZE(whitelist))
1276 return -EINVAL;
1277
cf67c70f
PZ		 1278 intel_runtime_pm_get(dev_priv);
1279
907b28c5
CW		 1280 switch (entry->size) {
1281 case 8:
1282 reg->val = I915_READ64(reg->offset);
1283 break;
1284 case 4:
1285 reg->val = I915_READ(reg->offset);
1286 break;
1287 case 2:
1288 reg->val = I915_READ16(reg->offset);
1289 break;
1290 case 1:
1291 reg->val = I915_READ8(reg->offset);
1292 break;
1293 default:
5f77eeb0 1294 MISSING_CASE(entry->size);
cf67c70f
PZ		 1295 ret = -EINVAL;
1296 goto out;
907b28c5
CW		 1297 }
1298
cf67c70f
PZ		 1299out:
1300 intel_runtime_pm_put(dev_priv);
1301 return ret;
907b28c5
CW		 1302}
1303
b6359918
MK		 1304int i915_get_reset_stats_ioctl(struct drm_device *dev,
1305 void *data, struct drm_file *file)
1306{
1307 struct drm_i915_private *dev_priv = dev->dev_private;
1308 struct drm_i915_reset_stats *args = data;
1309 struct i915_ctx_hang_stats *hs;
273497e5 1310 struct intel_context *ctx;
b6359918
MK		 1311 int ret;
1312
661df041
MK		 1313 if (args->flags || args->pad)
1314 return -EINVAL;
1315
821d66dd 1316 if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN))
b6359918
MK		 1317 return -EPERM;
1318
1319 ret = mutex_lock_interruptible(&dev->struct_mutex);
1320 if (ret)
1321 return ret;
1322
41bde553
BW		 1323 ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
1324 if (IS_ERR(ctx)) {
b6359918 1325 mutex_unlock(&dev->struct_mutex);
41bde553 1326 return PTR_ERR(ctx);
b6359918 1327 }
41bde553 1328 hs = &ctx->hang_stats;
b6359918
MK		 1329
1330 if (capable(CAP_SYS_ADMIN))
1331 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
1332 else
1333 args->reset_count = 0;
1334
1335 args->batch_active = hs->batch_active;
1336 args->batch_pending = hs->batch_pending;
1337
1338 mutex_unlock(&dev->struct_mutex);
1339
1340 return 0;
1341}
1342
59ea9054 1343static int i915_reset_complete(struct drm_device *dev)
907b28c5
CW		 1344{
1345 u8 gdrst;
59ea9054 1346 pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
73bbf6bd 1347 return (gdrst & GRDOM_RESET_STATUS) == 0;
907b28c5
CW		 1348}
1349
59ea9054 1350static int i915_do_reset(struct drm_device *dev)
907b28c5 1351{
73bbf6bd 1352 /* assert reset for at least 20 usec */
59ea9054 1353 pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
73bbf6bd 1354 udelay(20);
59ea9054 1355 pci_write_config_byte(dev->pdev, I915_GDRST, 0);
907b28c5 1356
59ea9054 1357 return wait_for(i915_reset_complete(dev), 500);
73bbf6bd
VS		 1358}
1359
1360static int g4x_reset_complete(struct drm_device *dev)
1361{
1362 u8 gdrst;
59ea9054 1363 pci_read_config_byte(dev->pdev, I915_GDRST, &gdrst);
73bbf6bd 1364 return (gdrst & GRDOM_RESET_ENABLE) == 0;
907b28c5
CW		 1365}
1366
408d4b9e
VS		 1367static int g33_do_reset(struct drm_device *dev)
1368{
408d4b9e
VS		 1369 pci_write_config_byte(dev->pdev, I915_GDRST, GRDOM_RESET_ENABLE);
1370 return wait_for(g4x_reset_complete(dev), 500);
1371}
1372
fa4f53c4
VS		 1373static int g4x_do_reset(struct drm_device *dev)
1374{
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 int ret;
1377
59ea9054 1378 pci_write_config_byte(dev->pdev, I915_GDRST,
fa4f53c4 1379 GRDOM_RENDER | GRDOM_RESET_ENABLE);
73bbf6bd 1380 ret = wait_for(g4x_reset_complete(dev), 500);
fa4f53c4
VS		 1381 if (ret)
1382 return ret;
1383
1384 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1385 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
1386 POSTING_READ(VDECCLK_GATE_D);
1387
59ea9054 1388 pci_write_config_byte(dev->pdev, I915_GDRST,
fa4f53c4 1389 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
73bbf6bd 1390 ret = wait_for(g4x_reset_complete(dev), 500);
fa4f53c4
VS		 1391 if (ret)
1392 return ret;
1393
1394 /* WaVcpClkGateDisableForMediaReset:ctg,elk */
1395 I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
1396 POSTING_READ(VDECCLK_GATE_D);
1397
59ea9054 1398 pci_write_config_byte(dev->pdev, I915_GDRST, 0);
fa4f53c4
VS		 1399
1400 return 0;
1401}
1402
907b28c5
CW		 1403static int ironlake_do_reset(struct drm_device *dev)
1404{
1405 struct drm_i915_private *dev_priv = dev->dev_private;
907b28c5
CW		 1406 int ret;
1407
907b28c5 1408 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
0f08ffd6 1409 ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
f67deb72 1410 ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
b3a3f03d 1411 ILK_GRDOM_RESET_ENABLE) == 0, 500);
907b28c5
CW		 1412 if (ret)
1413 return ret;
1414
907b28c5 1415 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
0f08ffd6 1416 ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
9aa7250f
VS		 1417 ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) &
1418 ILK_GRDOM_RESET_ENABLE) == 0, 500);
1419 if (ret)
1420 return ret;
1421
1422 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0);
1423
1424 return 0;
907b28c5
CW		 1425}
1426
1427static int gen6_do_reset(struct drm_device *dev)
1428{
1429 struct drm_i915_private *dev_priv = dev->dev_private;
1430 int ret;
907b28c5
CW		 1431
1432 /* Reset the chip */
1433
1434 /* GEN6_GDRST is not in the gt power well, no need to check
1435 * for fifo space for the write or forcewake the chip for
1436 * the read
1437 */
6af5d92f 1438 __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
907b28c5
CW		 1439
1440 /* Spin waiting for the device to ack the reset request */
6af5d92f 1441 ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
907b28c5 1442
0294ae7b 1443 intel_uncore_forcewake_reset(dev, true);
5babf0fc 1444
907b28c5
CW		 1445 return ret;
1446}
1447
1448int intel_gpu_reset(struct drm_device *dev)
1449{
542c184f
RB		 1450 if (INTEL_INFO(dev)->gen >= 6)
1451 return gen6_do_reset(dev);
1452 else if (IS_GEN5(dev))
1453 return ironlake_do_reset(dev);
1454 else if (IS_G4X(dev))
1455 return g4x_do_reset(dev);
408d4b9e
VS		 1456 else if (IS_G33(dev))
1457 return g33_do_reset(dev);
1458 else if (INTEL_INFO(dev)->gen >= 3)
59ea9054 1459 return i915_do_reset(dev);
542c184f
RB		 1460 else
1461 return -ENODEV;
907b28c5
CW		 1462}
1463
907b28c5
CW		 1464void intel_uncore_check_errors(struct drm_device *dev)
1465{
1466 struct drm_i915_private *dev_priv = dev->dev_private;
1467
1468 if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
6af5d92f 1469 (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
907b28c5 1470 DRM_ERROR("Unclaimed register before interrupt\n");
6af5d92f 1471 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
907b28c5
CW		 1472 }
1473}
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