[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / mediatek / mtk_drm_ddp_comp.c

/*
 * Copyright (c) 2015 MediaTek Inc.
 * Authors:
 *	YT Shen <yt.shen@mediatek.com>
 *	CK Hu <ck.hu@mediatek.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
#include "mtk_drm_drv.h"
#include "mtk_drm_plane.h"
#include "mtk_drm_ddp_comp.h"
#include "mtk_drm_crtc.h"

#define DISP_OD_EN				0x0000
#define DISP_OD_INTEN				0x0008
#define DISP_OD_INTSTA				0x000c
#define DISP_OD_CFG				0x0020
#define DISP_OD_SIZE				0x0030
#define DISP_DITHER_5				0x0114
#define DISP_DITHER_7				0x011c
#define DISP_DITHER_15				0x013c
#define DISP_DITHER_16				0x0140

#define DISP_REG_UFO_START			0x0000

#define DISP_AAL_EN				0x0000
#define DISP_AAL_SIZE				0x0030

#define DISP_GAMMA_EN				0x0000
#define DISP_GAMMA_CFG				0x0020
#define DISP_GAMMA_SIZE				0x0030
#define DISP_GAMMA_LUT				0x0700

#define LUT_10BIT_MASK				0x03ff

#define OD_RELAYMODE				BIT(0)

#define UFO_BYPASS				BIT(2)

#define AAL_EN					BIT(0)

#define GAMMA_EN				BIT(0)
#define GAMMA_LUT_EN				BIT(1)

#define DISP_DITHERING				BIT(2)
#define DITHER_LSB_ERR_SHIFT_R(x)		(((x) & 0x7) << 28)
#define DITHER_OVFLW_BIT_R(x)			(((x) & 0x7) << 24)
#define DITHER_ADD_LSHIFT_R(x)			(((x) & 0x7) << 20)
#define DITHER_ADD_RSHIFT_R(x)			(((x) & 0x7) << 16)
#define DITHER_NEW_BIT_MODE			BIT(0)
#define DITHER_LSB_ERR_SHIFT_B(x)		(((x) & 0x7) << 28)
#define DITHER_OVFLW_BIT_B(x)			(((x) & 0x7) << 24)
#define DITHER_ADD_LSHIFT_B(x)			(((x) & 0x7) << 20)
#define DITHER_ADD_RSHIFT_B(x)			(((x) & 0x7) << 16)
#define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)
#define DITHER_OVFLW_BIT_G(x)			(((x) & 0x7) << 8)
#define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)
#define DITHER_ADD_RSHIFT_G(x)			(((x) & 0x7) << 0)

void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc,
		    unsigned int CFG)
{
	/* If bpc equal to 0, the dithering function didn't be enabled */
	if (bpc == 0)
		return;

	if (bpc >= MTK_MIN_BPC) {
		writel(0, comp->regs + DISP_DITHER_5);
		writel(0, comp->regs + DISP_DITHER_7);
		writel(DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
		       DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
		       DITHER_NEW_BIT_MODE,
		       comp->regs + DISP_DITHER_15);
		writel(DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
		       DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
		       DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
		       DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
		       comp->regs + DISP_DITHER_16);
		writel(DISP_DITHERING, comp->regs + CFG);
	}
}

static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
			  unsigned int h, unsigned int vrefresh,
			  unsigned int bpc)
{
	writel(w << 16 | h, comp->regs + DISP_OD_SIZE);
	writel(OD_RELAYMODE, comp->regs + DISP_OD_CFG);
	mtk_dither_set(comp, bpc, DISP_OD_CFG);
}

static void mtk_od_start(struct mtk_ddp_comp *comp)
{
	writel(1, comp->regs + DISP_OD_EN);
}

static void mtk_ufoe_start(struct mtk_ddp_comp *comp)
{
	writel(UFO_BYPASS, comp->regs + DISP_REG_UFO_START);
}

static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
			   unsigned int h, unsigned int vrefresh,
			   unsigned int bpc)
{
	writel(h << 16 | w, comp->regs + DISP_AAL_SIZE);
}

static void mtk_aal_start(struct mtk_ddp_comp *comp)
{
	writel(AAL_EN, comp->regs + DISP_AAL_EN);
}

static void mtk_aal_stop(struct mtk_ddp_comp *comp)
{
	writel_relaxed(0x0, comp->regs + DISP_AAL_EN);
}

static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
			     unsigned int h, unsigned int vrefresh,
			     unsigned int bpc)
{
	writel(h << 16 | w, comp->regs + DISP_GAMMA_SIZE);
	mtk_dither_set(comp, bpc, DISP_GAMMA_CFG);
}

static void mtk_gamma_start(struct mtk_ddp_comp *comp)
{
	writel(GAMMA_EN, comp->regs  + DISP_GAMMA_EN);
}

static void mtk_gamma_stop(struct mtk_ddp_comp *comp)
{
	writel_relaxed(0x0, comp->regs  + DISP_GAMMA_EN);
}

static void mtk_gamma_set(struct mtk_ddp_comp *comp,
			  struct drm_crtc_state *state)
{
	unsigned int i, reg;
	struct drm_color_lut *lut;
	void __iomem *lut_base;
	u32 word;

	if (state->gamma_lut) {
		reg = readl(comp->regs + DISP_GAMMA_CFG);
		reg = reg | GAMMA_LUT_EN;
		writel(reg, comp->regs + DISP_GAMMA_CFG);
		lut_base = comp->regs + DISP_GAMMA_LUT;
		lut = (struct drm_color_lut *)state->gamma_lut->data;
		for (i = 0; i < MTK_LUT_SIZE; i++) {
			word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) +
				(((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) +
				((lut[i].blue >> 6) & LUT_10BIT_MASK);
			writel(word, (lut_base + i * 4));
		}
	}
}

static const struct mtk_ddp_comp_funcs ddp_aal = {
	.gamma_set = mtk_gamma_set,
	.config = mtk_aal_config,
	.start = mtk_aal_start,
	.stop = mtk_aal_stop,
};

static const struct mtk_ddp_comp_funcs ddp_gamma = {
	.gamma_set = mtk_gamma_set,
	.config = mtk_gamma_config,
	.start = mtk_gamma_start,
	.stop = mtk_gamma_stop,
};

static const struct mtk_ddp_comp_funcs ddp_od = {
	.config = mtk_od_config,
	.start = mtk_od_start,
};

static const struct mtk_ddp_comp_funcs ddp_ufoe = {
	.start = mtk_ufoe_start,
};

static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
	[MTK_DISP_OVL] = "ovl",
	[MTK_DISP_RDMA] = "rdma",
	[MTK_DISP_WDMA] = "wdma",
	[MTK_DISP_COLOR] = "color",
	[MTK_DISP_AAL] = "aal",
	[MTK_DISP_GAMMA] = "gamma",
	[MTK_DISP_UFOE] = "ufoe",
	[MTK_DSI] = "dsi",
	[MTK_DPI] = "dpi",
	[MTK_DISP_PWM] = "pwm",
	[MTK_DISP_MUTEX] = "mutex",
	[MTK_DISP_OD] = "od",
	[MTK_DISP_BLS] = "bls",
};

struct mtk_ddp_comp_match {
	enum mtk_ddp_comp_type type;
	int alias_id;
	const struct mtk_ddp_comp_funcs *funcs;
};

static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
	[DDP_COMPONENT_AAL]	= { MTK_DISP_AAL,	0, &ddp_aal },
	[DDP_COMPONENT_BLS]	= { MTK_DISP_BLS,	0, NULL },
	[DDP_COMPONENT_COLOR0]	= { MTK_DISP_COLOR,	0, NULL },
	[DDP_COMPONENT_COLOR1]	= { MTK_DISP_COLOR,	1, NULL },
	[DDP_COMPONENT_DPI0]	= { MTK_DPI,		0, NULL },
	[DDP_COMPONENT_DSI0]	= { MTK_DSI,		0, NULL },
	[DDP_COMPONENT_DSI1]	= { MTK_DSI,		1, NULL },
	[DDP_COMPONENT_GAMMA]	= { MTK_DISP_GAMMA,	0, &ddp_gamma },
	[DDP_COMPONENT_OD]	= { MTK_DISP_OD,	0, &ddp_od },
	[DDP_COMPONENT_OVL0]	= { MTK_DISP_OVL,	0, NULL },
	[DDP_COMPONENT_OVL1]	= { MTK_DISP_OVL,	1, NULL },
	[DDP_COMPONENT_PWM0]	= { MTK_DISP_PWM,	0, NULL },
	[DDP_COMPONENT_RDMA0]	= { MTK_DISP_RDMA,	0, NULL },
	[DDP_COMPONENT_RDMA1]	= { MTK_DISP_RDMA,	1, NULL },
	[DDP_COMPONENT_RDMA2]	= { MTK_DISP_RDMA,	2, NULL },
	[DDP_COMPONENT_UFOE]	= { MTK_DISP_UFOE,	0, &ddp_ufoe },
	[DDP_COMPONENT_WDMA0]	= { MTK_DISP_WDMA,	0, NULL },
	[DDP_COMPONENT_WDMA1]	= { MTK_DISP_WDMA,	1, NULL },
};

int mtk_ddp_comp_get_id(struct device_node *node,
			enum mtk_ddp_comp_type comp_type)
{
	int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
	int i;

	for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
		if (comp_type == mtk_ddp_matches[i].type &&
		    (id < 0 || id == mtk_ddp_matches[i].alias_id))
			return i;
	}

	return -EINVAL;
}

int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
		      struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id,
		      const struct mtk_ddp_comp_funcs *funcs)
{
	enum mtk_ddp_comp_type type;
	struct device_node *larb_node;
	struct platform_device *larb_pdev;

	if (comp_id < 0 || comp_id >= DDP_COMPONENT_ID_MAX)
		return -EINVAL;

	type = mtk_ddp_matches[comp_id].type;

	comp->id = comp_id;
	comp->funcs = funcs ?: mtk_ddp_matches[comp_id].funcs;

	if (comp_id == DDP_COMPONENT_BLS ||
	    comp_id == DDP_COMPONENT_DPI0 ||
	    comp_id == DDP_COMPONENT_DSI0 ||
	    comp_id == DDP_COMPONENT_PWM0) {
		comp->regs = NULL;
		comp->clk = NULL;
		comp->irq = 0;
		return 0;
	}

	comp->regs = of_iomap(node, 0);
	comp->irq = of_irq_get(node, 0);
	comp->clk = of_clk_get(node, 0);
	if (IS_ERR(comp->clk))
		comp->clk = NULL;

	/* Only DMA capable components need the LARB property */
	comp->larb_dev = NULL;
	if (type != MTK_DISP_OVL &&
	    type != MTK_DISP_RDMA &&
	    type != MTK_DISP_WDMA)
		return 0;

	larb_node = of_parse_phandle(node, "mediatek,larb", 0);
	if (!larb_node) {
		dev_err(dev,
			"Missing mediadek,larb phandle in %s node\n",
			node->full_name);
		return -EINVAL;
	}

	larb_pdev = of_find_device_by_node(larb_node);
	if (!larb_pdev) {
		dev_warn(dev, "Waiting for larb device %s\n",
			 larb_node->full_name);
		of_node_put(larb_node);
		return -EPROBE_DEFER;
	}
	of_node_put(larb_node);

	comp->larb_dev = &larb_pdev->dev;

	return 0;
}

int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp)
{
	struct mtk_drm_private *private = drm->dev_private;

	if (private->ddp_comp[comp->id])
		return -EBUSY;

	private->ddp_comp[comp->id] = comp;
	return 0;
}

void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp)
{
	struct mtk_drm_private *private = drm->dev_private;

	private->ddp_comp[comp->id] = NULL;
}
Commit	Line	Data
119f5173 CH	1	/*
	2	* Copyright (c) 2015 MediaTek Inc.
	3	* Authors:
	4	* YT Shen <yt.shen@mediatek.com>
	5	* CK Hu <ck.hu@mediatek.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16
	17	#include <linux/clk.h>
	18	#include <linux/of.h>
	19	#include <linux/of_address.h>
	20	#include <linux/of_irq.h>
	21	#include <linux/of_platform.h>
	22	#include <linux/platform_device.h>
	23	#include <drm/drmP.h>
	24	#include "mtk_drm_drv.h"
	25	#include "mtk_drm_plane.h"
	26	#include "mtk_drm_ddp_comp.h"
2f3f4dda	27	#include "mtk_drm_crtc.h"
119f5173 CH	28
	29	#define DISP_OD_EN 0x0000
	30	#define DISP_OD_INTEN 0x0008
	31	#define DISP_OD_INTSTA 0x000c
	32	#define DISP_OD_CFG 0x0020
	33	#define DISP_OD_SIZE 0x0030
72164364 BH	34	#define DISP_DITHER_5 0x0114
	35	#define DISP_DITHER_7 0x011c
	36	#define DISP_DITHER_15 0x013c
	37	#define DISP_DITHER_16 0x0140
119f5173 CH	38
	39	#define DISP_REG_UFO_START 0x0000
	40
0664d139 BH	41	#define DISP_AAL_EN 0x0000
	42	#define DISP_AAL_SIZE 0x0030
	43
e0a5d337	44	#define DISP_GAMMA_EN 0x0000
2f3f4dda	45	#define DISP_GAMMA_CFG 0x0020
e0a5d337	46	#define DISP_GAMMA_SIZE 0x0030
2f3f4dda BH	47	#define DISP_GAMMA_LUT 0x0700
	48
	49	#define LUT_10BIT_MASK 0x03ff
e0a5d337	50
72164364	51	#define OD_RELAYMODE BIT(0)
119f5173	52
72164364	53	#define UFO_BYPASS BIT(2)
119f5173	54
72164364	55	#define AAL_EN BIT(0)
0664d139	56
72164364 BH	57	#define GAMMA_EN BIT(0)
	58	#define GAMMA_LUT_EN BIT(1)
	59
	60	#define DISP_DITHERING BIT(2)
	61	#define DITHER_LSB_ERR_SHIFT_R(x) (((x) & 0x7) << 28)
	62	#define DITHER_OVFLW_BIT_R(x) (((x) & 0x7) << 24)
	63	#define DITHER_ADD_LSHIFT_R(x) (((x) & 0x7) << 20)
	64	#define DITHER_ADD_RSHIFT_R(x) (((x) & 0x7) << 16)
	65	#define DITHER_NEW_BIT_MODE BIT(0)
	66	#define DITHER_LSB_ERR_SHIFT_B(x) (((x) & 0x7) << 28)
	67	#define DITHER_OVFLW_BIT_B(x) (((x) & 0x7) << 24)
	68	#define DITHER_ADD_LSHIFT_B(x) (((x) & 0x7) << 20)
	69	#define DITHER_ADD_RSHIFT_B(x) (((x) & 0x7) << 16)
	70	#define DITHER_LSB_ERR_SHIFT_G(x) (((x) & 0x7) << 12)
	71	#define DITHER_OVFLW_BIT_G(x) (((x) & 0x7) << 8)
	72	#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
	73	#define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0)
	74
	75	void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc,
	76	unsigned int CFG)
	77	{
	78	/* If bpc equal to 0, the dithering function didn't be enabled */
	79	if (bpc == 0)
	80	return;
	81
	82	if (bpc >= MTK_MIN_BPC) {
	83	writel(0, comp->regs + DISP_DITHER_5);
	84	writel(0, comp->regs + DISP_DITHER_7);
	85	writel(DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) \|
	86	DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) \|
	87	DITHER_NEW_BIT_MODE,
	88	comp->regs + DISP_DITHER_15);
	89	writel(DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) \|
	90	DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) \|
	91	DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) \|
	92	DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
	93	comp->regs + DISP_DITHER_16);
	94	writel(DISP_DITHERING, comp->regs + CFG);
	95	}
	96	}
e0a5d337	97
119f5173	98	static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
72164364 BH	99	unsigned int h, unsigned int vrefresh,
72164364 BH	100	unsigned int bpc)
119f5173 CH	101	{
119f5173 CH	102	writel(w << 16 \| h, comp->regs + DISP_OD_SIZE);
1ee6f347	103	writel(OD_RELAYMODE, comp->regs + DISP_OD_CFG);
72164364	104	mtk_dither_set(comp, bpc, DISP_OD_CFG);
119f5173 CH	105	}
	106
	107	static void mtk_od_start(struct mtk_ddp_comp *comp)
	108	{
119f5173 CH	109	writel(1, comp->regs + DISP_OD_EN);
	110	}
	111
	112	static void mtk_ufoe_start(struct mtk_ddp_comp *comp)
	113	{
	114	writel(UFO_BYPASS, comp->regs + DISP_REG_UFO_START);
	115	}
	116
0664d139	117	static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
72164364 BH	118	unsigned int h, unsigned int vrefresh,
72164364 BH	119	unsigned int bpc)
0664d139 BH	120	{
	121	writel(h << 16 \| w, comp->regs + DISP_AAL_SIZE);
	122	}
	123
	124	static void mtk_aal_start(struct mtk_ddp_comp *comp)
	125	{
	126	writel(AAL_EN, comp->regs + DISP_AAL_EN);
	127	}
	128
	129	static void mtk_aal_stop(struct mtk_ddp_comp *comp)
	130	{
	131	writel_relaxed(0x0, comp->regs + DISP_AAL_EN);
	132	}
	133
e0a5d337	134	static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
72164364 BH	135	unsigned int h, unsigned int vrefresh,
72164364 BH	136	unsigned int bpc)
e0a5d337 BH	137	{
e0a5d337 BH	138	writel(h << 16 \| w, comp->regs + DISP_GAMMA_SIZE);
72164364	139	mtk_dither_set(comp, bpc, DISP_GAMMA_CFG);
e0a5d337 BH	140	}
	141
	142	static void mtk_gamma_start(struct mtk_ddp_comp *comp)
	143	{
	144	writel(GAMMA_EN, comp->regs + DISP_GAMMA_EN);
	145	}
	146
	147	static void mtk_gamma_stop(struct mtk_ddp_comp *comp)
	148	{
	149	writel_relaxed(0x0, comp->regs + DISP_GAMMA_EN);
	150	}
	151
2f3f4dda BH	152	static void mtk_gamma_set(struct mtk_ddp_comp *comp,
	153	struct drm_crtc_state *state)
	154	{
	155	unsigned int i, reg;
	156	struct drm_color_lut *lut;
	157	void __iomem *lut_base;
	158	u32 word;
	159
	160	if (state->gamma_lut) {
	161	reg = readl(comp->regs + DISP_GAMMA_CFG);
	162	reg = reg \| GAMMA_LUT_EN;
	163	writel(reg, comp->regs + DISP_GAMMA_CFG);
	164	lut_base = comp->regs + DISP_GAMMA_LUT;
	165	lut = (struct drm_color_lut *)state->gamma_lut->data;
	166	for (i = 0; i < MTK_LUT_SIZE; i++) {
	167	word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) +
	168	(((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) +
	169	((lut[i].blue >> 6) & LUT_10BIT_MASK);
	170	writel(word, (lut_base + i * 4));
	171	}
	172	}
	173	}
	174
0664d139	175	static const struct mtk_ddp_comp_funcs ddp_aal = {
2f3f4dda	176	.gamma_set = mtk_gamma_set,
0664d139 BH	177	.config = mtk_aal_config,
	178	.start = mtk_aal_start,
	179	.stop = mtk_aal_stop,
	180	};
	181
e0a5d337	182	static const struct mtk_ddp_comp_funcs ddp_gamma = {
2f3f4dda	183	.gamma_set = mtk_gamma_set,
e0a5d337 BH	184	.config = mtk_gamma_config,
	185	.start = mtk_gamma_start,
	186	.stop = mtk_gamma_stop,
	187	};
	188
119f5173 CH	189	static const struct mtk_ddp_comp_funcs ddp_od = {
	190	.config = mtk_od_config,
	191	.start = mtk_od_start,
	192	};
	193
	194	static const struct mtk_ddp_comp_funcs ddp_ufoe = {
	195	.start = mtk_ufoe_start,
	196	};
	197
	198	static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
	199	[MTK_DISP_OVL] = "ovl",
	200	[MTK_DISP_RDMA] = "rdma",
	201	[MTK_DISP_WDMA] = "wdma",
	202	[MTK_DISP_COLOR] = "color",
	203	[MTK_DISP_AAL] = "aal",
	204	[MTK_DISP_GAMMA] = "gamma",
	205	[MTK_DISP_UFOE] = "ufoe",
	206	[MTK_DSI] = "dsi",
	207	[MTK_DPI] = "dpi",
	208	[MTK_DISP_PWM] = "pwm",
	209	[MTK_DISP_MUTEX] = "mutex",
	210	[MTK_DISP_OD] = "od",
c37813de	211	[MTK_DISP_BLS] = "bls",
119f5173 CH	212	};
	213
	214	struct mtk_ddp_comp_match {
	215	enum mtk_ddp_comp_type type;
	216	int alias_id;
	217	const struct mtk_ddp_comp_funcs *funcs;
	218	};
	219
	220	static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
0664d139	221	[DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal },
c37813de	222	[DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
5ac5895a	223	[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL },
5ac5895a	224	[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL },
119f5173 CH	225	[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, NULL },
	226	[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL },
	227	[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL },
e0a5d337	228	[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
119f5173 CH	229	[DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od },
	230	[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL },
	231	[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL },
	232	[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
	233	[DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
	234	[DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
	235	[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
	236	[DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
	237	[DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
	238	[DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
	239	};
	240
	241	int mtk_ddp_comp_get_id(struct device_node *node,
	242	enum mtk_ddp_comp_type comp_type)
	243	{
	244	int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
	245	int i;
	246
	247	for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
	248	if (comp_type == mtk_ddp_matches[i].type &&
	249	(id < 0 \|\| id == mtk_ddp_matches[i].alias_id))
	250	return i;
	251	}
	252
	253	return -EINVAL;
	254	}
	255
	256	int mtk_ddp_comp_init(struct device dev, struct device_node node,
	257	struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id comp_id,
	258	const struct mtk_ddp_comp_funcs *funcs)
	259	{
	260	enum mtk_ddp_comp_type type;
	261	struct device_node *larb_node;
	262	struct platform_device *larb_pdev;
	263
	264	if (comp_id < 0 \|\| comp_id >= DDP_COMPONENT_ID_MAX)
	265	return -EINVAL;
	266
c5f228ef	267	type = mtk_ddp_matches[comp_id].type;
c5f228ef	268
119f5173 CH	269	comp->id = comp_id;
	270	comp->funcs = funcs ?: mtk_ddp_matches[comp_id].funcs;
	271
c37813de	272	if (comp_id == DDP_COMPONENT_BLS \|\|
c37813de	273	comp_id == DDP_COMPONENT_DPI0 \|\|
119f5173 CH	274	comp_id == DDP_COMPONENT_DSI0 \|\|
	275	comp_id == DDP_COMPONENT_PWM0) {
	276	comp->regs = NULL;
	277	comp->clk = NULL;
	278	comp->irq = 0;
	279	return 0;
	280	}
	281
	282	comp->regs = of_iomap(node, 0);
	283	comp->irq = of_irq_get(node, 0);
	284	comp->clk = of_clk_get(node, 0);
	285	if (IS_ERR(comp->clk))
	286	comp->clk = NULL;
	287
119f5173 CH	288	/* Only DMA capable components need the LARB property */
	289	comp->larb_dev = NULL;
	290	if (type != MTK_DISP_OVL &&
	291	type != MTK_DISP_RDMA &&
	292	type != MTK_DISP_WDMA)
	293	return 0;
	294
	295	larb_node = of_parse_phandle(node, "mediatek,larb", 0);
	296	if (!larb_node) {
	297	dev_err(dev,
	298	"Missing mediadek,larb phandle in %s node\n",
	299	node->full_name);
	300	return -EINVAL;
	301	}
	302
	303	larb_pdev = of_find_device_by_node(larb_node);
	304	if (!larb_pdev) {
	305	dev_warn(dev, "Waiting for larb device %s\n",
	306	larb_node->full_name);
	307	of_node_put(larb_node);
	308	return -EPROBE_DEFER;
	309	}
	310	of_node_put(larb_node);
	311
	312	comp->larb_dev = &larb_pdev->dev;
	313
	314	return 0;
	315	}
	316
	317	int mtk_ddp_comp_register(struct drm_device drm, struct mtk_ddp_comp comp)
	318	{
	319	struct mtk_drm_private *private = drm->dev_private;
	320
	321	if (private->ddp_comp[comp->id])
	322	return -EBUSY;
	323
	324	private->ddp_comp[comp->id] = comp;
	325	return 0;
	326	}
	327
	328	void mtk_ddp_comp_unregister(struct drm_device drm, struct mtk_ddp_comp comp)
	329	{
	330	struct mtk_drm_private *private = drm->dev_private;
	331
	332	private->ddp_comp[comp->id] = NULL;
	333	}