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414c4531 DA |
1 | /* |
2 | * Copyright 2010 Matt Turner. | |
3 | * Copyright 2012 Red Hat | |
4 | * | |
5 | * This file is subject to the terms and conditions of the GNU General | |
6 | * Public License version 2. See the file COPYING in the main | |
7 | * directory of this archive for more details. | |
8 | * | |
9 | * Authors: Matthew Garrett | |
10 | * Matt Turner | |
11 | * Dave Airlie | |
12 | */ | |
13 | ||
14 | #include <linux/delay.h> | |
15 | ||
760285e7 DH |
16 | #include <drm/drmP.h> |
17 | #include <drm/drm_crtc_helper.h> | |
414c4531 DA |
18 | |
19 | #include "mgag200_drv.h" | |
20 | ||
21 | #define MGAG200_LUT_SIZE 256 | |
22 | ||
23 | /* | |
24 | * This file contains setup code for the CRTC. | |
25 | */ | |
26 | ||
27 | static void mga_crtc_load_lut(struct drm_crtc *crtc) | |
28 | { | |
29 | struct mga_crtc *mga_crtc = to_mga_crtc(crtc); | |
30 | struct drm_device *dev = crtc->dev; | |
31 | struct mga_device *mdev = dev->dev_private; | |
32 | int i; | |
33 | ||
34 | if (!crtc->enabled) | |
35 | return; | |
36 | ||
37 | WREG8(DAC_INDEX + MGA1064_INDEX, 0); | |
38 | ||
39 | for (i = 0; i < MGAG200_LUT_SIZE; i++) { | |
40 | /* VGA registers */ | |
41 | WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_r[i]); | |
42 | WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]); | |
43 | WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_b[i]); | |
44 | } | |
45 | } | |
46 | ||
47 | static inline void mga_wait_vsync(struct mga_device *mdev) | |
48 | { | |
3cdc0e8d | 49 | unsigned long timeout = jiffies + HZ/10; |
414c4531 DA |
50 | unsigned int status = 0; |
51 | ||
52 | do { | |
53 | status = RREG32(MGAREG_Status); | |
3cdc0e8d CH |
54 | } while ((status & 0x08) && time_before(jiffies, timeout)); |
55 | timeout = jiffies + HZ/10; | |
414c4531 DA |
56 | status = 0; |
57 | do { | |
58 | status = RREG32(MGAREG_Status); | |
3cdc0e8d | 59 | } while (!(status & 0x08) && time_before(jiffies, timeout)); |
414c4531 DA |
60 | } |
61 | ||
62 | static inline void mga_wait_busy(struct mga_device *mdev) | |
63 | { | |
3cdc0e8d | 64 | unsigned long timeout = jiffies + HZ; |
414c4531 DA |
65 | unsigned int status = 0; |
66 | do { | |
67 | status = RREG8(MGAREG_Status + 2); | |
3cdc0e8d | 68 | } while ((status & 0x01) && time_before(jiffies, timeout)); |
414c4531 DA |
69 | } |
70 | ||
71 | /* | |
72 | * The core passes the desired mode to the CRTC code to see whether any | |
73 | * CRTC-specific modifications need to be made to it. We're in a position | |
74 | * to just pass that straight through, so this does nothing | |
75 | */ | |
76 | static bool mga_crtc_mode_fixup(struct drm_crtc *crtc, | |
e811f5ae LP |
77 | const struct drm_display_mode *mode, |
78 | struct drm_display_mode *adjusted_mode) | |
414c4531 DA |
79 | { |
80 | return true; | |
81 | } | |
82 | ||
83 | static int mga_g200se_set_plls(struct mga_device *mdev, long clock) | |
84 | { | |
85 | unsigned int vcomax, vcomin, pllreffreq; | |
86 | unsigned int delta, tmpdelta, permitteddelta; | |
87 | unsigned int testp, testm, testn; | |
88 | unsigned int p, m, n; | |
89 | unsigned int computed; | |
90 | ||
91 | m = n = p = 0; | |
92 | vcomax = 320000; | |
93 | vcomin = 160000; | |
94 | pllreffreq = 25000; | |
95 | ||
96 | delta = 0xffffffff; | |
97 | permitteddelta = clock * 5 / 1000; | |
98 | ||
99 | for (testp = 8; testp > 0; testp /= 2) { | |
100 | if (clock * testp > vcomax) | |
101 | continue; | |
102 | if (clock * testp < vcomin) | |
103 | continue; | |
104 | ||
105 | for (testn = 17; testn < 256; testn++) { | |
106 | for (testm = 1; testm < 32; testm++) { | |
107 | computed = (pllreffreq * testn) / | |
108 | (testm * testp); | |
109 | if (computed > clock) | |
110 | tmpdelta = computed - clock; | |
111 | else | |
112 | tmpdelta = clock - computed; | |
113 | if (tmpdelta < delta) { | |
114 | delta = tmpdelta; | |
115 | m = testm - 1; | |
116 | n = testn - 1; | |
117 | p = testp - 1; | |
118 | } | |
119 | } | |
120 | } | |
121 | } | |
122 | ||
123 | if (delta > permitteddelta) { | |
124 | printk(KERN_WARNING "PLL delta too large\n"); | |
125 | return 1; | |
126 | } | |
127 | ||
128 | WREG_DAC(MGA1064_PIX_PLLC_M, m); | |
129 | WREG_DAC(MGA1064_PIX_PLLC_N, n); | |
130 | WREG_DAC(MGA1064_PIX_PLLC_P, p); | |
131 | return 0; | |
132 | } | |
133 | ||
134 | static int mga_g200wb_set_plls(struct mga_device *mdev, long clock) | |
135 | { | |
136 | unsigned int vcomax, vcomin, pllreffreq; | |
137 | unsigned int delta, tmpdelta, permitteddelta; | |
138 | unsigned int testp, testm, testn; | |
139 | unsigned int p, m, n; | |
140 | unsigned int computed; | |
141 | int i, j, tmpcount, vcount; | |
142 | bool pll_locked = false; | |
143 | u8 tmp; | |
144 | ||
145 | m = n = p = 0; | |
146 | vcomax = 550000; | |
147 | vcomin = 150000; | |
148 | pllreffreq = 48000; | |
149 | ||
150 | delta = 0xffffffff; | |
151 | permitteddelta = clock * 5 / 1000; | |
152 | ||
153 | for (testp = 1; testp < 9; testp++) { | |
154 | if (clock * testp > vcomax) | |
155 | continue; | |
156 | if (clock * testp < vcomin) | |
157 | continue; | |
158 | ||
159 | for (testm = 1; testm < 17; testm++) { | |
160 | for (testn = 1; testn < 151; testn++) { | |
161 | computed = (pllreffreq * testn) / | |
162 | (testm * testp); | |
163 | if (computed > clock) | |
164 | tmpdelta = computed - clock; | |
165 | else | |
166 | tmpdelta = clock - computed; | |
167 | if (tmpdelta < delta) { | |
168 | delta = tmpdelta; | |
169 | n = testn - 1; | |
170 | m = (testm - 1) | ((n >> 1) & 0x80); | |
171 | p = testp - 1; | |
172 | } | |
173 | } | |
174 | } | |
175 | } | |
176 | ||
177 | for (i = 0; i <= 32 && pll_locked == false; i++) { | |
178 | if (i > 0) { | |
179 | WREG8(MGAREG_CRTC_INDEX, 0x1e); | |
180 | tmp = RREG8(MGAREG_CRTC_DATA); | |
181 | if (tmp < 0xff) | |
182 | WREG8(MGAREG_CRTC_DATA, tmp+1); | |
183 | } | |
184 | ||
185 | /* set pixclkdis to 1 */ | |
186 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
187 | tmp = RREG8(DAC_DATA); | |
188 | tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; | |
fb70a669 | 189 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
190 | |
191 | WREG8(DAC_INDEX, MGA1064_REMHEADCTL); | |
192 | tmp = RREG8(DAC_DATA); | |
193 | tmp |= MGA1064_REMHEADCTL_CLKDIS; | |
fb70a669 | 194 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
195 | |
196 | /* select PLL Set C */ | |
197 | tmp = RREG8(MGAREG_MEM_MISC_READ); | |
198 | tmp |= 0x3 << 2; | |
199 | WREG8(MGAREG_MEM_MISC_WRITE, tmp); | |
200 | ||
201 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
202 | tmp = RREG8(DAC_DATA); | |
203 | tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80; | |
fb70a669 | 204 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
205 | |
206 | udelay(500); | |
207 | ||
208 | /* reset the PLL */ | |
209 | WREG8(DAC_INDEX, MGA1064_VREF_CTL); | |
210 | tmp = RREG8(DAC_DATA); | |
211 | tmp &= ~0x04; | |
fb70a669 | 212 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
213 | |
214 | udelay(50); | |
215 | ||
216 | /* program pixel pll register */ | |
217 | WREG_DAC(MGA1064_WB_PIX_PLLC_N, n); | |
218 | WREG_DAC(MGA1064_WB_PIX_PLLC_M, m); | |
219 | WREG_DAC(MGA1064_WB_PIX_PLLC_P, p); | |
220 | ||
221 | udelay(50); | |
222 | ||
223 | /* turn pll on */ | |
224 | WREG8(DAC_INDEX, MGA1064_VREF_CTL); | |
225 | tmp = RREG8(DAC_DATA); | |
226 | tmp |= 0x04; | |
227 | WREG_DAC(MGA1064_VREF_CTL, tmp); | |
228 | ||
229 | udelay(500); | |
230 | ||
231 | /* select the pixel pll */ | |
232 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
233 | tmp = RREG8(DAC_DATA); | |
234 | tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; | |
235 | tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; | |
fb70a669 | 236 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
237 | |
238 | WREG8(DAC_INDEX, MGA1064_REMHEADCTL); | |
239 | tmp = RREG8(DAC_DATA); | |
240 | tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK; | |
241 | tmp |= MGA1064_REMHEADCTL_CLKSL_PLL; | |
fb70a669 | 242 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
243 | |
244 | /* reset dotclock rate bit */ | |
245 | WREG8(MGAREG_SEQ_INDEX, 1); | |
246 | tmp = RREG8(MGAREG_SEQ_DATA); | |
247 | tmp &= ~0x8; | |
248 | WREG8(MGAREG_SEQ_DATA, tmp); | |
249 | ||
250 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
251 | tmp = RREG8(DAC_DATA); | |
252 | tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; | |
fb70a669 | 253 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
254 | |
255 | vcount = RREG8(MGAREG_VCOUNT); | |
256 | ||
257 | for (j = 0; j < 30 && pll_locked == false; j++) { | |
258 | tmpcount = RREG8(MGAREG_VCOUNT); | |
259 | if (tmpcount < vcount) | |
260 | vcount = 0; | |
261 | if ((tmpcount - vcount) > 2) | |
262 | pll_locked = true; | |
263 | else | |
264 | udelay(5); | |
265 | } | |
266 | } | |
267 | WREG8(DAC_INDEX, MGA1064_REMHEADCTL); | |
268 | tmp = RREG8(DAC_DATA); | |
269 | tmp &= ~MGA1064_REMHEADCTL_CLKDIS; | |
270 | WREG_DAC(MGA1064_REMHEADCTL, tmp); | |
271 | return 0; | |
272 | } | |
273 | ||
274 | static int mga_g200ev_set_plls(struct mga_device *mdev, long clock) | |
275 | { | |
276 | unsigned int vcomax, vcomin, pllreffreq; | |
277 | unsigned int delta, tmpdelta, permitteddelta; | |
278 | unsigned int testp, testm, testn; | |
279 | unsigned int p, m, n; | |
280 | unsigned int computed; | |
281 | u8 tmp; | |
282 | ||
283 | m = n = p = 0; | |
284 | vcomax = 550000; | |
285 | vcomin = 150000; | |
286 | pllreffreq = 50000; | |
287 | ||
288 | delta = 0xffffffff; | |
289 | permitteddelta = clock * 5 / 1000; | |
290 | ||
291 | for (testp = 16; testp > 0; testp--) { | |
292 | if (clock * testp > vcomax) | |
293 | continue; | |
294 | if (clock * testp < vcomin) | |
295 | continue; | |
296 | ||
297 | for (testn = 1; testn < 257; testn++) { | |
298 | for (testm = 1; testm < 17; testm++) { | |
299 | computed = (pllreffreq * testn) / | |
300 | (testm * testp); | |
301 | if (computed > clock) | |
302 | tmpdelta = computed - clock; | |
303 | else | |
304 | tmpdelta = clock - computed; | |
305 | if (tmpdelta < delta) { | |
306 | delta = tmpdelta; | |
307 | n = testn - 1; | |
308 | m = testm - 1; | |
309 | p = testp - 1; | |
310 | } | |
311 | } | |
312 | } | |
313 | } | |
314 | ||
315 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
316 | tmp = RREG8(DAC_DATA); | |
317 | tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; | |
fb70a669 | 318 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
319 | |
320 | tmp = RREG8(MGAREG_MEM_MISC_READ); | |
321 | tmp |= 0x3 << 2; | |
322 | WREG8(MGAREG_MEM_MISC_WRITE, tmp); | |
323 | ||
324 | WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT); | |
325 | tmp = RREG8(DAC_DATA); | |
fb70a669 | 326 | WREG8(DAC_DATA, tmp & ~0x40); |
414c4531 DA |
327 | |
328 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
329 | tmp = RREG8(DAC_DATA); | |
330 | tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; | |
fb70a669 | 331 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
332 | |
333 | WREG_DAC(MGA1064_EV_PIX_PLLC_M, m); | |
334 | WREG_DAC(MGA1064_EV_PIX_PLLC_N, n); | |
335 | WREG_DAC(MGA1064_EV_PIX_PLLC_P, p); | |
336 | ||
337 | udelay(50); | |
338 | ||
339 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
340 | tmp = RREG8(DAC_DATA); | |
341 | tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; | |
fb70a669 | 342 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
343 | |
344 | udelay(500); | |
345 | ||
346 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
347 | tmp = RREG8(DAC_DATA); | |
348 | tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; | |
349 | tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; | |
fb70a669 | 350 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
351 | |
352 | WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT); | |
353 | tmp = RREG8(DAC_DATA); | |
fb70a669 | 354 | WREG8(DAC_DATA, tmp | 0x40); |
414c4531 DA |
355 | |
356 | tmp = RREG8(MGAREG_MEM_MISC_READ); | |
357 | tmp |= (0x3 << 2); | |
358 | WREG8(MGAREG_MEM_MISC_WRITE, tmp); | |
359 | ||
360 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
361 | tmp = RREG8(DAC_DATA); | |
362 | tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; | |
fb70a669 | 363 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
364 | |
365 | return 0; | |
366 | } | |
367 | ||
368 | static int mga_g200eh_set_plls(struct mga_device *mdev, long clock) | |
369 | { | |
370 | unsigned int vcomax, vcomin, pllreffreq; | |
371 | unsigned int delta, tmpdelta, permitteddelta; | |
372 | unsigned int testp, testm, testn; | |
373 | unsigned int p, m, n; | |
374 | unsigned int computed; | |
375 | int i, j, tmpcount, vcount; | |
376 | u8 tmp; | |
377 | bool pll_locked = false; | |
378 | ||
379 | m = n = p = 0; | |
380 | vcomax = 800000; | |
381 | vcomin = 400000; | |
260b3f12 | 382 | pllreffreq = 33333; |
414c4531 DA |
383 | |
384 | delta = 0xffffffff; | |
385 | permitteddelta = clock * 5 / 1000; | |
386 | ||
260b3f12 | 387 | for (testp = 16; testp > 0; testp >>= 1) { |
414c4531 DA |
388 | if (clock * testp > vcomax) |
389 | continue; | |
390 | if (clock * testp < vcomin) | |
391 | continue; | |
392 | ||
393 | for (testm = 1; testm < 33; testm++) { | |
260b3f12 | 394 | for (testn = 17; testn < 257; testn++) { |
414c4531 DA |
395 | computed = (pllreffreq * testn) / |
396 | (testm * testp); | |
397 | if (computed > clock) | |
398 | tmpdelta = computed - clock; | |
399 | else | |
400 | tmpdelta = clock - computed; | |
401 | if (tmpdelta < delta) { | |
402 | delta = tmpdelta; | |
403 | n = testn - 1; | |
260b3f12 | 404 | m = (testm - 1); |
414c4531 DA |
405 | p = testp - 1; |
406 | } | |
407 | if ((clock * testp) >= 600000) | |
260b3f12 | 408 | p |= 0x80; |
414c4531 DA |
409 | } |
410 | } | |
411 | } | |
412 | for (i = 0; i <= 32 && pll_locked == false; i++) { | |
413 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
414 | tmp = RREG8(DAC_DATA); | |
415 | tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; | |
fb70a669 | 416 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
417 | |
418 | tmp = RREG8(MGAREG_MEM_MISC_READ); | |
419 | tmp |= 0x3 << 2; | |
420 | WREG8(MGAREG_MEM_MISC_WRITE, tmp); | |
421 | ||
422 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
423 | tmp = RREG8(DAC_DATA); | |
424 | tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; | |
fb70a669 | 425 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
426 | |
427 | udelay(500); | |
428 | ||
429 | WREG_DAC(MGA1064_EH_PIX_PLLC_M, m); | |
430 | WREG_DAC(MGA1064_EH_PIX_PLLC_N, n); | |
431 | WREG_DAC(MGA1064_EH_PIX_PLLC_P, p); | |
432 | ||
433 | udelay(500); | |
434 | ||
435 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
436 | tmp = RREG8(DAC_DATA); | |
437 | tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK; | |
438 | tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL; | |
fb70a669 | 439 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
440 | |
441 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
442 | tmp = RREG8(DAC_DATA); | |
443 | tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; | |
444 | tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; | |
fb70a669 | 445 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
446 | |
447 | vcount = RREG8(MGAREG_VCOUNT); | |
448 | ||
449 | for (j = 0; j < 30 && pll_locked == false; j++) { | |
450 | tmpcount = RREG8(MGAREG_VCOUNT); | |
451 | if (tmpcount < vcount) | |
452 | vcount = 0; | |
453 | if ((tmpcount - vcount) > 2) | |
454 | pll_locked = true; | |
455 | else | |
456 | udelay(5); | |
457 | } | |
458 | } | |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
463 | static int mga_g200er_set_plls(struct mga_device *mdev, long clock) | |
464 | { | |
465 | unsigned int vcomax, vcomin, pllreffreq; | |
466 | unsigned int delta, tmpdelta; | |
9830605d | 467 | int testr, testn, testm, testo; |
414c4531 | 468 | unsigned int p, m, n; |
9830605d | 469 | unsigned int computed, vco; |
414c4531 | 470 | int tmp; |
9830605d | 471 | const unsigned int m_div_val[] = { 1, 2, 4, 8 }; |
414c4531 DA |
472 | |
473 | m = n = p = 0; | |
474 | vcomax = 1488000; | |
475 | vcomin = 1056000; | |
476 | pllreffreq = 48000; | |
477 | ||
478 | delta = 0xffffffff; | |
479 | ||
480 | for (testr = 0; testr < 4; testr++) { | |
481 | if (delta == 0) | |
482 | break; | |
483 | for (testn = 5; testn < 129; testn++) { | |
484 | if (delta == 0) | |
485 | break; | |
486 | for (testm = 3; testm >= 0; testm--) { | |
487 | if (delta == 0) | |
488 | break; | |
489 | for (testo = 5; testo < 33; testo++) { | |
9830605d | 490 | vco = pllreffreq * (testn + 1) / |
414c4531 | 491 | (testr + 1); |
9830605d | 492 | if (vco < vcomin) |
414c4531 | 493 | continue; |
9830605d | 494 | if (vco > vcomax) |
414c4531 | 495 | continue; |
9830605d | 496 | computed = vco / (m_div_val[testm] * (testo + 1)); |
414c4531 DA |
497 | if (computed > clock) |
498 | tmpdelta = computed - clock; | |
499 | else | |
500 | tmpdelta = clock - computed; | |
501 | if (tmpdelta < delta) { | |
502 | delta = tmpdelta; | |
503 | m = testm | (testo << 3); | |
504 | n = testn; | |
505 | p = testr | (testr << 3); | |
506 | } | |
507 | } | |
508 | } | |
509 | } | |
510 | } | |
511 | ||
512 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
513 | tmp = RREG8(DAC_DATA); | |
514 | tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS; | |
fb70a669 | 515 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
516 | |
517 | WREG8(DAC_INDEX, MGA1064_REMHEADCTL); | |
518 | tmp = RREG8(DAC_DATA); | |
519 | tmp |= MGA1064_REMHEADCTL_CLKDIS; | |
fb70a669 | 520 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
521 | |
522 | tmp = RREG8(MGAREG_MEM_MISC_READ); | |
523 | tmp |= (0x3<<2) | 0xc0; | |
524 | WREG8(MGAREG_MEM_MISC_WRITE, tmp); | |
525 | ||
526 | WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL); | |
527 | tmp = RREG8(DAC_DATA); | |
528 | tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS; | |
529 | tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN; | |
fb70a669 | 530 | WREG8(DAC_DATA, tmp); |
414c4531 DA |
531 | |
532 | udelay(500); | |
533 | ||
534 | WREG_DAC(MGA1064_ER_PIX_PLLC_N, n); | |
535 | WREG_DAC(MGA1064_ER_PIX_PLLC_M, m); | |
536 | WREG_DAC(MGA1064_ER_PIX_PLLC_P, p); | |
537 | ||
538 | udelay(50); | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
543 | static int mga_crtc_set_plls(struct mga_device *mdev, long clock) | |
544 | { | |
545 | switch(mdev->type) { | |
546 | case G200_SE_A: | |
547 | case G200_SE_B: | |
548 | return mga_g200se_set_plls(mdev, clock); | |
549 | break; | |
550 | case G200_WB: | |
551 | return mga_g200wb_set_plls(mdev, clock); | |
552 | break; | |
553 | case G200_EV: | |
554 | return mga_g200ev_set_plls(mdev, clock); | |
555 | break; | |
556 | case G200_EH: | |
557 | return mga_g200eh_set_plls(mdev, clock); | |
558 | break; | |
559 | case G200_ER: | |
560 | return mga_g200er_set_plls(mdev, clock); | |
561 | break; | |
562 | } | |
563 | return 0; | |
564 | } | |
565 | ||
566 | static void mga_g200wb_prepare(struct drm_crtc *crtc) | |
567 | { | |
568 | struct mga_device *mdev = crtc->dev->dev_private; | |
569 | u8 tmp; | |
570 | int iter_max; | |
571 | ||
572 | /* 1- The first step is to warn the BMC of an upcoming mode change. | |
573 | * We are putting the misc<0> to output.*/ | |
574 | ||
575 | WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL); | |
576 | tmp = RREG8(DAC_DATA); | |
577 | tmp |= 0x10; | |
578 | WREG_DAC(MGA1064_GEN_IO_CTL, tmp); | |
579 | ||
580 | /* we are putting a 1 on the misc<0> line */ | |
581 | WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); | |
582 | tmp = RREG8(DAC_DATA); | |
583 | tmp |= 0x10; | |
584 | WREG_DAC(MGA1064_GEN_IO_DATA, tmp); | |
585 | ||
586 | /* 2- Second step to mask and further scan request | |
587 | * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>) | |
588 | */ | |
589 | WREG8(DAC_INDEX, MGA1064_SPAREREG); | |
590 | tmp = RREG8(DAC_DATA); | |
591 | tmp |= 0x80; | |
592 | WREG_DAC(MGA1064_SPAREREG, tmp); | |
593 | ||
594 | /* 3a- the third step is to verifu if there is an active scan | |
595 | * We are searching for a 0 on remhsyncsts <XSPAREREG<0>) | |
596 | */ | |
597 | iter_max = 300; | |
598 | while (!(tmp & 0x1) && iter_max) { | |
599 | WREG8(DAC_INDEX, MGA1064_SPAREREG); | |
600 | tmp = RREG8(DAC_DATA); | |
601 | udelay(1000); | |
602 | iter_max--; | |
603 | } | |
604 | ||
605 | /* 3b- this step occurs only if the remove is actually scanning | |
606 | * we are waiting for the end of the frame which is a 1 on | |
607 | * remvsyncsts (XSPAREREG<1>) | |
608 | */ | |
609 | if (iter_max) { | |
610 | iter_max = 300; | |
611 | while ((tmp & 0x2) && iter_max) { | |
612 | WREG8(DAC_INDEX, MGA1064_SPAREREG); | |
613 | tmp = RREG8(DAC_DATA); | |
614 | udelay(1000); | |
615 | iter_max--; | |
616 | } | |
617 | } | |
618 | } | |
619 | ||
620 | static void mga_g200wb_commit(struct drm_crtc *crtc) | |
621 | { | |
622 | u8 tmp; | |
623 | struct mga_device *mdev = crtc->dev->dev_private; | |
624 | ||
625 | /* 1- The first step is to ensure that the vrsten and hrsten are set */ | |
626 | WREG8(MGAREG_CRTCEXT_INDEX, 1); | |
627 | tmp = RREG8(MGAREG_CRTCEXT_DATA); | |
628 | WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88); | |
629 | ||
630 | /* 2- second step is to assert the rstlvl2 */ | |
631 | WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); | |
632 | tmp = RREG8(DAC_DATA); | |
633 | tmp |= 0x8; | |
634 | WREG8(DAC_DATA, tmp); | |
635 | ||
636 | /* wait 10 us */ | |
637 | udelay(10); | |
638 | ||
639 | /* 3- deassert rstlvl2 */ | |
640 | tmp &= ~0x08; | |
641 | WREG8(DAC_INDEX, MGA1064_REMHEADCTL2); | |
642 | WREG8(DAC_DATA, tmp); | |
643 | ||
644 | /* 4- remove mask of scan request */ | |
645 | WREG8(DAC_INDEX, MGA1064_SPAREREG); | |
646 | tmp = RREG8(DAC_DATA); | |
647 | tmp &= ~0x80; | |
648 | WREG8(DAC_DATA, tmp); | |
649 | ||
650 | /* 5- put back a 0 on the misc<0> line */ | |
651 | WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA); | |
652 | tmp = RREG8(DAC_DATA); | |
653 | tmp &= ~0x10; | |
654 | WREG_DAC(MGA1064_GEN_IO_DATA, tmp); | |
655 | } | |
656 | ||
9f1d0366 CH |
657 | /* |
658 | This is how the framebuffer base address is stored in g200 cards: | |
659 | * Assume @offset is the gpu_addr variable of the framebuffer object | |
660 | * Then addr is the number of _pixels_ (not bytes) from the start of | |
661 | VRAM to the first pixel we want to display. (divided by 2 for 32bit | |
662 | framebuffers) | |
663 | * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers | |
664 | addr<20> -> CRTCEXT0<6> | |
665 | addr<19-16> -> CRTCEXT0<3-0> | |
666 | addr<15-8> -> CRTCC<7-0> | |
667 | addr<7-0> -> CRTCD<7-0> | |
668 | CRTCEXT0 has to be programmed last to trigger an update and make the | |
669 | new addr variable take effect. | |
670 | */ | |
414c4531 DA |
671 | void mga_set_start_address(struct drm_crtc *crtc, unsigned offset) |
672 | { | |
673 | struct mga_device *mdev = crtc->dev->dev_private; | |
674 | u32 addr; | |
675 | int count; | |
9f1d0366 | 676 | u8 crtcext0; |
414c4531 DA |
677 | |
678 | while (RREG8(0x1fda) & 0x08); | |
679 | while (!(RREG8(0x1fda) & 0x08)); | |
680 | ||
681 | count = RREG8(MGAREG_VCOUNT) + 2; | |
682 | while (RREG8(MGAREG_VCOUNT) < count); | |
683 | ||
9f1d0366 CH |
684 | WREG8(MGAREG_CRTCEXT_INDEX, 0); |
685 | crtcext0 = RREG8(MGAREG_CRTCEXT_DATA); | |
686 | crtcext0 &= 0xB0; | |
687 | addr = offset / 8; | |
688 | /* Can't store addresses any higher than that... | |
689 | but we also don't have more than 16MB of memory, so it should be fine. */ | |
690 | WARN_ON(addr > 0x1fffff); | |
691 | crtcext0 |= (!!(addr & (1<<20)))<<6; | |
414c4531 DA |
692 | WREG_CRT(0x0d, (u8)(addr & 0xff)); |
693 | WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff); | |
9f1d0366 | 694 | WREG_ECRT(0x0, ((u8)(addr >> 16) & 0xf) | crtcext0); |
414c4531 DA |
695 | } |
696 | ||
697 | ||
698 | /* ast is different - we will force move buffers out of VRAM */ | |
699 | static int mga_crtc_do_set_base(struct drm_crtc *crtc, | |
700 | struct drm_framebuffer *fb, | |
701 | int x, int y, int atomic) | |
702 | { | |
703 | struct mga_device *mdev = crtc->dev->dev_private; | |
704 | struct drm_gem_object *obj; | |
705 | struct mga_framebuffer *mga_fb; | |
706 | struct mgag200_bo *bo; | |
707 | int ret; | |
708 | u64 gpu_addr; | |
709 | ||
710 | /* push the previous fb to system ram */ | |
711 | if (!atomic && fb) { | |
712 | mga_fb = to_mga_framebuffer(fb); | |
713 | obj = mga_fb->obj; | |
714 | bo = gem_to_mga_bo(obj); | |
715 | ret = mgag200_bo_reserve(bo, false); | |
716 | if (ret) | |
717 | return ret; | |
718 | mgag200_bo_push_sysram(bo); | |
719 | mgag200_bo_unreserve(bo); | |
720 | } | |
721 | ||
722 | mga_fb = to_mga_framebuffer(crtc->fb); | |
723 | obj = mga_fb->obj; | |
724 | bo = gem_to_mga_bo(obj); | |
725 | ||
726 | ret = mgag200_bo_reserve(bo, false); | |
727 | if (ret) | |
728 | return ret; | |
729 | ||
730 | ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr); | |
731 | if (ret) { | |
732 | mgag200_bo_unreserve(bo); | |
733 | return ret; | |
734 | } | |
735 | ||
736 | if (&mdev->mfbdev->mfb == mga_fb) { | |
737 | /* if pushing console in kmap it */ | |
738 | ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap); | |
739 | if (ret) | |
740 | DRM_ERROR("failed to kmap fbcon\n"); | |
741 | ||
742 | } | |
743 | mgag200_bo_unreserve(bo); | |
744 | ||
745 | DRM_INFO("mga base %llx\n", gpu_addr); | |
746 | ||
747 | mga_set_start_address(crtc, (u32)gpu_addr); | |
748 | ||
749 | return 0; | |
750 | } | |
751 | ||
752 | static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, | |
753 | struct drm_framebuffer *old_fb) | |
754 | { | |
755 | return mga_crtc_do_set_base(crtc, old_fb, x, y, 0); | |
756 | } | |
757 | ||
758 | static int mga_crtc_mode_set(struct drm_crtc *crtc, | |
759 | struct drm_display_mode *mode, | |
760 | struct drm_display_mode *adjusted_mode, | |
761 | int x, int y, struct drm_framebuffer *old_fb) | |
762 | { | |
763 | struct drm_device *dev = crtc->dev; | |
764 | struct mga_device *mdev = dev->dev_private; | |
765 | int hdisplay, hsyncstart, hsyncend, htotal; | |
766 | int vdisplay, vsyncstart, vsyncend, vtotal; | |
767 | int pitch; | |
768 | int option = 0, option2 = 0; | |
769 | int i; | |
770 | unsigned char misc = 0; | |
771 | unsigned char ext_vga[6]; | |
414c4531 DA |
772 | u8 bppshift; |
773 | ||
774 | static unsigned char dacvalue[] = { | |
775 | /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0, | |
776 | /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0, | |
777 | /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0, | |
778 | /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20, | |
779 | /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, | |
780 | /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40, | |
781 | /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83, | |
782 | /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A, | |
783 | /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0, | |
784 | /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0 | |
785 | }; | |
786 | ||
787 | bppshift = mdev->bpp_shifts[(crtc->fb->bits_per_pixel >> 3) - 1]; | |
788 | ||
789 | switch (mdev->type) { | |
790 | case G200_SE_A: | |
791 | case G200_SE_B: | |
792 | dacvalue[MGA1064_VREF_CTL] = 0x03; | |
793 | dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; | |
794 | dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN | | |
795 | MGA1064_MISC_CTL_VGA8 | | |
796 | MGA1064_MISC_CTL_DAC_RAM_CS; | |
797 | if (mdev->has_sdram) | |
798 | option = 0x40049120; | |
799 | else | |
800 | option = 0x4004d120; | |
801 | option2 = 0x00008000; | |
802 | break; | |
803 | case G200_WB: | |
804 | dacvalue[MGA1064_VREF_CTL] = 0x07; | |
805 | option = 0x41049120; | |
806 | option2 = 0x0000b000; | |
807 | break; | |
808 | case G200_EV: | |
809 | dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL; | |
810 | dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | | |
811 | MGA1064_MISC_CTL_DAC_RAM_CS; | |
812 | option = 0x00000120; | |
813 | option2 = 0x0000b000; | |
814 | break; | |
815 | case G200_EH: | |
816 | dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 | | |
817 | MGA1064_MISC_CTL_DAC_RAM_CS; | |
818 | option = 0x00000120; | |
819 | option2 = 0x0000b000; | |
820 | break; | |
821 | case G200_ER: | |
414c4531 DA |
822 | break; |
823 | } | |
824 | ||
825 | switch (crtc->fb->bits_per_pixel) { | |
826 | case 8: | |
827 | dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits; | |
828 | break; | |
829 | case 16: | |
830 | if (crtc->fb->depth == 15) | |
831 | dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits; | |
832 | else | |
833 | dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits; | |
834 | break; | |
835 | case 24: | |
836 | dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits; | |
837 | break; | |
838 | case 32: | |
839 | dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits; | |
840 | break; | |
841 | } | |
842 | ||
843 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) | |
844 | misc |= 0x40; | |
845 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
846 | misc |= 0x80; | |
847 | ||
848 | ||
849 | for (i = 0; i < sizeof(dacvalue); i++) { | |
9d8aa55f | 850 | if ((i <= 0x17) || |
414c4531 DA |
851 | (i == 0x1b) || |
852 | (i == 0x1c) || | |
853 | ((i >= 0x1f) && (i <= 0x29)) || | |
854 | ((i >= 0x30) && (i <= 0x37))) | |
855 | continue; | |
856 | if (IS_G200_SE(mdev) && | |
857 | ((i == 0x2c) || (i == 0x2d) || (i == 0x2e))) | |
858 | continue; | |
859 | if ((mdev->type == G200_EV || mdev->type == G200_WB || mdev->type == G200_EH) && | |
860 | (i >= 0x44) && (i <= 0x4e)) | |
861 | continue; | |
862 | ||
863 | WREG_DAC(i, dacvalue[i]); | |
864 | } | |
865 | ||
1812a3db CH |
866 | if (mdev->type == G200_ER) |
867 | WREG_DAC(0x90, 0); | |
414c4531 DA |
868 | |
869 | if (option) | |
870 | pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option); | |
871 | if (option2) | |
872 | pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2); | |
873 | ||
874 | WREG_SEQ(2, 0xf); | |
875 | WREG_SEQ(3, 0); | |
876 | WREG_SEQ(4, 0xe); | |
877 | ||
878 | pitch = crtc->fb->pitches[0] / (crtc->fb->bits_per_pixel / 8); | |
879 | if (crtc->fb->bits_per_pixel == 24) | |
880 | pitch = pitch >> (4 - bppshift); | |
881 | else | |
882 | pitch = pitch >> (4 - bppshift); | |
883 | ||
884 | hdisplay = mode->hdisplay / 8 - 1; | |
885 | hsyncstart = mode->hsync_start / 8 - 1; | |
886 | hsyncend = mode->hsync_end / 8 - 1; | |
887 | htotal = mode->htotal / 8 - 1; | |
888 | ||
889 | /* Work around hardware quirk */ | |
890 | if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04) | |
891 | htotal++; | |
892 | ||
893 | vdisplay = mode->vdisplay - 1; | |
894 | vsyncstart = mode->vsync_start - 1; | |
895 | vsyncend = mode->vsync_end - 1; | |
896 | vtotal = mode->vtotal - 2; | |
897 | ||
898 | WREG_GFX(0, 0); | |
899 | WREG_GFX(1, 0); | |
900 | WREG_GFX(2, 0); | |
901 | WREG_GFX(3, 0); | |
902 | WREG_GFX(4, 0); | |
903 | WREG_GFX(5, 0x40); | |
904 | WREG_GFX(6, 0x5); | |
905 | WREG_GFX(7, 0xf); | |
906 | WREG_GFX(8, 0xf); | |
907 | ||
908 | WREG_CRT(0, htotal - 4); | |
909 | WREG_CRT(1, hdisplay); | |
910 | WREG_CRT(2, hdisplay); | |
911 | WREG_CRT(3, (htotal & 0x1F) | 0x80); | |
912 | WREG_CRT(4, hsyncstart); | |
913 | WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F)); | |
914 | WREG_CRT(6, vtotal & 0xFF); | |
915 | WREG_CRT(7, ((vtotal & 0x100) >> 8) | | |
916 | ((vdisplay & 0x100) >> 7) | | |
917 | ((vsyncstart & 0x100) >> 6) | | |
918 | ((vdisplay & 0x100) >> 5) | | |
919 | ((vdisplay & 0x100) >> 4) | /* linecomp */ | |
920 | ((vtotal & 0x200) >> 4)| | |
921 | ((vdisplay & 0x200) >> 3) | | |
922 | ((vsyncstart & 0x200) >> 2)); | |
923 | WREG_CRT(9, ((vdisplay & 0x200) >> 4) | | |
924 | ((vdisplay & 0x200) >> 3)); | |
925 | WREG_CRT(10, 0); | |
926 | WREG_CRT(11, 0); | |
927 | WREG_CRT(12, 0); | |
928 | WREG_CRT(13, 0); | |
929 | WREG_CRT(14, 0); | |
930 | WREG_CRT(15, 0); | |
931 | WREG_CRT(16, vsyncstart & 0xFF); | |
932 | WREG_CRT(17, (vsyncend & 0x0F) | 0x20); | |
933 | WREG_CRT(18, vdisplay & 0xFF); | |
934 | WREG_CRT(19, pitch & 0xFF); | |
935 | WREG_CRT(20, 0); | |
936 | WREG_CRT(21, vdisplay & 0xFF); | |
937 | WREG_CRT(22, (vtotal + 1) & 0xFF); | |
938 | WREG_CRT(23, 0xc3); | |
939 | WREG_CRT(24, vdisplay & 0xFF); | |
940 | ||
941 | ext_vga[0] = 0; | |
942 | ext_vga[5] = 0; | |
943 | ||
944 | /* TODO interlace */ | |
945 | ||
946 | ext_vga[0] |= (pitch & 0x300) >> 4; | |
947 | ext_vga[1] = (((htotal - 4) & 0x100) >> 8) | | |
948 | ((hdisplay & 0x100) >> 7) | | |
949 | ((hsyncstart & 0x100) >> 6) | | |
950 | (htotal & 0x40); | |
951 | ext_vga[2] = ((vtotal & 0xc00) >> 10) | | |
952 | ((vdisplay & 0x400) >> 8) | | |
953 | ((vdisplay & 0xc00) >> 7) | | |
954 | ((vsyncstart & 0xc00) >> 5) | | |
955 | ((vdisplay & 0x400) >> 3); | |
956 | if (crtc->fb->bits_per_pixel == 24) | |
957 | ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80; | |
958 | else | |
959 | ext_vga[3] = ((1 << bppshift) - 1) | 0x80; | |
960 | ext_vga[4] = 0; | |
961 | if (mdev->type == G200_WB) | |
962 | ext_vga[1] |= 0x88; | |
963 | ||
414c4531 DA |
964 | /* Set pixel clocks */ |
965 | misc = 0x2d; | |
966 | WREG8(MGA_MISC_OUT, misc); | |
967 | ||
968 | mga_crtc_set_plls(mdev, mode->clock); | |
969 | ||
970 | for (i = 0; i < 6; i++) { | |
971 | WREG_ECRT(i, ext_vga[i]); | |
972 | } | |
973 | ||
974 | if (mdev->type == G200_ER) | |
1812a3db | 975 | WREG_ECRT(0x24, 0x5); |
414c4531 DA |
976 | |
977 | if (mdev->type == G200_EV) { | |
978 | WREG_ECRT(6, 0); | |
979 | } | |
980 | ||
981 | WREG_ECRT(0, ext_vga[0]); | |
982 | /* Enable mga pixel clock */ | |
983 | misc = 0x2d; | |
984 | ||
985 | WREG8(MGA_MISC_OUT, misc); | |
986 | ||
987 | if (adjusted_mode) | |
988 | memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode)); | |
989 | ||
990 | mga_crtc_do_set_base(crtc, old_fb, x, y, 0); | |
991 | ||
992 | /* reset tagfifo */ | |
993 | if (mdev->type == G200_ER) { | |
994 | u32 mem_ctl = RREG32(MGAREG_MEMCTL); | |
995 | u8 seq1; | |
996 | ||
997 | /* screen off */ | |
998 | WREG8(MGAREG_SEQ_INDEX, 0x01); | |
999 | seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20; | |
1000 | WREG8(MGAREG_SEQ_DATA, seq1); | |
1001 | ||
1002 | WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000); | |
1003 | udelay(1000); | |
1004 | WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000); | |
1005 | ||
1006 | WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20); | |
1007 | } | |
1008 | ||
1009 | ||
1010 | if (IS_G200_SE(mdev)) { | |
1011 | if (mdev->reg_1e24 >= 0x02) { | |
1012 | u8 hi_pri_lvl; | |
1013 | u32 bpp; | |
1014 | u32 mb; | |
1015 | ||
1016 | if (crtc->fb->bits_per_pixel > 16) | |
1017 | bpp = 32; | |
1018 | else if (crtc->fb->bits_per_pixel > 8) | |
1019 | bpp = 16; | |
1020 | else | |
1021 | bpp = 8; | |
1022 | ||
1023 | mb = (mode->clock * bpp) / 1000; | |
1024 | if (mb > 3100) | |
1025 | hi_pri_lvl = 0; | |
1026 | else if (mb > 2600) | |
1027 | hi_pri_lvl = 1; | |
1028 | else if (mb > 1900) | |
1029 | hi_pri_lvl = 2; | |
1030 | else if (mb > 1160) | |
1031 | hi_pri_lvl = 3; | |
1032 | else if (mb > 440) | |
1033 | hi_pri_lvl = 4; | |
1034 | else | |
1035 | hi_pri_lvl = 5; | |
1036 | ||
91f8f105 CH |
1037 | WREG8(MGAREG_CRTCEXT_INDEX, 0x06); |
1038 | WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl); | |
414c4531 | 1039 | } else { |
91f8f105 | 1040 | WREG8(MGAREG_CRTCEXT_INDEX, 0x06); |
414c4531 | 1041 | if (mdev->reg_1e24 >= 0x01) |
91f8f105 | 1042 | WREG8(MGAREG_CRTCEXT_DATA, 0x03); |
414c4531 | 1043 | else |
91f8f105 | 1044 | WREG8(MGAREG_CRTCEXT_DATA, 0x04); |
414c4531 DA |
1045 | } |
1046 | } | |
1047 | return 0; | |
1048 | } | |
1049 | ||
1050 | #if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */ | |
1051 | static int mga_suspend(struct drm_crtc *crtc) | |
1052 | { | |
1053 | struct mga_crtc *mga_crtc = to_mga_crtc(crtc); | |
1054 | struct drm_device *dev = crtc->dev; | |
1055 | struct mga_device *mdev = dev->dev_private; | |
1056 | struct pci_dev *pdev = dev->pdev; | |
1057 | int option; | |
1058 | ||
1059 | if (mdev->suspended) | |
1060 | return 0; | |
1061 | ||
1062 | WREG_SEQ(1, 0x20); | |
1063 | WREG_ECRT(1, 0x30); | |
1064 | /* Disable the pixel clock */ | |
1065 | WREG_DAC(0x1a, 0x05); | |
1066 | /* Power down the DAC */ | |
1067 | WREG_DAC(0x1e, 0x18); | |
1068 | /* Power down the pixel PLL */ | |
1069 | WREG_DAC(0x1a, 0x0d); | |
1070 | ||
1071 | /* Disable PLLs and clocks */ | |
1072 | pci_read_config_dword(pdev, PCI_MGA_OPTION, &option); | |
1073 | option &= ~(0x1F8024); | |
1074 | pci_write_config_dword(pdev, PCI_MGA_OPTION, option); | |
1075 | pci_set_power_state(pdev, PCI_D3hot); | |
1076 | pci_disable_device(pdev); | |
1077 | ||
1078 | mdev->suspended = true; | |
1079 | ||
1080 | return 0; | |
1081 | } | |
1082 | ||
1083 | static int mga_resume(struct drm_crtc *crtc) | |
1084 | { | |
1085 | struct mga_crtc *mga_crtc = to_mga_crtc(crtc); | |
1086 | struct drm_device *dev = crtc->dev; | |
1087 | struct mga_device *mdev = dev->dev_private; | |
1088 | struct pci_dev *pdev = dev->pdev; | |
1089 | int option; | |
1090 | ||
1091 | if (!mdev->suspended) | |
1092 | return 0; | |
1093 | ||
1094 | pci_set_power_state(pdev, PCI_D0); | |
1095 | pci_enable_device(pdev); | |
1096 | ||
1097 | /* Disable sysclk */ | |
1098 | pci_read_config_dword(pdev, PCI_MGA_OPTION, &option); | |
1099 | option &= ~(0x4); | |
1100 | pci_write_config_dword(pdev, PCI_MGA_OPTION, option); | |
1101 | ||
1102 | mdev->suspended = false; | |
1103 | ||
1104 | return 0; | |
1105 | } | |
1106 | ||
1107 | #endif | |
1108 | ||
1109 | static void mga_crtc_dpms(struct drm_crtc *crtc, int mode) | |
1110 | { | |
1111 | struct drm_device *dev = crtc->dev; | |
1112 | struct mga_device *mdev = dev->dev_private; | |
1113 | u8 seq1 = 0, crtcext1 = 0; | |
1114 | ||
1115 | switch (mode) { | |
1116 | case DRM_MODE_DPMS_ON: | |
1117 | seq1 = 0; | |
1118 | crtcext1 = 0; | |
1119 | mga_crtc_load_lut(crtc); | |
1120 | break; | |
1121 | case DRM_MODE_DPMS_STANDBY: | |
1122 | seq1 = 0x20; | |
1123 | crtcext1 = 0x10; | |
1124 | break; | |
1125 | case DRM_MODE_DPMS_SUSPEND: | |
1126 | seq1 = 0x20; | |
1127 | crtcext1 = 0x20; | |
1128 | break; | |
1129 | case DRM_MODE_DPMS_OFF: | |
1130 | seq1 = 0x20; | |
1131 | crtcext1 = 0x30; | |
1132 | break; | |
1133 | } | |
1134 | ||
1135 | #if 0 | |
1136 | if (mode == DRM_MODE_DPMS_OFF) { | |
1137 | mga_suspend(crtc); | |
1138 | } | |
1139 | #endif | |
1140 | WREG8(MGAREG_SEQ_INDEX, 0x01); | |
1141 | seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20; | |
1142 | mga_wait_vsync(mdev); | |
1143 | mga_wait_busy(mdev); | |
1144 | WREG8(MGAREG_SEQ_DATA, seq1); | |
1145 | msleep(20); | |
1146 | WREG8(MGAREG_CRTCEXT_INDEX, 0x01); | |
1147 | crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30; | |
1148 | WREG8(MGAREG_CRTCEXT_DATA, crtcext1); | |
1149 | ||
1150 | #if 0 | |
1151 | if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) { | |
1152 | mga_resume(crtc); | |
1153 | drm_helper_resume_force_mode(dev); | |
1154 | } | |
1155 | #endif | |
1156 | } | |
1157 | ||
1158 | /* | |
1159 | * This is called before a mode is programmed. A typical use might be to | |
1160 | * enable DPMS during the programming to avoid seeing intermediate stages, | |
1161 | * but that's not relevant to us | |
1162 | */ | |
1163 | static void mga_crtc_prepare(struct drm_crtc *crtc) | |
1164 | { | |
1165 | struct drm_device *dev = crtc->dev; | |
1166 | struct mga_device *mdev = dev->dev_private; | |
1167 | u8 tmp; | |
1168 | ||
1169 | /* mga_resume(crtc);*/ | |
1170 | ||
1171 | WREG8(MGAREG_CRTC_INDEX, 0x11); | |
1172 | tmp = RREG8(MGAREG_CRTC_DATA); | |
1173 | WREG_CRT(0x11, tmp | 0x80); | |
1174 | ||
1175 | if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) { | |
1176 | WREG_SEQ(0, 1); | |
1177 | msleep(50); | |
1178 | WREG_SEQ(1, 0x20); | |
1179 | msleep(20); | |
1180 | } else { | |
1181 | WREG8(MGAREG_SEQ_INDEX, 0x1); | |
1182 | tmp = RREG8(MGAREG_SEQ_DATA); | |
1183 | ||
1184 | /* start sync reset */ | |
1185 | WREG_SEQ(0, 1); | |
1186 | WREG_SEQ(1, tmp | 0x20); | |
1187 | } | |
1188 | ||
1189 | if (mdev->type == G200_WB) | |
1190 | mga_g200wb_prepare(crtc); | |
1191 | ||
1192 | WREG_CRT(17, 0); | |
1193 | } | |
1194 | ||
1195 | /* | |
1196 | * This is called after a mode is programmed. It should reverse anything done | |
1197 | * by the prepare function | |
1198 | */ | |
1199 | static void mga_crtc_commit(struct drm_crtc *crtc) | |
1200 | { | |
1201 | struct drm_device *dev = crtc->dev; | |
1202 | struct mga_device *mdev = dev->dev_private; | |
1203 | struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private; | |
1204 | u8 tmp; | |
1205 | ||
1206 | if (mdev->type == G200_WB) | |
1207 | mga_g200wb_commit(crtc); | |
1208 | ||
1209 | if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) { | |
1210 | msleep(50); | |
1211 | WREG_SEQ(1, 0x0); | |
1212 | msleep(20); | |
1213 | WREG_SEQ(0, 0x3); | |
1214 | } else { | |
1215 | WREG8(MGAREG_SEQ_INDEX, 0x1); | |
1216 | tmp = RREG8(MGAREG_SEQ_DATA); | |
1217 | ||
1218 | tmp &= ~0x20; | |
1219 | WREG_SEQ(0x1, tmp); | |
1220 | WREG_SEQ(0, 3); | |
1221 | } | |
1222 | crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON); | |
1223 | } | |
1224 | ||
1225 | /* | |
1226 | * The core can pass us a set of gamma values to program. We actually only | |
1227 | * use this for 8-bit mode so can't perform smooth fades on deeper modes, | |
1228 | * but it's a requirement that we provide the function | |
1229 | */ | |
1230 | static void mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, | |
1231 | u16 *blue, uint32_t start, uint32_t size) | |
1232 | { | |
1233 | struct mga_crtc *mga_crtc = to_mga_crtc(crtc); | |
1234 | int end = (start + size > MGAG200_LUT_SIZE) ? MGAG200_LUT_SIZE : start + size; | |
1235 | int i; | |
1236 | ||
1237 | for (i = start; i < end; i++) { | |
1238 | mga_crtc->lut_r[i] = red[i] >> 8; | |
1239 | mga_crtc->lut_g[i] = green[i] >> 8; | |
1240 | mga_crtc->lut_b[i] = blue[i] >> 8; | |
1241 | } | |
1242 | mga_crtc_load_lut(crtc); | |
1243 | } | |
1244 | ||
1245 | /* Simple cleanup function */ | |
1246 | static void mga_crtc_destroy(struct drm_crtc *crtc) | |
1247 | { | |
1248 | struct mga_crtc *mga_crtc = to_mga_crtc(crtc); | |
1249 | ||
1250 | drm_crtc_cleanup(crtc); | |
1251 | kfree(mga_crtc); | |
1252 | } | |
1253 | ||
1254 | /* These provide the minimum set of functions required to handle a CRTC */ | |
1255 | static const struct drm_crtc_funcs mga_crtc_funcs = { | |
a080db9f CH |
1256 | .cursor_set = mga_crtc_cursor_set, |
1257 | .cursor_move = mga_crtc_cursor_move, | |
414c4531 DA |
1258 | .gamma_set = mga_crtc_gamma_set, |
1259 | .set_config = drm_crtc_helper_set_config, | |
1260 | .destroy = mga_crtc_destroy, | |
1261 | }; | |
1262 | ||
1263 | static const struct drm_crtc_helper_funcs mga_helper_funcs = { | |
1264 | .dpms = mga_crtc_dpms, | |
1265 | .mode_fixup = mga_crtc_mode_fixup, | |
1266 | .mode_set = mga_crtc_mode_set, | |
1267 | .mode_set_base = mga_crtc_mode_set_base, | |
1268 | .prepare = mga_crtc_prepare, | |
1269 | .commit = mga_crtc_commit, | |
1270 | .load_lut = mga_crtc_load_lut, | |
1271 | }; | |
1272 | ||
1273 | /* CRTC setup */ | |
f1998fe2 | 1274 | static void mga_crtc_init(struct mga_device *mdev) |
414c4531 | 1275 | { |
414c4531 DA |
1276 | struct mga_crtc *mga_crtc; |
1277 | int i; | |
1278 | ||
1279 | mga_crtc = kzalloc(sizeof(struct mga_crtc) + | |
1280 | (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)), | |
1281 | GFP_KERNEL); | |
1282 | ||
1283 | if (mga_crtc == NULL) | |
1284 | return; | |
1285 | ||
f1998fe2 | 1286 | drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs); |
414c4531 DA |
1287 | |
1288 | drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE); | |
1289 | mdev->mode_info.crtc = mga_crtc; | |
1290 | ||
1291 | for (i = 0; i < MGAG200_LUT_SIZE; i++) { | |
1292 | mga_crtc->lut_r[i] = i; | |
1293 | mga_crtc->lut_g[i] = i; | |
1294 | mga_crtc->lut_b[i] = i; | |
1295 | } | |
1296 | ||
1297 | drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs); | |
1298 | } | |
1299 | ||
1300 | /** Sets the color ramps on behalf of fbcon */ | |
1301 | void mga_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green, | |
1302 | u16 blue, int regno) | |
1303 | { | |
1304 | struct mga_crtc *mga_crtc = to_mga_crtc(crtc); | |
1305 | ||
1306 | mga_crtc->lut_r[regno] = red >> 8; | |
1307 | mga_crtc->lut_g[regno] = green >> 8; | |
1308 | mga_crtc->lut_b[regno] = blue >> 8; | |
1309 | } | |
1310 | ||
1311 | /** Gets the color ramps on behalf of fbcon */ | |
1312 | void mga_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green, | |
1313 | u16 *blue, int regno) | |
1314 | { | |
1315 | struct mga_crtc *mga_crtc = to_mga_crtc(crtc); | |
1316 | ||
1317 | *red = (u16)mga_crtc->lut_r[regno] << 8; | |
1318 | *green = (u16)mga_crtc->lut_g[regno] << 8; | |
1319 | *blue = (u16)mga_crtc->lut_b[regno] << 8; | |
1320 | } | |
1321 | ||
1322 | /* | |
1323 | * The encoder comes after the CRTC in the output pipeline, but before | |
1324 | * the connector. It's responsible for ensuring that the digital | |
1325 | * stream is appropriately converted into the output format. Setup is | |
1326 | * very simple in this case - all we have to do is inform qemu of the | |
1327 | * colour depth in order to ensure that it displays appropriately | |
1328 | */ | |
1329 | ||
1330 | /* | |
1331 | * These functions are analagous to those in the CRTC code, but are intended | |
1332 | * to handle any encoder-specific limitations | |
1333 | */ | |
1334 | static bool mga_encoder_mode_fixup(struct drm_encoder *encoder, | |
e811f5ae LP |
1335 | const struct drm_display_mode *mode, |
1336 | struct drm_display_mode *adjusted_mode) | |
414c4531 DA |
1337 | { |
1338 | return true; | |
1339 | } | |
1340 | ||
1341 | static void mga_encoder_mode_set(struct drm_encoder *encoder, | |
1342 | struct drm_display_mode *mode, | |
1343 | struct drm_display_mode *adjusted_mode) | |
1344 | { | |
1345 | ||
1346 | } | |
1347 | ||
1348 | static void mga_encoder_dpms(struct drm_encoder *encoder, int state) | |
1349 | { | |
1350 | return; | |
1351 | } | |
1352 | ||
1353 | static void mga_encoder_prepare(struct drm_encoder *encoder) | |
1354 | { | |
1355 | } | |
1356 | ||
1357 | static void mga_encoder_commit(struct drm_encoder *encoder) | |
1358 | { | |
1359 | } | |
1360 | ||
1361 | void mga_encoder_destroy(struct drm_encoder *encoder) | |
1362 | { | |
1363 | struct mga_encoder *mga_encoder = to_mga_encoder(encoder); | |
1364 | drm_encoder_cleanup(encoder); | |
1365 | kfree(mga_encoder); | |
1366 | } | |
1367 | ||
1368 | static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = { | |
1369 | .dpms = mga_encoder_dpms, | |
1370 | .mode_fixup = mga_encoder_mode_fixup, | |
1371 | .mode_set = mga_encoder_mode_set, | |
1372 | .prepare = mga_encoder_prepare, | |
1373 | .commit = mga_encoder_commit, | |
1374 | }; | |
1375 | ||
1376 | static const struct drm_encoder_funcs mga_encoder_encoder_funcs = { | |
1377 | .destroy = mga_encoder_destroy, | |
1378 | }; | |
1379 | ||
1380 | static struct drm_encoder *mga_encoder_init(struct drm_device *dev) | |
1381 | { | |
1382 | struct drm_encoder *encoder; | |
1383 | struct mga_encoder *mga_encoder; | |
1384 | ||
1385 | mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL); | |
1386 | if (!mga_encoder) | |
1387 | return NULL; | |
1388 | ||
1389 | encoder = &mga_encoder->base; | |
1390 | encoder->possible_crtcs = 0x1; | |
1391 | ||
1392 | drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs, | |
1393 | DRM_MODE_ENCODER_DAC); | |
1394 | drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs); | |
1395 | ||
1396 | return encoder; | |
1397 | } | |
1398 | ||
1399 | ||
1400 | static int mga_vga_get_modes(struct drm_connector *connector) | |
1401 | { | |
1402 | struct mga_connector *mga_connector = to_mga_connector(connector); | |
1403 | struct edid *edid; | |
1404 | int ret = 0; | |
1405 | ||
1406 | edid = drm_get_edid(connector, &mga_connector->i2c->adapter); | |
1407 | if (edid) { | |
1408 | drm_mode_connector_update_edid_property(connector, edid); | |
1409 | ret = drm_add_edid_modes(connector, edid); | |
414c4531 DA |
1410 | kfree(edid); |
1411 | } | |
1412 | return ret; | |
1413 | } | |
1414 | ||
1415 | static int mga_vga_mode_valid(struct drm_connector *connector, | |
1416 | struct drm_display_mode *mode) | |
1417 | { | |
0ba53171 CH |
1418 | struct drm_device *dev = connector->dev; |
1419 | struct mga_device *mdev = (struct mga_device*)dev->dev_private; | |
1420 | struct mga_fbdev *mfbdev = mdev->mfbdev; | |
1421 | struct drm_fb_helper *fb_helper = &mfbdev->helper; | |
1422 | struct drm_fb_helper_connector *fb_helper_conn = NULL; | |
1423 | int bpp = 32; | |
1424 | int i = 0; | |
1425 | ||
414c4531 DA |
1426 | /* FIXME: Add bandwidth and g200se limitations */ |
1427 | ||
1428 | if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 || | |
1429 | mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 || | |
1430 | mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 || | |
1431 | mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) { | |
1432 | return MODE_BAD; | |
1433 | } | |
1434 | ||
0ba53171 CH |
1435 | /* Validate the mode input by the user */ |
1436 | for (i = 0; i < fb_helper->connector_count; i++) { | |
1437 | if (fb_helper->connector_info[i]->connector == connector) { | |
1438 | /* Found the helper for this connector */ | |
1439 | fb_helper_conn = fb_helper->connector_info[i]; | |
1440 | if (fb_helper_conn->cmdline_mode.specified) { | |
1441 | if (fb_helper_conn->cmdline_mode.bpp_specified) { | |
1442 | bpp = fb_helper_conn->cmdline_mode.bpp; | |
1443 | } | |
1444 | } | |
1445 | } | |
1446 | } | |
1447 | ||
1448 | if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) { | |
1449 | if (fb_helper_conn) | |
1450 | fb_helper_conn->cmdline_mode.specified = false; | |
1451 | return MODE_BAD; | |
1452 | } | |
1453 | ||
414c4531 DA |
1454 | return MODE_OK; |
1455 | } | |
1456 | ||
1457 | struct drm_encoder *mga_connector_best_encoder(struct drm_connector | |
1458 | *connector) | |
1459 | { | |
1460 | int enc_id = connector->encoder_ids[0]; | |
1461 | struct drm_mode_object *obj; | |
1462 | struct drm_encoder *encoder; | |
1463 | ||
1464 | /* pick the encoder ids */ | |
1465 | if (enc_id) { | |
1466 | obj = | |
1467 | drm_mode_object_find(connector->dev, enc_id, | |
1468 | DRM_MODE_OBJECT_ENCODER); | |
1469 | if (!obj) | |
1470 | return NULL; | |
1471 | encoder = obj_to_encoder(obj); | |
1472 | return encoder; | |
1473 | } | |
1474 | return NULL; | |
1475 | } | |
1476 | ||
1477 | static enum drm_connector_status mga_vga_detect(struct drm_connector | |
1478 | *connector, bool force) | |
1479 | { | |
1480 | return connector_status_connected; | |
1481 | } | |
1482 | ||
1483 | static void mga_connector_destroy(struct drm_connector *connector) | |
1484 | { | |
1485 | struct mga_connector *mga_connector = to_mga_connector(connector); | |
1486 | mgag200_i2c_destroy(mga_connector->i2c); | |
1487 | drm_connector_cleanup(connector); | |
1488 | kfree(connector); | |
1489 | } | |
1490 | ||
1491 | struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = { | |
1492 | .get_modes = mga_vga_get_modes, | |
1493 | .mode_valid = mga_vga_mode_valid, | |
1494 | .best_encoder = mga_connector_best_encoder, | |
1495 | }; | |
1496 | ||
1497 | struct drm_connector_funcs mga_vga_connector_funcs = { | |
1498 | .dpms = drm_helper_connector_dpms, | |
1499 | .detect = mga_vga_detect, | |
1500 | .fill_modes = drm_helper_probe_single_connector_modes, | |
1501 | .destroy = mga_connector_destroy, | |
1502 | }; | |
1503 | ||
1504 | static struct drm_connector *mga_vga_init(struct drm_device *dev) | |
1505 | { | |
1506 | struct drm_connector *connector; | |
1507 | struct mga_connector *mga_connector; | |
1508 | ||
1509 | mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL); | |
1510 | if (!mga_connector) | |
1511 | return NULL; | |
1512 | ||
1513 | connector = &mga_connector->base; | |
1514 | ||
1515 | drm_connector_init(dev, connector, | |
1516 | &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA); | |
1517 | ||
1518 | drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs); | |
1519 | ||
1520 | mga_connector->i2c = mgag200_i2c_create(dev); | |
1521 | if (!mga_connector->i2c) | |
1522 | DRM_ERROR("failed to add ddc bus\n"); | |
1523 | ||
1524 | return connector; | |
1525 | } | |
1526 | ||
1527 | ||
1528 | int mgag200_modeset_init(struct mga_device *mdev) | |
1529 | { | |
1530 | struct drm_encoder *encoder; | |
1531 | struct drm_connector *connector; | |
1532 | int ret; | |
1533 | ||
1534 | mdev->mode_info.mode_config_initialized = true; | |
1535 | ||
1536 | mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH; | |
1537 | mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT; | |
1538 | ||
1539 | mdev->dev->mode_config.fb_base = mdev->mc.vram_base; | |
1540 | ||
f1998fe2 | 1541 | mga_crtc_init(mdev); |
414c4531 DA |
1542 | |
1543 | encoder = mga_encoder_init(mdev->dev); | |
1544 | if (!encoder) { | |
1545 | DRM_ERROR("mga_encoder_init failed\n"); | |
1546 | return -1; | |
1547 | } | |
1548 | ||
1549 | connector = mga_vga_init(mdev->dev); | |
1550 | if (!connector) { | |
1551 | DRM_ERROR("mga_vga_init failed\n"); | |
1552 | return -1; | |
1553 | } | |
1554 | ||
1555 | drm_mode_connector_attach_encoder(connector, encoder); | |
1556 | ||
1557 | ret = mgag200_fbdev_init(mdev); | |
1558 | if (ret) { | |
1559 | DRM_ERROR("mga_fbdev_init failed\n"); | |
1560 | return ret; | |
1561 | } | |
1562 | ||
1563 | return 0; | |
1564 | } | |
1565 | ||
1566 | void mgag200_modeset_fini(struct mga_device *mdev) | |
1567 | { | |
1568 | ||
1569 | } |