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drm/mgag200: Added support for the new device G200eH3
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / mgag200 / mgag200_mode.c
CommitLineData
414c4531
DA		 1/*
2 * Copyright 2010 Matt Turner.
3 * Copyright 2012 Red Hat
4 *
5 * This file is subject to the terms and conditions of the GNU General
6 * Public License version 2. See the file COPYING in the main
7 * directory of this archive for more details.
8 *
9 * Authors: Matthew Garrett
10 * Matt Turner
11 * Dave Airlie
12 */
13
14#include <linux/delay.h>
15
760285e7
DH		 16#include <drm/drmP.h>
17#include <drm/drm_crtc_helper.h>
3cb9ae4f 18#include <drm/drm_plane_helper.h>
414c4531
DA		 19
20#include "mgag200_drv.h"
21
22#define MGAG200_LUT_SIZE 256
23
24/*
25 * This file contains setup code for the CRTC.
26 */
27
28static void mga_crtc_load_lut(struct drm_crtc *crtc)
29{
30 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
31 struct drm_device *dev = crtc->dev;
32 struct mga_device *mdev = dev->dev_private;
f4510a27 33 struct drm_framebuffer *fb = crtc->primary->fb;
414c4531
DA		 34 int i;
35
36 if (!crtc->enabled)
37 return;
38
39 WREG8(DAC_INDEX + MGA1064_INDEX, 0);
40
de7500ea
EE		 41 if (fb && fb->bits_per_pixel == 16) {
42 int inc = (fb->depth == 15) ? 8 : 4;
43 u8 r, b;
44 for (i = 0; i < MGAG200_LUT_SIZE; i += inc) {
45 if (fb->depth == 16) {
46 if (i > (MGAG200_LUT_SIZE >> 1)) {
47 r = b = 0;
48 } else {
49 r = mga_crtc->lut_r[i << 1];
50 b = mga_crtc->lut_b[i << 1];
51 }
52 } else {
53 r = mga_crtc->lut_r[i];
54 b = mga_crtc->lut_b[i];
55 }
56 /* VGA registers */
57 WREG8(DAC_INDEX + MGA1064_COL_PAL, r);
58 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
59 WREG8(DAC_INDEX + MGA1064_COL_PAL, b);
60 }
61 return;
62 }
414c4531
DA		 63 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
64 /* VGA registers */
65 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_r[i]);
66 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_g[i]);
67 WREG8(DAC_INDEX + MGA1064_COL_PAL, mga_crtc->lut_b[i]);
68 }
69}
70
71static inline void mga_wait_vsync(struct mga_device *mdev)
72{
3cdc0e8d 73 unsigned long timeout = jiffies + HZ/10;
414c4531
DA		 74 unsigned int status = 0;
75
76 do {
77 status = RREG32(MGAREG_Status);
3cdc0e8d
CH		 78 } while ((status & 0x08) && time_before(jiffies, timeout));
79 timeout = jiffies + HZ/10;
414c4531
DA		 80 status = 0;
81 do {
82 status = RREG32(MGAREG_Status);
3cdc0e8d 83 } while (!(status & 0x08) && time_before(jiffies, timeout));
414c4531
DA		 84}
85
86static inline void mga_wait_busy(struct mga_device *mdev)
87{
3cdc0e8d 88 unsigned long timeout = jiffies + HZ;
414c4531
DA		 89 unsigned int status = 0;
90 do {
91 status = RREG8(MGAREG_Status + 2);
3cdc0e8d 92 } while ((status & 0x01) && time_before(jiffies, timeout));
414c4531
DA		 93}
94
e829d7ef
ML		 95#define P_ARRAY_SIZE 9
96
414c4531
DA		 97static int mga_g200se_set_plls(struct mga_device *mdev, long clock)
98{
99 unsigned int vcomax, vcomin, pllreffreq;
100 unsigned int delta, tmpdelta, permitteddelta;
101 unsigned int testp, testm, testn;
102 unsigned int p, m, n;
103 unsigned int computed;
e829d7ef
ML		 104 unsigned int pvalues_e4[P_ARRAY_SIZE] = {16, 14, 12, 10, 8, 6, 4, 2, 1};
105 unsigned int fvv;
106 unsigned int i;
414c4531 107
e829d7ef 108 if (mdev->unique_rev_id <= 0x03) {
414c4531 109
e829d7ef
ML		 110 m = n = p = 0;
111 vcomax = 320000;
112 vcomin = 160000;
113 pllreffreq = 25000;
414c4531 114
e829d7ef
ML		 115 delta = 0xffffffff;
116 permitteddelta = clock * 5 / 1000;
414c4531 117
e829d7ef
ML		 118 for (testp = 8; testp > 0; testp /= 2) {
119 if (clock * testp > vcomax)
120 continue;
121 if (clock * testp < vcomin)
122 continue;
123
124 for (testn = 17; testn < 256; testn++) {
125 for (testm = 1; testm < 32; testm++) {
126 computed = (pllreffreq * testn) /
127 (testm * testp);
128 if (computed > clock)
129 tmpdelta = computed - clock;
130 else
131 tmpdelta = clock - computed;
132 if (tmpdelta < delta) {
133 delta = tmpdelta;
134 m = testm - 1;
135 n = testn - 1;
136 p = testp - 1;
137 }
138 }
139 }
140 }
141 } else {
142
143
144 m = n = p = 0;
145 vcomax = 1600000;
146 vcomin = 800000;
147 pllreffreq = 25000;
148
149 if (clock < 25000)
150 clock = 25000;
151
152 clock = clock * 2;
153
154 delta = 0xFFFFFFFF;
155 /* Permited delta is 0.5% as VESA Specification */
156 permitteddelta = clock * 5 / 1000;
157
158 for (i = 0 ; i < P_ARRAY_SIZE ; i++) {
159 testp = pvalues_e4[i];
160
161 if ((clock * testp) > vcomax)
162 continue;
163 if ((clock * testp) < vcomin)
164 continue;
165
166 for (testn = 50; testn <= 256; testn++) {
167 for (testm = 1; testm <= 32; testm++) {
168 computed = (pllreffreq * testn) /
169 (testm * testp);
170 if (computed > clock)
171 tmpdelta = computed - clock;
172 else
173 tmpdelta = clock - computed;
174
175 if (tmpdelta < delta) {
176 delta = tmpdelta;
177 m = testm - 1;
178 n = testn - 1;
179 p = testp - 1;
180 }
414c4531
DA		 181 }
182 }
183 }
e829d7ef 184
d3922b69 185 fvv = pllreffreq * (n + 1) / (m + 1);
e829d7ef
ML		 186 fvv = (fvv - 800000) / 50000;
187
188 if (fvv > 15)
189 fvv = 15;
190
191 p |= (fvv << 4);
192 m |= 0x80;
193
194 clock = clock / 2;
414c4531
DA		 195 }
196
197 if (delta > permitteddelta) {
198 printk(KERN_WARNING "PLL delta too large\n");
199 return 1;
200 }
201
202 WREG_DAC(MGA1064_PIX_PLLC_M, m);
203 WREG_DAC(MGA1064_PIX_PLLC_N, n);
204 WREG_DAC(MGA1064_PIX_PLLC_P, p);
d3922b69
ML		 205
206 if (mdev->unique_rev_id >= 0x04) {
207 WREG_DAC(0x1a, 0x09);
208 msleep(20);
209 WREG_DAC(0x1a, 0x01);
210
211 }
212
414c4531
DA		 213 return 0;
214}
215
216static int mga_g200wb_set_plls(struct mga_device *mdev, long clock)
217{
218 unsigned int vcomax, vcomin, pllreffreq;
546aee51 219 unsigned int delta, tmpdelta;
6d857c18 220 unsigned int testp, testm, testn, testp2;
414c4531
DA		 221 unsigned int p, m, n;
222 unsigned int computed;
223 int i, j, tmpcount, vcount;
224 bool pll_locked = false;
225 u8 tmp;
226
227 m = n = p = 0;
414c4531
DA		 228
229 delta = 0xffffffff;
414c4531 230
6d857c18
ML		 231 if (mdev->type == G200_EW3) {
232
233 vcomax = 800000;
234 vcomin = 400000;
235 pllreffreq = 25000;
236
237 for (testp = 1; testp < 8; testp++) {
238 for (testp2 = 1; testp2 < 8; testp2++) {
239 if (testp < testp2)
240 continue;
241 if ((clock * testp * testp2) > vcomax)
242 continue;
243 if ((clock * testp * testp2) < vcomin)
244 continue;
245 for (testm = 1; testm < 26; testm++) {
246 for (testn = 32; testn < 2048 ; testn++) {
247 computed = (pllreffreq * testn) /
248 (testm * testp * testp2);
249 if (computed > clock)
250 tmpdelta = computed - clock;
251 else
252 tmpdelta = clock - computed;
253 if (tmpdelta < delta) {
254 delta = tmpdelta;
255 m = ((testn & 0x100) >> 1) |
256 (testm);
257 n = (testn & 0xFF);
258 p = ((testn & 0x600) >> 3) |
259 (testp2 << 3) |
260 (testp);
261 }
262 }
263 }
264 }
265 }
266 } else {
414c4531 267
6d857c18
ML		 268 vcomax = 550000;
269 vcomin = 150000;
270 pllreffreq = 48000;
271
272 for (testp = 1; testp < 9; testp++) {
273 if (clock * testp > vcomax)
274 continue;
275 if (clock * testp < vcomin)
276 continue;
277
278 for (testm = 1; testm < 17; testm++) {
279 for (testn = 1; testn < 151; testn++) {
280 computed = (pllreffreq * testn) /
281 (testm * testp);
282 if (computed > clock)
283 tmpdelta = computed - clock;
284 else
285 tmpdelta = clock - computed;
286 if (tmpdelta < delta) {
287 delta = tmpdelta;
288 n = testn - 1;
289 m = (testm - 1) |
290 ((n >> 1) & 0x80);
291 p = testp - 1;
292 }
414c4531
DA		 293 }
294 }
295 }
296 }
297
298 for (i = 0; i <= 32 && pll_locked == false; i++) {
299 if (i > 0) {
300 WREG8(MGAREG_CRTC_INDEX, 0x1e);
301 tmp = RREG8(MGAREG_CRTC_DATA);
302 if (tmp < 0xff)
303 WREG8(MGAREG_CRTC_DATA, tmp+1);
304 }
305
306 /* set pixclkdis to 1 */
307 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
308 tmp = RREG8(DAC_DATA);
309 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
fb70a669 310 WREG8(DAC_DATA, tmp);
414c4531
DA		 311
312 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
313 tmp = RREG8(DAC_DATA);
314 tmp |= MGA1064_REMHEADCTL_CLKDIS;
fb70a669 315 WREG8(DAC_DATA, tmp);
414c4531
DA		 316
317 /* select PLL Set C */
318 tmp = RREG8(MGAREG_MEM_MISC_READ);
319 tmp |= 0x3 << 2;
320 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
321
322 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
323 tmp = RREG8(DAC_DATA);
324 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN | 0x80;
fb70a669 325 WREG8(DAC_DATA, tmp);
414c4531
DA		 326
327 udelay(500);
328
329 /* reset the PLL */
330 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
331 tmp = RREG8(DAC_DATA);
332 tmp &= ~0x04;
fb70a669 333 WREG8(DAC_DATA, tmp);
414c4531
DA		 334
335 udelay(50);
336
337 /* program pixel pll register */
338 WREG_DAC(MGA1064_WB_PIX_PLLC_N, n);
339 WREG_DAC(MGA1064_WB_PIX_PLLC_M, m);
340 WREG_DAC(MGA1064_WB_PIX_PLLC_P, p);
341
342 udelay(50);
343
344 /* turn pll on */
345 WREG8(DAC_INDEX, MGA1064_VREF_CTL);
346 tmp = RREG8(DAC_DATA);
347 tmp |= 0x04;
348 WREG_DAC(MGA1064_VREF_CTL, tmp);
349
350 udelay(500);
351
352 /* select the pixel pll */
353 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
354 tmp = RREG8(DAC_DATA);
355 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
356 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
fb70a669 357 WREG8(DAC_DATA, tmp);
414c4531
DA		 358
359 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
360 tmp = RREG8(DAC_DATA);
361 tmp &= ~MGA1064_REMHEADCTL_CLKSL_MSK;
362 tmp |= MGA1064_REMHEADCTL_CLKSL_PLL;
fb70a669 363 WREG8(DAC_DATA, tmp);
414c4531
DA		 364
365 /* reset dotclock rate bit */
366 WREG8(MGAREG_SEQ_INDEX, 1);
367 tmp = RREG8(MGAREG_SEQ_DATA);
368 tmp &= ~0x8;
369 WREG8(MGAREG_SEQ_DATA, tmp);
370
371 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
372 tmp = RREG8(DAC_DATA);
373 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
fb70a669 374 WREG8(DAC_DATA, tmp);
414c4531
DA		 375
376 vcount = RREG8(MGAREG_VCOUNT);
377
378 for (j = 0; j < 30 && pll_locked == false; j++) {
379 tmpcount = RREG8(MGAREG_VCOUNT);
380 if (tmpcount < vcount)
381 vcount = 0;
382 if ((tmpcount - vcount) > 2)
383 pll_locked = true;
384 else
385 udelay(5);
386 }
387 }
388 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
389 tmp = RREG8(DAC_DATA);
390 tmp &= ~MGA1064_REMHEADCTL_CLKDIS;
391 WREG_DAC(MGA1064_REMHEADCTL, tmp);
392 return 0;
393}
394
395static int mga_g200ev_set_plls(struct mga_device *mdev, long clock)
396{
397 unsigned int vcomax, vcomin, pllreffreq;
546aee51 398 unsigned int delta, tmpdelta;
414c4531
DA		 399 unsigned int testp, testm, testn;
400 unsigned int p, m, n;
401 unsigned int computed;
402 u8 tmp;
403
404 m = n = p = 0;
405 vcomax = 550000;
406 vcomin = 150000;
407 pllreffreq = 50000;
408
409 delta = 0xffffffff;
414c4531
DA		 410
411 for (testp = 16; testp > 0; testp--) {
412 if (clock * testp > vcomax)
413 continue;
414 if (clock * testp < vcomin)
415 continue;
416
417 for (testn = 1; testn < 257; testn++) {
418 for (testm = 1; testm < 17; testm++) {
419 computed = (pllreffreq * testn) /
420 (testm * testp);
421 if (computed > clock)
422 tmpdelta = computed - clock;
423 else
424 tmpdelta = clock - computed;
425 if (tmpdelta < delta) {
426 delta = tmpdelta;
427 n = testn - 1;
428 m = testm - 1;
429 p = testp - 1;
430 }
431 }
432 }
433 }
434
435 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
436 tmp = RREG8(DAC_DATA);
437 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
fb70a669 438 WREG8(DAC_DATA, tmp);
414c4531
DA		 439
440 tmp = RREG8(MGAREG_MEM_MISC_READ);
441 tmp |= 0x3 << 2;
442 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
443
444 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
445 tmp = RREG8(DAC_DATA);
fb70a669 446 WREG8(DAC_DATA, tmp & ~0x40);
414c4531
DA		 447
448 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
449 tmp = RREG8(DAC_DATA);
450 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
fb70a669 451 WREG8(DAC_DATA, tmp);
414c4531
DA		 452
453 WREG_DAC(MGA1064_EV_PIX_PLLC_M, m);
454 WREG_DAC(MGA1064_EV_PIX_PLLC_N, n);
455 WREG_DAC(MGA1064_EV_PIX_PLLC_P, p);
456
457 udelay(50);
458
459 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
460 tmp = RREG8(DAC_DATA);
461 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
fb70a669 462 WREG8(DAC_DATA, tmp);
414c4531
DA		 463
464 udelay(500);
465
466 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
467 tmp = RREG8(DAC_DATA);
468 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
469 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
fb70a669 470 WREG8(DAC_DATA, tmp);
414c4531
DA		 471
472 WREG8(DAC_INDEX, MGA1064_PIX_PLL_STAT);
473 tmp = RREG8(DAC_DATA);
fb70a669 474 WREG8(DAC_DATA, tmp | 0x40);
414c4531
DA		 475
476 tmp = RREG8(MGAREG_MEM_MISC_READ);
477 tmp |= (0x3 << 2);
478 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
479
480 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
481 tmp = RREG8(DAC_DATA);
482 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
fb70a669 483 WREG8(DAC_DATA, tmp);
414c4531
DA		 484
485 return 0;
486}
487
488static int mga_g200eh_set_plls(struct mga_device *mdev, long clock)
489{
490 unsigned int vcomax, vcomin, pllreffreq;
546aee51 491 unsigned int delta, tmpdelta;
414c4531
DA		 492 unsigned int testp, testm, testn;
493 unsigned int p, m, n;
494 unsigned int computed;
495 int i, j, tmpcount, vcount;
496 u8 tmp;
497 bool pll_locked = false;
498
499 m = n = p = 0;
414c4531 500
79a07390
ML		 501 if (mdev->type == G200_EH3) {
502 vcomax = 3000000;
503 vcomin = 1500000;
504 pllreffreq = 25000;
414c4531 505
79a07390 506 delta = 0xffffffff;
414c4531 507
79a07390
ML		 508 testp = 0;
509
510 for (testm = 150; testm >= 6; testm--) {
511 if (clock * testm > vcomax)
512 continue;
513 if (clock * testm < vcomin)
514 continue;
515 for (testn = 120; testn >= 60; testn--) {
516 computed = (pllreffreq * testn) / testm;
414c4531
DA		 517 if (computed > clock)
518 tmpdelta = computed - clock;
519 else
520 tmpdelta = clock - computed;
521 if (tmpdelta < delta) {
522 delta = tmpdelta;
79a07390
ML		 523 n = testn;
524 m = testm;
525 p = testp;
526 }
527 if (delta == 0)
528 break;
529 }
530 if (delta == 0)
531 break;
532 }
533 } else {
534
535 vcomax = 800000;
536 vcomin = 400000;
537 pllreffreq = 33333;
538
539 delta = 0xffffffff;
540
541 for (testp = 16; testp > 0; testp >>= 1) {
542 if (clock * testp > vcomax)
543 continue;
544 if (clock * testp < vcomin)
545 continue;
546
547 for (testm = 1; testm < 33; testm++) {
548 for (testn = 17; testn < 257; testn++) {
549 computed = (pllreffreq * testn) /
550 (testm * testp);
551 if (computed > clock)
552 tmpdelta = computed - clock;
553 else
554 tmpdelta = clock - computed;
555 if (tmpdelta < delta) {
556 delta = tmpdelta;
557 n = testn - 1;
558 m = (testm - 1);
559 p = testp - 1;
560 }
561 if ((clock * testp) >= 600000)
562 p |= 0x80;
414c4531 563 }
414c4531
DA		 564 }
565 }
566 }
567 for (i = 0; i <= 32 && pll_locked == false; i++) {
568 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
569 tmp = RREG8(DAC_DATA);
570 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
fb70a669 571 WREG8(DAC_DATA, tmp);
414c4531
DA		 572
573 tmp = RREG8(MGAREG_MEM_MISC_READ);
574 tmp |= 0x3 << 2;
575 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
576
577 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
578 tmp = RREG8(DAC_DATA);
579 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
fb70a669 580 WREG8(DAC_DATA, tmp);
414c4531
DA		 581
582 udelay(500);
583
584 WREG_DAC(MGA1064_EH_PIX_PLLC_M, m);
585 WREG_DAC(MGA1064_EH_PIX_PLLC_N, n);
586 WREG_DAC(MGA1064_EH_PIX_PLLC_P, p);
587
588 udelay(500);
589
590 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
591 tmp = RREG8(DAC_DATA);
592 tmp &= ~MGA1064_PIX_CLK_CTL_SEL_MSK;
593 tmp |= MGA1064_PIX_CLK_CTL_SEL_PLL;
fb70a669 594 WREG8(DAC_DATA, tmp);
414c4531
DA		 595
596 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
597 tmp = RREG8(DAC_DATA);
598 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
599 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
fb70a669 600 WREG8(DAC_DATA, tmp);
414c4531
DA		 601
602 vcount = RREG8(MGAREG_VCOUNT);
603
604 for (j = 0; j < 30 && pll_locked == false; j++) {
605 tmpcount = RREG8(MGAREG_VCOUNT);
606 if (tmpcount < vcount)
607 vcount = 0;
608 if ((tmpcount - vcount) > 2)
609 pll_locked = true;
610 else
611 udelay(5);
612 }
613 }
614
615 return 0;
616}
617
618static int mga_g200er_set_plls(struct mga_device *mdev, long clock)
619{
620 unsigned int vcomax, vcomin, pllreffreq;
621 unsigned int delta, tmpdelta;
9830605d 622 int testr, testn, testm, testo;
414c4531 623 unsigned int p, m, n;
9830605d 624 unsigned int computed, vco;
414c4531 625 int tmp;
9830605d 626 const unsigned int m_div_val[] = { 1, 2, 4, 8 };
414c4531
DA		 627
628 m = n = p = 0;
629 vcomax = 1488000;
630 vcomin = 1056000;
631 pllreffreq = 48000;
632
633 delta = 0xffffffff;
634
635 for (testr = 0; testr < 4; testr++) {
636 if (delta == 0)
637 break;
638 for (testn = 5; testn < 129; testn++) {
639 if (delta == 0)
640 break;
641 for (testm = 3; testm >= 0; testm--) {
642 if (delta == 0)
643 break;
644 for (testo = 5; testo < 33; testo++) {
9830605d 645 vco = pllreffreq * (testn + 1) /
414c4531 646 (testr + 1);
9830605d 647 if (vco < vcomin)
414c4531 648 continue;
9830605d 649 if (vco > vcomax)
414c4531 650 continue;
9830605d 651 computed = vco / (m_div_val[testm] * (testo + 1));
414c4531
DA		 652 if (computed > clock)
653 tmpdelta = computed - clock;
654 else
655 tmpdelta = clock - computed;
656 if (tmpdelta < delta) {
657 delta = tmpdelta;
658 m = testm | (testo << 3);
659 n = testn;
660 p = testr | (testr << 3);
661 }
662 }
663 }
664 }
665 }
666
667 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
668 tmp = RREG8(DAC_DATA);
669 tmp |= MGA1064_PIX_CLK_CTL_CLK_DIS;
fb70a669 670 WREG8(DAC_DATA, tmp);
414c4531
DA		 671
672 WREG8(DAC_INDEX, MGA1064_REMHEADCTL);
673 tmp = RREG8(DAC_DATA);
674 tmp |= MGA1064_REMHEADCTL_CLKDIS;
fb70a669 675 WREG8(DAC_DATA, tmp);
414c4531
DA		 676
677 tmp = RREG8(MGAREG_MEM_MISC_READ);
678 tmp |= (0x3<<2) | 0xc0;
679 WREG8(MGAREG_MEM_MISC_WRITE, tmp);
680
681 WREG8(DAC_INDEX, MGA1064_PIX_CLK_CTL);
682 tmp = RREG8(DAC_DATA);
683 tmp &= ~MGA1064_PIX_CLK_CTL_CLK_DIS;
684 tmp |= MGA1064_PIX_CLK_CTL_CLK_POW_DOWN;
fb70a669 685 WREG8(DAC_DATA, tmp);
414c4531
DA		 686
687 udelay(500);
688
689 WREG_DAC(MGA1064_ER_PIX_PLLC_N, n);
690 WREG_DAC(MGA1064_ER_PIX_PLLC_M, m);
691 WREG_DAC(MGA1064_ER_PIX_PLLC_P, p);
692
693 udelay(50);
694
695 return 0;
696}
697
698static int mga_crtc_set_plls(struct mga_device *mdev, long clock)
699{
700 switch(mdev->type) {
701 case G200_SE_A:
702 case G200_SE_B:
703 return mga_g200se_set_plls(mdev, clock);
704 break;
705 case G200_WB:
6d857c18 706 case G200_EW3:
414c4531
DA		 707 return mga_g200wb_set_plls(mdev, clock);
708 break;
709 case G200_EV:
710 return mga_g200ev_set_plls(mdev, clock);
711 break;
712 case G200_EH:
79a07390 713 case G200_EH3:
414c4531
DA		 714 return mga_g200eh_set_plls(mdev, clock);
715 break;
716 case G200_ER:
717 return mga_g200er_set_plls(mdev, clock);
718 break;
719 }
720 return 0;
721}
722
723static void mga_g200wb_prepare(struct drm_crtc *crtc)
724{
725 struct mga_device *mdev = crtc->dev->dev_private;
726 u8 tmp;
727 int iter_max;
728
729 /* 1- The first step is to warn the BMC of an upcoming mode change.
730 * We are putting the misc<0> to output.*/
731
732 WREG8(DAC_INDEX, MGA1064_GEN_IO_CTL);
733 tmp = RREG8(DAC_DATA);
734 tmp |= 0x10;
735 WREG_DAC(MGA1064_GEN_IO_CTL, tmp);
736
737 /* we are putting a 1 on the misc<0> line */
738 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
739 tmp = RREG8(DAC_DATA);
740 tmp |= 0x10;
741 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
742
743 /* 2- Second step to mask and further scan request
744 * This will be done by asserting the remfreqmsk bit (XSPAREREG<7>)
745 */
746 WREG8(DAC_INDEX, MGA1064_SPAREREG);
747 tmp = RREG8(DAC_DATA);
748 tmp |= 0x80;
749 WREG_DAC(MGA1064_SPAREREG, tmp);
750
751 /* 3a- the third step is to verifu if there is an active scan
752 * We are searching for a 0 on remhsyncsts <XSPAREREG<0>)
753 */
754 iter_max = 300;
755 while (!(tmp & 0x1) && iter_max) {
756 WREG8(DAC_INDEX, MGA1064_SPAREREG);
757 tmp = RREG8(DAC_DATA);
758 udelay(1000);
759 iter_max--;
760 }
761
762 /* 3b- this step occurs only if the remove is actually scanning
763 * we are waiting for the end of the frame which is a 1 on
764 * remvsyncsts (XSPAREREG<1>)
765 */
766 if (iter_max) {
767 iter_max = 300;
768 while ((tmp & 0x2) && iter_max) {
769 WREG8(DAC_INDEX, MGA1064_SPAREREG);
770 tmp = RREG8(DAC_DATA);
771 udelay(1000);
772 iter_max--;
773 }
774 }
775}
776
777static void mga_g200wb_commit(struct drm_crtc *crtc)
778{
779 u8 tmp;
780 struct mga_device *mdev = crtc->dev->dev_private;
781
782 /* 1- The first step is to ensure that the vrsten and hrsten are set */
783 WREG8(MGAREG_CRTCEXT_INDEX, 1);
784 tmp = RREG8(MGAREG_CRTCEXT_DATA);
785 WREG8(MGAREG_CRTCEXT_DATA, tmp | 0x88);
786
787 /* 2- second step is to assert the rstlvl2 */
788 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
789 tmp = RREG8(DAC_DATA);
790 tmp |= 0x8;
791 WREG8(DAC_DATA, tmp);
792
793 /* wait 10 us */
794 udelay(10);
795
796 /* 3- deassert rstlvl2 */
797 tmp &= ~0x08;
798 WREG8(DAC_INDEX, MGA1064_REMHEADCTL2);
799 WREG8(DAC_DATA, tmp);
800
801 /* 4- remove mask of scan request */
802 WREG8(DAC_INDEX, MGA1064_SPAREREG);
803 tmp = RREG8(DAC_DATA);
804 tmp &= ~0x80;
805 WREG8(DAC_DATA, tmp);
806
807 /* 5- put back a 0 on the misc<0> line */
808 WREG8(DAC_INDEX, MGA1064_GEN_IO_DATA);
809 tmp = RREG8(DAC_DATA);
810 tmp &= ~0x10;
811 WREG_DAC(MGA1064_GEN_IO_DATA, tmp);
812}
813
9f1d0366
CH		 814/*
815 This is how the framebuffer base address is stored in g200 cards:
816 * Assume @offset is the gpu_addr variable of the framebuffer object
817 * Then addr is the number of _pixels_ (not bytes) from the start of
818 VRAM to the first pixel we want to display. (divided by 2 for 32bit
819 framebuffers)
820 * addr is stored in the CRTCEXT0, CRTCC and CRTCD registers
821 addr<20> -> CRTCEXT0<6>
822 addr<19-16> -> CRTCEXT0<3-0>
823 addr<15-8> -> CRTCC<7-0>
824 addr<7-0> -> CRTCD<7-0>
825 CRTCEXT0 has to be programmed last to trigger an update and make the
826 new addr variable take effect.
827 */
080fd6b5 828static void mga_set_start_address(struct drm_crtc *crtc, unsigned offset)
414c4531
DA		 829{
830 struct mga_device *mdev = crtc->dev->dev_private;
831 u32 addr;
832 int count;
9f1d0366 833 u8 crtcext0;
414c4531
DA		 834
835 while (RREG8(0x1fda) & 0x08);
836 while (!(RREG8(0x1fda) & 0x08));
837
838 count = RREG8(MGAREG_VCOUNT) + 2;
839 while (RREG8(MGAREG_VCOUNT) < count);
840
9f1d0366
CH		 841 WREG8(MGAREG_CRTCEXT_INDEX, 0);
842 crtcext0 = RREG8(MGAREG_CRTCEXT_DATA);
843 crtcext0 &= 0xB0;
844 addr = offset / 8;
845 /* Can't store addresses any higher than that...
846 but we also don't have more than 16MB of memory, so it should be fine. */
847 WARN_ON(addr > 0x1fffff);
848 crtcext0 |= (!!(addr & (1<<20)))<<6;
414c4531
DA		 849 WREG_CRT(0x0d, (u8)(addr & 0xff));
850 WREG_CRT(0x0c, (u8)(addr >> 8) & 0xff);
9f1d0366 851 WREG_ECRT(0x0, ((u8)(addr >> 16) & 0xf) | crtcext0);
414c4531
DA		 852}
853
854
855/* ast is different - we will force move buffers out of VRAM */
856static int mga_crtc_do_set_base(struct drm_crtc *crtc,
857 struct drm_framebuffer *fb,
858 int x, int y, int atomic)
859{
860 struct mga_device *mdev = crtc->dev->dev_private;
861 struct drm_gem_object *obj;
862 struct mga_framebuffer *mga_fb;
863 struct mgag200_bo *bo;
864 int ret;
865 u64 gpu_addr;
866
867 /* push the previous fb to system ram */
868 if (!atomic && fb) {
869 mga_fb = to_mga_framebuffer(fb);
870 obj = mga_fb->obj;
871 bo = gem_to_mga_bo(obj);
872 ret = mgag200_bo_reserve(bo, false);
873 if (ret)
874 return ret;
875 mgag200_bo_push_sysram(bo);
876 mgag200_bo_unreserve(bo);
877 }
878
f4510a27 879 mga_fb = to_mga_framebuffer(crtc->primary->fb);
414c4531
DA		 880 obj = mga_fb->obj;
881 bo = gem_to_mga_bo(obj);
882
883 ret = mgag200_bo_reserve(bo, false);
884 if (ret)
885 return ret;
886
887 ret = mgag200_bo_pin(bo, TTM_PL_FLAG_VRAM, &gpu_addr);
888 if (ret) {
889 mgag200_bo_unreserve(bo);
890 return ret;
891 }
892
893 if (&mdev->mfbdev->mfb == mga_fb) {
894 /* if pushing console in kmap it */
895 ret = ttm_bo_kmap(&bo->bo, 0, bo->bo.num_pages, &bo->kmap);
896 if (ret)
897 DRM_ERROR("failed to kmap fbcon\n");
898
899 }
900 mgag200_bo_unreserve(bo);
901
414c4531
DA		 902 mga_set_start_address(crtc, (u32)gpu_addr);
903
904 return 0;
905}
906
907static int mga_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
908 struct drm_framebuffer *old_fb)
909{
910 return mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
911}
912
913static int mga_crtc_mode_set(struct drm_crtc *crtc,
914 struct drm_display_mode *mode,
915 struct drm_display_mode *adjusted_mode,
916 int x, int y, struct drm_framebuffer *old_fb)
917{
918 struct drm_device *dev = crtc->dev;
919 struct mga_device *mdev = dev->dev_private;
920 int hdisplay, hsyncstart, hsyncend, htotal;
921 int vdisplay, vsyncstart, vsyncend, vtotal;
922 int pitch;
923 int option = 0, option2 = 0;
924 int i;
925 unsigned char misc = 0;
926 unsigned char ext_vga[6];
414c4531
DA		 927 u8 bppshift;
928
929 static unsigned char dacvalue[] = {
930 /* 0x00: */ 0, 0, 0, 0, 0, 0, 0x00, 0,
931 /* 0x08: */ 0, 0, 0, 0, 0, 0, 0, 0,
932 /* 0x10: */ 0, 0, 0, 0, 0, 0, 0, 0,
933 /* 0x18: */ 0x00, 0, 0xC9, 0xFF, 0xBF, 0x20, 0x1F, 0x20,
934 /* 0x20: */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
935 /* 0x28: */ 0x00, 0x00, 0x00, 0x00, 0, 0, 0, 0x40,
936 /* 0x30: */ 0x00, 0xB0, 0x00, 0xC2, 0x34, 0x14, 0x02, 0x83,
937 /* 0x38: */ 0x00, 0x93, 0x00, 0x77, 0x00, 0x00, 0x00, 0x3A,
938 /* 0x40: */ 0, 0, 0, 0, 0, 0, 0, 0,
939 /* 0x48: */ 0, 0, 0, 0, 0, 0, 0, 0
940 };
941
f4510a27 942 bppshift = mdev->bpp_shifts[(crtc->primary->fb->bits_per_pixel >> 3) - 1];
414c4531
DA		 943
944 switch (mdev->type) {
945 case G200_SE_A:
946 case G200_SE_B:
947 dacvalue[MGA1064_VREF_CTL] = 0x03;
948 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
949 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_DAC_EN |
950 MGA1064_MISC_CTL_VGA8 |
951 MGA1064_MISC_CTL_DAC_RAM_CS;
952 if (mdev->has_sdram)
953 option = 0x40049120;
954 else
955 option = 0x4004d120;
956 option2 = 0x00008000;
957 break;
958 case G200_WB:
6d857c18 959 case G200_EW3:
414c4531
DA		 960 dacvalue[MGA1064_VREF_CTL] = 0x07;
961 option = 0x41049120;
962 option2 = 0x0000b000;
963 break;
964 case G200_EV:
965 dacvalue[MGA1064_PIX_CLK_CTL] = MGA1064_PIX_CLK_CTL_SEL_PLL;
966 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
967 MGA1064_MISC_CTL_DAC_RAM_CS;
968 option = 0x00000120;
969 option2 = 0x0000b000;
970 break;
971 case G200_EH:
79a07390 972 case G200_EH3:
414c4531
DA		 973 dacvalue[MGA1064_MISC_CTL] = MGA1064_MISC_CTL_VGA8 |
974 MGA1064_MISC_CTL_DAC_RAM_CS;
975 option = 0x00000120;
976 option2 = 0x0000b000;
977 break;
978 case G200_ER:
414c4531
DA		 979 break;
980 }
981
f4510a27 982 switch (crtc->primary->fb->bits_per_pixel) {
414c4531
DA		 983 case 8:
984 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_8bits;
985 break;
986 case 16:
f4510a27 987 if (crtc->primary->fb->depth == 15)
414c4531
DA		 988 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_15bits;
989 else
990 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_16bits;
991 break;
992 case 24:
993 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_24bits;
994 break;
995 case 32:
996 dacvalue[MGA1064_MUL_CTL] = MGA1064_MUL_CTL_32_24bits;
997 break;
998 }
999
1000 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1001 misc |= 0x40;
1002 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1003 misc |= 0x80;
1004
1005
1006 for (i = 0; i < sizeof(dacvalue); i++) {
9d8aa55f 1007 if ((i <= 0x17) ||
414c4531
DA		 1008 (i == 0x1b) ||
1009 (i == 0x1c) ||
1010 ((i >= 0x1f) && (i <= 0x29)) ||
1011 ((i >= 0x30) && (i <= 0x37)))
1012 continue;
1013 if (IS_G200_SE(mdev) &&
1014 ((i == 0x2c) || (i == 0x2d) || (i == 0x2e)))
1015 continue;
6d857c18
ML		 1016 if ((mdev->type == G200_EV ||
1017 mdev->type == G200_WB ||
1018 mdev->type == G200_EH ||
79a07390
ML		 1019 mdev->type == G200_EW3 ||
1020 mdev->type == G200_EH3) &&
414c4531
DA		 1021 (i >= 0x44) && (i <= 0x4e))
1022 continue;
1023
1024 WREG_DAC(i, dacvalue[i]);
1025 }
1026
1812a3db
CH		 1027 if (mdev->type == G200_ER)
1028 WREG_DAC(0x90, 0);
414c4531
DA		 1029
1030 if (option)
1031 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION, option);
1032 if (option2)
1033 pci_write_config_dword(dev->pdev, PCI_MGA_OPTION2, option2);
1034
1035 WREG_SEQ(2, 0xf);
1036 WREG_SEQ(3, 0);
1037 WREG_SEQ(4, 0xe);
1038
f4510a27
MR		 1039 pitch = crtc->primary->fb->pitches[0] / (crtc->primary->fb->bits_per_pixel / 8);
1040 if (crtc->primary->fb->bits_per_pixel == 24)
da558398 1041 pitch = (pitch * 3) >> (4 - bppshift);
414c4531
DA		 1042 else
1043 pitch = pitch >> (4 - bppshift);
1044
1045 hdisplay = mode->hdisplay / 8 - 1;
1046 hsyncstart = mode->hsync_start / 8 - 1;
1047 hsyncend = mode->hsync_end / 8 - 1;
1048 htotal = mode->htotal / 8 - 1;
1049
1050 /* Work around hardware quirk */
1051 if ((htotal & 0x07) == 0x06 || (htotal & 0x07) == 0x04)
1052 htotal++;
1053
1054 vdisplay = mode->vdisplay - 1;
1055 vsyncstart = mode->vsync_start - 1;
1056 vsyncend = mode->vsync_end - 1;
1057 vtotal = mode->vtotal - 2;
1058
1059 WREG_GFX(0, 0);
1060 WREG_GFX(1, 0);
1061 WREG_GFX(2, 0);
1062 WREG_GFX(3, 0);
1063 WREG_GFX(4, 0);
1064 WREG_GFX(5, 0x40);
1065 WREG_GFX(6, 0x5);
1066 WREG_GFX(7, 0xf);
1067 WREG_GFX(8, 0xf);
1068
1069 WREG_CRT(0, htotal - 4);
1070 WREG_CRT(1, hdisplay);
1071 WREG_CRT(2, hdisplay);
1072 WREG_CRT(3, (htotal & 0x1F) | 0x80);
1073 WREG_CRT(4, hsyncstart);
1074 WREG_CRT(5, ((htotal & 0x20) << 2) | (hsyncend & 0x1F));
1075 WREG_CRT(6, vtotal & 0xFF);
1076 WREG_CRT(7, ((vtotal & 0x100) >> 8) |
1077 ((vdisplay & 0x100) >> 7) |
1078 ((vsyncstart & 0x100) >> 6) |
1079 ((vdisplay & 0x100) >> 5) |
1080 ((vdisplay & 0x100) >> 4) | /* linecomp */
1081 ((vtotal & 0x200) >> 4)|
1082 ((vdisplay & 0x200) >> 3) |
1083 ((vsyncstart & 0x200) >> 2));
1084 WREG_CRT(9, ((vdisplay & 0x200) >> 4) |
1085 ((vdisplay & 0x200) >> 3));
1086 WREG_CRT(10, 0);
1087 WREG_CRT(11, 0);
1088 WREG_CRT(12, 0);
1089 WREG_CRT(13, 0);
1090 WREG_CRT(14, 0);
1091 WREG_CRT(15, 0);
1092 WREG_CRT(16, vsyncstart & 0xFF);
1093 WREG_CRT(17, (vsyncend & 0x0F) | 0x20);
1094 WREG_CRT(18, vdisplay & 0xFF);
1095 WREG_CRT(19, pitch & 0xFF);
1096 WREG_CRT(20, 0);
1097 WREG_CRT(21, vdisplay & 0xFF);
1098 WREG_CRT(22, (vtotal + 1) & 0xFF);
1099 WREG_CRT(23, 0xc3);
1100 WREG_CRT(24, vdisplay & 0xFF);
1101
1102 ext_vga[0] = 0;
1103 ext_vga[5] = 0;
1104
1105 /* TODO interlace */
1106
1107 ext_vga[0] |= (pitch & 0x300) >> 4;
1108 ext_vga[1] = (((htotal - 4) & 0x100) >> 8) |
1109 ((hdisplay & 0x100) >> 7) |
1110 ((hsyncstart & 0x100) >> 6) |
1111 (htotal & 0x40);
1112 ext_vga[2] = ((vtotal & 0xc00) >> 10) |
1113 ((vdisplay & 0x400) >> 8) |
1114 ((vdisplay & 0xc00) >> 7) |
1115 ((vsyncstart & 0xc00) >> 5) |
1116 ((vdisplay & 0x400) >> 3);
f4510a27 1117 if (crtc->primary->fb->bits_per_pixel == 24)
414c4531
DA		 1118 ext_vga[3] = (((1 << bppshift) * 3) - 1) | 0x80;
1119 else
1120 ext_vga[3] = ((1 << bppshift) - 1) | 0x80;
1121 ext_vga[4] = 0;
6d857c18 1122 if (mdev->type == G200_WB || mdev->type == G200_EW3)
414c4531
DA		 1123 ext_vga[1] |= 0x88;
1124
414c4531
DA		 1125 /* Set pixel clocks */
1126 misc = 0x2d;
1127 WREG8(MGA_MISC_OUT, misc);
1128
1129 mga_crtc_set_plls(mdev, mode->clock);
1130
1131 for (i = 0; i < 6; i++) {
1132 WREG_ECRT(i, ext_vga[i]);
1133 }
1134
1135 if (mdev->type == G200_ER)
1812a3db 1136 WREG_ECRT(0x24, 0x5);
414c4531 1137
6d857c18
ML		 1138 if (mdev->type == G200_EW3)
1139 WREG_ECRT(0x34, 0x5);
1140
414c4531
DA		 1141 if (mdev->type == G200_EV) {
1142 WREG_ECRT(6, 0);
1143 }
1144
1145 WREG_ECRT(0, ext_vga[0]);
1146 /* Enable mga pixel clock */
1147 misc = 0x2d;
1148
1149 WREG8(MGA_MISC_OUT, misc);
1150
1151 if (adjusted_mode)
1152 memcpy(&mdev->mode, mode, sizeof(struct drm_display_mode));
1153
1154 mga_crtc_do_set_base(crtc, old_fb, x, y, 0);
1155
1156 /* reset tagfifo */
1157 if (mdev->type == G200_ER) {
1158 u32 mem_ctl = RREG32(MGAREG_MEMCTL);
1159 u8 seq1;
1160
1161 /* screen off */
1162 WREG8(MGAREG_SEQ_INDEX, 0x01);
1163 seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20;
1164 WREG8(MGAREG_SEQ_DATA, seq1);
1165
1166 WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000);
1167 udelay(1000);
1168 WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000);
1169
1170 WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20);
1171 }
1172
1173
1174 if (IS_G200_SE(mdev)) {
abbee623 1175 if (mdev->unique_rev_id >= 0x02) {
414c4531
DA		 1176 u8 hi_pri_lvl;
1177 u32 bpp;
1178 u32 mb;
1179
f4510a27 1180 if (crtc->primary->fb->bits_per_pixel > 16)
414c4531 1181 bpp = 32;
f4510a27 1182 else if (crtc->primary->fb->bits_per_pixel > 8)
414c4531
DA		 1183 bpp = 16;
1184 else
1185 bpp = 8;
1186
1187 mb = (mode->clock * bpp) / 1000;
1188 if (mb > 3100)
1189 hi_pri_lvl = 0;
1190 else if (mb > 2600)
1191 hi_pri_lvl = 1;
1192 else if (mb > 1900)
1193 hi_pri_lvl = 2;
1194 else if (mb > 1160)
1195 hi_pri_lvl = 3;
1196 else if (mb > 440)
1197 hi_pri_lvl = 4;
1198 else
1199 hi_pri_lvl = 5;
1200
91f8f105
CH		 1201 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1202 WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl);
414c4531 1203 } else {
91f8f105 1204 WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
abbee623 1205 if (mdev->unique_rev_id >= 0x01)
91f8f105 1206 WREG8(MGAREG_CRTCEXT_DATA, 0x03);
414c4531 1207 else
91f8f105 1208 WREG8(MGAREG_CRTCEXT_DATA, 0x04);
414c4531
DA		 1209 }
1210 }
1211 return 0;
1212}
1213
1214#if 0 /* code from mjg to attempt D3 on crtc dpms off - revisit later */
1215static int mga_suspend(struct drm_crtc *crtc)
1216{
1217 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1218 struct drm_device *dev = crtc->dev;
1219 struct mga_device *mdev = dev->dev_private;
1220 struct pci_dev *pdev = dev->pdev;
1221 int option;
1222
1223 if (mdev->suspended)
1224 return 0;
1225
1226 WREG_SEQ(1, 0x20);
1227 WREG_ECRT(1, 0x30);
1228 /* Disable the pixel clock */
1229 WREG_DAC(0x1a, 0x05);
1230 /* Power down the DAC */
1231 WREG_DAC(0x1e, 0x18);
1232 /* Power down the pixel PLL */
1233 WREG_DAC(0x1a, 0x0d);
1234
1235 /* Disable PLLs and clocks */
1236 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1237 option &= ~(0x1F8024);
1238 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1239 pci_set_power_state(pdev, PCI_D3hot);
1240 pci_disable_device(pdev);
1241
1242 mdev->suspended = true;
1243
1244 return 0;
1245}
1246
1247static int mga_resume(struct drm_crtc *crtc)
1248{
1249 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1250 struct drm_device *dev = crtc->dev;
1251 struct mga_device *mdev = dev->dev_private;
1252 struct pci_dev *pdev = dev->pdev;
1253 int option;
1254
1255 if (!mdev->suspended)
1256 return 0;
1257
1258 pci_set_power_state(pdev, PCI_D0);
1259 pci_enable_device(pdev);
1260
1261 /* Disable sysclk */
1262 pci_read_config_dword(pdev, PCI_MGA_OPTION, &option);
1263 option &= ~(0x4);
1264 pci_write_config_dword(pdev, PCI_MGA_OPTION, option);
1265
1266 mdev->suspended = false;
1267
1268 return 0;
1269}
1270
1271#endif
1272
1273static void mga_crtc_dpms(struct drm_crtc *crtc, int mode)
1274{
1275 struct drm_device *dev = crtc->dev;
1276 struct mga_device *mdev = dev->dev_private;
1277 u8 seq1 = 0, crtcext1 = 0;
1278
1279 switch (mode) {
1280 case DRM_MODE_DPMS_ON:
1281 seq1 = 0;
1282 crtcext1 = 0;
1283 mga_crtc_load_lut(crtc);
1284 break;
1285 case DRM_MODE_DPMS_STANDBY:
1286 seq1 = 0x20;
1287 crtcext1 = 0x10;
1288 break;
1289 case DRM_MODE_DPMS_SUSPEND:
1290 seq1 = 0x20;
1291 crtcext1 = 0x20;
1292 break;
1293 case DRM_MODE_DPMS_OFF:
1294 seq1 = 0x20;
1295 crtcext1 = 0x30;
1296 break;
1297 }
1298
1299#if 0
1300 if (mode == DRM_MODE_DPMS_OFF) {
1301 mga_suspend(crtc);
1302 }
1303#endif
1304 WREG8(MGAREG_SEQ_INDEX, 0x01);
1305 seq1 |= RREG8(MGAREG_SEQ_DATA) & ~0x20;
1306 mga_wait_vsync(mdev);
1307 mga_wait_busy(mdev);
1308 WREG8(MGAREG_SEQ_DATA, seq1);
1309 msleep(20);
1310 WREG8(MGAREG_CRTCEXT_INDEX, 0x01);
1311 crtcext1 |= RREG8(MGAREG_CRTCEXT_DATA) & ~0x30;
1312 WREG8(MGAREG_CRTCEXT_DATA, crtcext1);
1313
1314#if 0
1315 if (mode == DRM_MODE_DPMS_ON && mdev->suspended == true) {
1316 mga_resume(crtc);
1317 drm_helper_resume_force_mode(dev);
1318 }
1319#endif
1320}
1321
1322/*
1323 * This is called before a mode is programmed. A typical use might be to
1324 * enable DPMS during the programming to avoid seeing intermediate stages,
1325 * but that's not relevant to us
1326 */
1327static void mga_crtc_prepare(struct drm_crtc *crtc)
1328{
1329 struct drm_device *dev = crtc->dev;
1330 struct mga_device *mdev = dev->dev_private;
1331 u8 tmp;
1332
1333 /* mga_resume(crtc);*/
1334
1335 WREG8(MGAREG_CRTC_INDEX, 0x11);
1336 tmp = RREG8(MGAREG_CRTC_DATA);
1337 WREG_CRT(0x11, tmp | 0x80);
1338
1339 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1340 WREG_SEQ(0, 1);
1341 msleep(50);
1342 WREG_SEQ(1, 0x20);
1343 msleep(20);
1344 } else {
1345 WREG8(MGAREG_SEQ_INDEX, 0x1);
1346 tmp = RREG8(MGAREG_SEQ_DATA);
1347
1348 /* start sync reset */
1349 WREG_SEQ(0, 1);
1350 WREG_SEQ(1, tmp | 0x20);
1351 }
1352
6d857c18 1353 if (mdev->type == G200_WB || mdev->type == G200_EW3)
414c4531
DA		 1354 mga_g200wb_prepare(crtc);
1355
1356 WREG_CRT(17, 0);
1357}
1358
1359/*
1360 * This is called after a mode is programmed. It should reverse anything done
1361 * by the prepare function
1362 */
1363static void mga_crtc_commit(struct drm_crtc *crtc)
1364{
1365 struct drm_device *dev = crtc->dev;
1366 struct mga_device *mdev = dev->dev_private;
d584ff82 1367 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
414c4531
DA		 1368 u8 tmp;
1369
6d857c18 1370 if (mdev->type == G200_WB || mdev->type == G200_EW3)
414c4531
DA		 1371 mga_g200wb_commit(crtc);
1372
1373 if (mdev->type == G200_SE_A || mdev->type == G200_SE_B) {
1374 msleep(50);
1375 WREG_SEQ(1, 0x0);
1376 msleep(20);
1377 WREG_SEQ(0, 0x3);
1378 } else {
1379 WREG8(MGAREG_SEQ_INDEX, 0x1);
1380 tmp = RREG8(MGAREG_SEQ_DATA);
1381
1382 tmp &= ~0x20;
1383 WREG_SEQ(0x1, tmp);
1384 WREG_SEQ(0, 3);
1385 }
1386 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
1387}
1388
1389/*
1390 * The core can pass us a set of gamma values to program. We actually only
1391 * use this for 8-bit mode so can't perform smooth fades on deeper modes,
1392 * but it's a requirement that we provide the function
1393 */
7ea77283
ML		 1394static int mga_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
1395 u16 *blue, uint32_t size)
414c4531
DA		 1396{
1397 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
414c4531
DA		 1398 int i;
1399
7ea77283 1400 for (i = 0; i < size; i++) {
414c4531
DA		 1401 mga_crtc->lut_r[i] = red[i] >> 8;
1402 mga_crtc->lut_g[i] = green[i] >> 8;
1403 mga_crtc->lut_b[i] = blue[i] >> 8;
1404 }
1405 mga_crtc_load_lut(crtc);
7ea77283
ML		 1406
1407 return 0;
414c4531
DA		 1408}
1409
1410/* Simple cleanup function */
1411static void mga_crtc_destroy(struct drm_crtc *crtc)
1412{
1413 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1414
1415 drm_crtc_cleanup(crtc);
1416 kfree(mga_crtc);
1417}
1418
64c29076
EE		 1419static void mga_crtc_disable(struct drm_crtc *crtc)
1420{
1421 int ret;
1422 DRM_DEBUG_KMS("\n");
1423 mga_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
f4510a27
MR		 1424 if (crtc->primary->fb) {
1425 struct mga_framebuffer *mga_fb = to_mga_framebuffer(crtc->primary->fb);
64c29076
EE		 1426 struct drm_gem_object *obj = mga_fb->obj;
1427 struct mgag200_bo *bo = gem_to_mga_bo(obj);
1428 ret = mgag200_bo_reserve(bo, false);
1429 if (ret)
1430 return;
1431 mgag200_bo_push_sysram(bo);
1432 mgag200_bo_unreserve(bo);
1433 }
f4510a27 1434 crtc->primary->fb = NULL;
64c29076
EE		 1435}
1436
414c4531
DA		 1437/* These provide the minimum set of functions required to handle a CRTC */
1438static const struct drm_crtc_funcs mga_crtc_funcs = {
a080db9f
CH		 1439 .cursor_set = mga_crtc_cursor_set,
1440 .cursor_move = mga_crtc_cursor_move,
414c4531
DA		 1441 .gamma_set = mga_crtc_gamma_set,
1442 .set_config = drm_crtc_helper_set_config,
1443 .destroy = mga_crtc_destroy,
1444};
1445
1446static const struct drm_crtc_helper_funcs mga_helper_funcs = {
64c29076 1447 .disable = mga_crtc_disable,
414c4531 1448 .dpms = mga_crtc_dpms,
414c4531
DA		 1449 .mode_set = mga_crtc_mode_set,
1450 .mode_set_base = mga_crtc_mode_set_base,
1451 .prepare = mga_crtc_prepare,
1452 .commit = mga_crtc_commit,
1453 .load_lut = mga_crtc_load_lut,
1454};
1455
1456/* CRTC setup */
f1998fe2 1457static void mga_crtc_init(struct mga_device *mdev)
414c4531 1458{
414c4531
DA		 1459 struct mga_crtc *mga_crtc;
1460 int i;
1461
1462 mga_crtc = kzalloc(sizeof(struct mga_crtc) +
1463 (MGAG200FB_CONN_LIMIT * sizeof(struct drm_connector *)),
1464 GFP_KERNEL);
1465
1466 if (mga_crtc == NULL)
1467 return;
1468
f1998fe2 1469 drm_crtc_init(mdev->dev, &mga_crtc->base, &mga_crtc_funcs);
414c4531
DA		 1470
1471 drm_mode_crtc_set_gamma_size(&mga_crtc->base, MGAG200_LUT_SIZE);
1472 mdev->mode_info.crtc = mga_crtc;
1473
1474 for (i = 0; i < MGAG200_LUT_SIZE; i++) {
1475 mga_crtc->lut_r[i] = i;
1476 mga_crtc->lut_g[i] = i;
1477 mga_crtc->lut_b[i] = i;
1478 }
1479
1480 drm_crtc_helper_add(&mga_crtc->base, &mga_helper_funcs);
1481}
1482
1483/** Sets the color ramps on behalf of fbcon */
1484void mga_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
1485 u16 blue, int regno)
1486{
1487 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1488
1489 mga_crtc->lut_r[regno] = red >> 8;
1490 mga_crtc->lut_g[regno] = green >> 8;
1491 mga_crtc->lut_b[regno] = blue >> 8;
1492}
1493
1494/** Gets the color ramps on behalf of fbcon */
1495void mga_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
1496 u16 *blue, int regno)
1497{
1498 struct mga_crtc *mga_crtc = to_mga_crtc(crtc);
1499
1500 *red = (u16)mga_crtc->lut_r[regno] << 8;
1501 *green = (u16)mga_crtc->lut_g[regno] << 8;
1502 *blue = (u16)mga_crtc->lut_b[regno] << 8;
1503}
1504
1505/*
1506 * The encoder comes after the CRTC in the output pipeline, but before
1507 * the connector. It's responsible for ensuring that the digital
1508 * stream is appropriately converted into the output format. Setup is
1509 * very simple in this case - all we have to do is inform qemu of the
1510 * colour depth in order to ensure that it displays appropriately
1511 */
1512
1513/*
1514 * These functions are analagous to those in the CRTC code, but are intended
1515 * to handle any encoder-specific limitations
1516 */
414c4531
DA		 1517static void mga_encoder_mode_set(struct drm_encoder *encoder,
1518 struct drm_display_mode *mode,
1519 struct drm_display_mode *adjusted_mode)
1520{
1521
1522}
1523
1524static void mga_encoder_dpms(struct drm_encoder *encoder, int state)
1525{
1526 return;
1527}
1528
1529static void mga_encoder_prepare(struct drm_encoder *encoder)
1530{
1531}
1532
1533static void mga_encoder_commit(struct drm_encoder *encoder)
1534{
1535}
1536
080fd6b5 1537static void mga_encoder_destroy(struct drm_encoder *encoder)
414c4531
DA		 1538{
1539 struct mga_encoder *mga_encoder = to_mga_encoder(encoder);
1540 drm_encoder_cleanup(encoder);
1541 kfree(mga_encoder);
1542}
1543
1544static const struct drm_encoder_helper_funcs mga_encoder_helper_funcs = {
1545 .dpms = mga_encoder_dpms,
414c4531
DA		 1546 .mode_set = mga_encoder_mode_set,
1547 .prepare = mga_encoder_prepare,
1548 .commit = mga_encoder_commit,
1549};
1550
1551static const struct drm_encoder_funcs mga_encoder_encoder_funcs = {
1552 .destroy = mga_encoder_destroy,
1553};
1554
1555static struct drm_encoder *mga_encoder_init(struct drm_device *dev)
1556{
1557 struct drm_encoder *encoder;
1558 struct mga_encoder *mga_encoder;
1559
1560 mga_encoder = kzalloc(sizeof(struct mga_encoder), GFP_KERNEL);
1561 if (!mga_encoder)
1562 return NULL;
1563
1564 encoder = &mga_encoder->base;
1565 encoder->possible_crtcs = 0x1;
1566
1567 drm_encoder_init(dev, encoder, &mga_encoder_encoder_funcs,
13a3d91f 1568 DRM_MODE_ENCODER_DAC, NULL);
414c4531
DA		 1569 drm_encoder_helper_add(encoder, &mga_encoder_helper_funcs);
1570
1571 return encoder;
1572}
1573
1574
1575static int mga_vga_get_modes(struct drm_connector *connector)
1576{
1577 struct mga_connector *mga_connector = to_mga_connector(connector);
1578 struct edid *edid;
1579 int ret = 0;
1580
1581 edid = drm_get_edid(connector, &mga_connector->i2c->adapter);
1582 if (edid) {
1583 drm_mode_connector_update_edid_property(connector, edid);
1584 ret = drm_add_edid_modes(connector, edid);
414c4531
DA		 1585 kfree(edid);
1586 }
1587 return ret;
1588}
1589
abbee623
JL		 1590static uint32_t mga_vga_calculate_mode_bandwidth(struct drm_display_mode *mode,
1591 int bits_per_pixel)
1592{
1593 uint32_t total_area, divisor;
c24ca5be 1594 uint64_t active_area, pixels_per_second, bandwidth;
abbee623
JL		 1595 uint64_t bytes_per_pixel = (bits_per_pixel + 7) / 8;
1596
1597 divisor = 1024;
1598
1599 if (!mode->htotal || !mode->vtotal || !mode->clock)
1600 return 0;
1601
1602 active_area = mode->hdisplay * mode->vdisplay;
1603 total_area = mode->htotal * mode->vtotal;
1604
1605 pixels_per_second = active_area * mode->clock * 1000;
1606 do_div(pixels_per_second, total_area);
1607
1608 bandwidth = pixels_per_second * bytes_per_pixel * 100;
1609 do_div(bandwidth, divisor);
1610
1611 return (uint32_t)(bandwidth);
1612}
1613
1614#define MODE_BANDWIDTH MODE_BAD
1615
414c4531
DA		 1616static int mga_vga_mode_valid(struct drm_connector *connector,
1617 struct drm_display_mode *mode)
1618{
0ba53171
CH		 1619 struct drm_device *dev = connector->dev;
1620 struct mga_device *mdev = (struct mga_device*)dev->dev_private;
0ba53171 1621 int bpp = 32;
0ba53171 1622
abbee623
JL		 1623 if (IS_G200_SE(mdev)) {
1624 if (mdev->unique_rev_id == 0x01) {
1625 if (mode->hdisplay > 1600)
1626 return MODE_VIRTUAL_X;
1627 if (mode->vdisplay > 1200)
1628 return MODE_VIRTUAL_Y;
1629 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1630 > (24400 * 1024))
1631 return MODE_BANDWIDTH;
e829d7ef 1632 } else if (mdev->unique_rev_id == 0x02) {
abbee623
JL		 1633 if (mode->hdisplay > 1920)
1634 return MODE_VIRTUAL_X;
1635 if (mode->vdisplay > 1200)
1636 return MODE_VIRTUAL_Y;
1637 if (mga_vga_calculate_mode_bandwidth(mode, bpp)
1638 > (30100 * 1024))
1639 return MODE_BANDWIDTH;
1640 }
1641 } else if (mdev->type == G200_WB) {
1642 if (mode->hdisplay > 1280)
1643 return MODE_VIRTUAL_X;
1644 if (mode->vdisplay > 1024)
1645 return MODE_VIRTUAL_Y;
1646 if (mga_vga_calculate_mode_bandwidth(mode,
1647 bpp > (31877 * 1024)))
1648 return MODE_BANDWIDTH;
1649 } else if (mdev->type == G200_EV &&
1650 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1651 > (32700 * 1024))) {
1652 return MODE_BANDWIDTH;
ec22b4aa 1653 } else if (mdev->type == G200_EH &&
abbee623
JL		 1654 (mga_vga_calculate_mode_bandwidth(mode, bpp)
1655 > (37500 * 1024))) {
1656 return MODE_BANDWIDTH;
ec22b4aa 1657 } else if (mdev->type == G200_ER &&
abbee623
JL		 1658 (mga_vga_calculate_mode_bandwidth(mode,
1659 bpp) > (55000 * 1024))) {
1660 return MODE_BANDWIDTH;
1661 }
414c4531 1662
25161084
AJ		 1663 if ((mode->hdisplay % 8) != 0 || (mode->hsync_start % 8) != 0 ||
1664 (mode->hsync_end % 8) != 0 || (mode->htotal % 8) != 0) {
1665 return MODE_H_ILLEGAL;
1666 }
1667
414c4531
DA		 1668 if (mode->crtc_hdisplay > 2048 || mode->crtc_hsync_start > 4096 ||
1669 mode->crtc_hsync_end > 4096 || mode->crtc_htotal > 4096 ||
1670 mode->crtc_vdisplay > 2048 || mode->crtc_vsync_start > 4096 ||
1671 mode->crtc_vsync_end > 4096 || mode->crtc_vtotal > 4096) {
1672 return MODE_BAD;
1673 }
1674
0ba53171 1675 /* Validate the mode input by the user */
eaf99c74
CW		 1676 if (connector->cmdline_mode.specified) {
1677 if (connector->cmdline_mode.bpp_specified)
1678 bpp = connector->cmdline_mode.bpp;
0ba53171
CH		 1679 }
1680
1681 if ((mode->hdisplay * mode->vdisplay * (bpp/8)) > mdev->mc.vram_size) {
eaf99c74
CW		 1682 if (connector->cmdline_mode.specified)
1683 connector->cmdline_mode.specified = false;
0ba53171
CH		 1684 return MODE_BAD;
1685 }
1686
414c4531
DA		 1687 return MODE_OK;
1688}
1689
080fd6b5 1690static struct drm_encoder *mga_connector_best_encoder(struct drm_connector
414c4531
DA		 1691 *connector)
1692{
1693 int enc_id = connector->encoder_ids[0];
414c4531 1694 /* pick the encoder ids */
c7e95114
RC		 1695 if (enc_id)
1696 return drm_encoder_find(connector->dev, enc_id);
414c4531
DA		 1697 return NULL;
1698}
1699
414c4531
DA		 1700static void mga_connector_destroy(struct drm_connector *connector)
1701{
1702 struct mga_connector *mga_connector = to_mga_connector(connector);
1703 mgag200_i2c_destroy(mga_connector->i2c);
1704 drm_connector_cleanup(connector);
1705 kfree(connector);
1706}
1707
71cb7495 1708static const struct drm_connector_helper_funcs mga_vga_connector_helper_funcs = {
414c4531
DA		 1709 .get_modes = mga_vga_get_modes,
1710 .mode_valid = mga_vga_mode_valid,
1711 .best_encoder = mga_connector_best_encoder,
1712};
1713
71cb7495 1714static const struct drm_connector_funcs mga_vga_connector_funcs = {
414c4531 1715 .dpms = drm_helper_connector_dpms,
414c4531
DA		 1716 .fill_modes = drm_helper_probe_single_connector_modes,
1717 .destroy = mga_connector_destroy,
1718};
1719
1720static struct drm_connector *mga_vga_init(struct drm_device *dev)
1721{
1722 struct drm_connector *connector;
1723 struct mga_connector *mga_connector;
1724
1725 mga_connector = kzalloc(sizeof(struct mga_connector), GFP_KERNEL);
1726 if (!mga_connector)
1727 return NULL;
1728
1729 connector = &mga_connector->base;
1730
1731 drm_connector_init(dev, connector,
1732 &mga_vga_connector_funcs, DRM_MODE_CONNECTOR_VGA);
1733
1734 drm_connector_helper_add(connector, &mga_vga_connector_helper_funcs);
1735
34ea3d38 1736 drm_connector_register(connector);
3d5a1c5e 1737
414c4531
DA		 1738 mga_connector->i2c = mgag200_i2c_create(dev);
1739 if (!mga_connector->i2c)
1740 DRM_ERROR("failed to add ddc bus\n");
1741
1742 return connector;
1743}
1744
1745
1746int mgag200_modeset_init(struct mga_device *mdev)
1747{
1748 struct drm_encoder *encoder;
1749 struct drm_connector *connector;
1750 int ret;
1751
1752 mdev->mode_info.mode_config_initialized = true;
1753
1754 mdev->dev->mode_config.max_width = MGAG200_MAX_FB_WIDTH;
1755 mdev->dev->mode_config.max_height = MGAG200_MAX_FB_HEIGHT;
1756
1757 mdev->dev->mode_config.fb_base = mdev->mc.vram_base;
1758
f1998fe2 1759 mga_crtc_init(mdev);
414c4531
DA		 1760
1761 encoder = mga_encoder_init(mdev->dev);
1762 if (!encoder) {
1763 DRM_ERROR("mga_encoder_init failed\n");
1764 return -1;
1765 }
1766
1767 connector = mga_vga_init(mdev->dev);
1768 if (!connector) {
1769 DRM_ERROR("mga_vga_init failed\n");
1770 return -1;
1771 }
1772
1773 drm_mode_connector_attach_encoder(connector, encoder);
1774
1775 ret = mgag200_fbdev_init(mdev);
1776 if (ret) {
1777 DRM_ERROR("mga_fbdev_init failed\n");
1778 return ret;
1779 }
1780
1781 return 0;
1782}
1783
1784void mgag200_modeset_fini(struct mga_device *mdev)
1785{
1786
1787}
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