[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / msm / adreno / adreno_gpu.c

/*
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <robdclark@gmail.com>
 *
 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "adreno_gpu.h"
#include "msm_gem.h"
#include "msm_mmu.h"

#define RB_SIZE    SZ_32K
#define RB_BLKSIZE 16

int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value)
{
	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);

	switch (param) {
	case MSM_PARAM_GPU_ID:
		*value = adreno_gpu->info->revn;
		return 0;
	case MSM_PARAM_GMEM_SIZE:
		*value = adreno_gpu->gmem;
		return 0;
	case MSM_PARAM_CHIP_ID:
		*value = adreno_gpu->rev.patchid |
				(adreno_gpu->rev.minor << 8) |
				(adreno_gpu->rev.major << 16) |
				(adreno_gpu->rev.core << 24);
		return 0;
	case MSM_PARAM_MAX_FREQ:
		*value = adreno_gpu->base.fast_rate;
		return 0;
	case MSM_PARAM_TIMESTAMP:
		if (adreno_gpu->funcs->get_timestamp)
			return adreno_gpu->funcs->get_timestamp(gpu, value);
		return -EINVAL;
	default:
		DBG("%s: invalid param: %u", gpu->name, param);
		return -EINVAL;
	}
}

#define rbmemptr(adreno_gpu, member)  \
	((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member))

int adreno_hw_init(struct msm_gpu *gpu)
{
	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	int ret;

	DBG("%s", gpu->name);

	ret = msm_gem_get_iova(gpu->rb->bo, gpu->id, &gpu->rb_iova);
	if (ret) {
		gpu->rb_iova = 0;
		dev_err(gpu->dev->dev, "could not map ringbuffer: %d\n", ret);
		return ret;
	}

	/* Setup REG_CP_RB_CNTL: */
	adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
			/* size is log2(quad-words): */
			AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) |
			AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)) |
			(adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));

	/* Setup ringbuffer address: */
	adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_BASE, gpu->rb_iova);

	if (!adreno_is_a430(adreno_gpu))
		adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
						rbmemptr(adreno_gpu, rptr));

	return 0;
}

static uint32_t get_wptr(struct msm_ringbuffer *ring)
{
	return ring->cur - ring->start;
}

/* Use this helper to read rptr, since a430 doesn't update rptr in memory */
static uint32_t get_rptr(struct adreno_gpu *adreno_gpu)
{
	if (adreno_is_a430(adreno_gpu))
		return adreno_gpu->memptrs->rptr = adreno_gpu_read(
			adreno_gpu, REG_ADRENO_CP_RB_RPTR);
	else
		return adreno_gpu->memptrs->rptr;
}

uint32_t adreno_last_fence(struct msm_gpu *gpu)
{
	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	return adreno_gpu->memptrs->fence;
}

void adreno_recover(struct msm_gpu *gpu)
{
	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	struct drm_device *dev = gpu->dev;
	int ret;

	gpu->funcs->pm_suspend(gpu);

	/* reset ringbuffer: */
	gpu->rb->cur = gpu->rb->start;

	/* reset completed fence seqno: */
	adreno_gpu->memptrs->fence = gpu->fctx->completed_fence;
	adreno_gpu->memptrs->rptr  = 0;
	adreno_gpu->memptrs->wptr  = 0;

	gpu->funcs->pm_resume(gpu);
	ret = gpu->funcs->hw_init(gpu);
	if (ret) {
		dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
		/* hmm, oh well? */
	}
}

void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
		struct msm_file_private *ctx)
{
	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	struct msm_drm_private *priv = gpu->dev->dev_private;
	struct msm_ringbuffer *ring = gpu->rb;
	unsigned i;

	for (i = 0; i < submit->nr_cmds; i++) {
		switch (submit->cmd[i].type) {
		case MSM_SUBMIT_CMD_IB_TARGET_BUF:
			/* ignore IB-targets */
			break;
		case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
			/* ignore if there has not been a ctx switch: */
			if (priv->lastctx == ctx)
				break;
		case MSM_SUBMIT_CMD_BUF:
			OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ?
				CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
			OUT_RING(ring, submit->cmd[i].iova);
			OUT_RING(ring, submit->cmd[i].size);
			OUT_PKT2(ring);
			break;
		}
	}

	OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
	OUT_RING(ring, submit->fence->seqno);

	if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) {
		/* Flush HLSQ lazy updates to make sure there is nothing
		 * pending for indirect loads after the timestamp has
		 * passed:
		 */
		OUT_PKT3(ring, CP_EVENT_WRITE, 1);
		OUT_RING(ring, HLSQ_FLUSH);

		OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
		OUT_RING(ring, 0x00000000);
	}

	OUT_PKT3(ring, CP_EVENT_WRITE, 3);
	OUT_RING(ring, CACHE_FLUSH_TS);
	OUT_RING(ring, rbmemptr(adreno_gpu, fence));
	OUT_RING(ring, submit->fence->seqno);

	/* we could maybe be clever and only CP_COND_EXEC the interrupt: */
	OUT_PKT3(ring, CP_INTERRUPT, 1);
	OUT_RING(ring, 0x80000000);

	/* Workaround for missing irq issue on 8x16/a306.  Unsure if the
	 * root cause is a platform issue or some a306 quirk, but this
	 * keeps things humming along:
	 */
	if (adreno_is_a306(adreno_gpu)) {
		OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
		OUT_RING(ring, 0x00000000);
		OUT_PKT3(ring, CP_INTERRUPT, 1);
		OUT_RING(ring, 0x80000000);
	}

#if 0
	if (adreno_is_a3xx(adreno_gpu)) {
		/* Dummy set-constant to trigger context rollover */
		OUT_PKT3(ring, CP_SET_CONSTANT, 2);
		OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
		OUT_RING(ring, 0x00000000);
	}
#endif

	gpu->funcs->flush(gpu);
}

void adreno_flush(struct msm_gpu *gpu)
{
	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	uint32_t wptr = get_wptr(gpu->rb);

	/* ensure writes to ringbuffer have hit system memory: */
	mb();

	adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
}

void adreno_idle(struct msm_gpu *gpu)
{
	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	uint32_t wptr = get_wptr(gpu->rb);
	int ret;

	/* wait for CP to drain ringbuffer: */
	ret = spin_until(get_rptr(adreno_gpu) == wptr);

	if (ret)
		DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name);

	/* TODO maybe we need to reset GPU here to recover from hang? */
}

#ifdef CONFIG_DEBUG_FS
void adreno_show(struct msm_gpu *gpu, struct seq_file *m)
{
	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	int i;

	seq_printf(m, "revision: %d (%d.%d.%d.%d)\n",
			adreno_gpu->info->revn, adreno_gpu->rev.core,
			adreno_gpu->rev.major, adreno_gpu->rev.minor,
			adreno_gpu->rev.patchid);

	seq_printf(m, "fence:    %d/%d\n", adreno_gpu->memptrs->fence,
			gpu->fctx->last_fence);
	seq_printf(m, "rptr:     %d\n", get_rptr(adreno_gpu));
	seq_printf(m, "wptr:     %d\n", adreno_gpu->memptrs->wptr);
	seq_printf(m, "rb wptr:  %d\n", get_wptr(gpu->rb));

	gpu->funcs->pm_resume(gpu);

	/* dump these out in a form that can be parsed by demsm: */
	seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->name);
	for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
		uint32_t start = adreno_gpu->registers[i];
		uint32_t end   = adreno_gpu->registers[i+1];
		uint32_t addr;

		for (addr = start; addr <= end; addr++) {
			uint32_t val = gpu_read(gpu, addr);
			seq_printf(m, "IO:R %08x %08x\n", addr<<2, val);
		}
	}

	gpu->funcs->pm_suspend(gpu);
}
#endif

/* Dump common gpu status and scratch registers on any hang, to make
 * the hangcheck logs more useful.  The scratch registers seem always
 * safe to read when GPU has hung (unlike some other regs, depending
 * on how the GPU hung), and they are useful to match up to cmdstream
 * dumps when debugging hangs:
 */
void adreno_dump_info(struct msm_gpu *gpu)
{
	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	int i;

	printk("revision: %d (%d.%d.%d.%d)\n",
			adreno_gpu->info->revn, adreno_gpu->rev.core,
			adreno_gpu->rev.major, adreno_gpu->rev.minor,
			adreno_gpu->rev.patchid);

	printk("fence:    %d/%d\n", adreno_gpu->memptrs->fence,
			gpu->fctx->last_fence);
	printk("rptr:     %d\n", get_rptr(adreno_gpu));
	printk("wptr:     %d\n", adreno_gpu->memptrs->wptr);
	printk("rb wptr:  %d\n", get_wptr(gpu->rb));

	for (i = 0; i < 8; i++) {
		printk("CP_SCRATCH_REG%d: %u\n", i,
			gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i));
	}
}

/* would be nice to not have to duplicate the _show() stuff with printk(): */
void adreno_dump(struct msm_gpu *gpu)
{
	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	int i;

	/* dump these out in a form that can be parsed by demsm: */
	printk("IO:region %s 00000000 00020000\n", gpu->name);
	for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
		uint32_t start = adreno_gpu->registers[i];
		uint32_t end   = adreno_gpu->registers[i+1];
		uint32_t addr;

		for (addr = start; addr <= end; addr++) {
			uint32_t val = gpu_read(gpu, addr);
			printk("IO:R %08x %08x\n", addr<<2, val);
		}
	}
}

static uint32_t ring_freewords(struct msm_gpu *gpu)
{
	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	uint32_t size = gpu->rb->size / 4;
	uint32_t wptr = get_wptr(gpu->rb);
	uint32_t rptr = get_rptr(adreno_gpu);
	return (rptr + (size - 1) - wptr) % size;
}

void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords)
{
	if (spin_until(ring_freewords(gpu) >= ndwords))
		DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name);
}

static const char *iommu_ports[] = {
		"gfx3d_user", "gfx3d_priv",
		"gfx3d1_user", "gfx3d1_priv",
};

int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
		struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs)
{
	struct adreno_platform_config *config = pdev->dev.platform_data;
	struct msm_gpu *gpu = &adreno_gpu->base;
	struct msm_mmu *mmu;
	int ret;

	adreno_gpu->funcs = funcs;
	adreno_gpu->info = adreno_info(config->rev);
	adreno_gpu->gmem = adreno_gpu->info->gmem;
	adreno_gpu->revn = adreno_gpu->info->revn;
	adreno_gpu->rev = config->rev;

	gpu->fast_rate = config->fast_rate;
	gpu->slow_rate = config->slow_rate;
	gpu->bus_freq  = config->bus_freq;
#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
	gpu->bus_scale_table = config->bus_scale_table;
#endif

	DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
			gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);

	ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
			adreno_gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq",
			RB_SIZE);
	if (ret)
		return ret;

	ret = request_firmware(&adreno_gpu->pm4, adreno_gpu->info->pm4fw, drm->dev);
	if (ret) {
		dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n",
				adreno_gpu->info->pm4fw, ret);
		return ret;
	}

	ret = request_firmware(&adreno_gpu->pfp, adreno_gpu->info->pfpfw, drm->dev);
	if (ret) {
		dev_err(drm->dev, "failed to load %s PFP firmware: %d\n",
				adreno_gpu->info->pfpfw, ret);
		return ret;
	}

	mmu = gpu->aspace->mmu;
	if (mmu) {
		ret = mmu->funcs->attach(mmu, iommu_ports,
				ARRAY_SIZE(iommu_ports));
		if (ret)
			return ret;
	}

	mutex_lock(&drm->struct_mutex);
	adreno_gpu->memptrs_bo = msm_gem_new(drm, sizeof(*adreno_gpu->memptrs),
			MSM_BO_UNCACHED);
	mutex_unlock(&drm->struct_mutex);
	if (IS_ERR(adreno_gpu->memptrs_bo)) {
		ret = PTR_ERR(adreno_gpu->memptrs_bo);
		adreno_gpu->memptrs_bo = NULL;
		dev_err(drm->dev, "could not allocate memptrs: %d\n", ret);
		return ret;
	}

	adreno_gpu->memptrs = msm_gem_get_vaddr(adreno_gpu->memptrs_bo);
	if (IS_ERR(adreno_gpu->memptrs)) {
		dev_err(drm->dev, "could not vmap memptrs\n");
		return -ENOMEM;
	}

	ret = msm_gem_get_iova(adreno_gpu->memptrs_bo, gpu->id,
			&adreno_gpu->memptrs_iova);
	if (ret) {
		dev_err(drm->dev, "could not map memptrs: %d\n", ret);
		return ret;
	}

	return 0;
}

void adreno_gpu_cleanup(struct adreno_gpu *gpu)
{
	if (gpu->memptrs_bo) {
		if (gpu->memptrs)
			msm_gem_put_vaddr(gpu->memptrs_bo);

		if (gpu->memptrs_iova)
			msm_gem_put_iova(gpu->memptrs_bo, gpu->base.id);

		drm_gem_object_unreference_unlocked(gpu->memptrs_bo);
	}
	release_firmware(gpu->pm4);
	release_firmware(gpu->pfp);
	msm_gpu_cleanup(&gpu->base);
}
Commit	Line	Data
7198e6b0 RC	1	/*
	2	* Copyright (C) 2013 Red Hat
	3	* Author: Rob Clark <robdclark@gmail.com>
	4	*
91b74e97 AG	5	* Copyright (c) 2014 The Linux Foundation. All rights reserved.
91b74e97 AG	6	*
7198e6b0 RC	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License version 2 as published by
	9	* the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "adreno_gpu.h"
	21	#include "msm_gem.h"
871d812a	22	#include "msm_mmu.h"
7198e6b0	23
7198e6b0 RC	24	#define RB_SIZE SZ_32K
	25	#define RB_BLKSIZE 16
	26
	27	int adreno_get_param(struct msm_gpu gpu, uint32_t param, uint64_t value)
	28	{
	29	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	30
	31	switch (param) {
	32	case MSM_PARAM_GPU_ID:
	33	*value = adreno_gpu->info->revn;
	34	return 0;
	35	case MSM_PARAM_GMEM_SIZE:
55459968	36	*value = adreno_gpu->gmem;
7198e6b0	37	return 0;
4e1cbaa3 RC	38	case MSM_PARAM_CHIP_ID:
	39	*value = adreno_gpu->rev.patchid \|
	40	(adreno_gpu->rev.minor << 8) \|
	41	(adreno_gpu->rev.major << 16) \|
	42	(adreno_gpu->rev.core << 24);
	43	return 0;
4102a9e5 RC	44	case MSM_PARAM_MAX_FREQ:
	45	*value = adreno_gpu->base.fast_rate;
	46	return 0;
6c77d1ab RC	47	case MSM_PARAM_TIMESTAMP:
	48	if (adreno_gpu->funcs->get_timestamp)
	49	return adreno_gpu->funcs->get_timestamp(gpu, value);
	50	return -EINVAL;
7198e6b0 RC	51	default:
	52	DBG("%s: invalid param: %u", gpu->name, param);
	53	return -EINVAL;
	54	}
	55	}
	56
	57	#define rbmemptr(adreno_gpu, member) \
	58	((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member))
	59
	60	int adreno_hw_init(struct msm_gpu *gpu)
	61	{
	62	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
944fc36c	63	int ret;
7198e6b0 RC	64
	65	DBG("%s", gpu->name);
	66
a1ad3523	67	ret = msm_gem_get_iova(gpu->rb->bo, gpu->id, &gpu->rb_iova);
944fc36c RC	68	if (ret) {
	69	gpu->rb_iova = 0;
	70	dev_err(gpu->dev->dev, "could not map ringbuffer: %d\n", ret);
	71	return ret;
	72	}
	73
7198e6b0	74	/* Setup REG_CP_RB_CNTL: */
91b74e97	75	adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_CNTL,
7198e6b0 RC	76	/* size is log2(quad-words): */
7198e6b0 RC	77	AXXX_CP_RB_CNTL_BUFSZ(ilog2(gpu->rb->size / 8)) \|
7d0c5ee9 CS	78	AXXX_CP_RB_CNTL_BLKSZ(ilog2(RB_BLKSIZE / 8)) \|
7d0c5ee9 CS	79	(adreno_is_a430(adreno_gpu) ? AXXX_CP_RB_CNTL_NO_UPDATE : 0));
7198e6b0 RC	80
7198e6b0 RC	81	/* Setup ringbuffer address: */
91b74e97	82	adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_BASE, gpu->rb_iova);
7198e6b0	83
7d0c5ee9 CS	84	if (!adreno_is_a430(adreno_gpu))
	85	adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_RPTR_ADDR,
	86	rbmemptr(adreno_gpu, rptr));
7198e6b0 RC	87
	88	return 0;
	89	}
	90
	91	static uint32_t get_wptr(struct msm_ringbuffer *ring)
	92	{
	93	return ring->cur - ring->start;
	94	}
	95
7d0c5ee9 CS	96	/* Use this helper to read rptr, since a430 doesn't update rptr in memory */
	97	static uint32_t get_rptr(struct adreno_gpu *adreno_gpu)
	98	{
	99	if (adreno_is_a430(adreno_gpu))
	100	return adreno_gpu->memptrs->rptr = adreno_gpu_read(
	101	adreno_gpu, REG_ADRENO_CP_RB_RPTR);
	102	else
	103	return adreno_gpu->memptrs->rptr;
	104	}
	105
7198e6b0 RC	106	uint32_t adreno_last_fence(struct msm_gpu *gpu)
	107	{
	108	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	109	return adreno_gpu->memptrs->fence;
	110	}
	111
bd6f82d8 RC	112	void adreno_recover(struct msm_gpu *gpu)
	113	{
	114	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	115	struct drm_device *dev = gpu->dev;
	116	int ret;
	117
	118	gpu->funcs->pm_suspend(gpu);
	119
	120	/* reset ringbuffer: */
	121	gpu->rb->cur = gpu->rb->start;
	122
27557343 RC	123	/* reset completed fence seqno: */
27557343 RC	124	adreno_gpu->memptrs->fence = gpu->fctx->completed_fence;
26791c48 RC	125	adreno_gpu->memptrs->rptr = 0;
26791c48 RC	126	adreno_gpu->memptrs->wptr = 0;
bd6f82d8 RC	127
	128	gpu->funcs->pm_resume(gpu);
	129	ret = gpu->funcs->hw_init(gpu);
	130	if (ret) {
	131	dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
	132	/* hmm, oh well? */
	133	}
	134	}
	135
1193c3bc	136	void adreno_submit(struct msm_gpu gpu, struct msm_gem_submit submit,
7198e6b0 RC	137	struct msm_file_private *ctx)
	138	{
	139	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	140	struct msm_drm_private *priv = gpu->dev->dev_private;
	141	struct msm_ringbuffer *ring = gpu->rb;
6b597ce2	142	unsigned i;
7198e6b0	143
7198e6b0 RC	144	for (i = 0; i < submit->nr_cmds; i++) {
	145	switch (submit->cmd[i].type) {
	146	case MSM_SUBMIT_CMD_IB_TARGET_BUF:
	147	/* ignore IB-targets */
	148	break;
	149	case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
	150	/* ignore if there has not been a ctx switch: */
	151	if (priv->lastctx == ctx)
	152	break;
	153	case MSM_SUBMIT_CMD_BUF:
357ff00b CS	154	OUT_PKT3(ring, adreno_is_a430(adreno_gpu) ?
357ff00b CS	155	CP_INDIRECT_BUFFER_PFE : CP_INDIRECT_BUFFER_PFD, 2);
7198e6b0 RC	156	OUT_RING(ring, submit->cmd[i].iova);
7198e6b0 RC	157	OUT_RING(ring, submit->cmd[i].size);
6b597ce2	158	OUT_PKT2(ring);
7198e6b0 RC	159	break;
	160	}
	161	}
	162
7198e6b0	163	OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);
b6295f9a	164	OUT_RING(ring, submit->fence->seqno);
7198e6b0	165
23bd62fd	166	if (adreno_is_a3xx(adreno_gpu) \|\| adreno_is_a4xx(adreno_gpu)) {
7198e6b0 RC	167	/* Flush HLSQ lazy updates to make sure there is nothing
	168	* pending for indirect loads after the timestamp has
	169	* passed:
	170	*/
	171	OUT_PKT3(ring, CP_EVENT_WRITE, 1);
	172	OUT_RING(ring, HLSQ_FLUSH);
	173
	174	OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
	175	OUT_RING(ring, 0x00000000);
	176	}
	177
	178	OUT_PKT3(ring, CP_EVENT_WRITE, 3);
	179	OUT_RING(ring, CACHE_FLUSH_TS);
	180	OUT_RING(ring, rbmemptr(adreno_gpu, fence));
b6295f9a	181	OUT_RING(ring, submit->fence->seqno);
7198e6b0 RC	182
	183	/* we could maybe be clever and only CP_COND_EXEC the interrupt: */
	184	OUT_PKT3(ring, CP_INTERRUPT, 1);
	185	OUT_RING(ring, 0x80000000);
	186
d735fdc3 RC	187	/* Workaround for missing irq issue on 8x16/a306. Unsure if the
	188	* root cause is a platform issue or some a306 quirk, but this
	189	* keeps things humming along:
	190	*/
	191	if (adreno_is_a306(adreno_gpu)) {
	192	OUT_PKT3(ring, CP_WAIT_FOR_IDLE, 1);
	193	OUT_RING(ring, 0x00000000);
	194	OUT_PKT3(ring, CP_INTERRUPT, 1);
	195	OUT_RING(ring, 0x80000000);
	196	}
	197
7198e6b0 RC	198	#if 0
	199	if (adreno_is_a3xx(adreno_gpu)) {
	200	/* Dummy set-constant to trigger context rollover */
	201	OUT_PKT3(ring, CP_SET_CONSTANT, 2);
	202	OUT_RING(ring, CP_REG(REG_A3XX_HLSQ_CL_KERNEL_GROUP_X_REG));
	203	OUT_RING(ring, 0x00000000);
	204	}
	205	#endif
	206
	207	gpu->funcs->flush(gpu);
7198e6b0 RC	208	}
	209
	210	void adreno_flush(struct msm_gpu *gpu)
	211	{
91b74e97	212	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
7198e6b0 RC	213	uint32_t wptr = get_wptr(gpu->rb);
	214
	215	/* ensure writes to ringbuffer have hit system memory: */
	216	mb();
	217
91b74e97	218	adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr);
7198e6b0 RC	219	}
	220
	221	void adreno_idle(struct msm_gpu *gpu)
	222	{
	223	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
0963756f	224	uint32_t wptr = get_wptr(gpu->rb);
7d0c5ee9	225	int ret;
7198e6b0	226
0963756f	227	/* wait for CP to drain ringbuffer: */
7d0c5ee9 CS	228	ret = spin_until(get_rptr(adreno_gpu) == wptr);
	229
	230	if (ret)
0963756f	231	DRM_ERROR("%s: timeout waiting to drain ringbuffer!\n", gpu->name);
7198e6b0 RC	232
	233	/* TODO maybe we need to reset GPU here to recover from hang? */
	234	}
	235
	236	#ifdef CONFIG_DEBUG_FS
	237	void adreno_show(struct msm_gpu gpu, struct seq_file m)
	238	{
	239	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
3bcefb04	240	int i;
7198e6b0 RC	241
	242	seq_printf(m, "revision: %d (%d.%d.%d.%d)\n",
	243	adreno_gpu->info->revn, adreno_gpu->rev.core,
	244	adreno_gpu->rev.major, adreno_gpu->rev.minor,
	245	adreno_gpu->rev.patchid);
	246
	247	seq_printf(m, "fence: %d/%d\n", adreno_gpu->memptrs->fence,
ca762a8a	248	gpu->fctx->last_fence);
7d0c5ee9	249	seq_printf(m, "rptr: %d\n", get_rptr(adreno_gpu));
7198e6b0 RC	250	seq_printf(m, "wptr: %d\n", adreno_gpu->memptrs->wptr);
7198e6b0 RC	251	seq_printf(m, "rb wptr: %d\n", get_wptr(gpu->rb));
3bcefb04 RC	252
	253	gpu->funcs->pm_resume(gpu);
	254
	255	/* dump these out in a form that can be parsed by demsm: */
	256	seq_printf(m, "IO:region %s 00000000 00020000\n", gpu->name);
	257	for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
	258	uint32_t start = adreno_gpu->registers[i];
	259	uint32_t end = adreno_gpu->registers[i+1];
	260	uint32_t addr;
	261
	262	for (addr = start; addr <= end; addr++) {
	263	uint32_t val = gpu_read(gpu, addr);
	264	seq_printf(m, "IO:R %08x %08x\n", addr<<2, val);
	265	}
	266	}
	267
	268	gpu->funcs->pm_suspend(gpu);
7198e6b0 RC	269	}
	270	#endif
	271
26716185 RC	272	/* Dump common gpu status and scratch registers on any hang, to make
	273	* the hangcheck logs more useful. The scratch registers seem always
	274	* safe to read when GPU has hung (unlike some other regs, depending
	275	* on how the GPU hung), and they are useful to match up to cmdstream
	276	* dumps when debugging hangs:
	277	*/
	278	void adreno_dump_info(struct msm_gpu *gpu)
5b6ef08e RC	279	{
5b6ef08e RC	280	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
3bcefb04	281	int i;
5b6ef08e RC	282
	283	printk("revision: %d (%d.%d.%d.%d)\n",
	284	adreno_gpu->info->revn, adreno_gpu->rev.core,
	285	adreno_gpu->rev.major, adreno_gpu->rev.minor,
	286	adreno_gpu->rev.patchid);
	287
	288	printk("fence: %d/%d\n", adreno_gpu->memptrs->fence,
ca762a8a	289	gpu->fctx->last_fence);
7d0c5ee9	290	printk("rptr: %d\n", get_rptr(adreno_gpu));
5b6ef08e RC	291	printk("wptr: %d\n", adreno_gpu->memptrs->wptr);
	292	printk("rb wptr: %d\n", get_wptr(gpu->rb));
	293
26716185 RC	294	for (i = 0; i < 8; i++) {
	295	printk("CP_SCRATCH_REG%d: %u\n", i,
	296	gpu_read(gpu, REG_AXXX_CP_SCRATCH_REG0 + i));
	297	}
	298	}
	299
	300	/* would be nice to not have to duplicate the _show() stuff with printk(): */
	301	void adreno_dump(struct msm_gpu *gpu)
	302	{
	303	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
	304	int i;
	305
3bcefb04 RC	306	/* dump these out in a form that can be parsed by demsm: */
	307	printk("IO:region %s 00000000 00020000\n", gpu->name);
	308	for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) {
	309	uint32_t start = adreno_gpu->registers[i];
	310	uint32_t end = adreno_gpu->registers[i+1];
	311	uint32_t addr;
	312
	313	for (addr = start; addr <= end; addr++) {
	314	uint32_t val = gpu_read(gpu, addr);
	315	printk("IO:R %08x %08x\n", addr<<2, val);
	316	}
	317	}
5b6ef08e RC	318	}
5b6ef08e RC	319
0963756f	320	static uint32_t ring_freewords(struct msm_gpu *gpu)
7198e6b0 RC	321	{
7198e6b0 RC	322	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
0963756f RC	323	uint32_t size = gpu->rb->size / 4;
0963756f RC	324	uint32_t wptr = get_wptr(gpu->rb);
7d0c5ee9	325	uint32_t rptr = get_rptr(adreno_gpu);
0963756f RC	326	return (rptr + (size - 1) - wptr) % size;
	327	}
	328
	329	void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords)
	330	{
	331	if (spin_until(ring_freewords(gpu) >= ndwords))
	332	DRM_ERROR("%s: timeout waiting for ringbuffer space\n", gpu->name);
7198e6b0 RC	333	}
	334
	335	static const char *iommu_ports[] = {
	336	"gfx3d_user", "gfx3d_priv",
	337	"gfx3d1_user", "gfx3d1_priv",
	338	};
	339
7198e6b0	340	int adreno_gpu_init(struct drm_device drm, struct platform_device pdev,
3526e9fb	341	struct adreno_gpu adreno_gpu, const struct adreno_gpu_funcs funcs)
7198e6b0	342	{
3526e9fb RC	343	struct adreno_platform_config *config = pdev->dev.platform_data;
3526e9fb RC	344	struct msm_gpu *gpu = &adreno_gpu->base;
871d812a	345	struct msm_mmu *mmu;
e2550b7a	346	int ret;
7198e6b0	347
3526e9fb RC	348	adreno_gpu->funcs = funcs;
	349	adreno_gpu->info = adreno_info(config->rev);
	350	adreno_gpu->gmem = adreno_gpu->info->gmem;
	351	adreno_gpu->revn = adreno_gpu->info->revn;
	352	adreno_gpu->rev = config->rev;
	353
	354	gpu->fast_rate = config->fast_rate;
	355	gpu->slow_rate = config->slow_rate;
	356	gpu->bus_freq = config->bus_freq;
6490ad47	357	#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
3526e9fb RC	358	gpu->bus_scale_table = config->bus_scale_table;
	359	#endif
	360
	361	DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
	362	gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
7198e6b0	363
0122f96f RC	364	ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
	365	adreno_gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq",
	366	RB_SIZE);
	367	if (ret)
	368	return ret;
	369
3526e9fb	370	ret = request_firmware(&adreno_gpu->pm4, adreno_gpu->info->pm4fw, drm->dev);
7198e6b0 RC	371	if (ret) {
7198e6b0 RC	372	dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n",
3526e9fb	373	adreno_gpu->info->pm4fw, ret);
7198e6b0 RC	374	return ret;
	375	}
	376
3526e9fb	377	ret = request_firmware(&adreno_gpu->pfp, adreno_gpu->info->pfpfw, drm->dev);
7198e6b0 RC	378	if (ret) {
7198e6b0 RC	379	dev_err(drm->dev, "failed to load %s PFP firmware: %d\n",
3526e9fb	380	adreno_gpu->info->pfpfw, ret);
7198e6b0 RC	381	return ret;
	382	}
	383
667ce33e	384	mmu = gpu->aspace->mmu;
871d812a RC	385	if (mmu) {
	386	ret = mmu->funcs->attach(mmu, iommu_ports,
	387	ARRAY_SIZE(iommu_ports));
	388	if (ret)
	389	return ret;
	390	}
7198e6b0	391
a1ad3523	392	mutex_lock(&drm->struct_mutex);
3526e9fb	393	adreno_gpu->memptrs_bo = msm_gem_new(drm, sizeof(*adreno_gpu->memptrs),
7198e6b0	394	MSM_BO_UNCACHED);
a1ad3523	395	mutex_unlock(&drm->struct_mutex);
3526e9fb RC	396	if (IS_ERR(adreno_gpu->memptrs_bo)) {
	397	ret = PTR_ERR(adreno_gpu->memptrs_bo);
	398	adreno_gpu->memptrs_bo = NULL;
7198e6b0 RC	399	dev_err(drm->dev, "could not allocate memptrs: %d\n", ret);
	400	return ret;
	401	}
	402
18f23049	403	adreno_gpu->memptrs = msm_gem_get_vaddr(adreno_gpu->memptrs_bo);
69a834c2	404	if (IS_ERR(adreno_gpu->memptrs)) {
7198e6b0 RC	405	dev_err(drm->dev, "could not vmap memptrs\n");
	406	return -ENOMEM;
	407	}
	408
3526e9fb RC	409	ret = msm_gem_get_iova(adreno_gpu->memptrs_bo, gpu->id,
3526e9fb RC	410	&adreno_gpu->memptrs_iova);
7198e6b0 RC	411	if (ret) {
	412	dev_err(drm->dev, "could not map memptrs: %d\n", ret);
	413	return ret;
	414	}
	415
	416	return 0;
	417	}
	418
	419	void adreno_gpu_cleanup(struct adreno_gpu *gpu)
	420	{
	421	if (gpu->memptrs_bo) {
18f23049 RC	422	if (gpu->memptrs)
	423	msm_gem_put_vaddr(gpu->memptrs_bo);
	424
7198e6b0 RC	425	if (gpu->memptrs_iova)
7198e6b0 RC	426	msm_gem_put_iova(gpu->memptrs_bo, gpu->base.id);
18f23049	427
774449eb	428	drm_gem_object_unreference_unlocked(gpu->memptrs_bo);
7198e6b0	429	}
5acb07ea ME	430	release_firmware(gpu->pm4);
5acb07ea ME	431	release_firmware(gpu->pfp);
7198e6b0 RC	432	msm_gpu_cleanup(&gpu->base);
7198e6b0 RC	433	}