[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / msm / adreno / adreno_gpu.h

/*
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <robdclark@gmail.com>
 *
 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __ADRENO_GPU_H__
#define __ADRENO_GPU_H__

#include <linux/firmware.h>

#include "msm_gpu.h"

#include "adreno_common.xml.h"
#include "adreno_pm4.xml.h"

#define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
#define REG_SKIP ~0
#define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP

/**
 * adreno_regs: List of registers that are used in across all
 * 3D devices. Each device type has different offset value for the same
 * register, so an array of register offsets are declared for every device
 * and are indexed by the enumeration values defined in this enum
 */
enum adreno_regs {
	REG_ADRENO_CP_RB_BASE,
	REG_ADRENO_CP_RB_BASE_HI,
	REG_ADRENO_CP_RB_RPTR_ADDR,
	REG_ADRENO_CP_RB_RPTR_ADDR_HI,
	REG_ADRENO_CP_RB_RPTR,
	REG_ADRENO_CP_RB_WPTR,
	REG_ADRENO_CP_RB_CNTL,
	REG_ADRENO_REGISTER_MAX,
};

enum adreno_quirks {
	ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
	ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
};

struct adreno_rev {
	uint8_t  core;
	uint8_t  major;
	uint8_t  minor;
	uint8_t  patchid;
};

#define ADRENO_REV(core, major, minor, patchid) \
	((struct adreno_rev){ core, major, minor, patchid })

struct adreno_gpu_funcs {
	struct msm_gpu_funcs base;
	int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
};

struct adreno_info {
	struct adreno_rev rev;
	uint32_t revn;
	const char *name;
	const char *pm4fw, *pfpfw;
	uint32_t gmem;
	struct msm_gpu *(*init)(struct drm_device *dev);
};

const struct adreno_info *adreno_info(struct adreno_rev rev);

#define rbmemptr(adreno_gpu, member)  \
	((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member))

struct adreno_rbmemptrs {
	volatile uint32_t rptr;
	volatile uint32_t wptr;
	volatile uint32_t fence;
};

struct adreno_gpu {
	struct msm_gpu base;
	struct adreno_rev rev;
	const struct adreno_info *info;
	uint32_t gmem;  /* actual gmem size */
	uint32_t revn;  /* numeric revision name */
	const struct adreno_gpu_funcs *funcs;

	/* interesting register offsets to dump: */
	const unsigned int *registers;

	/* firmware: */
	const struct firmware *pm4, *pfp;

	/* ringbuffer rptr/wptr: */
	// TODO should this be in msm_ringbuffer?  I think it would be
	// different for z180..
	struct adreno_rbmemptrs *memptrs;
	struct drm_gem_object *memptrs_bo;
	uint64_t memptrs_iova;

	/*
	 * Register offsets are different between some GPUs.
	 * GPU specific offsets will be exported by GPU specific
	 * code (a3xx_gpu.c) and stored in this common location.
	 */
	const unsigned int *reg_offsets;

	uint32_t quirks;
};
#define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)

/* platform config data (ie. from DT, or pdata) */
struct adreno_platform_config {
	struct adreno_rev rev;
	uint32_t fast_rate, slow_rate, bus_freq;
#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
	struct msm_bus_scale_pdata *bus_scale_table;
#endif
	uint32_t quirks;
};

#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)

#define spin_until(X) ({                                   \
	int __ret = -ETIMEDOUT;                            \
	unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
	do {                                               \
		if (X) {                                   \
			__ret = 0;                         \
			break;                             \
		}                                          \
	} while (time_before(jiffies, __t));               \
	__ret;                                             \
})


static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
{
	return (gpu->revn >= 300) && (gpu->revn < 400);
}

static inline bool adreno_is_a305(struct adreno_gpu *gpu)
{
	return gpu->revn == 305;
}

static inline bool adreno_is_a306(struct adreno_gpu *gpu)
{
	/* yes, 307, because a305c is 306 */
	return gpu->revn == 307;
}

static inline bool adreno_is_a320(struct adreno_gpu *gpu)
{
	return gpu->revn == 320;
}

static inline bool adreno_is_a330(struct adreno_gpu *gpu)
{
	return gpu->revn == 330;
}

static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
{
	return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
}

static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
{
	return (gpu->revn >= 400) && (gpu->revn < 500);
}

static inline int adreno_is_a420(struct adreno_gpu *gpu)
{
	return gpu->revn == 420;
}

static inline int adreno_is_a430(struct adreno_gpu *gpu)
{
       return gpu->revn == 430;
}

static inline int adreno_is_a530(struct adreno_gpu *gpu)
{
	return gpu->revn == 530;
}

int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
int adreno_hw_init(struct msm_gpu *gpu);
uint32_t adreno_last_fence(struct msm_gpu *gpu);
void adreno_recover(struct msm_gpu *gpu);
void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
		struct msm_file_private *ctx);
void adreno_flush(struct msm_gpu *gpu);
bool adreno_idle(struct msm_gpu *gpu);
#ifdef CONFIG_DEBUG_FS
void adreno_show(struct msm_gpu *gpu, struct seq_file *m);
#endif
void adreno_dump_info(struct msm_gpu *gpu);
void adreno_dump(struct msm_gpu *gpu);
void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords);

int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
		struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs);
void adreno_gpu_cleanup(struct adreno_gpu *gpu);


/* ringbuffer helpers (the parts that are adreno specific) */

static inline void
OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
{
	adreno_wait_ring(ring->gpu, cnt+1);
	OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
}

/* no-op packet: */
static inline void
OUT_PKT2(struct msm_ringbuffer *ring)
{
	adreno_wait_ring(ring->gpu, 1);
	OUT_RING(ring, CP_TYPE2_PKT);
}

static inline void
OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
{
	adreno_wait_ring(ring->gpu, cnt+1);
	OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
}

static inline u32 PM4_PARITY(u32 val)
{
	return (0x9669 >> (0xF & (val ^
		(val >> 4) ^ (val >> 8) ^ (val >> 12) ^
		(val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
		(val >> 28)))) & 1;
}

/* Maximum number of values that can be executed for one opcode */
#define TYPE4_MAX_PAYLOAD 127

#define PKT4(_reg, _cnt) \
	(CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
	 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))

static inline void
OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
{
	adreno_wait_ring(ring->gpu, cnt + 1);
	OUT_RING(ring, PKT4(regindx, cnt));
}

static inline void
OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
{
	adreno_wait_ring(ring->gpu, cnt + 1);
	OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
		((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
}

/*
 * adreno_reg_check() - Checks the validity of a register enum
 * @gpu:		Pointer to struct adreno_gpu
 * @offset_name:	The register enum that is checked
 */
static inline bool adreno_reg_check(struct adreno_gpu *gpu,
		enum adreno_regs offset_name)
{
	if (offset_name >= REG_ADRENO_REGISTER_MAX ||
			!gpu->reg_offsets[offset_name]) {
		BUG();
	}

	/*
	 * REG_SKIP is a special value that tell us that the register in
	 * question isn't implemented on target but don't trigger a BUG(). This
	 * is used to cleanly implement adreno_gpu_write64() and
	 * adreno_gpu_read64() in a generic fashion
	 */
	if (gpu->reg_offsets[offset_name] == REG_SKIP)
		return false;

	return true;
}

static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
		enum adreno_regs offset_name)
{
	u32 reg = gpu->reg_offsets[offset_name];
	u32 val = 0;
	if(adreno_reg_check(gpu,offset_name))
		val = gpu_read(&gpu->base, reg - 1);
	return val;
}

static inline void adreno_gpu_write(struct adreno_gpu *gpu,
		enum adreno_regs offset_name, u32 data)
{
	u32 reg = gpu->reg_offsets[offset_name];
	if(adreno_reg_check(gpu, offset_name))
		gpu_write(&gpu->base, reg - 1, data);
}

struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);

static inline void adreno_gpu_write64(struct adreno_gpu *gpu,
		enum adreno_regs lo, enum adreno_regs hi, u64 data)
{
	adreno_gpu_write(gpu, lo, lower_32_bits(data));
	adreno_gpu_write(gpu, hi, upper_32_bits(data));
}

/*
 * Given a register and a count, return a value to program into
 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
 * registers starting at _reg.
 *
 * The register base needs to be a multiple of the length. If it is not, the
 * hardware will quietly mask off the bits for you and shift the size. For
 * example, if you intend the protection to start at 0x07 for a length of 4
 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
 * expose registers you intended to protect!
 */
#define ADRENO_PROTECT_RW(_reg, _len) \
	((1 << 30) | (1 << 29) | \
	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))

/*
 * Same as above, but allow reads over the range. For areas of mixed use (such
 * as performance counters) this allows us to protect a much larger range with a
 * single register
 */
#define ADRENO_PROTECT_RDONLY(_reg, _len) \
	((1 << 29) \
	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))

#endif /* __ADRENO_GPU_H__ */
Commit	Line	Data
7198e6b0 RC	1	/*
	2	* Copyright (C) 2013 Red Hat
	3	* Author: Rob Clark <robdclark@gmail.com>
	4	*
91b74e97 AG	5	* Copyright (c) 2014 The Linux Foundation. All rights reserved.
91b74e97 AG	6	*
7198e6b0 RC	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License version 2 as published by
	9	* the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#ifndef __ADRENO_GPU_H__
	21	#define __ADRENO_GPU_H__
	22
	23	#include <linux/firmware.h>
	24
	25	#include "msm_gpu.h"
	26
	27	#include "adreno_common.xml.h"
	28	#include "adreno_pm4.xml.h"
	29
91b74e97	30	#define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
fb039981 JC	31	#define REG_SKIP ~0
	32	#define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP
	33
91b74e97 AG	34	/**
	35	* adreno_regs: List of registers that are used in across all
	36	* 3D devices. Each device type has different offset value for the same
	37	* register, so an array of register offsets are declared for every device
	38	* and are indexed by the enumeration values defined in this enum
	39	*/
	40	enum adreno_regs {
91b74e97	41	REG_ADRENO_CP_RB_BASE,
fb039981	42	REG_ADRENO_CP_RB_BASE_HI,
91b74e97	43	REG_ADRENO_CP_RB_RPTR_ADDR,
fb039981	44	REG_ADRENO_CP_RB_RPTR_ADDR_HI,
91b74e97 AG	45	REG_ADRENO_CP_RB_RPTR,
91b74e97 AG	46	REG_ADRENO_CP_RB_WPTR,
91b74e97	47	REG_ADRENO_CP_RB_CNTL,
91b74e97 AG	48	REG_ADRENO_REGISTER_MAX,
	49	};
	50
b5f103ab JC	51	enum adreno_quirks {
	52	ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
	53	ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
	54	};
	55
7198e6b0 RC	56	struct adreno_rev {
	57	uint8_t core;
	58	uint8_t major;
	59	uint8_t minor;
	60	uint8_t patchid;
	61	};
	62
	63	#define ADRENO_REV(core, major, minor, patchid) \
	64	((struct adreno_rev){ core, major, minor, patchid })
	65
	66	struct adreno_gpu_funcs {
	67	struct msm_gpu_funcs base;
6c77d1ab	68	int (get_timestamp)(struct msm_gpu gpu, uint64_t *value);
7198e6b0 RC	69	};
7198e6b0 RC	70
e2550b7a RC	71	struct adreno_info {
	72	struct adreno_rev rev;
	73	uint32_t revn;
	74	const char *name;
	75	const char pm4fw, pfpfw;
	76	uint32_t gmem;
	77	struct msm_gpu (init)(struct drm_device *dev);
	78	};
	79
	80	const struct adreno_info *adreno_info(struct adreno_rev rev);
7198e6b0	81
b5f103ab JC	82	#define rbmemptr(adreno_gpu, member) \
	83	((adreno_gpu)->memptrs_iova + offsetof(struct adreno_rbmemptrs, member))
	84
7198e6b0 RC	85	struct adreno_rbmemptrs {
	86	volatile uint32_t rptr;
	87	volatile uint32_t wptr;
	88	volatile uint32_t fence;
	89	};
	90
	91	struct adreno_gpu {
	92	struct msm_gpu base;
	93	struct adreno_rev rev;
	94	const struct adreno_info *info;
55459968	95	uint32_t gmem; /* actual gmem size */
7198e6b0 RC	96	uint32_t revn; /* numeric revision name */
	97	const struct adreno_gpu_funcs *funcs;
	98
3bcefb04 RC	99	/* interesting register offsets to dump: */
	100	const unsigned int *registers;
	101
7198e6b0 RC	102	/* firmware: */
	103	const struct firmware pm4, pfp;
	104
	105	/* ringbuffer rptr/wptr: */
	106	// TODO should this be in msm_ringbuffer? I think it would be
	107	// different for z180..
	108	struct adreno_rbmemptrs *memptrs;
	109	struct drm_gem_object *memptrs_bo;
78babc16	110	uint64_t memptrs_iova;
91b74e97 AG	111
	112	/*
	113	* Register offsets are different between some GPUs.
	114	* GPU specific offsets will be exported by GPU specific
	115	* code (a3xx_gpu.c) and stored in this common location.
	116	*/
	117	const unsigned int *reg_offsets;
b5f103ab JC	118
b5f103ab JC	119	uint32_t quirks;
7198e6b0 RC	120	};
	121	#define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
	122
	123	/* platform config data (ie. from DT, or pdata) */
	124	struct adreno_platform_config {
	125	struct adreno_rev rev;
	126	uint32_t fast_rate, slow_rate, bus_freq;
6490ad47	127	#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
bf2b33af RC	128	struct msm_bus_scale_pdata *bus_scale_table;
bf2b33af RC	129	#endif
b5f103ab	130	uint32_t quirks;
7198e6b0 RC	131	};
7198e6b0 RC	132
0963756f RC	133	#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
	134
	135	#define spin_until(X) ({ \
	136	int __ret = -ETIMEDOUT; \
	137	unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
	138	do { \
	139	if (X) { \
	140	__ret = 0; \
	141	break; \
	142	} \
	143	} while (time_before(jiffies, __t)); \
	144	__ret; \
	145	})
	146
7198e6b0 RC	147
	148	static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
	149	{
	150	return (gpu->revn >= 300) && (gpu->revn < 400);
	151	}
	152
	153	static inline bool adreno_is_a305(struct adreno_gpu *gpu)
	154	{
	155	return gpu->revn == 305;
	156	}
	157
de558cd2 RC	158	static inline bool adreno_is_a306(struct adreno_gpu *gpu)
	159	{
	160	/* yes, 307, because a305c is 306 */
	161	return gpu->revn == 307;
	162	}
	163
7198e6b0 RC	164	static inline bool adreno_is_a320(struct adreno_gpu *gpu)
	165	{
	166	return gpu->revn == 320;
	167	}
	168
	169	static inline bool adreno_is_a330(struct adreno_gpu *gpu)
	170	{
	171	return gpu->revn == 330;
	172	}
	173
55459968 RC	174	static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
	175	{
	176	return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
	177	}
	178
23bd62fd AG	179	static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
	180	{
	181	return (gpu->revn >= 400) && (gpu->revn < 500);
	182	}
	183
	184	static inline int adreno_is_a420(struct adreno_gpu *gpu)
	185	{
	186	return gpu->revn == 420;
	187	}
	188
357ff00b CS	189	static inline int adreno_is_a430(struct adreno_gpu *gpu)
	190	{
	191	return gpu->revn == 430;
	192	}
	193
b5f103ab JC	194	static inline int adreno_is_a530(struct adreno_gpu *gpu)
	195	{
	196	return gpu->revn == 530;
	197	}
	198
7198e6b0 RC	199	int adreno_get_param(struct msm_gpu gpu, uint32_t param, uint64_t value);
	200	int adreno_hw_init(struct msm_gpu *gpu);
	201	uint32_t adreno_last_fence(struct msm_gpu *gpu);
bd6f82d8	202	void adreno_recover(struct msm_gpu *gpu);
1193c3bc	203	void adreno_submit(struct msm_gpu gpu, struct msm_gem_submit submit,
7198e6b0 RC	204	struct msm_file_private *ctx);
7198e6b0 RC	205	void adreno_flush(struct msm_gpu *gpu);
c4a8d475	206	bool adreno_idle(struct msm_gpu *gpu);
7198e6b0 RC	207	#ifdef CONFIG_DEBUG_FS
	208	void adreno_show(struct msm_gpu gpu, struct seq_file m);
	209	#endif
26716185	210	void adreno_dump_info(struct msm_gpu *gpu);
5b6ef08e	211	void adreno_dump(struct msm_gpu *gpu);
7198e6b0 RC	212	void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords);
	213
	214	int adreno_gpu_init(struct drm_device drm, struct platform_device pdev,
3526e9fb	215	struct adreno_gpu gpu, const struct adreno_gpu_funcs funcs);
7198e6b0 RC	216	void adreno_gpu_cleanup(struct adreno_gpu *gpu);
	217
	218
	219	/* ringbuffer helpers (the parts that are adreno specific) */
	220
	221	static inline void
	222	OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
	223	{
	224	adreno_wait_ring(ring->gpu, cnt+1);
	225	OUT_RING(ring, CP_TYPE0_PKT \| ((cnt-1) << 16) \| (regindx & 0x7FFF));
	226	}
	227
	228	/* no-op packet: */
	229	static inline void
	230	OUT_PKT2(struct msm_ringbuffer *ring)
	231	{
	232	adreno_wait_ring(ring->gpu, 1);
	233	OUT_RING(ring, CP_TYPE2_PKT);
	234	}
	235
	236	static inline void
	237	OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
	238	{
	239	adreno_wait_ring(ring->gpu, cnt+1);
	240	OUT_RING(ring, CP_TYPE3_PKT \| ((cnt-1) << 16) \| ((opcode & 0xFF) << 8));
	241	}
	242
05b9401b JC	243	static inline u32 PM4_PARITY(u32 val)
	244	{
	245	return (0x9669 >> (0xF & (val ^
	246	(val >> 4) ^ (val >> 8) ^ (val >> 12) ^
	247	(val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
	248	(val >> 28)))) & 1;
	249	}
	250
	251	/* Maximum number of values that can be executed for one opcode */
	252	#define TYPE4_MAX_PAYLOAD 127
	253
	254	#define PKT4(_reg, _cnt) \
	255	(CP_TYPE4_PKT \| ((_cnt) << 0) \| (PM4_PARITY((_cnt)) << 7) \| \
	256	(((_reg) & 0x3FFFF) << 8) \| (PM4_PARITY((_reg)) << 27))
	257
	258	static inline void
	259	OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
	260	{
	261	adreno_wait_ring(ring->gpu, cnt + 1);
	262	OUT_RING(ring, PKT4(regindx, cnt));
	263	}
	264
	265	static inline void
	266	OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
	267	{
	268	adreno_wait_ring(ring->gpu, cnt + 1);
	269	OUT_RING(ring, CP_TYPE7_PKT \| (cnt << 0) \| (PM4_PARITY(cnt) << 15) \|
	270	((opcode & 0x7F) << 16) \| (PM4_PARITY(opcode) << 23));
	271	}
	272
91b74e97	273	/*
fb039981	274	* adreno_reg_check() - Checks the validity of a register enum
91b74e97 AG	275	* @gpu: Pointer to struct adreno_gpu
	276	* @offset_name: The register enum that is checked
	277	*/
	278	static inline bool adreno_reg_check(struct adreno_gpu *gpu,
	279	enum adreno_regs offset_name)
	280	{
	281	if (offset_name >= REG_ADRENO_REGISTER_MAX \|\|
	282	!gpu->reg_offsets[offset_name]) {
	283	BUG();
	284	}
fb039981 JC	285
	286	/*
	287	* REG_SKIP is a special value that tell us that the register in
	288	* question isn't implemented on target but don't trigger a BUG(). This
	289	* is used to cleanly implement adreno_gpu_write64() and
	290	* adreno_gpu_read64() in a generic fashion
	291	*/
	292	if (gpu->reg_offsets[offset_name] == REG_SKIP)
	293	return false;
	294
91b74e97 AG	295	return true;
	296	}
	297
	298	static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
	299	enum adreno_regs offset_name)
	300	{
	301	u32 reg = gpu->reg_offsets[offset_name];
	302	u32 val = 0;
	303	if(adreno_reg_check(gpu,offset_name))
	304	val = gpu_read(&gpu->base, reg - 1);
	305	return val;
	306	}
	307
	308	static inline void adreno_gpu_write(struct adreno_gpu *gpu,
	309	enum adreno_regs offset_name, u32 data)
	310	{
	311	u32 reg = gpu->reg_offsets[offset_name];
	312	if(adreno_reg_check(gpu, offset_name))
	313	gpu_write(&gpu->base, reg - 1, data);
	314	}
7198e6b0	315
a5725ab0 BX	316	struct msm_gpu a3xx_gpu_init(struct drm_device dev);
a5725ab0 BX	317	struct msm_gpu a4xx_gpu_init(struct drm_device dev);
b5f103ab	318	struct msm_gpu a5xx_gpu_init(struct drm_device dev);
a5725ab0	319
fb039981 JC	320	static inline void adreno_gpu_write64(struct adreno_gpu *gpu,
	321	enum adreno_regs lo, enum adreno_regs hi, u64 data)
	322	{
	323	adreno_gpu_write(gpu, lo, lower_32_bits(data));
	324	adreno_gpu_write(gpu, hi, upper_32_bits(data));
	325	}
	326
b5f103ab JC	327	/*
	328	* Given a register and a count, return a value to program into
	329	* REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
	330	* registers starting at _reg.
	331	*
	332	* The register base needs to be a multiple of the length. If it is not, the
	333	* hardware will quietly mask off the bits for you and shift the size. For
	334	* example, if you intend the protection to start at 0x07 for a length of 4
	335	* (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
	336	* expose registers you intended to protect!
	337	*/
	338	#define ADRENO_PROTECT_RW(_reg, _len) \
	339	((1 << 30) \| (1 << 29) \| \
	340	((ilog2((_len)) & 0x1F) << 24) \| (((_reg) << 2) & 0xFFFFF))
	341
	342	/*
	343	* Same as above, but allow reads over the range. For areas of mixed use (such
	344	* as performance counters) this allows us to protect a much larger range with a
	345	* single register
	346	*/
	347	#define ADRENO_PROTECT_RDONLY(_reg, _len) \
	348	((1 << 29) \
	349	((ilog2((_len)) & 0x1F) << 24) \| (((_reg) << 2) & 0xFFFFF))
	350
7198e6b0	351	#endif /* __ADRENO_GPU_H__ */