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25fdd593 JS |
1 | /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. |
2 | * | |
3 | * This program is free software; you can redistribute it and/or modify | |
4 | * it under the terms of the GNU General Public License version 2 and | |
5 | * only version 2 as published by the Free Software Foundation. | |
6 | * | |
7 | * This program is distributed in the hope that it will be useful, | |
8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
10 | * GNU General Public License for more details. | |
11 | */ | |
12 | ||
13 | #include <linux/iopoll.h> | |
14 | ||
15 | #include "dpu_hw_mdss.h" | |
16 | #include "dpu_hwio.h" | |
17 | #include "dpu_hw_catalog.h" | |
18 | #include "dpu_hw_pingpong.h" | |
25fdd593 JS |
19 | #include "dpu_kms.h" |
20 | #include "dpu_trace.h" | |
21 | ||
22 | #define PP_TEAR_CHECK_EN 0x000 | |
23 | #define PP_SYNC_CONFIG_VSYNC 0x004 | |
24 | #define PP_SYNC_CONFIG_HEIGHT 0x008 | |
25 | #define PP_SYNC_WRCOUNT 0x00C | |
26 | #define PP_VSYNC_INIT_VAL 0x010 | |
27 | #define PP_INT_COUNT_VAL 0x014 | |
28 | #define PP_SYNC_THRESH 0x018 | |
29 | #define PP_START_POS 0x01C | |
30 | #define PP_RD_PTR_IRQ 0x020 | |
31 | #define PP_WR_PTR_IRQ 0x024 | |
32 | #define PP_OUT_LINE_COUNT 0x028 | |
33 | #define PP_LINE_COUNT 0x02C | |
34 | ||
35 | #define PP_FBC_MODE 0x034 | |
36 | #define PP_FBC_BUDGET_CTL 0x038 | |
37 | #define PP_FBC_LOSSY_MODE 0x03C | |
38 | ||
39 | static struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp, | |
40 | struct dpu_mdss_cfg *m, | |
41 | void __iomem *addr, | |
42 | struct dpu_hw_blk_reg_map *b) | |
43 | { | |
44 | int i; | |
45 | ||
46 | for (i = 0; i < m->pingpong_count; i++) { | |
47 | if (pp == m->pingpong[i].id) { | |
48 | b->base_off = addr; | |
49 | b->blk_off = m->pingpong[i].base; | |
50 | b->length = m->pingpong[i].len; | |
51 | b->hwversion = m->hwversion; | |
52 | b->log_mask = DPU_DBG_MASK_PINGPONG; | |
53 | return &m->pingpong[i]; | |
54 | } | |
55 | } | |
56 | ||
57 | return ERR_PTR(-EINVAL); | |
58 | } | |
59 | ||
60 | static int dpu_hw_pp_setup_te_config(struct dpu_hw_pingpong *pp, | |
61 | struct dpu_hw_tear_check *te) | |
62 | { | |
63 | struct dpu_hw_blk_reg_map *c; | |
64 | int cfg; | |
65 | ||
66 | if (!pp || !te) | |
67 | return -EINVAL; | |
68 | c = &pp->hw; | |
69 | ||
70 | cfg = BIT(19); /*VSYNC_COUNTER_EN */ | |
71 | if (te->hw_vsync_mode) | |
72 | cfg |= BIT(20); | |
73 | ||
74 | cfg |= te->vsync_count; | |
75 | ||
76 | DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg); | |
77 | DPU_REG_WRITE(c, PP_SYNC_CONFIG_HEIGHT, te->sync_cfg_height); | |
78 | DPU_REG_WRITE(c, PP_VSYNC_INIT_VAL, te->vsync_init_val); | |
79 | DPU_REG_WRITE(c, PP_RD_PTR_IRQ, te->rd_ptr_irq); | |
80 | DPU_REG_WRITE(c, PP_START_POS, te->start_pos); | |
81 | DPU_REG_WRITE(c, PP_SYNC_THRESH, | |
82 | ((te->sync_threshold_continue << 16) | | |
83 | te->sync_threshold_start)); | |
84 | DPU_REG_WRITE(c, PP_SYNC_WRCOUNT, | |
85 | (te->start_pos + te->sync_threshold_start + 1)); | |
86 | ||
87 | return 0; | |
88 | } | |
89 | ||
90 | static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp, | |
91 | u32 timeout_us) | |
92 | { | |
93 | struct dpu_hw_blk_reg_map *c; | |
94 | u32 val; | |
95 | int rc; | |
96 | ||
97 | if (!pp) | |
98 | return -EINVAL; | |
99 | ||
100 | c = &pp->hw; | |
101 | rc = readl_poll_timeout(c->base_off + c->blk_off + PP_LINE_COUNT, | |
102 | val, (val & 0xffff) >= 1, 10, timeout_us); | |
103 | ||
104 | return rc; | |
105 | } | |
106 | ||
107 | static int dpu_hw_pp_enable_te(struct dpu_hw_pingpong *pp, bool enable) | |
108 | { | |
109 | struct dpu_hw_blk_reg_map *c; | |
110 | ||
111 | if (!pp) | |
112 | return -EINVAL; | |
113 | c = &pp->hw; | |
114 | ||
115 | DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, enable); | |
116 | return 0; | |
117 | } | |
118 | ||
119 | static int dpu_hw_pp_connect_external_te(struct dpu_hw_pingpong *pp, | |
120 | bool enable_external_te) | |
121 | { | |
122 | struct dpu_hw_blk_reg_map *c = &pp->hw; | |
123 | u32 cfg; | |
124 | int orig; | |
125 | ||
126 | if (!pp) | |
127 | return -EINVAL; | |
128 | ||
129 | c = &pp->hw; | |
130 | cfg = DPU_REG_READ(c, PP_SYNC_CONFIG_VSYNC); | |
131 | orig = (bool)(cfg & BIT(20)); | |
132 | if (enable_external_te) | |
133 | cfg |= BIT(20); | |
134 | else | |
135 | cfg &= ~BIT(20); | |
136 | DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg); | |
137 | trace_dpu_pp_connect_ext_te(pp->idx - PINGPONG_0, cfg); | |
138 | ||
139 | return orig; | |
140 | } | |
141 | ||
142 | static int dpu_hw_pp_get_vsync_info(struct dpu_hw_pingpong *pp, | |
143 | struct dpu_hw_pp_vsync_info *info) | |
144 | { | |
145 | struct dpu_hw_blk_reg_map *c; | |
146 | u32 val; | |
147 | ||
148 | if (!pp || !info) | |
149 | return -EINVAL; | |
150 | c = &pp->hw; | |
151 | ||
152 | val = DPU_REG_READ(c, PP_VSYNC_INIT_VAL); | |
153 | info->rd_ptr_init_val = val & 0xffff; | |
154 | ||
155 | val = DPU_REG_READ(c, PP_INT_COUNT_VAL); | |
156 | info->rd_ptr_frame_count = (val & 0xffff0000) >> 16; | |
157 | info->rd_ptr_line_count = val & 0xffff; | |
158 | ||
159 | val = DPU_REG_READ(c, PP_LINE_COUNT); | |
160 | info->wr_ptr_line_count = val & 0xffff; | |
161 | ||
162 | return 0; | |
163 | } | |
164 | ||
165 | static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp) | |
166 | { | |
167 | struct dpu_hw_blk_reg_map *c = &pp->hw; | |
168 | u32 height, init; | |
169 | u32 line = 0xFFFF; | |
170 | ||
171 | if (!pp) | |
172 | return 0; | |
173 | c = &pp->hw; | |
174 | ||
175 | init = DPU_REG_READ(c, PP_VSYNC_INIT_VAL) & 0xFFFF; | |
176 | height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0xFFFF; | |
177 | ||
178 | if (height < init) | |
0841851f | 179 | return line; |
25fdd593 JS |
180 | |
181 | line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0xFFFF; | |
182 | ||
183 | if (line < init) | |
184 | line += (0xFFFF - init); | |
185 | else | |
186 | line -= init; | |
187 | ||
25fdd593 JS |
188 | return line; |
189 | } | |
190 | ||
191 | static void _setup_pingpong_ops(struct dpu_hw_pingpong_ops *ops, | |
192 | const struct dpu_pingpong_cfg *hw_cap) | |
193 | { | |
194 | ops->setup_tearcheck = dpu_hw_pp_setup_te_config; | |
195 | ops->enable_tearcheck = dpu_hw_pp_enable_te; | |
196 | ops->connect_external_te = dpu_hw_pp_connect_external_te; | |
197 | ops->get_vsync_info = dpu_hw_pp_get_vsync_info; | |
198 | ops->poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr; | |
199 | ops->get_line_count = dpu_hw_pp_get_line_count; | |
200 | }; | |
201 | ||
53edf462 | 202 | static struct dpu_hw_blk_ops dpu_hw_ops; |
25fdd593 JS |
203 | |
204 | struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx, | |
205 | void __iomem *addr, | |
206 | struct dpu_mdss_cfg *m) | |
207 | { | |
208 | struct dpu_hw_pingpong *c; | |
209 | struct dpu_pingpong_cfg *cfg; | |
25fdd593 JS |
210 | |
211 | c = kzalloc(sizeof(*c), GFP_KERNEL); | |
212 | if (!c) | |
213 | return ERR_PTR(-ENOMEM); | |
214 | ||
215 | cfg = _pingpong_offset(idx, m, addr, &c->hw); | |
216 | if (IS_ERR_OR_NULL(cfg)) { | |
217 | kfree(c); | |
218 | return ERR_PTR(-EINVAL); | |
219 | } | |
220 | ||
221 | c->idx = idx; | |
222 | c->caps = cfg; | |
223 | _setup_pingpong_ops(&c->ops, c->caps); | |
224 | ||
53edf462 | 225 | dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx, &dpu_hw_ops); |
25fdd593 JS |
226 | |
227 | return c; | |
25fdd593 JS |
228 | } |
229 | ||
230 | void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp) | |
231 | { | |
232 | if (pp) | |
233 | dpu_hw_blk_destroy(&pp->base); | |
234 | kfree(pp); | |
235 | } |