[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / msm / disp / dpu1 / dpu_hw_pingpong.c

/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/iopoll.h>

#include "dpu_hw_mdss.h"
#include "dpu_hwio.h"
#include "dpu_hw_catalog.h"
#include "dpu_hw_pingpong.h"
#include "dpu_kms.h"
#include "dpu_trace.h"

#define PP_TEAR_CHECK_EN                0x000
#define PP_SYNC_CONFIG_VSYNC            0x004
#define PP_SYNC_CONFIG_HEIGHT           0x008
#define PP_SYNC_WRCOUNT                 0x00C
#define PP_VSYNC_INIT_VAL               0x010
#define PP_INT_COUNT_VAL                0x014
#define PP_SYNC_THRESH                  0x018
#define PP_START_POS                    0x01C
#define PP_RD_PTR_IRQ                   0x020
#define PP_WR_PTR_IRQ                   0x024
#define PP_OUT_LINE_COUNT               0x028
#define PP_LINE_COUNT                   0x02C

#define PP_FBC_MODE                     0x034
#define PP_FBC_BUDGET_CTL               0x038
#define PP_FBC_LOSSY_MODE               0x03C

static struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp,
		struct dpu_mdss_cfg *m,
		void __iomem *addr,
		struct dpu_hw_blk_reg_map *b)
{
	int i;

	for (i = 0; i < m->pingpong_count; i++) {
		if (pp == m->pingpong[i].id) {
			b->base_off = addr;
			b->blk_off = m->pingpong[i].base;
			b->length = m->pingpong[i].len;
			b->hwversion = m->hwversion;
			b->log_mask = DPU_DBG_MASK_PINGPONG;
			return &m->pingpong[i];
		}
	}

	return ERR_PTR(-EINVAL);
}

static int dpu_hw_pp_setup_te_config(struct dpu_hw_pingpong *pp,
		struct dpu_hw_tear_check *te)
{
	struct dpu_hw_blk_reg_map *c;
	int cfg;

	if (!pp || !te)
		return -EINVAL;
	c = &pp->hw;

	cfg = BIT(19); /*VSYNC_COUNTER_EN */
	if (te->hw_vsync_mode)
		cfg |= BIT(20);

	cfg |= te->vsync_count;

	DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);
	DPU_REG_WRITE(c, PP_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);
	DPU_REG_WRITE(c, PP_VSYNC_INIT_VAL, te->vsync_init_val);
	DPU_REG_WRITE(c, PP_RD_PTR_IRQ, te->rd_ptr_irq);
	DPU_REG_WRITE(c, PP_START_POS, te->start_pos);
	DPU_REG_WRITE(c, PP_SYNC_THRESH,
			((te->sync_threshold_continue << 16) |
			 te->sync_threshold_start));
	DPU_REG_WRITE(c, PP_SYNC_WRCOUNT,
			(te->start_pos + te->sync_threshold_start + 1));

	return 0;
}

static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp,
		u32 timeout_us)
{
	struct dpu_hw_blk_reg_map *c;
	u32 val;
	int rc;

	if (!pp)
		return -EINVAL;

	c = &pp->hw;
	rc = readl_poll_timeout(c->base_off + c->blk_off + PP_LINE_COUNT,
			val, (val & 0xffff) >= 1, 10, timeout_us);

	return rc;
}

static int dpu_hw_pp_enable_te(struct dpu_hw_pingpong *pp, bool enable)
{
	struct dpu_hw_blk_reg_map *c;

	if (!pp)
		return -EINVAL;
	c = &pp->hw;

	DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, enable);
	return 0;
}

static int dpu_hw_pp_connect_external_te(struct dpu_hw_pingpong *pp,
		bool enable_external_te)
{
	struct dpu_hw_blk_reg_map *c = &pp->hw;
	u32 cfg;
	int orig;

	if (!pp)
		return -EINVAL;

	c = &pp->hw;
	cfg = DPU_REG_READ(c, PP_SYNC_CONFIG_VSYNC);
	orig = (bool)(cfg & BIT(20));
	if (enable_external_te)
		cfg |= BIT(20);
	else
		cfg &= ~BIT(20);
	DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);
	trace_dpu_pp_connect_ext_te(pp->idx - PINGPONG_0, cfg);

	return orig;
}

static int dpu_hw_pp_get_vsync_info(struct dpu_hw_pingpong *pp,
		struct dpu_hw_pp_vsync_info *info)
{
	struct dpu_hw_blk_reg_map *c;
	u32 val;

	if (!pp || !info)
		return -EINVAL;
	c = &pp->hw;

	val = DPU_REG_READ(c, PP_VSYNC_INIT_VAL);
	info->rd_ptr_init_val = val & 0xffff;

	val = DPU_REG_READ(c, PP_INT_COUNT_VAL);
	info->rd_ptr_frame_count = (val & 0xffff0000) >> 16;
	info->rd_ptr_line_count = val & 0xffff;

	val = DPU_REG_READ(c, PP_LINE_COUNT);
	info->wr_ptr_line_count = val & 0xffff;

	return 0;
}

static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp)
{
	struct dpu_hw_blk_reg_map *c = &pp->hw;
	u32 height, init;
	u32 line = 0xFFFF;

	if (!pp)
		return 0;
	c = &pp->hw;

	init = DPU_REG_READ(c, PP_VSYNC_INIT_VAL) & 0xFFFF;
	height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0xFFFF;

	if (height < init)
		return line;

	line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0xFFFF;

	if (line < init)
		line += (0xFFFF - init);
	else
		line -= init;

	return line;
}

static void _setup_pingpong_ops(struct dpu_hw_pingpong_ops *ops,
	const struct dpu_pingpong_cfg *hw_cap)
{
	ops->setup_tearcheck = dpu_hw_pp_setup_te_config;
	ops->enable_tearcheck = dpu_hw_pp_enable_te;
	ops->connect_external_te = dpu_hw_pp_connect_external_te;
	ops->get_vsync_info = dpu_hw_pp_get_vsync_info;
	ops->poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr;
	ops->get_line_count = dpu_hw_pp_get_line_count;
};

static struct dpu_hw_blk_ops dpu_hw_ops = {
	.start = NULL,
	.stop = NULL,
};

struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx,
		void __iomem *addr,
		struct dpu_mdss_cfg *m)
{
	struct dpu_hw_pingpong *c;
	struct dpu_pingpong_cfg *cfg;
	int rc;

	c = kzalloc(sizeof(*c), GFP_KERNEL);
	if (!c)
		return ERR_PTR(-ENOMEM);

	cfg = _pingpong_offset(idx, m, addr, &c->hw);
	if (IS_ERR_OR_NULL(cfg)) {
		kfree(c);
		return ERR_PTR(-EINVAL);
	}

	c->idx = idx;
	c->caps = cfg;
	_setup_pingpong_ops(&c->ops, c->caps);

	rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx, &dpu_hw_ops);
	if (rc) {
		DPU_ERROR("failed to init hw blk %d\n", rc);
		goto blk_init_error;
	}

	return c;

blk_init_error:
	kzfree(c);

	return ERR_PTR(rc);
}

void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp)
{
	if (pp)
		dpu_hw_blk_destroy(&pp->base);
	kfree(pp);
}
Commit	Line	Data
25fdd593 JS	1	/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
	2	*
	3	* This program is free software; you can redistribute it and/or modify
	4	* it under the terms of the GNU General Public License version 2 and
	5	* only version 2 as published by the Free Software Foundation.
	6	*
	7	* This program is distributed in the hope that it will be useful,
	8	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	9	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	10	* GNU General Public License for more details.
	11	*/
	12
	13	#include <linux/iopoll.h>
	14
	15	#include "dpu_hw_mdss.h"
	16	#include "dpu_hwio.h"
	17	#include "dpu_hw_catalog.h"
	18	#include "dpu_hw_pingpong.h"
25fdd593 JS	19	#include "dpu_kms.h"
	20	#include "dpu_trace.h"
	21
	22	#define PP_TEAR_CHECK_EN 0x000
	23	#define PP_SYNC_CONFIG_VSYNC 0x004
	24	#define PP_SYNC_CONFIG_HEIGHT 0x008
	25	#define PP_SYNC_WRCOUNT 0x00C
	26	#define PP_VSYNC_INIT_VAL 0x010
	27	#define PP_INT_COUNT_VAL 0x014
	28	#define PP_SYNC_THRESH 0x018
	29	#define PP_START_POS 0x01C
	30	#define PP_RD_PTR_IRQ 0x020
	31	#define PP_WR_PTR_IRQ 0x024
	32	#define PP_OUT_LINE_COUNT 0x028
	33	#define PP_LINE_COUNT 0x02C
	34
	35	#define PP_FBC_MODE 0x034
	36	#define PP_FBC_BUDGET_CTL 0x038
	37	#define PP_FBC_LOSSY_MODE 0x03C
	38
	39	static struct dpu_pingpong_cfg *_pingpong_offset(enum dpu_pingpong pp,
	40	struct dpu_mdss_cfg *m,
	41	void __iomem *addr,
	42	struct dpu_hw_blk_reg_map *b)
	43	{
	44	int i;
	45
	46	for (i = 0; i < m->pingpong_count; i++) {
	47	if (pp == m->pingpong[i].id) {
	48	b->base_off = addr;
	49	b->blk_off = m->pingpong[i].base;
	50	b->length = m->pingpong[i].len;
	51	b->hwversion = m->hwversion;
	52	b->log_mask = DPU_DBG_MASK_PINGPONG;
	53	return &m->pingpong[i];
	54	}
	55	}
	56
	57	return ERR_PTR(-EINVAL);
	58	}
	59
	60	static int dpu_hw_pp_setup_te_config(struct dpu_hw_pingpong *pp,
	61	struct dpu_hw_tear_check *te)
	62	{
	63	struct dpu_hw_blk_reg_map *c;
	64	int cfg;
	65
	66	if (!pp \|\| !te)
	67	return -EINVAL;
	68	c = &pp->hw;
	69
	70	cfg = BIT(19); /VSYNC_COUNTER_EN /
	71	if (te->hw_vsync_mode)
	72	cfg \|= BIT(20);
	73
	74	cfg \|= te->vsync_count;
	75
	76	DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);
	77	DPU_REG_WRITE(c, PP_SYNC_CONFIG_HEIGHT, te->sync_cfg_height);
	78	DPU_REG_WRITE(c, PP_VSYNC_INIT_VAL, te->vsync_init_val);
	79	DPU_REG_WRITE(c, PP_RD_PTR_IRQ, te->rd_ptr_irq);
	80	DPU_REG_WRITE(c, PP_START_POS, te->start_pos);
	81	DPU_REG_WRITE(c, PP_SYNC_THRESH,
	82	((te->sync_threshold_continue << 16) \|
83	te->sync_threshold_start));
84	DPU_REG_WRITE(c, PP_SYNC_WRCOUNT,
85	(te->start_pos + te->sync_threshold_start + 1));
86
87	return 0;
88	}
89
90	static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp,
91	u32 timeout_us)
92	{
93	struct dpu_hw_blk_reg_map *c;
94	u32 val;
95	int rc;
96
97	if (!pp)
98	return -EINVAL;
99
100	c = &pp->hw;
101	rc = readl_poll_timeout(c->base_off + c->blk_off + PP_LINE_COUNT,
102	val, (val & 0xffff) >= 1, 10, timeout_us);
103
104	return rc;
105	}
106
107	static int dpu_hw_pp_enable_te(struct dpu_hw_pingpong *pp, bool enable)
108	{
109	struct dpu_hw_blk_reg_map *c;
110
111	if (!pp)
112	return -EINVAL;
113	c = &pp->hw;
114
115	DPU_REG_WRITE(c, PP_TEAR_CHECK_EN, enable);
116	return 0;
117	}
118
119	static int dpu_hw_pp_connect_external_te(struct dpu_hw_pingpong *pp,
120	bool enable_external_te)
121	{
122	struct dpu_hw_blk_reg_map *c = &pp->hw;
123	u32 cfg;
124	int orig;
125
126	if (!pp)
127	return -EINVAL;
128
129	c = &pp->hw;
130	cfg = DPU_REG_READ(c, PP_SYNC_CONFIG_VSYNC);
131	orig = (bool)(cfg & BIT(20));
132	if (enable_external_te)
133	cfg \|= BIT(20);
134	else
135	cfg &= ~BIT(20);
136	DPU_REG_WRITE(c, PP_SYNC_CONFIG_VSYNC, cfg);
137	trace_dpu_pp_connect_ext_te(pp->idx - PINGPONG_0, cfg);
138
139	return orig;
140	}
141
142	static int dpu_hw_pp_get_vsync_info(struct dpu_hw_pingpong *pp,
143	struct dpu_hw_pp_vsync_info *info)
144	{
145	struct dpu_hw_blk_reg_map *c;
146	u32 val;
147
148	if (!pp \|\| !info)
149	return -EINVAL;
150	c = &pp->hw;
151
152	val = DPU_REG_READ(c, PP_VSYNC_INIT_VAL);
153	info->rd_ptr_init_val = val & 0xffff;
154
155	val = DPU_REG_READ(c, PP_INT_COUNT_VAL);
156	info->rd_ptr_frame_count = (val & 0xffff0000) >> 16;
157	info->rd_ptr_line_count = val & 0xffff;
158
159	val = DPU_REG_READ(c, PP_LINE_COUNT);
160	info->wr_ptr_line_count = val & 0xffff;
161
162	return 0;
163	}
164
165	static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp)
166	{
167	struct dpu_hw_blk_reg_map *c = &pp->hw;
168	u32 height, init;
169	u32 line = 0xFFFF;
170
171	if (!pp)
172	return 0;
173	c = &pp->hw;
174
175	init = DPU_REG_READ(c, PP_VSYNC_INIT_VAL) & 0xFFFF;
176	height = DPU_REG_READ(c, PP_SYNC_CONFIG_HEIGHT) & 0xFFFF;
177
178	if (height < init)
0841851f	179	return line;
25fdd593 JS	180
	181	line = DPU_REG_READ(c, PP_INT_COUNT_VAL) & 0xFFFF;
	182
	183	if (line < init)
	184	line += (0xFFFF - init);
	185	else
	186	line -= init;
	187
25fdd593 JS	188	return line;
	189	}
	190
	191	static void _setup_pingpong_ops(struct dpu_hw_pingpong_ops *ops,
	192	const struct dpu_pingpong_cfg *hw_cap)
	193	{
	194	ops->setup_tearcheck = dpu_hw_pp_setup_te_config;
	195	ops->enable_tearcheck = dpu_hw_pp_enable_te;
	196	ops->connect_external_te = dpu_hw_pp_connect_external_te;
	197	ops->get_vsync_info = dpu_hw_pp_get_vsync_info;
	198	ops->poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr;
	199	ops->get_line_count = dpu_hw_pp_get_line_count;
	200	};
	201
	202	static struct dpu_hw_blk_ops dpu_hw_ops = {
	203	.start = NULL,
	204	.stop = NULL,
	205	};
	206
	207	struct dpu_hw_pingpong *dpu_hw_pingpong_init(enum dpu_pingpong idx,
	208	void __iomem *addr,
	209	struct dpu_mdss_cfg *m)
	210	{
	211	struct dpu_hw_pingpong *c;
	212	struct dpu_pingpong_cfg *cfg;
	213	int rc;
	214
	215	c = kzalloc(sizeof(*c), GFP_KERNEL);
	216	if (!c)
	217	return ERR_PTR(-ENOMEM);
	218
	219	cfg = _pingpong_offset(idx, m, addr, &c->hw);
	220	if (IS_ERR_OR_NULL(cfg)) {
	221	kfree(c);
	222	return ERR_PTR(-EINVAL);
	223	}
	224
	225	c->idx = idx;
	226	c->caps = cfg;
	227	_setup_pingpong_ops(&c->ops, c->caps);
	228
	229	rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_PINGPONG, idx, &dpu_hw_ops);
	230	if (rc) {
	231	DPU_ERROR("failed to init hw blk %d\n", rc);
	232	goto blk_init_error;
	233	}
	234
	235	return c;
	236
	237	blk_init_error:
	238	kzfree(c);
	239
	240	return ERR_PTR(rc);
	241	}
	242
	243	void dpu_hw_pingpong_destroy(struct dpu_hw_pingpong *pp)
	244	{
	245	if (pp)
	246	dpu_hw_blk_destroy(&pp->base);
	247	kfree(pp);
	248	}