[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / msm / disp / mdp4 / mdp4_kms.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <robdclark@gmail.com>
 */

#ifndef __MDP4_KMS_H__
#define __MDP4_KMS_H__

#include <drm/drm_panel.h>

#include "msm_drv.h"
#include "msm_kms.h"
#include "disp/mdp_kms.h"
#include "mdp4.xml.h"

struct device_node;

struct mdp4_kms {
	struct mdp_kms base;

	struct drm_device *dev;

	int rev;

	void __iomem *mmio;

	struct regulator *vdd;

	struct clk *clk;
	struct clk *pclk;
	struct clk *lut_clk;
	struct clk *axi_clk;

	struct mdp_irq error_handler;

	bool rpm_enabled;

	/* empty/blank cursor bo to use when cursor is "disabled" */
	struct drm_gem_object *blank_cursor_bo;
	uint64_t blank_cursor_iova;
};
#define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)

/* platform config data (ie. from DT, or pdata) */
struct mdp4_platform_config {
	struct iommu_domain *iommu;
	uint32_t max_clk;
};

static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
{
	msm_writel(data, mdp4_kms->mmio + reg);
}

static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
{
	return msm_readl(mdp4_kms->mmio + reg);
}

static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
{
	switch (pipe) {
	case VG1:      return MDP4_OVERLAY_FLUSH_VG1;
	case VG2:      return MDP4_OVERLAY_FLUSH_VG2;
	case RGB1:     return MDP4_OVERLAY_FLUSH_RGB1;
	case RGB2:     return MDP4_OVERLAY_FLUSH_RGB2;
	default:       return 0;
	}
}

static inline uint32_t ovlp2flush(int ovlp)
{
	switch (ovlp) {
	case 0:        return MDP4_OVERLAY_FLUSH_OVLP0;
	case 1:        return MDP4_OVERLAY_FLUSH_OVLP1;
	default:       return 0;
	}
}

static inline uint32_t dma2irq(enum mdp4_dma dma)
{
	switch (dma) {
	case DMA_P:    return MDP4_IRQ_DMA_P_DONE;
	case DMA_S:    return MDP4_IRQ_DMA_S_DONE;
	case DMA_E:    return MDP4_IRQ_DMA_E_DONE;
	default:       return 0;
	}
}

static inline uint32_t dma2err(enum mdp4_dma dma)
{
	switch (dma) {
	case DMA_P:    return MDP4_IRQ_PRIMARY_INTF_UDERRUN;
	case DMA_S:    return 0;  // ???
	case DMA_E:    return MDP4_IRQ_EXTERNAL_INTF_UDERRUN;
	default:       return 0;
	}
}

static inline uint32_t mixercfg(uint32_t mixer_cfg, int mixer,
		enum mdp4_pipe pipe, enum mdp_mixer_stage_id stage)
{
	switch (pipe) {
	case VG1:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE0(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
		break;
	case VG2:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE1(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
		break;
	case RGB1:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE2(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
		break;
	case RGB2:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE3(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
		break;
	case RGB3:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE4(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
		break;
	case VG3:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE5(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
		break;
	case VG4:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE6(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
		break;
	default:
		WARN(1, "invalid pipe");
		break;
	}

	return mixer_cfg;
}

int mdp4_disable(struct mdp4_kms *mdp4_kms);
int mdp4_enable(struct mdp4_kms *mdp4_kms);

void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
		uint32_t old_irqmask);
void mdp4_irq_preinstall(struct msm_kms *kms);
int mdp4_irq_postinstall(struct msm_kms *kms);
void mdp4_irq_uninstall(struct msm_kms *kms);
irqreturn_t mdp4_irq(struct msm_kms *kms);
int mdp4_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
void mdp4_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);

static inline uint32_t mdp4_pipe_caps(enum mdp4_pipe pipe)
{
	switch (pipe) {
	case VG1:
	case VG2:
	case VG3:
	case VG4:
		return MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
	case RGB1:
	case RGB2:
	case RGB3:
		return MDP_PIPE_CAP_SCALE;
	default:
		return 0;
	}
}

enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane);
struct drm_plane *mdp4_plane_init(struct drm_device *dev,
		enum mdp4_pipe pipe_id, bool private_plane);

uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc);
void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config);
void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer);
void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc);
struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
		struct drm_plane *plane, int id, int ovlp_id,
		enum mdp4_dma dma_id);

long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev);

long mdp4_lcdc_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev,
		struct device_node *panel_node);

struct drm_connector *mdp4_lvds_connector_init(struct drm_device *dev,
		struct device_node *panel_node, struct drm_encoder *encoder);

#ifdef CONFIG_DRM_MSM_DSI
struct drm_encoder *mdp4_dsi_encoder_init(struct drm_device *dev);
#else
static inline struct drm_encoder *mdp4_dsi_encoder_init(struct drm_device *dev)
{
	return ERR_PTR(-ENODEV);
}
#endif

#ifdef CONFIG_COMMON_CLK
struct clk *mpd4_lvds_pll_init(struct drm_device *dev);
#else
static inline struct clk *mpd4_lvds_pll_init(struct drm_device *dev)
{
	return ERR_PTR(-ENODEV);
}
#endif

#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
/* bus scaling data is associated with extra pointless platform devices,
 * "dtv", etc.. this is a bit of a hack, but we need a way for encoders
 * to find their pdata to make the bus-scaling stuff work.
 */
static inline void *mdp4_find_pdata(const char *devname)
{
	struct device *dev;
	dev = bus_find_device_by_name(&platform_bus_type, NULL, devname);
	return dev ? dev->platform_data : NULL;
}
#endif

#endif /* __MDP4_KMS_H__ */
Commit	Line	Data
caab277b	1	/* SPDX-License-Identifier: GPL-2.0-only */
c8afe684 RC	2	/*
	3	* Copyright (C) 2013 Red Hat
	4	* Author: Rob Clark <robdclark@gmail.com>
c8afe684 RC	5	*/
	6
	7	#ifndef __MDP4_KMS_H__
	8	#define __MDP4_KMS_H__
	9
78f27b1c MY	10	#include <drm/drm_panel.h>
78f27b1c MY	11
c8afe684	12	#include "msm_drv.h"
dd2da6e3	13	#include "msm_kms.h"
14be3200	14	#include "disp/mdp_kms.h"
c8afe684 RC	15	#include "mdp4.xml.h"
c8afe684 RC	16
78f27b1c	17	struct device_node;
3e87599b	18
c8afe684	19	struct mdp4_kms {
9e0efa63	20	struct mdp_kms base;
c8afe684 RC	21
	22	struct drm_device *dev;
	23
	24	int rev;
	25
c8afe684 RC	26	void __iomem *mmio;
c8afe684 RC	27
c8afe684 RC	28	struct regulator *vdd;
	29
	30	struct clk *clk;
	31	struct clk *pclk;
	32	struct clk *lut_clk;
e8abb5b5	33	struct clk *axi_clk;
c8afe684	34
9e0efa63	35	struct mdp_irq error_handler;
7d8d9f67	36
cd792726 AT	37	bool rpm_enabled;
cd792726 AT	38
7d8d9f67 RC	39	/* empty/blank cursor bo to use when cursor is "disabled" */
7d8d9f67 RC	40	struct drm_gem_object *blank_cursor_bo;
78babc16	41	uint64_t blank_cursor_iova;
c8afe684 RC	42	};
	43	#define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)
	44
	45	/* platform config data (ie. from DT, or pdata) */
	46	struct mdp4_platform_config {
	47	struct iommu_domain *iommu;
	48	uint32_t max_clk;
	49	};
	50
c8afe684 RC	51	static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
	52	{
	53	msm_writel(data, mdp4_kms->mmio + reg);
	54	}
	55
	56	static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
	57	{
	58	return msm_readl(mdp4_kms->mmio + reg);
	59	}
	60
22ba8b6b	61	static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
c8afe684 RC	62	{
	63	switch (pipe) {
	64	case VG1: return MDP4_OVERLAY_FLUSH_VG1;
	65	case VG2: return MDP4_OVERLAY_FLUSH_VG2;
	66	case RGB1: return MDP4_OVERLAY_FLUSH_RGB1;
f9a1ca5c	67	case RGB2: return MDP4_OVERLAY_FLUSH_RGB2;
c8afe684 RC	68	default: return 0;
	69	}
	70	}
	71
	72	static inline uint32_t ovlp2flush(int ovlp)
	73	{
	74	switch (ovlp) {
	75	case 0: return MDP4_OVERLAY_FLUSH_OVLP0;
	76	case 1: return MDP4_OVERLAY_FLUSH_OVLP1;
	77	default: return 0;
	78	}
	79	}
	80
	81	static inline uint32_t dma2irq(enum mdp4_dma dma)
	82	{
	83	switch (dma) {
	84	case DMA_P: return MDP4_IRQ_DMA_P_DONE;
	85	case DMA_S: return MDP4_IRQ_DMA_S_DONE;
	86	case DMA_E: return MDP4_IRQ_DMA_E_DONE;
	87	default: return 0;
	88	}
	89	}
	90
	91	static inline uint32_t dma2err(enum mdp4_dma dma)
	92	{
	93	switch (dma) {
	94	case DMA_P: return MDP4_IRQ_PRIMARY_INTF_UDERRUN;
	95	case DMA_S: return 0; // ???
	96	case DMA_E: return MDP4_IRQ_EXTERNAL_INTF_UDERRUN;
	97	default: return 0;
	98	}
	99	}
	100
d65bd0e4 RC	101	static inline uint32_t mixercfg(uint32_t mixer_cfg, int mixer,
d65bd0e4 RC	102	enum mdp4_pipe pipe, enum mdp_mixer_stage_id stage)
a8623918	103	{
a8623918 RC	104	switch (pipe) {
a8623918 RC	105	case VG1:
d65bd0e4 RC	106	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK \|
	107	MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
	108	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE0(stage) \|
a8623918 RC	109	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
	110	break;
	111	case VG2:
d65bd0e4 RC	112	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK \|
	113	MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
	114	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE1(stage) \|
a8623918 RC	115	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
	116	break;
	117	case RGB1:
d65bd0e4 RC	118	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK \|
	119	MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
	120	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE2(stage) \|
a8623918 RC	121	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
	122	break;
	123	case RGB2:
d65bd0e4 RC	124	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK \|
	125	MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
	126	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE3(stage) \|
a8623918 RC	127	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
	128	break;
	129	case RGB3:
d65bd0e4 RC	130	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK \|
	131	MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
	132	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE4(stage) \|
a8623918 RC	133	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
	134	break;
	135	case VG3:
d65bd0e4 RC	136	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK \|
	137	MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
	138	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE5(stage) \|
a8623918 RC	139	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
	140	break;
	141	case VG4:
d65bd0e4 RC	142	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK \|
	143	MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
	144	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE6(stage) \|
a8623918 RC	145	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
	146	break;
	147	default:
2abd1c88	148	WARN(1, "invalid pipe");
a8623918 RC	149	break;
	150	}
	151
	152	return mixer_cfg;
	153	}
	154
c8afe684 RC	155	int mdp4_disable(struct mdp4_kms *mdp4_kms);
	156	int mdp4_enable(struct mdp4_kms *mdp4_kms);
	157
29f034d7	158	void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
29f034d7	159	uint32_t old_irqmask);
c8afe684 RC	160	void mdp4_irq_preinstall(struct msm_kms *kms);
	161	int mdp4_irq_postinstall(struct msm_kms *kms);
	162	void mdp4_irq_uninstall(struct msm_kms *kms);
	163	irqreturn_t mdp4_irq(struct msm_kms *kms);
c8afe684 RC	164	int mdp4_enable_vblank(struct msm_kms kms, struct drm_crtc crtc);
	165	void mdp4_disable_vblank(struct msm_kms kms, struct drm_crtc crtc);
	166
3498409f	167	static inline uint32_t mdp4_pipe_caps(enum mdp4_pipe pipe)
7ca12718 SV	168	{
	169	switch (pipe) {
	170	case VG1:
	171	case VG2:
	172	case VG3:
	173	case VG4:
3498409f	174	return MDP_PIPE_CAP_HFLIP \| MDP_PIPE_CAP_VFLIP \|
	175	MDP_PIPE_CAP_SCALE \| MDP_PIPE_CAP_CSC;
	176	case RGB1:
	177	case RGB2:
	178	case RGB3:
	179	return MDP_PIPE_CAP_SCALE;
7ca12718	180	default:
3498409f	181	return 0;
7ca12718 SV	182	}
	183	}
	184
22ba8b6b	185	enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane);
c8afe684	186	struct drm_plane mdp4_plane_init(struct drm_device dev,
22ba8b6b	187	enum mdp4_pipe pipe_id, bool private_plane);
c8afe684 RC	188
c8afe684 RC	189	uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc);
c8afe684	190	void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config);
d65bd0e4	191	void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer);
0a5c9aad	192	void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc);
c8afe684 RC	193	struct drm_crtc mdp4_crtc_init(struct drm_device dev,
	194	struct drm_plane *plane, int id, int ovlp_id,
	195	enum mdp4_dma dma_id);
	196
	197	long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
	198	struct drm_encoder mdp4_dtv_encoder_init(struct drm_device dev);
	199
3e87599b RC	200	long mdp4_lcdc_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
3e87599b RC	201	struct drm_encoder mdp4_lcdc_encoder_init(struct drm_device dev,
a6bf7f63	202	struct device_node *panel_node);
3e87599b RC	203
3e87599b RC	204	struct drm_connector mdp4_lvds_connector_init(struct drm_device dev,
a6bf7f63	205	struct device_node panel_node, struct drm_encoder encoder);
3e87599b	206
776638e7 VSB	207	#ifdef CONFIG_DRM_MSM_DSI
	208	struct drm_encoder mdp4_dsi_encoder_init(struct drm_device dev);
	209	#else
	210	static inline struct drm_encoder mdp4_dsi_encoder_init(struct drm_device dev)
	211	{
	212	return ERR_PTR(-ENODEV);
	213	}
	214	#endif
	215
3e87599b RC	216	#ifdef CONFIG_COMMON_CLK
	217	struct clk mpd4_lvds_pll_init(struct drm_device dev);
	218	#else
	219	static inline struct clk mpd4_lvds_pll_init(struct drm_device dev)
	220	{
	221	return ERR_PTR(-ENODEV);
	222	}
	223	#endif
	224
6490ad47	225	#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
c8afe684 RC	226	/* bus scaling data is associated with extra pointless platform devices,
	227	* "dtv", etc.. this is a bit of a hack, but we need a way for encoders
	228	* to find their pdata to make the bus-scaling stuff work.
	229	*/
	230	static inline void mdp4_find_pdata(const char devname)
	231	{
	232	struct device *dev;
8dcbde0f	233	dev = bus_find_device_by_name(&platform_bus_type, NULL, devname);
c8afe684 RC	234	return dev ? dev->platform_data : NULL;
	235	}
	236	#endif
	237
	238	#endif /* __MDP4_KMS_H__ */