[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / msm / disp / mdp5 / mdp5_cfg.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
 */

#include "mdp5_kms.h"
#include "mdp5_cfg.h"

struct mdp5_cfg_handler {
	int revision;
	struct mdp5_cfg config;
};

/* mdp5_cfg must be exposed (used in mdp5.xml.h) */
const struct mdp5_cfg_hw *mdp5_cfg = NULL;

const struct mdp5_cfg_hw msm8x74v1_config = {
	.name = "msm8x74v1",
	.mdp = {
		.count = 1,
		.caps = MDP_CAP_SMP |
			0,
	},
	.smp = {
		.mmb_count = 22,
		.mmb_size = 4096,
		.clients = {
			[SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
			[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
			[SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
		},
	},
	.ctl = {
		.count = 5,
		.base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
		.flush_hw_mask = 0x0003ffff,
	},
	.pipe_vig = {
		.count = 3,
		.base = { 0x01100, 0x01500, 0x01900 },
		.caps = MDP_PIPE_CAP_HFLIP |
			MDP_PIPE_CAP_VFLIP |
			MDP_PIPE_CAP_SCALE |
			MDP_PIPE_CAP_CSC   |
			0,
	},
	.pipe_rgb = {
		.count = 3,
		.base = { 0x01d00, 0x02100, 0x02500 },
		.caps = MDP_PIPE_CAP_HFLIP |
			MDP_PIPE_CAP_VFLIP |
			MDP_PIPE_CAP_SCALE |
			0,
	},
	.pipe_dma = {
		.count = 2,
		.base = { 0x02900, 0x02d00 },
		.caps = MDP_PIPE_CAP_HFLIP |
			MDP_PIPE_CAP_VFLIP |
			0,
	},
	.lm = {
		.count = 5,
		.base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
		.instances = {
				{ .id = 0, .pp = 0, .dspp = 0,
				  .caps = MDP_LM_CAP_DISPLAY, },
				{ .id = 1, .pp = 1, .dspp = 1,
				  .caps = MDP_LM_CAP_DISPLAY, },
				{ .id = 2, .pp = 2, .dspp = 2,
				  .caps = MDP_LM_CAP_DISPLAY, },
				{ .id = 3, .pp = -1, .dspp = -1,
				  .caps = MDP_LM_CAP_WB },
				{ .id = 4, .pp = -1, .dspp = -1,
				  .caps = MDP_LM_CAP_WB },
			     },
		.nb_stages = 5,
		.max_width = 2048,
		.max_height = 0xFFFF,
	},
	.dspp = {
		.count = 3,
		.base = { 0x04500, 0x04900, 0x04d00 },
	},
	.pp = {
		.count = 3,
		.base = { 0x21a00, 0x21b00, 0x21c00 },
	},
	.intf = {
		.base = { 0x21000, 0x21200, 0x21400, 0x21600 },
		.connect = {
			[0] = INTF_eDP,
			[1] = INTF_DSI,
			[2] = INTF_DSI,
			[3] = INTF_HDMI,
		},
	},
	.max_clk = 200000000,
};

const struct mdp5_cfg_hw msm8x74v2_config = {
	.name = "msm8x74",
	.mdp = {
		.count = 1,
		.caps = MDP_CAP_SMP |
			0,
	},
	.smp = {
		.mmb_count = 22,
		.mmb_size = 4096,
		.clients = {
			[SSPP_VIG0] =  1, [SSPP_VIG1] =  4, [SSPP_VIG2] =  7,
			[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
			[SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
		},
	},
	.ctl = {
		.count = 5,
		.base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
		.flush_hw_mask = 0x0003ffff,
	},
	.pipe_vig = {
		.count = 3,
		.base = { 0x01100, 0x01500, 0x01900 },
		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
				MDP_PIPE_CAP_DECIMATION,
	},
	.pipe_rgb = {
		.count = 3,
		.base = { 0x01d00, 0x02100, 0x02500 },
		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
	},
	.pipe_dma = {
		.count = 2,
		.base = { 0x02900, 0x02d00 },
		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
	},
	.lm = {
		.count = 5,
		.base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
		.instances = {
				{ .id = 0, .pp = 0, .dspp = 0,
				  .caps = MDP_LM_CAP_DISPLAY, },
				{ .id = 1, .pp = 1, .dspp = 1,
				  .caps = MDP_LM_CAP_DISPLAY, },
				{ .id = 2, .pp = 2, .dspp = 2,
				  .caps = MDP_LM_CAP_DISPLAY, },
				{ .id = 3, .pp = -1, .dspp = -1,
				  .caps = MDP_LM_CAP_WB, },
				{ .id = 4, .pp = -1, .dspp = -1,
				  .caps = MDP_LM_CAP_WB, },
			     },
		.nb_stages = 5,
		.max_width = 2048,
		.max_height = 0xFFFF,
	},
	.dspp = {
		.count = 3,
		.base = { 0x04500, 0x04900, 0x04d00 },
	},
	.ad = {
		.count = 2,
		.base = { 0x13000, 0x13200 },
	},
	.pp = {
		.count = 3,
		.base = { 0x12c00, 0x12d00, 0x12e00 },
	},
	.intf = {
		.base = { 0x12400, 0x12600, 0x12800, 0x12a00 },
		.connect = {
			[0] = INTF_eDP,
			[1] = INTF_DSI,
			[2] = INTF_DSI,
			[3] = INTF_HDMI,
		},
	},
	.max_clk = 200000000,
};

const struct mdp5_cfg_hw apq8084_config = {
	.name = "apq8084",
	.mdp = {
		.count = 1,
		.caps = MDP_CAP_SMP |
			MDP_CAP_SRC_SPLIT |
			0,
	},
	.smp = {
		.mmb_count = 44,
		.mmb_size = 8192,
		.clients = {
			[SSPP_VIG0] =  1, [SSPP_VIG1] =  4,
			[SSPP_VIG2] =  7, [SSPP_VIG3] = 19,
			[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
			[SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
			[SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
		},
		.reserved_state[0] = GENMASK(7, 0),	/* first 8 MMBs */
		.reserved = {
			/* Two SMP blocks are statically tied to RGB pipes: */
			[16] = 2, [17] = 2, [18] = 2, [22] = 2,
		},
	},
	.ctl = {
		.count = 5,
		.base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
		.flush_hw_mask = 0x003fffff,
	},
	.pipe_vig = {
		.count = 4,
		.base = { 0x01100, 0x01500, 0x01900, 0x01d00 },
		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
				MDP_PIPE_CAP_DECIMATION,
	},
	.pipe_rgb = {
		.count = 4,
		.base = { 0x02100, 0x02500, 0x02900, 0x02d00 },
		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
	},
	.pipe_dma = {
		.count = 2,
		.base = { 0x03100, 0x03500 },
		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
	},
	.lm = {
		.count = 6,
		.base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 },
		.instances = {
				{ .id = 0, .pp = 0, .dspp = 0,
				  .caps = MDP_LM_CAP_DISPLAY |
					  MDP_LM_CAP_PAIR, },
				{ .id = 1, .pp = 1, .dspp = 1,
				  .caps = MDP_LM_CAP_DISPLAY, },
				{ .id = 2, .pp = 2, .dspp = 2,
				  .caps = MDP_LM_CAP_DISPLAY |
					  MDP_LM_CAP_PAIR, },
				{ .id = 3, .pp = -1, .dspp = -1,
				  .caps = MDP_LM_CAP_WB, },
				{ .id = 4, .pp = -1, .dspp = -1,
				  .caps = MDP_LM_CAP_WB, },
				{ .id = 5, .pp = 3, .dspp = 3,
				  .caps = MDP_LM_CAP_DISPLAY, },
			     },
		.nb_stages = 5,
		.max_width = 2048,
		.max_height = 0xFFFF,
	},
	.dspp = {
		.count = 4,
		.base = { 0x05100, 0x05500, 0x05900, 0x05d00 },

	},
	.ad = {
		.count = 3,
		.base = { 0x13400, 0x13600, 0x13800 },
	},
	.pp = {
		.count = 4,
		.base = { 0x12e00, 0x12f00, 0x13000, 0x13100 },
	},
	.intf = {
		.base = { 0x12400, 0x12600, 0x12800, 0x12a00, 0x12c00 },
		.connect = {
			[0] = INTF_eDP,
			[1] = INTF_DSI,
			[2] = INTF_DSI,
			[3] = INTF_HDMI,
		},
	},
	.max_clk = 320000000,
};

const struct mdp5_cfg_hw msm8x16_config = {
	.name = "msm8x16",
	.mdp = {
		.count = 1,
		.base = { 0x0 },
		.caps = MDP_CAP_SMP |
			0,
	},
	.smp = {
		.mmb_count = 8,
		.mmb_size = 8192,
		.clients = {
			[SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
			[SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
		},
	},
	.ctl = {
		.count = 5,
		.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
		.flush_hw_mask = 0x4003ffff,
	},
	.pipe_vig = {
		.count = 1,
		.base = { 0x04000 },
		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
				MDP_PIPE_CAP_DECIMATION,
	},
	.pipe_rgb = {
		.count = 2,
		.base = { 0x14000, 0x16000 },
		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
				MDP_PIPE_CAP_DECIMATION,
	},
	.pipe_dma = {
		.count = 1,
		.base = { 0x24000 },
		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
	},
	.lm = {
		.count = 2, /* LM0 and LM3 */
		.base = { 0x44000, 0x47000 },
		.instances = {
				{ .id = 0, .pp = 0, .dspp = 0,
				  .caps = MDP_LM_CAP_DISPLAY, },
				{ .id = 3, .pp = -1, .dspp = -1,
				  .caps = MDP_LM_CAP_WB },
			     },
		.nb_stages = 8,
		.max_width = 2048,
		.max_height = 0xFFFF,
	},
	.dspp = {
		.count = 1,
		.base = { 0x54000 },

	},
	.intf = {
		.base = { 0x00000, 0x6a800 },
		.connect = {
			[0] = INTF_DISABLED,
			[1] = INTF_DSI,
		},
	},
	.max_clk = 320000000,
};

const struct mdp5_cfg_hw msm8x94_config = {
	.name = "msm8x94",
	.mdp = {
		.count = 1,
		.caps = MDP_CAP_SMP |
			MDP_CAP_SRC_SPLIT |
			0,
	},
	.smp = {
		.mmb_count = 44,
		.mmb_size = 8192,
		.clients = {
			[SSPP_VIG0] =  1, [SSPP_VIG1] =  4,
			[SSPP_VIG2] =  7, [SSPP_VIG3] = 19,
			[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
			[SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
			[SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
		},
		.reserved_state[0] = GENMASK(23, 0),	/* first 24 MMBs */
		.reserved = {
			 [1] = 1,  [4] = 1,  [7] = 1, [19] = 1,
			[16] = 5, [17] = 5, [18] = 5, [22] = 5,
		},
	},
	.ctl = {
		.count = 5,
		.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
		.flush_hw_mask = 0xf0ffffff,
	},
	.pipe_vig = {
		.count = 4,
		.base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC |
				MDP_PIPE_CAP_DECIMATION,
	},
	.pipe_rgb = {
		.count = 4,
		.base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_DECIMATION,
	},
	.pipe_dma = {
		.count = 2,
		.base = { 0x24000, 0x26000 },
		.caps = MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP,
	},
	.lm = {
		.count = 6,
		.base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
		.instances = {
				{ .id = 0, .pp = 0, .dspp = 0,
				  .caps = MDP_LM_CAP_DISPLAY |
					  MDP_LM_CAP_PAIR, },
				{ .id = 1, .pp = 1, .dspp = 1,
				  .caps = MDP_LM_CAP_DISPLAY, },
				{ .id = 2, .pp = 2, .dspp = 2,
				  .caps = MDP_LM_CAP_DISPLAY |
					  MDP_LM_CAP_PAIR, },
				{ .id = 3, .pp = -1, .dspp = -1,
				  .caps = MDP_LM_CAP_WB, },
				{ .id = 4, .pp = -1, .dspp = -1,
				  .caps = MDP_LM_CAP_WB, },
				{ .id = 5, .pp = 3, .dspp = 3,
				  .caps = MDP_LM_CAP_DISPLAY, },
			     },
		.nb_stages = 8,
		.max_width = 2048,
		.max_height = 0xFFFF,
	},
	.dspp = {
		.count = 4,
		.base = { 0x54000, 0x56000, 0x58000, 0x5a000 },

	},
	.ad = {
		.count = 3,
		.base = { 0x78000, 0x78800, 0x79000 },
	},
	.pp = {
		.count = 4,
		.base = { 0x70000, 0x70800, 0x71000, 0x71800 },
	},
	.intf = {
		.base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
		.connect = {
			[0] = INTF_DISABLED,
			[1] = INTF_DSI,
			[2] = INTF_DSI,
			[3] = INTF_HDMI,
		},
	},
	.max_clk = 400000000,
};

const struct mdp5_cfg_hw msm8x96_config = {
	.name = "msm8x96",
	.mdp = {
		.count = 1,
		.caps = MDP_CAP_DSC |
			MDP_CAP_CDM |
			MDP_CAP_SRC_SPLIT |
			0,
	},
	.ctl = {
		.count = 5,
		.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
		.flush_hw_mask = 0xf4ffffff,
	},
	.pipe_vig = {
		.count = 4,
		.base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
		.caps = MDP_PIPE_CAP_HFLIP	|
			MDP_PIPE_CAP_VFLIP	|
			MDP_PIPE_CAP_SCALE	|
			MDP_PIPE_CAP_CSC	|
			MDP_PIPE_CAP_DECIMATION	|
			MDP_PIPE_CAP_SW_PIX_EXT	|
			0,
	},
	.pipe_rgb = {
		.count = 4,
		.base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
		.caps = MDP_PIPE_CAP_HFLIP	|
			MDP_PIPE_CAP_VFLIP	|
			MDP_PIPE_CAP_SCALE	|
			MDP_PIPE_CAP_DECIMATION	|
			MDP_PIPE_CAP_SW_PIX_EXT	|
			0,
	},
	.pipe_dma = {
		.count = 2,
		.base = { 0x24000, 0x26000 },
		.caps = MDP_PIPE_CAP_HFLIP	|
			MDP_PIPE_CAP_VFLIP	|
			MDP_PIPE_CAP_SW_PIX_EXT	|
			0,
	},
	.pipe_cursor = {
		.count = 2,
		.base = { 0x34000, 0x36000 },
		.caps = MDP_PIPE_CAP_HFLIP	|
			MDP_PIPE_CAP_VFLIP	|
			MDP_PIPE_CAP_SW_PIX_EXT	|
			MDP_PIPE_CAP_CURSOR	|
			0,
	},

	.lm = {
		.count = 6,
		.base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
		.instances = {
				{ .id = 0, .pp = 0, .dspp = 0,
				  .caps = MDP_LM_CAP_DISPLAY |
					  MDP_LM_CAP_PAIR, },
				{ .id = 1, .pp = 1, .dspp = 1,
				  .caps = MDP_LM_CAP_DISPLAY, },
				{ .id = 2, .pp = 2, .dspp = -1,
				  .caps = MDP_LM_CAP_DISPLAY |
					  MDP_LM_CAP_PAIR, },
				{ .id = 3, .pp = -1, .dspp = -1,
				  .caps = MDP_LM_CAP_WB, },
				{ .id = 4, .pp = -1, .dspp = -1,
				  .caps = MDP_LM_CAP_WB, },
				{ .id = 5, .pp = 3, .dspp = -1,
				  .caps = MDP_LM_CAP_DISPLAY, },
			     },
		.nb_stages = 8,
		.max_width = 2560,
		.max_height = 0xFFFF,
	},
	.dspp = {
		.count = 2,
		.base = { 0x54000, 0x56000 },
	},
	.ad = {
		.count = 3,
		.base = { 0x78000, 0x78800, 0x79000 },
	},
	.pp = {
		.count = 4,
		.base = { 0x70000, 0x70800, 0x71000, 0x71800 },
	},
	.cdm = {
		.count = 1,
		.base = { 0x79200 },
	},
	.dsc = {
		.count = 2,
		.base = { 0x80000, 0x80400 },
	},
	.intf = {
		.base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
		.connect = {
			[0] = INTF_DISABLED,
			[1] = INTF_DSI,
			[2] = INTF_DSI,
			[3] = INTF_HDMI,
		},
	},
	.max_clk = 412500000,
};

const struct mdp5_cfg_hw msm8917_config = {
	.name = "msm8917",
	.mdp = {
		.count = 1,
		.caps = MDP_CAP_CDM,
	},
	.ctl = {
		.count = 3,
		.base = { 0x01000, 0x01200, 0x01400 },
		.flush_hw_mask = 0xffffffff,
	},
	.pipe_vig = {
		.count = 1,
		.base = { 0x04000 },
		.caps = MDP_PIPE_CAP_HFLIP	|
			MDP_PIPE_CAP_VFLIP	|
			MDP_PIPE_CAP_SCALE	|
			MDP_PIPE_CAP_CSC	|
			MDP_PIPE_CAP_DECIMATION	|
			MDP_PIPE_CAP_SW_PIX_EXT	|
			0,
	},
	.pipe_rgb = {
		.count = 2,
		.base = { 0x14000, 0x16000 },
		.caps = MDP_PIPE_CAP_HFLIP	|
			MDP_PIPE_CAP_VFLIP	|
			MDP_PIPE_CAP_DECIMATION	|
			MDP_PIPE_CAP_SW_PIX_EXT	|
			0,
	},
	.pipe_dma = {
		.count = 1,
		.base = { 0x24000 },
		.caps = MDP_PIPE_CAP_HFLIP	|
			MDP_PIPE_CAP_VFLIP	|
			MDP_PIPE_CAP_SW_PIX_EXT	|
			0,
	},
	.pipe_cursor = {
		.count = 1,
		.base = { 0x34000 },
		.caps = MDP_PIPE_CAP_HFLIP	|
			MDP_PIPE_CAP_VFLIP	|
			MDP_PIPE_CAP_SW_PIX_EXT	|
			MDP_PIPE_CAP_CURSOR	|
			0,
	},

	.lm = {
		.count = 2,
		.base = { 0x44000, 0x45000 },
		.instances = {
				{ .id = 0, .pp = 0, .dspp = 0,
				  .caps = MDP_LM_CAP_DISPLAY, },
				{ .id = 1, .pp = -1, .dspp = -1,
				  .caps = MDP_LM_CAP_WB },
			     },
		.nb_stages = 8,
		.max_width = 2048,
		.max_height = 0xFFFF,
	},
	.dspp = {
		.count = 1,
		.base = { 0x54000 },

	},
	.pp = {
		.count = 1,
		.base = { 0x70000 },
	},
	.cdm = {
		.count = 1,
		.base = { 0x79200 },
	},
	.intf = {
		.base = { 0x6a000, 0x6a800 },
		.connect = {
			[0] = INTF_DISABLED,
			[1] = INTF_DSI,
		},
	},
	.max_clk = 320000000,
};

static const struct mdp5_cfg_handler cfg_handlers[] = {
	{ .revision = 0, .config = { .hw = &msm8x74v1_config } },
	{ .revision = 2, .config = { .hw = &msm8x74v2_config } },
	{ .revision = 3, .config = { .hw = &apq8084_config } },
	{ .revision = 6, .config = { .hw = &msm8x16_config } },
	{ .revision = 9, .config = { .hw = &msm8x94_config } },
	{ .revision = 7, .config = { .hw = &msm8x96_config } },
	{ .revision = 15, .config = { .hw = &msm8917_config } },
};

static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev);

const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_handler)
{
	return cfg_handler->config.hw;
}

struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_handler)
{
	return &cfg_handler->config;
}

int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler)
{
	return cfg_handler->revision;
}

void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_handler)
{
	kfree(cfg_handler);
}

struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
		uint32_t major, uint32_t minor)
{
	struct drm_device *dev = mdp5_kms->dev;
	struct platform_device *pdev = to_platform_device(dev->dev);
	struct mdp5_cfg_handler *cfg_handler;
	struct mdp5_cfg_platform *pconfig;
	int i, ret = 0;

	cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);
	if (unlikely(!cfg_handler)) {
		ret = -ENOMEM;
		goto fail;
	}

	if (major != 1) {
		DRM_DEV_ERROR(dev->dev, "unexpected MDP major version: v%d.%d\n",
				major, minor);
		ret = -ENXIO;
		goto fail;
	}

	/* only after mdp5_cfg global pointer's init can we access the hw */
	for (i = 0; i < ARRAY_SIZE(cfg_handlers); i++) {
		if (cfg_handlers[i].revision != minor)
			continue;
		mdp5_cfg = cfg_handlers[i].config.hw;

		break;
	}
	if (unlikely(!mdp5_cfg)) {
		DRM_DEV_ERROR(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
				major, minor);
		ret = -ENXIO;
		goto fail;
	}

	cfg_handler->revision = minor;
	cfg_handler->config.hw = mdp5_cfg;

	pconfig = mdp5_get_config(pdev);
	memcpy(&cfg_handler->config.platform, pconfig, sizeof(*pconfig));

	DBG("MDP5: %s hw config selected", mdp5_cfg->name);

	return cfg_handler;

fail:
	if (cfg_handler)
		mdp5_cfg_destroy(cfg_handler);

	return NULL;
}

static struct mdp5_cfg_platform *mdp5_get_config(struct platform_device *dev)
{
	static struct mdp5_cfg_platform config = {};

	config.iommu = iommu_domain_alloc(&platform_bus_type);
	if (config.iommu) {
		config.iommu->geometry.aperture_start = 0x1000;
		config.iommu->geometry.aperture_end = 0xffffffff;
	}

	return &config;
}
Commit	Line	Data
97fb5e8d	1	// SPDX-License-Identifier: GPL-2.0-only
2e362e17	2	/*
02dfd9d2	3	* Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
2e362e17 SV	4	*/
	5
	6	#include "mdp5_kms.h"
	7	#include "mdp5_cfg.h"
	8
	9	struct mdp5_cfg_handler {
	10	int revision;
	11	struct mdp5_cfg config;
	12	};
	13
	14	/* mdp5_cfg must be exposed (used in mdp5.xml.h) */
	15	const struct mdp5_cfg_hw *mdp5_cfg = NULL;
	16
8a94b0aa	17	const struct mdp5_cfg_hw msm8x74v1_config = {
	18	.name = "msm8x74v1",
	19	.mdp = {
	20	.count = 1,
d879eb5a SV	21	.caps = MDP_CAP_SMP \|
d879eb5a SV	22	0,
8a94b0aa	23	},
	24	.smp = {
	25	.mmb_count = 22,
	26	.mmb_size = 4096,
	27	.clients = {
	28	[SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
	29	[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
	30	[SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
	31	},
	32	},
	33	.ctl = {
	34	.count = 5,
031d63dd	35	.base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
8a94b0aa	36	.flush_hw_mask = 0x0003ffff,
	37	},
	38	.pipe_vig = {
	39	.count = 3,
031d63dd	40	.base = { 0x01100, 0x01500, 0x01900 },
8a94b0aa	41	.caps = MDP_PIPE_CAP_HFLIP \|
	42	MDP_PIPE_CAP_VFLIP \|
	43	MDP_PIPE_CAP_SCALE \|
	44	MDP_PIPE_CAP_CSC \|
	45	0,
	46	},
	47	.pipe_rgb = {
	48	.count = 3,
031d63dd	49	.base = { 0x01d00, 0x02100, 0x02500 },
8a94b0aa	50	.caps = MDP_PIPE_CAP_HFLIP \|
	51	MDP_PIPE_CAP_VFLIP \|
	52	MDP_PIPE_CAP_SCALE \|
	53	0,
	54	},
	55	.pipe_dma = {
	56	.count = 2,
031d63dd	57	.base = { 0x02900, 0x02d00 },
8a94b0aa	58	.caps = MDP_PIPE_CAP_HFLIP \|
	59	MDP_PIPE_CAP_VFLIP \|
	60	0,
	61	},
	62	.lm = {
	63	.count = 5,
031d63dd	64	.base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
384dbd8c AT	65	.instances = {
	66	{ .id = 0, .pp = 0, .dspp = 0,
	67	.caps = MDP_LM_CAP_DISPLAY, },
	68	{ .id = 1, .pp = 1, .dspp = 1,
	69	.caps = MDP_LM_CAP_DISPLAY, },
	70	{ .id = 2, .pp = 2, .dspp = 2,
	71	.caps = MDP_LM_CAP_DISPLAY, },
	72	{ .id = 3, .pp = -1, .dspp = -1,
	73	.caps = MDP_LM_CAP_WB },
	74	{ .id = 4, .pp = -1, .dspp = -1,
	75	.caps = MDP_LM_CAP_WB },
	76	},
8a94b0aa	77	.nb_stages = 5,
aa3c2ba1 RC	78	.max_width = 2048,
aa3c2ba1 RC	79	.max_height = 0xFFFF,
8a94b0aa	80	},
	81	.dspp = {
	82	.count = 3,
031d63dd	83	.base = { 0x04500, 0x04900, 0x04d00 },
8a94b0aa	84	},
	85	.pp = {
	86	.count = 3,
031d63dd	87	.base = { 0x21a00, 0x21b00, 0x21c00 },
8a94b0aa	88	},
8a94b0aa	89	.intf = {
031d63dd	90	.base = { 0x21000, 0x21200, 0x21400, 0x21600 },
8a94b0aa	91	.connect = {
	92	[0] = INTF_eDP,
	93	[1] = INTF_DSI,
	94	[2] = INTF_DSI,
	95	[3] = INTF_HDMI,
	96	},
	97	},
	98	.max_clk = 200000000,
	99	};
	100
	101	const struct mdp5_cfg_hw msm8x74v2_config = {
2e362e17	102	.name = "msm8x74",
f5253812 SV	103	.mdp = {
f5253812 SV	104	.count = 1,
d879eb5a SV	105	.caps = MDP_CAP_SMP \|
d879eb5a SV	106	0,
f5253812	107	},
2e362e17 SV	108	.smp = {
	109	.mmb_count = 22,
	110	.mmb_size = 4096,
6fa6acdf SV	111	.clients = {
	112	[SSPP_VIG0] = 1, [SSPP_VIG1] = 4, [SSPP_VIG2] = 7,
	113	[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
	114	[SSPP_RGB0] = 16, [SSPP_RGB1] = 17, [SSPP_RGB2] = 18,
	115	},
2e362e17 SV	116	},
	117	.ctl = {
	118	.count = 5,
031d63dd	119	.base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
389b09a1	120	.flush_hw_mask = 0x0003ffff,
2e362e17 SV	121	},
	122	.pipe_vig = {
	123	.count = 3,
031d63dd	124	.base = { 0x01100, 0x01500, 0x01900 },
3498409f	125	.caps = MDP_PIPE_CAP_HFLIP \| MDP_PIPE_CAP_VFLIP \|
	126	MDP_PIPE_CAP_SCALE \| MDP_PIPE_CAP_CSC \|
	127	MDP_PIPE_CAP_DECIMATION,
2e362e17 SV	128	},
	129	.pipe_rgb = {
	130	.count = 3,
031d63dd	131	.base = { 0x01d00, 0x02100, 0x02500 },
3498409f	132	.caps = MDP_PIPE_CAP_HFLIP \| MDP_PIPE_CAP_VFLIP \|
3498409f	133	MDP_PIPE_CAP_SCALE \| MDP_PIPE_CAP_DECIMATION,
2e362e17 SV	134	},
	135	.pipe_dma = {
	136	.count = 2,
031d63dd	137	.base = { 0x02900, 0x02d00 },
3498409f	138	.caps = MDP_PIPE_CAP_HFLIP \| MDP_PIPE_CAP_VFLIP,
2e362e17 SV	139	},
	140	.lm = {
	141	.count = 5,
031d63dd	142	.base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 },
384dbd8c AT	143	.instances = {
	144	{ .id = 0, .pp = 0, .dspp = 0,
	145	.caps = MDP_LM_CAP_DISPLAY, },
	146	{ .id = 1, .pp = 1, .dspp = 1,
	147	.caps = MDP_LM_CAP_DISPLAY, },
	148	{ .id = 2, .pp = 2, .dspp = 2,
	149	.caps = MDP_LM_CAP_DISPLAY, },
	150	{ .id = 3, .pp = -1, .dspp = -1,
	151	.caps = MDP_LM_CAP_WB, },
	152	{ .id = 4, .pp = -1, .dspp = -1,
	153	.caps = MDP_LM_CAP_WB, },
	154	},
2e362e17	155	.nb_stages = 5,
9b7a9fc2 HL	156	.max_width = 2048,
9b7a9fc2 HL	157	.max_height = 0xFFFF,
2e362e17 SV	158	},
	159	.dspp = {
	160	.count = 3,
031d63dd	161	.base = { 0x04500, 0x04900, 0x04d00 },
2e362e17 SV	162	},
	163	.ad = {
	164	.count = 2,
031d63dd	165	.base = { 0x13000, 0x13200 },
2e362e17	166	},
38305907 HL	167	.pp = {
38305907 HL	168	.count = 3,
031d63dd	169	.base = { 0x12c00, 0x12d00, 0x12e00 },
38305907	170	},
2e362e17	171	.intf = {
031d63dd	172	.base = { 0x12400, 0x12600, 0x12800, 0x12a00 },
fe34464d SV	173	.connect = {
	174	[0] = INTF_eDP,
	175	[1] = INTF_DSI,
	176	[2] = INTF_DSI,
	177	[3] = INTF_HDMI,
	178	},
67ac0a2d	179	},
2e362e17 SV	180	.max_clk = 200000000,
	181	};
	182
	183	const struct mdp5_cfg_hw apq8084_config = {
	184	.name = "apq8084",
f5253812 SV	185	.mdp = {
f5253812 SV	186	.count = 1,
d879eb5a	187	.caps = MDP_CAP_SMP \|
621da7d9	188	MDP_CAP_SRC_SPLIT \|
d879eb5a	189	0,
f5253812	190	},
2e362e17 SV	191	.smp = {
	192	.mmb_count = 44,
	193	.mmb_size = 8192,
6fa6acdf SV	194	.clients = {
	195	[SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
	196	[SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
	197	[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
	198	[SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
	199	[SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
	200	},
2e362e17	201	.reserved_state[0] = GENMASK(7, 0), /* first 8 MMBs */
6fa6acdf SV	202	.reserved = {
	203	/* Two SMP blocks are statically tied to RGB pipes: */
	204	[16] = 2, [17] = 2, [18] = 2, [22] = 2,
	205	},
2e362e17 SV	206	},
	207	.ctl = {
	208	.count = 5,
031d63dd	209	.base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 },
389b09a1	210	.flush_hw_mask = 0x003fffff,
2e362e17 SV	211	},
	212	.pipe_vig = {
	213	.count = 4,
031d63dd	214	.base = { 0x01100, 0x01500, 0x01900, 0x01d00 },
3498409f	215	.caps = MDP_PIPE_CAP_HFLIP \| MDP_PIPE_CAP_VFLIP \|
	216	MDP_PIPE_CAP_SCALE \| MDP_PIPE_CAP_CSC \|
	217	MDP_PIPE_CAP_DECIMATION,
2e362e17 SV	218	},
	219	.pipe_rgb = {
	220	.count = 4,
031d63dd	221	.base = { 0x02100, 0x02500, 0x02900, 0x02d00 },
3498409f	222	.caps = MDP_PIPE_CAP_HFLIP \| MDP_PIPE_CAP_VFLIP \|
3498409f	223	MDP_PIPE_CAP_SCALE \| MDP_PIPE_CAP_DECIMATION,
2e362e17 SV	224	},
	225	.pipe_dma = {
	226	.count = 2,
031d63dd	227	.base = { 0x03100, 0x03500 },
3498409f	228	.caps = MDP_PIPE_CAP_HFLIP \| MDP_PIPE_CAP_VFLIP,
2e362e17 SV	229	},
	230	.lm = {
	231	.count = 6,
031d63dd	232	.base = { 0x03900, 0x03d00, 0x04100, 0x04500, 0x04900, 0x04d00 },
384dbd8c AT	233	.instances = {
384dbd8c AT	234	{ .id = 0, .pp = 0, .dspp = 0,
621da7d9 AT	235	.caps = MDP_LM_CAP_DISPLAY \|
621da7d9 AT	236	MDP_LM_CAP_PAIR, },
384dbd8c AT	237	{ .id = 1, .pp = 1, .dspp = 1,
	238	.caps = MDP_LM_CAP_DISPLAY, },
	239	{ .id = 2, .pp = 2, .dspp = 2,
621da7d9 AT	240	.caps = MDP_LM_CAP_DISPLAY \|
621da7d9 AT	241	MDP_LM_CAP_PAIR, },
384dbd8c AT	242	{ .id = 3, .pp = -1, .dspp = -1,
	243	.caps = MDP_LM_CAP_WB, },
	244	{ .id = 4, .pp = -1, .dspp = -1,
	245	.caps = MDP_LM_CAP_WB, },
	246	{ .id = 5, .pp = 3, .dspp = 3,
	247	.caps = MDP_LM_CAP_DISPLAY, },
	248	},
2e362e17	249	.nb_stages = 5,
9b7a9fc2 HL	250	.max_width = 2048,
9b7a9fc2 HL	251	.max_height = 0xFFFF,
2e362e17 SV	252	},
	253	.dspp = {
	254	.count = 4,
031d63dd	255	.base = { 0x05100, 0x05500, 0x05900, 0x05d00 },
2e362e17 SV	256
	257	},
	258	.ad = {
	259	.count = 3,
031d63dd	260	.base = { 0x13400, 0x13600, 0x13800 },
2e362e17	261	},
38305907 HL	262	.pp = {
38305907 HL	263	.count = 4,
031d63dd	264	.base = { 0x12e00, 0x12f00, 0x13000, 0x13100 },
38305907	265	},
2e362e17	266	.intf = {
031d63dd	267	.base = { 0x12400, 0x12600, 0x12800, 0x12a00, 0x12c00 },
fe34464d SV	268	.connect = {
	269	[0] = INTF_eDP,
	270	[1] = INTF_DSI,
	271	[2] = INTF_DSI,
	272	[3] = INTF_HDMI,
	273	},
67ac0a2d	274	},
2e362e17 SV	275	.max_clk = 320000000,
	276	};
	277
02dfd9d2 SV	278	const struct mdp5_cfg_hw msm8x16_config = {
	279	.name = "msm8x16",
	280	.mdp = {
	281	.count = 1,
031d63dd	282	.base = { 0x0 },
d879eb5a SV	283	.caps = MDP_CAP_SMP \|
d879eb5a SV	284	0,
02dfd9d2 SV	285	},
	286	.smp = {
	287	.mmb_count = 8,
	288	.mmb_size = 8192,
	289	.clients = {
	290	[SSPP_VIG0] = 1, [SSPP_DMA0] = 4,
	291	[SSPP_RGB0] = 7, [SSPP_RGB1] = 8,
	292	},
	293	},
	294	.ctl = {
	295	.count = 5,
031d63dd	296	.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
02dfd9d2 SV	297	.flush_hw_mask = 0x4003ffff,
	298	},
	299	.pipe_vig = {
	300	.count = 1,
031d63dd	301	.base = { 0x04000 },
3498409f	302	.caps = MDP_PIPE_CAP_HFLIP \| MDP_PIPE_CAP_VFLIP \|
	303	MDP_PIPE_CAP_SCALE \| MDP_PIPE_CAP_CSC \|
	304	MDP_PIPE_CAP_DECIMATION,
02dfd9d2 SV	305	},
	306	.pipe_rgb = {
	307	.count = 2,
031d63dd	308	.base = { 0x14000, 0x16000 },
3498409f	309	.caps = MDP_PIPE_CAP_HFLIP \| MDP_PIPE_CAP_VFLIP \|
2c381848	310	MDP_PIPE_CAP_DECIMATION,
02dfd9d2 SV	311	},
	312	.pipe_dma = {
	313	.count = 1,
031d63dd	314	.base = { 0x24000 },
3498409f	315	.caps = MDP_PIPE_CAP_HFLIP \| MDP_PIPE_CAP_VFLIP,
02dfd9d2 SV	316	},
	317	.lm = {
	318	.count = 2, /* LM0 and LM3 */
031d63dd	319	.base = { 0x44000, 0x47000 },
384dbd8c AT	320	.instances = {
	321	{ .id = 0, .pp = 0, .dspp = 0,
	322	.caps = MDP_LM_CAP_DISPLAY, },
	323	{ .id = 3, .pp = -1, .dspp = -1,
	324	.caps = MDP_LM_CAP_WB },
	325	},
702673f6	326	.nb_stages = 8,
9b7a9fc2 HL	327	.max_width = 2048,
9b7a9fc2 HL	328	.max_height = 0xFFFF,
02dfd9d2 SV	329	},
	330	.dspp = {
	331	.count = 1,
031d63dd	332	.base = { 0x54000 },
02dfd9d2 SV	333
	334	},
	335	.intf = {
031d63dd	336	.base = { 0x00000, 0x6a800 },
fe34464d SV	337	.connect = {
	338	[0] = INTF_DISABLED,
	339	[1] = INTF_DSI,
	340	},
02dfd9d2	341	},
02dfd9d2 SV	342	.max_clk = 320000000,
	343	};
	344
3a84f846 SV	345	const struct mdp5_cfg_hw msm8x94_config = {
	346	.name = "msm8x94",
	347	.mdp = {
	348	.count = 1,
d879eb5a	349	.caps = MDP_CAP_SMP \|
621da7d9	350	MDP_CAP_SRC_SPLIT \|
d879eb5a	351	0,
3a84f846 SV	352	},
	353	.smp = {
	354	.mmb_count = 44,
	355	.mmb_size = 8192,
	356	.clients = {
	357	[SSPP_VIG0] = 1, [SSPP_VIG1] = 4,
	358	[SSPP_VIG2] = 7, [SSPP_VIG3] = 19,
	359	[SSPP_DMA0] = 10, [SSPP_DMA1] = 13,
	360	[SSPP_RGB0] = 16, [SSPP_RGB1] = 17,
	361	[SSPP_RGB2] = 18, [SSPP_RGB3] = 22,
	362	},
	363	.reserved_state[0] = GENMASK(23, 0), /* first 24 MMBs */
	364	.reserved = {
	365	[1] = 1, [4] = 1, [7] = 1, [19] = 1,
	366	[16] = 5, [17] = 5, [18] = 5, [22] = 5,
	367	},
	368	},
	369	.ctl = {
	370	.count = 5,
031d63dd	371	.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
3a84f846 SV	372	.flush_hw_mask = 0xf0ffffff,
	373	},
	374	.pipe_vig = {
	375	.count = 4,
031d63dd	376	.base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
3498409f	377	.caps = MDP_PIPE_CAP_HFLIP \| MDP_PIPE_CAP_VFLIP \|
	378	MDP_PIPE_CAP_SCALE \| MDP_PIPE_CAP_CSC \|
	379	MDP_PIPE_CAP_DECIMATION,
3a84f846 SV	380	},
	381	.pipe_rgb = {
	382	.count = 4,
031d63dd	383	.base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
3498409f	384	.caps = MDP_PIPE_CAP_HFLIP \| MDP_PIPE_CAP_VFLIP \|
3498409f	385	MDP_PIPE_CAP_SCALE \| MDP_PIPE_CAP_DECIMATION,
3a84f846 SV	386	},
	387	.pipe_dma = {
	388	.count = 2,
031d63dd	389	.base = { 0x24000, 0x26000 },
3498409f	390	.caps = MDP_PIPE_CAP_HFLIP \| MDP_PIPE_CAP_VFLIP,
3a84f846 SV	391	},
	392	.lm = {
	393	.count = 6,
031d63dd	394	.base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
384dbd8c AT	395	.instances = {
384dbd8c AT	396	{ .id = 0, .pp = 0, .dspp = 0,
621da7d9 AT	397	.caps = MDP_LM_CAP_DISPLAY \|
621da7d9 AT	398	MDP_LM_CAP_PAIR, },
384dbd8c AT	399	{ .id = 1, .pp = 1, .dspp = 1,
	400	.caps = MDP_LM_CAP_DISPLAY, },
	401	{ .id = 2, .pp = 2, .dspp = 2,
621da7d9 AT	402	.caps = MDP_LM_CAP_DISPLAY \|
621da7d9 AT	403	MDP_LM_CAP_PAIR, },
384dbd8c AT	404	{ .id = 3, .pp = -1, .dspp = -1,
	405	.caps = MDP_LM_CAP_WB, },
	406	{ .id = 4, .pp = -1, .dspp = -1,
	407	.caps = MDP_LM_CAP_WB, },
	408	{ .id = 5, .pp = 3, .dspp = 3,
	409	.caps = MDP_LM_CAP_DISPLAY, },
	410	},
3a84f846	411	.nb_stages = 8,
9b7a9fc2 HL	412	.max_width = 2048,
9b7a9fc2 HL	413	.max_height = 0xFFFF,
3a84f846 SV	414	},
	415	.dspp = {
	416	.count = 4,
031d63dd	417	.base = { 0x54000, 0x56000, 0x58000, 0x5a000 },
3a84f846 SV	418
	419	},
	420	.ad = {
	421	.count = 3,
031d63dd	422	.base = { 0x78000, 0x78800, 0x79000 },
3a84f846 SV	423	},
	424	.pp = {
	425	.count = 4,
031d63dd	426	.base = { 0x70000, 0x70800, 0x71000, 0x71800 },
3a84f846 SV	427	},
3a84f846 SV	428	.intf = {
031d63dd	429	.base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
3a84f846 SV	430	.connect = {
	431	[0] = INTF_DISABLED,
	432	[1] = INTF_DSI,
	433	[2] = INTF_DSI,
	434	[3] = INTF_HDMI,
	435	},
	436	},
d879eb5a SV	437	.max_clk = 400000000,
	438	};
	439
	440	const struct mdp5_cfg_hw msm8x96_config = {
	441	.name = "msm8x96",
	442	.mdp = {
	443	.count = 1,
d879eb5a SV	444	.caps = MDP_CAP_DSC \|
d879eb5a SV	445	MDP_CAP_CDM \|
621da7d9	446	MDP_CAP_SRC_SPLIT \|
d879eb5a SV	447	0,
	448	},
	449	.ctl = {
	450	.count = 5,
031d63dd	451	.base = { 0x01000, 0x01200, 0x01400, 0x01600, 0x01800 },
d879eb5a SV	452	.flush_hw_mask = 0xf4ffffff,
	453	},
	454	.pipe_vig = {
	455	.count = 4,
031d63dd	456	.base = { 0x04000, 0x06000, 0x08000, 0x0a000 },
d879eb5a SV	457	.caps = MDP_PIPE_CAP_HFLIP \|
	458	MDP_PIPE_CAP_VFLIP \|
	459	MDP_PIPE_CAP_SCALE \|
	460	MDP_PIPE_CAP_CSC \|
	461	MDP_PIPE_CAP_DECIMATION \|
	462	MDP_PIPE_CAP_SW_PIX_EXT \|
	463	0,
	464	},
	465	.pipe_rgb = {
	466	.count = 4,
031d63dd	467	.base = { 0x14000, 0x16000, 0x18000, 0x1a000 },
d879eb5a SV	468	.caps = MDP_PIPE_CAP_HFLIP \|
	469	MDP_PIPE_CAP_VFLIP \|
	470	MDP_PIPE_CAP_SCALE \|
	471	MDP_PIPE_CAP_DECIMATION \|
	472	MDP_PIPE_CAP_SW_PIX_EXT \|
	473	0,
	474	},
	475	.pipe_dma = {
	476	.count = 2,
031d63dd	477	.base = { 0x24000, 0x26000 },
d879eb5a SV	478	.caps = MDP_PIPE_CAP_HFLIP \|
	479	MDP_PIPE_CAP_VFLIP \|
	480	MDP_PIPE_CAP_SW_PIX_EXT \|
	481	0,
	482	},
5798c8e0 AT	483	.pipe_cursor = {
	484	.count = 2,
	485	.base = { 0x34000, 0x36000 },
	486	.caps = MDP_PIPE_CAP_HFLIP \|
	487	MDP_PIPE_CAP_VFLIP \|
	488	MDP_PIPE_CAP_SW_PIX_EXT \|
	489	MDP_PIPE_CAP_CURSOR \|
	490	0,
	491	},
	492
d879eb5a SV	493	.lm = {
d879eb5a SV	494	.count = 6,
031d63dd	495	.base = { 0x44000, 0x45000, 0x46000, 0x47000, 0x48000, 0x49000 },
384dbd8c AT	496	.instances = {
384dbd8c AT	497	{ .id = 0, .pp = 0, .dspp = 0,
621da7d9 AT	498	.caps = MDP_LM_CAP_DISPLAY \|
621da7d9 AT	499	MDP_LM_CAP_PAIR, },
384dbd8c AT	500	{ .id = 1, .pp = 1, .dspp = 1,
	501	.caps = MDP_LM_CAP_DISPLAY, },
	502	{ .id = 2, .pp = 2, .dspp = -1,
621da7d9 AT	503	.caps = MDP_LM_CAP_DISPLAY \|
621da7d9 AT	504	MDP_LM_CAP_PAIR, },
384dbd8c AT	505	{ .id = 3, .pp = -1, .dspp = -1,
	506	.caps = MDP_LM_CAP_WB, },
	507	{ .id = 4, .pp = -1, .dspp = -1,
	508	.caps = MDP_LM_CAP_WB, },
	509	{ .id = 5, .pp = 3, .dspp = -1,
	510	.caps = MDP_LM_CAP_DISPLAY, },
	511	},
d879eb5a SV	512	.nb_stages = 8,
	513	.max_width = 2560,
	514	.max_height = 0xFFFF,
	515	},
	516	.dspp = {
	517	.count = 2,
031d63dd	518	.base = { 0x54000, 0x56000 },
d879eb5a SV	519	},
	520	.ad = {
	521	.count = 3,
031d63dd	522	.base = { 0x78000, 0x78800, 0x79000 },
d879eb5a SV	523	},
	524	.pp = {
	525	.count = 4,
031d63dd	526	.base = { 0x70000, 0x70800, 0x71000, 0x71800 },
d879eb5a SV	527	},
	528	.cdm = {
	529	.count = 1,
031d63dd	530	.base = { 0x79200 },
d879eb5a SV	531	},
	532	.dsc = {
	533	.count = 2,
031d63dd	534	.base = { 0x80000, 0x80400 },
d879eb5a SV	535	},
d879eb5a SV	536	.intf = {
031d63dd	537	.base = { 0x6a000, 0x6a800, 0x6b000, 0x6b800, 0x6c000 },
d879eb5a SV	538	.connect = {
	539	[0] = INTF_DISABLED,
	540	[1] = INTF_DSI,
	541	[2] = INTF_DSI,
	542	[3] = INTF_HDMI,
	543	},
	544	},
	545	.max_clk = 412500000,
3a84f846 SV	546	};
3a84f846 SV	547
a5cd7b55 JM	548	const struct mdp5_cfg_hw msm8917_config = {
	549	.name = "msm8917",
	550	.mdp = {
	551	.count = 1,
	552	.caps = MDP_CAP_CDM,
	553	},
	554	.ctl = {
	555	.count = 3,
	556	.base = { 0x01000, 0x01200, 0x01400 },
	557	.flush_hw_mask = 0xffffffff,
	558	},
	559	.pipe_vig = {
	560	.count = 1,
	561	.base = { 0x04000 },
	562	.caps = MDP_PIPE_CAP_HFLIP \|
	563	MDP_PIPE_CAP_VFLIP \|
	564	MDP_PIPE_CAP_SCALE \|
	565	MDP_PIPE_CAP_CSC \|
	566	MDP_PIPE_CAP_DECIMATION \|
	567	MDP_PIPE_CAP_SW_PIX_EXT \|
	568	0,
	569	},
	570	.pipe_rgb = {
	571	.count = 2,
	572	.base = { 0x14000, 0x16000 },
	573	.caps = MDP_PIPE_CAP_HFLIP \|
	574	MDP_PIPE_CAP_VFLIP \|
	575	MDP_PIPE_CAP_DECIMATION \|
	576	MDP_PIPE_CAP_SW_PIX_EXT \|
	577	0,
	578	},
	579	.pipe_dma = {
	580	.count = 1,
	581	.base = { 0x24000 },
	582	.caps = MDP_PIPE_CAP_HFLIP \|
	583	MDP_PIPE_CAP_VFLIP \|
	584	MDP_PIPE_CAP_SW_PIX_EXT \|
	585	0,
	586	},
	587	.pipe_cursor = {
	588	.count = 1,
	589	.base = { 0x34000 },
	590	.caps = MDP_PIPE_CAP_HFLIP \|
	591	MDP_PIPE_CAP_VFLIP \|
	592	MDP_PIPE_CAP_SW_PIX_EXT \|
	593	MDP_PIPE_CAP_CURSOR \|
	594	0,
	595	},
	596
	597	.lm = {
	598	.count = 2,
	599	.base = { 0x44000, 0x45000 },
	600	.instances = {
	601	{ .id = 0, .pp = 0, .dspp = 0,
	602	.caps = MDP_LM_CAP_DISPLAY, },
	603	{ .id = 1, .pp = -1, .dspp = -1,
	604	.caps = MDP_LM_CAP_WB },
	605	},
	606	.nb_stages = 8,
	607	.max_width = 2048,
	608	.max_height = 0xFFFF,
	609	},
	610	.dspp = {
	611	.count = 1,
612	.base = { 0x54000 },
613
614	},
615	.pp = {
616	.count = 1,
617	.base = { 0x70000 },
618	},
619	.cdm = {
620	.count = 1,
621	.base = { 0x79200 },
622	},
623	.intf = {
624	.base = { 0x6a000, 0x6a800 },
625	.connect = {
626	[0] = INTF_DISABLED,
627	[1] = INTF_DSI,
628	},
629	},
630	.max_clk = 320000000,
631	};
632
2e362e17	633	static const struct mdp5_cfg_handler cfg_handlers[] = {
8a94b0aa	634	{ .revision = 0, .config = { .hw = &msm8x74v1_config } },
8a94b0aa	635	{ .revision = 2, .config = { .hw = &msm8x74v2_config } },
2e362e17	636	{ .revision = 3, .config = { .hw = &apq8084_config } },
02dfd9d2	637	{ .revision = 6, .config = { .hw = &msm8x16_config } },
3a84f846	638	{ .revision = 9, .config = { .hw = &msm8x94_config } },
d879eb5a	639	{ .revision = 7, .config = { .hw = &msm8x96_config } },
a5cd7b55	640	{ .revision = 15, .config = { .hw = &msm8917_config } },
2e362e17 SV	641	};
2e362e17 SV	642
2e362e17 SV	643	static struct mdp5_cfg_platform mdp5_get_config(struct platform_device dev);
2e362e17 SV	644
42238da8	645	const struct mdp5_cfg_hw mdp5_cfg_get_hw_config(struct mdp5_cfg_handler cfg_handler)
2e362e17	646	{
2e362e17 SV	647	return cfg_handler->config.hw;
	648	}
	649
42238da8	650	struct mdp5_cfg mdp5_cfg_get_config(struct mdp5_cfg_handler cfg_handler)
2e362e17	651	{
2e362e17 SV	652	return &cfg_handler->config;
	653	}
	654
42238da8	655	int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_handler)
2e362e17	656	{
2e362e17 SV	657	return cfg_handler->revision;
	658	}
	659
42238da8	660	void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_handler)
2e362e17	661	{
2e362e17 SV	662	kfree(cfg_handler);
	663	}
	664
42238da8	665	struct mdp5_cfg_handler mdp5_cfg_init(struct mdp5_kms mdp5_kms,
2e362e17 SV	666	uint32_t major, uint32_t minor)
	667	{
	668	struct drm_device *dev = mdp5_kms->dev;
76adb460	669	struct platform_device *pdev = to_platform_device(dev->dev);
2e362e17 SV	670	struct mdp5_cfg_handler *cfg_handler;
	671	struct mdp5_cfg_platform *pconfig;
	672	int i, ret = 0;
	673
	674	cfg_handler = kzalloc(sizeof(*cfg_handler), GFP_KERNEL);
	675	if (unlikely(!cfg_handler)) {
	676	ret = -ENOMEM;
	677	goto fail;
	678	}
	679
	680	if (major != 1) {
6a41da17	681	DRM_DEV_ERROR(dev->dev, "unexpected MDP major version: v%d.%d\n",
2e362e17 SV	682	major, minor);
	683	ret = -ENXIO;
	684	goto fail;
	685	}
	686
	687	/* only after mdp5_cfg global pointer's init can we access the hw */
	688	for (i = 0; i < ARRAY_SIZE(cfg_handlers); i++) {
	689	if (cfg_handlers[i].revision != minor)
	690	continue;
	691	mdp5_cfg = cfg_handlers[i].config.hw;
	692
	693	break;
	694	}
	695	if (unlikely(!mdp5_cfg)) {
6a41da17	696	DRM_DEV_ERROR(dev->dev, "unexpected MDP minor revision: v%d.%d\n",
2e362e17 SV	697	major, minor);
	698	ret = -ENXIO;
	699	goto fail;
	700	}
	701
	702	cfg_handler->revision = minor;
	703	cfg_handler->config.hw = mdp5_cfg;
	704
	705	pconfig = mdp5_get_config(pdev);
	706	memcpy(&cfg_handler->config.platform, pconfig, sizeof(*pconfig));
	707
	708	DBG("MDP5: %s hw config selected", mdp5_cfg->name);
	709
	710	return cfg_handler;
	711
	712	fail:
	713	if (cfg_handler)
	714	mdp5_cfg_destroy(cfg_handler);
	715
	716	return NULL;
	717	}
	718
	719	static struct mdp5_cfg_platform mdp5_get_config(struct platform_device dev)
	720	{
	721	static struct mdp5_cfg_platform config = {};
d50c192a	722
2e362e17	723	config.iommu = iommu_domain_alloc(&platform_bus_type);
667ce33e RC	724	if (config.iommu) {
	725	config.iommu->geometry.aperture_start = 0x1000;
	726	config.iommu->geometry.aperture_end = 0xffffffff;
	727	}
2e362e17 SV	728
	729	return &config;
	730	}