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97fb5e8d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
a689554b HL |
2 | /* |
3 | * Copyright (c) 2015, The Linux Foundation. All rights reserved. | |
a689554b HL |
4 | */ |
5 | ||
6 | #include <linux/clk.h> | |
7 | #include <linux/delay.h> | |
8 | #include <linux/err.h> | |
9 | #include <linux/gpio.h> | |
964a0754 | 10 | #include <linux/gpio/consumer.h> |
a689554b HL |
11 | #include <linux/interrupt.h> |
12 | #include <linux/of_device.h> | |
13 | #include <linux/of_gpio.h> | |
14 | #include <linux/of_irq.h> | |
ab8909b0 | 15 | #include <linux/pinctrl/consumer.h> |
f7009d26 | 16 | #include <linux/of_graph.h> |
a689554b HL |
17 | #include <linux/regulator/consumer.h> |
18 | #include <linux/spinlock.h> | |
0c7df47f AT |
19 | #include <linux/mfd/syscon.h> |
20 | #include <linux/regmap.h> | |
a689554b HL |
21 | #include <video/mipi_display.h> |
22 | ||
23 | #include "dsi.h" | |
24 | #include "dsi.xml.h" | |
0c7df47f | 25 | #include "sfpb.xml.h" |
d248b61f | 26 | #include "dsi_cfg.h" |
f59f62d5 | 27 | #include "msm_kms.h" |
a689554b HL |
28 | |
29 | static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) | |
30 | { | |
31 | u32 ver; | |
a689554b HL |
32 | |
33 | if (!major || !minor) | |
34 | return -EINVAL; | |
35 | ||
648d5063 AT |
36 | /* |
37 | * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 | |
a689554b | 38 | * makes all other registers 4-byte shifted down. |
648d5063 AT |
39 | * |
40 | * In order to identify between DSI6G(v3) and beyond, and DSIv2 and | |
41 | * older, we read the DSI_VERSION register without any shift(offset | |
42 | * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In | |
43 | * the case of DSI6G, this has to be zero (the offset points to a | |
44 | * scratch register which we never touch) | |
a689554b | 45 | */ |
648d5063 AT |
46 | |
47 | ver = msm_readl(base + REG_DSI_VERSION); | |
48 | if (ver) { | |
49 | /* older dsi host, there is no register shift */ | |
a689554b HL |
50 | ver = FIELD(ver, DSI_VERSION_MAJOR); |
51 | if (ver <= MSM_DSI_VER_MAJOR_V2) { | |
52 | /* old versions */ | |
53 | *major = ver; | |
54 | *minor = 0; | |
55 | return 0; | |
56 | } else { | |
57 | return -EINVAL; | |
58 | } | |
59 | } else { | |
648d5063 AT |
60 | /* |
61 | * newer host, offset 0 has 6G_HW_VERSION, the rest of the | |
62 | * registers are shifted down, read DSI_VERSION again with | |
63 | * the shifted offset | |
64 | */ | |
a689554b HL |
65 | ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); |
66 | ver = FIELD(ver, DSI_VERSION_MAJOR); | |
67 | if (ver == MSM_DSI_VER_MAJOR_6G) { | |
68 | /* 6G version */ | |
69 | *major = ver; | |
648d5063 | 70 | *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); |
a689554b HL |
71 | return 0; |
72 | } else { | |
73 | return -EINVAL; | |
74 | } | |
75 | } | |
76 | } | |
77 | ||
78 | #define DSI_ERR_STATE_ACK 0x0000 | |
79 | #define DSI_ERR_STATE_TIMEOUT 0x0001 | |
80 | #define DSI_ERR_STATE_DLN0_PHY 0x0002 | |
81 | #define DSI_ERR_STATE_FIFO 0x0004 | |
82 | #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 | |
83 | #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 | |
84 | #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 | |
85 | ||
86 | #define DSI_CLK_CTRL_ENABLE_CLKS \ | |
87 | (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ | |
88 | DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ | |
89 | DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ | |
90 | DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) | |
91 | ||
92 | struct msm_dsi_host { | |
93 | struct mipi_dsi_host base; | |
94 | ||
95 | struct platform_device *pdev; | |
96 | struct drm_device *dev; | |
97 | ||
98 | int id; | |
99 | ||
100 | void __iomem *ctrl_base; | |
ec31abf6 | 101 | struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; |
6e0eb52e AT |
102 | |
103 | struct clk *bus_clks[DSI_BUS_CLK_MAX]; | |
104 | ||
a689554b HL |
105 | struct clk *byte_clk; |
106 | struct clk *esc_clk; | |
107 | struct clk *pixel_clk; | |
9d32c498 HL |
108 | struct clk *byte_clk_src; |
109 | struct clk *pixel_clk_src; | |
c1d97083 | 110 | struct clk *byte_intf_clk; |
9d32c498 | 111 | |
a689554b | 112 | u32 byte_clk_rate; |
ed9976a0 | 113 | u32 pixel_clk_rate; |
4bfa9748 AT |
114 | u32 esc_clk_rate; |
115 | ||
116 | /* DSI v2 specific clocks */ | |
117 | struct clk *src_clk; | |
118 | struct clk *esc_clk_src; | |
119 | struct clk *dsi_clk_src; | |
120 | ||
121 | u32 src_clk_rate; | |
a689554b HL |
122 | |
123 | struct gpio_desc *disp_en_gpio; | |
124 | struct gpio_desc *te_gpio; | |
125 | ||
d248b61f | 126 | const struct msm_dsi_cfg_handler *cfg_hnd; |
a689554b HL |
127 | |
128 | struct completion dma_comp; | |
129 | struct completion video_comp; | |
130 | struct mutex dev_mutex; | |
131 | struct mutex cmd_mutex; | |
a689554b HL |
132 | spinlock_t intr_lock; /* Protect interrupt ctrl register */ |
133 | ||
134 | u32 err_work_state; | |
135 | struct work_struct err_work; | |
8d23ea40 | 136 | struct work_struct hpd_work; |
a689554b HL |
137 | struct workqueue_struct *workqueue; |
138 | ||
4ff9d4cb | 139 | /* DSI 6G TX buffer*/ |
a689554b | 140 | struct drm_gem_object *tx_gem_obj; |
4ff9d4cb AT |
141 | |
142 | /* DSI v2 TX buffer */ | |
143 | void *tx_buf; | |
144 | dma_addr_t tx_buf_paddr; | |
145 | ||
146 | int tx_size; | |
147 | ||
a689554b HL |
148 | u8 *rx_buf; |
149 | ||
0c7df47f AT |
150 | struct regmap *sfpb; |
151 | ||
a689554b HL |
152 | struct drm_display_mode *mode; |
153 | ||
a9ddac9c AT |
154 | /* connected device info */ |
155 | struct device_node *device_node; | |
a689554b HL |
156 | unsigned int channel; |
157 | unsigned int lanes; | |
158 | enum mipi_dsi_pixel_format format; | |
159 | unsigned long mode_flags; | |
160 | ||
26f7d1f4 AT |
161 | /* lane data parsed via DT */ |
162 | int dlane_swap; | |
163 | int num_data_lanes; | |
164 | ||
a689554b HL |
165 | u32 dma_cmd_ctrl_restore; |
166 | ||
167 | bool registered; | |
168 | bool power_on; | |
9c5638d7 | 169 | bool enabled; |
a689554b HL |
170 | int irq; |
171 | }; | |
172 | ||
173 | static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt) | |
174 | { | |
175 | switch (fmt) { | |
176 | case MIPI_DSI_FMT_RGB565: return 16; | |
177 | case MIPI_DSI_FMT_RGB666_PACKED: return 18; | |
178 | case MIPI_DSI_FMT_RGB666: | |
179 | case MIPI_DSI_FMT_RGB888: | |
180 | default: return 24; | |
181 | } | |
182 | } | |
183 | ||
184 | static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) | |
185 | { | |
d248b61f | 186 | return msm_readl(msm_host->ctrl_base + reg); |
a689554b HL |
187 | } |
188 | static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) | |
189 | { | |
d248b61f | 190 | msm_writel(data, msm_host->ctrl_base + reg); |
a689554b HL |
191 | } |
192 | ||
193 | static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host); | |
194 | static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host); | |
195 | ||
d248b61f HL |
196 | static const struct msm_dsi_cfg_handler *dsi_get_config( |
197 | struct msm_dsi_host *msm_host) | |
a689554b | 198 | { |
d248b61f | 199 | const struct msm_dsi_cfg_handler *cfg_hnd = NULL; |
31c92767 | 200 | struct device *dev = &msm_host->pdev->dev; |
a689554b | 201 | struct regulator *gdsc_reg; |
31c92767 | 202 | struct clk *ahb_clk; |
d248b61f | 203 | int ret; |
a689554b HL |
204 | u32 major = 0, minor = 0; |
205 | ||
31c92767 | 206 | gdsc_reg = regulator_get(dev, "gdsc"); |
bdc80de2 | 207 | if (IS_ERR(gdsc_reg)) { |
a689554b | 208 | pr_err("%s: cannot get gdsc\n", __func__); |
d248b61f | 209 | goto exit; |
a689554b | 210 | } |
31c92767 | 211 | |
29a1157c | 212 | ahb_clk = msm_clk_get(msm_host->pdev, "iface"); |
31c92767 AT |
213 | if (IS_ERR(ahb_clk)) { |
214 | pr_err("%s: cannot get interface clock\n", __func__); | |
215 | goto put_gdsc; | |
216 | } | |
217 | ||
f6be1121 AT |
218 | pm_runtime_get_sync(dev); |
219 | ||
a689554b HL |
220 | ret = regulator_enable(gdsc_reg); |
221 | if (ret) { | |
222 | pr_err("%s: unable to enable gdsc\n", __func__); | |
29a1157c | 223 | goto put_gdsc; |
a689554b | 224 | } |
31c92767 AT |
225 | |
226 | ret = clk_prepare_enable(ahb_clk); | |
a689554b HL |
227 | if (ret) { |
228 | pr_err("%s: unable to enable ahb_clk\n", __func__); | |
d248b61f | 229 | goto disable_gdsc; |
a689554b HL |
230 | } |
231 | ||
232 | ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); | |
a689554b HL |
233 | if (ret) { |
234 | pr_err("%s: Invalid version\n", __func__); | |
d248b61f | 235 | goto disable_clks; |
a689554b HL |
236 | } |
237 | ||
d248b61f | 238 | cfg_hnd = msm_dsi_cfg_get(major, minor); |
a689554b | 239 | |
d248b61f HL |
240 | DBG("%s: Version %x:%x\n", __func__, major, minor); |
241 | ||
242 | disable_clks: | |
31c92767 | 243 | clk_disable_unprepare(ahb_clk); |
d248b61f HL |
244 | disable_gdsc: |
245 | regulator_disable(gdsc_reg); | |
a18a0ea0 | 246 | pm_runtime_put_sync(dev); |
d248b61f HL |
247 | put_gdsc: |
248 | regulator_put(gdsc_reg); | |
249 | exit: | |
250 | return cfg_hnd; | |
a689554b HL |
251 | } |
252 | ||
253 | static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) | |
254 | { | |
255 | return container_of(host, struct msm_dsi_host, base); | |
256 | } | |
257 | ||
258 | static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host) | |
259 | { | |
260 | struct regulator_bulk_data *s = msm_host->supplies; | |
d248b61f HL |
261 | const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; |
262 | int num = msm_host->cfg_hnd->cfg->reg_cfg.num; | |
a689554b HL |
263 | int i; |
264 | ||
265 | DBG(""); | |
266 | for (i = num - 1; i >= 0; i--) | |
267 | if (regs[i].disable_load >= 0) | |
2c33ce00 DA |
268 | regulator_set_load(s[i].consumer, |
269 | regs[i].disable_load); | |
a689554b HL |
270 | |
271 | regulator_bulk_disable(num, s); | |
272 | } | |
273 | ||
274 | static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host) | |
275 | { | |
276 | struct regulator_bulk_data *s = msm_host->supplies; | |
d248b61f HL |
277 | const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; |
278 | int num = msm_host->cfg_hnd->cfg->reg_cfg.num; | |
a689554b HL |
279 | int ret, i; |
280 | ||
281 | DBG(""); | |
282 | for (i = 0; i < num; i++) { | |
283 | if (regs[i].enable_load >= 0) { | |
2c33ce00 DA |
284 | ret = regulator_set_load(s[i].consumer, |
285 | regs[i].enable_load); | |
a689554b HL |
286 | if (ret < 0) { |
287 | pr_err("regulator %d set op mode failed, %d\n", | |
288 | i, ret); | |
289 | goto fail; | |
290 | } | |
291 | } | |
292 | } | |
293 | ||
294 | ret = regulator_bulk_enable(num, s); | |
295 | if (ret < 0) { | |
296 | pr_err("regulator enable failed, %d\n", ret); | |
297 | goto fail; | |
298 | } | |
299 | ||
300 | return 0; | |
301 | ||
302 | fail: | |
303 | for (i--; i >= 0; i--) | |
2c33ce00 | 304 | regulator_set_load(s[i].consumer, regs[i].disable_load); |
a689554b HL |
305 | return ret; |
306 | } | |
307 | ||
308 | static int dsi_regulator_init(struct msm_dsi_host *msm_host) | |
309 | { | |
310 | struct regulator_bulk_data *s = msm_host->supplies; | |
d248b61f HL |
311 | const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; |
312 | int num = msm_host->cfg_hnd->cfg->reg_cfg.num; | |
a689554b HL |
313 | int i, ret; |
314 | ||
315 | for (i = 0; i < num; i++) | |
316 | s[i].supply = regs[i].name; | |
317 | ||
318 | ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s); | |
319 | if (ret < 0) { | |
320 | pr_err("%s: failed to init regulator, ret=%d\n", | |
321 | __func__, ret); | |
322 | return ret; | |
323 | } | |
324 | ||
a689554b HL |
325 | return 0; |
326 | } | |
327 | ||
c4d8cfe5 SS |
328 | int dsi_clk_init_v2(struct msm_dsi_host *msm_host) |
329 | { | |
330 | struct platform_device *pdev = msm_host->pdev; | |
331 | int ret = 0; | |
332 | ||
333 | msm_host->src_clk = msm_clk_get(pdev, "src"); | |
334 | ||
335 | if (IS_ERR(msm_host->src_clk)) { | |
336 | ret = PTR_ERR(msm_host->src_clk); | |
337 | pr_err("%s: can't find src clock. ret=%d\n", | |
338 | __func__, ret); | |
339 | msm_host->src_clk = NULL; | |
340 | return ret; | |
341 | } | |
342 | ||
343 | msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk); | |
344 | if (!msm_host->esc_clk_src) { | |
345 | ret = -ENODEV; | |
346 | pr_err("%s: can't get esc clock parent. ret=%d\n", | |
347 | __func__, ret); | |
348 | return ret; | |
349 | } | |
350 | ||
351 | msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk); | |
352 | if (!msm_host->dsi_clk_src) { | |
353 | ret = -ENODEV; | |
354 | pr_err("%s: can't get src clock parent. ret=%d\n", | |
355 | __func__, ret); | |
356 | } | |
357 | ||
358 | return ret; | |
359 | } | |
360 | ||
361 | int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) | |
362 | { | |
363 | struct platform_device *pdev = msm_host->pdev; | |
364 | int ret = 0; | |
365 | ||
366 | msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); | |
367 | if (IS_ERR(msm_host->byte_intf_clk)) { | |
368 | ret = PTR_ERR(msm_host->byte_intf_clk); | |
369 | pr_err("%s: can't find byte_intf clock. ret=%d\n", | |
370 | __func__, ret); | |
371 | } | |
372 | ||
373 | return ret; | |
374 | } | |
375 | ||
a689554b HL |
376 | static int dsi_clk_init(struct msm_dsi_host *msm_host) |
377 | { | |
db9a3750 | 378 | struct platform_device *pdev = msm_host->pdev; |
4bfa9748 AT |
379 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
380 | const struct msm_dsi_config *cfg = cfg_hnd->cfg; | |
6e0eb52e AT |
381 | int i, ret = 0; |
382 | ||
383 | /* get bus clocks */ | |
384 | for (i = 0; i < cfg->num_bus_clks; i++) { | |
db9a3750 | 385 | msm_host->bus_clks[i] = msm_clk_get(pdev, |
6e0eb52e AT |
386 | cfg->bus_clk_names[i]); |
387 | if (IS_ERR(msm_host->bus_clks[i])) { | |
388 | ret = PTR_ERR(msm_host->bus_clks[i]); | |
db9a3750 | 389 | pr_err("%s: Unable to get %s clock, ret = %d\n", |
6e0eb52e AT |
390 | __func__, cfg->bus_clk_names[i], ret); |
391 | goto exit; | |
392 | } | |
a689554b HL |
393 | } |
394 | ||
6e0eb52e | 395 | /* get link and source clocks */ |
db9a3750 | 396 | msm_host->byte_clk = msm_clk_get(pdev, "byte"); |
a689554b HL |
397 | if (IS_ERR(msm_host->byte_clk)) { |
398 | ret = PTR_ERR(msm_host->byte_clk); | |
db9a3750 | 399 | pr_err("%s: can't find dsi_byte clock. ret=%d\n", |
a689554b HL |
400 | __func__, ret); |
401 | msm_host->byte_clk = NULL; | |
402 | goto exit; | |
403 | } | |
404 | ||
db9a3750 | 405 | msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); |
a689554b HL |
406 | if (IS_ERR(msm_host->pixel_clk)) { |
407 | ret = PTR_ERR(msm_host->pixel_clk); | |
db9a3750 | 408 | pr_err("%s: can't find dsi_pixel clock. ret=%d\n", |
a689554b HL |
409 | __func__, ret); |
410 | msm_host->pixel_clk = NULL; | |
411 | goto exit; | |
412 | } | |
413 | ||
db9a3750 | 414 | msm_host->esc_clk = msm_clk_get(pdev, "core"); |
a689554b HL |
415 | if (IS_ERR(msm_host->esc_clk)) { |
416 | ret = PTR_ERR(msm_host->esc_clk); | |
db9a3750 | 417 | pr_err("%s: can't find dsi_esc clock. ret=%d\n", |
a689554b HL |
418 | __func__, ret); |
419 | msm_host->esc_clk = NULL; | |
420 | goto exit; | |
421 | } | |
422 | ||
e6c4c78c AT |
423 | msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk); |
424 | if (!msm_host->byte_clk_src) { | |
425 | ret = -ENODEV; | |
db9a3750 | 426 | pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret); |
9d32c498 HL |
427 | goto exit; |
428 | } | |
429 | ||
e6c4c78c AT |
430 | msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk); |
431 | if (!msm_host->pixel_clk_src) { | |
432 | ret = -ENODEV; | |
db9a3750 | 433 | pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret); |
4bfa9748 | 434 | goto exit; |
9d32c498 HL |
435 | } |
436 | ||
8f7ca540 SS |
437 | if (cfg_hnd->ops->clk_init_ver) |
438 | ret = cfg_hnd->ops->clk_init_ver(msm_host); | |
a689554b HL |
439 | exit: |
440 | return ret; | |
441 | } | |
442 | ||
443 | static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host) | |
444 | { | |
6e0eb52e AT |
445 | const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; |
446 | int i, ret; | |
a689554b HL |
447 | |
448 | DBG("id=%d", msm_host->id); | |
449 | ||
6e0eb52e AT |
450 | for (i = 0; i < cfg->num_bus_clks; i++) { |
451 | ret = clk_prepare_enable(msm_host->bus_clks[i]); | |
452 | if (ret) { | |
453 | pr_err("%s: failed to enable bus clock %d ret %d\n", | |
454 | __func__, i, ret); | |
455 | goto err; | |
456 | } | |
a689554b HL |
457 | } |
458 | ||
459 | return 0; | |
6e0eb52e AT |
460 | err: |
461 | for (; i > 0; i--) | |
462 | clk_disable_unprepare(msm_host->bus_clks[i]); | |
a689554b | 463 | |
a689554b HL |
464 | return ret; |
465 | } | |
466 | ||
467 | static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host) | |
468 | { | |
6e0eb52e AT |
469 | const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; |
470 | int i; | |
471 | ||
a689554b | 472 | DBG(""); |
6e0eb52e AT |
473 | |
474 | for (i = cfg->num_bus_clks - 1; i >= 0; i--) | |
475 | clk_disable_unprepare(msm_host->bus_clks[i]); | |
a689554b HL |
476 | } |
477 | ||
f54ca1a0 AT |
478 | int msm_dsi_runtime_suspend(struct device *dev) |
479 | { | |
480 | struct platform_device *pdev = to_platform_device(dev); | |
481 | struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); | |
482 | struct mipi_dsi_host *host = msm_dsi->host; | |
483 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
484 | ||
485 | if (!msm_host->cfg_hnd) | |
486 | return 0; | |
487 | ||
488 | dsi_bus_clk_disable(msm_host); | |
489 | ||
490 | return 0; | |
491 | } | |
492 | ||
493 | int msm_dsi_runtime_resume(struct device *dev) | |
494 | { | |
495 | struct platform_device *pdev = to_platform_device(dev); | |
496 | struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); | |
497 | struct mipi_dsi_host *host = msm_dsi->host; | |
498 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
499 | ||
500 | if (!msm_host->cfg_hnd) | |
501 | return 0; | |
502 | ||
503 | return dsi_bus_clk_enable(msm_host); | |
504 | } | |
505 | ||
c4d8cfe5 | 506 | int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) |
a689554b HL |
507 | { |
508 | int ret; | |
509 | ||
510 | DBG("Set clk rates: pclk=%d, byteclk=%d", | |
511 | msm_host->mode->clock, msm_host->byte_clk_rate); | |
512 | ||
513 | ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); | |
514 | if (ret) { | |
515 | pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); | |
516 | goto error; | |
517 | } | |
518 | ||
ed9976a0 | 519 | ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); |
a689554b HL |
520 | if (ret) { |
521 | pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); | |
522 | goto error; | |
523 | } | |
524 | ||
c1d97083 AT |
525 | if (msm_host->byte_intf_clk) { |
526 | ret = clk_set_rate(msm_host->byte_intf_clk, | |
527 | msm_host->byte_clk_rate / 2); | |
528 | if (ret) { | |
529 | pr_err("%s: Failed to set rate byte intf clk, %d\n", | |
530 | __func__, ret); | |
531 | goto error; | |
532 | } | |
533 | } | |
534 | ||
a689554b HL |
535 | ret = clk_prepare_enable(msm_host->esc_clk); |
536 | if (ret) { | |
537 | pr_err("%s: Failed to enable dsi esc clk\n", __func__); | |
538 | goto error; | |
539 | } | |
540 | ||
541 | ret = clk_prepare_enable(msm_host->byte_clk); | |
542 | if (ret) { | |
543 | pr_err("%s: Failed to enable dsi byte clk\n", __func__); | |
544 | goto byte_clk_err; | |
545 | } | |
546 | ||
547 | ret = clk_prepare_enable(msm_host->pixel_clk); | |
548 | if (ret) { | |
549 | pr_err("%s: Failed to enable dsi pixel clk\n", __func__); | |
550 | goto pixel_clk_err; | |
551 | } | |
552 | ||
c1d97083 AT |
553 | if (msm_host->byte_intf_clk) { |
554 | ret = clk_prepare_enable(msm_host->byte_intf_clk); | |
555 | if (ret) { | |
556 | pr_err("%s: Failed to enable byte intf clk\n", | |
557 | __func__); | |
558 | goto byte_intf_clk_err; | |
559 | } | |
560 | } | |
561 | ||
a689554b HL |
562 | return 0; |
563 | ||
c1d97083 AT |
564 | byte_intf_clk_err: |
565 | clk_disable_unprepare(msm_host->pixel_clk); | |
a689554b HL |
566 | pixel_clk_err: |
567 | clk_disable_unprepare(msm_host->byte_clk); | |
568 | byte_clk_err: | |
569 | clk_disable_unprepare(msm_host->esc_clk); | |
570 | error: | |
571 | return ret; | |
572 | } | |
573 | ||
c4d8cfe5 | 574 | int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) |
a689554b | 575 | { |
4bfa9748 AT |
576 | int ret; |
577 | ||
578 | DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d", | |
579 | msm_host->mode->clock, msm_host->byte_clk_rate, | |
580 | msm_host->esc_clk_rate, msm_host->src_clk_rate); | |
581 | ||
582 | ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); | |
583 | if (ret) { | |
584 | pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); | |
585 | goto error; | |
586 | } | |
587 | ||
588 | ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); | |
589 | if (ret) { | |
590 | pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); | |
591 | goto error; | |
592 | } | |
593 | ||
594 | ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); | |
595 | if (ret) { | |
596 | pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); | |
597 | goto error; | |
598 | } | |
599 | ||
ed9976a0 | 600 | ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); |
4bfa9748 AT |
601 | if (ret) { |
602 | pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); | |
603 | goto error; | |
604 | } | |
605 | ||
606 | ret = clk_prepare_enable(msm_host->byte_clk); | |
607 | if (ret) { | |
608 | pr_err("%s: Failed to enable dsi byte clk\n", __func__); | |
609 | goto error; | |
610 | } | |
611 | ||
612 | ret = clk_prepare_enable(msm_host->esc_clk); | |
613 | if (ret) { | |
614 | pr_err("%s: Failed to enable dsi esc clk\n", __func__); | |
615 | goto esc_clk_err; | |
616 | } | |
617 | ||
618 | ret = clk_prepare_enable(msm_host->src_clk); | |
619 | if (ret) { | |
620 | pr_err("%s: Failed to enable dsi src clk\n", __func__); | |
621 | goto src_clk_err; | |
622 | } | |
623 | ||
624 | ret = clk_prepare_enable(msm_host->pixel_clk); | |
625 | if (ret) { | |
626 | pr_err("%s: Failed to enable dsi pixel clk\n", __func__); | |
627 | goto pixel_clk_err; | |
628 | } | |
629 | ||
630 | return 0; | |
631 | ||
632 | pixel_clk_err: | |
633 | clk_disable_unprepare(msm_host->src_clk); | |
634 | src_clk_err: | |
a689554b | 635 | clk_disable_unprepare(msm_host->esc_clk); |
4bfa9748 | 636 | esc_clk_err: |
a689554b | 637 | clk_disable_unprepare(msm_host->byte_clk); |
4bfa9748 AT |
638 | error: |
639 | return ret; | |
640 | } | |
641 | ||
c4d8cfe5 SS |
642 | void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) |
643 | { | |
644 | clk_disable_unprepare(msm_host->esc_clk); | |
645 | clk_disable_unprepare(msm_host->pixel_clk); | |
646 | if (msm_host->byte_intf_clk) | |
647 | clk_disable_unprepare(msm_host->byte_intf_clk); | |
648 | clk_disable_unprepare(msm_host->byte_clk); | |
649 | } | |
650 | ||
651 | void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) | |
652 | { | |
653 | clk_disable_unprepare(msm_host->pixel_clk); | |
654 | clk_disable_unprepare(msm_host->src_clk); | |
655 | clk_disable_unprepare(msm_host->esc_clk); | |
656 | clk_disable_unprepare(msm_host->byte_clk); | |
657 | } | |
658 | ||
a6bcddbc | 659 | static u32 dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi) |
c4d8cfe5 SS |
660 | { |
661 | struct drm_display_mode *mode = msm_host->mode; | |
c4d8cfe5 SS |
662 | u32 pclk_rate; |
663 | ||
664 | pclk_rate = mode->clock * 1000; | |
ed9976a0 CU |
665 | |
666 | /* | |
667 | * For dual DSI mode, the current DRM mode has the complete width of the | |
668 | * panel. Since, the complete panel is driven by two DSI controllers, | |
a6bcddbc | 669 | * the clock rates have to be split between the two dsi controllers. |
ed9976a0 CU |
670 | * Adjust the byte and pixel clock rates for each dsi host accordingly. |
671 | */ | |
672 | if (is_dual_dsi) | |
673 | pclk_rate /= 2; | |
674 | ||
a6bcddbc SP |
675 | return pclk_rate; |
676 | } | |
677 | ||
678 | static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_dual_dsi) | |
679 | { | |
680 | u8 lanes = msm_host->lanes; | |
681 | u32 bpp = dsi_get_bpp(msm_host->format); | |
682 | u32 pclk_rate = dsi_get_pclk_rate(msm_host, is_dual_dsi); | |
683 | u64 pclk_bpp = (u64)pclk_rate * bpp; | |
684 | ||
685 | if (lanes == 0) { | |
c4d8cfe5 | 686 | pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); |
a6bcddbc | 687 | lanes = 1; |
c4d8cfe5 SS |
688 | } |
689 | ||
a6bcddbc | 690 | do_div(pclk_bpp, (8 * lanes)); |
c4d8cfe5 | 691 | |
a6bcddbc SP |
692 | msm_host->pixel_clk_rate = pclk_rate; |
693 | msm_host->byte_clk_rate = pclk_bpp; | |
694 | ||
695 | DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate, | |
696 | msm_host->byte_clk_rate); | |
697 | ||
698 | } | |
699 | ||
700 | int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi) | |
701 | { | |
702 | if (!msm_host->mode) { | |
703 | pr_err("%s: mode not set\n", __func__); | |
704 | return -EINVAL; | |
705 | } | |
c4d8cfe5 | 706 | |
a6bcddbc SP |
707 | dsi_calc_pclk(msm_host, is_dual_dsi); |
708 | msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); | |
c4d8cfe5 SS |
709 | return 0; |
710 | } | |
711 | ||
ed9976a0 | 712 | int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi) |
c4d8cfe5 | 713 | { |
c4d8cfe5 | 714 | u32 bpp = dsi_get_bpp(msm_host->format); |
2d0b10fc | 715 | u64 pclk_bpp; |
c4d8cfe5 SS |
716 | unsigned int esc_mhz, esc_div; |
717 | unsigned long byte_mhz; | |
718 | ||
a6bcddbc | 719 | dsi_calc_pclk(msm_host, is_dual_dsi); |
c4d8cfe5 | 720 | |
a6bcddbc SP |
721 | pclk_bpp = (u64)dsi_get_pclk_rate(msm_host, is_dual_dsi) * bpp; |
722 | do_div(pclk_bpp, 8); | |
723 | msm_host->src_clk_rate = pclk_bpp; | |
c4d8cfe5 SS |
724 | |
725 | /* | |
726 | * esc clock is byte clock followed by a 4 bit divider, | |
727 | * we need to find an escape clock frequency within the | |
728 | * mipi DSI spec range within the maximum divider limit | |
729 | * We iterate here between an escape clock frequencey | |
730 | * between 20 Mhz to 5 Mhz and pick up the first one | |
731 | * that can be supported by our divider | |
732 | */ | |
733 | ||
734 | byte_mhz = msm_host->byte_clk_rate / 1000000; | |
735 | ||
736 | for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { | |
737 | esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); | |
738 | ||
739 | /* | |
740 | * TODO: Ideally, we shouldn't know what sort of divider | |
741 | * is available in mmss_cc, we're just assuming that | |
742 | * it'll always be a 4 bit divider. Need to come up with | |
743 | * a better way here. | |
744 | */ | |
745 | if (esc_div >= 1 && esc_div <= 16) | |
746 | break; | |
747 | } | |
748 | ||
749 | if (esc_mhz < 5) | |
750 | return -EINVAL; | |
751 | ||
752 | msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; | |
753 | ||
754 | DBG("esc=%d, src=%d", msm_host->esc_clk_rate, | |
755 | msm_host->src_clk_rate); | |
756 | ||
757 | return 0; | |
758 | } | |
759 | ||
a689554b HL |
760 | static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) |
761 | { | |
762 | u32 intr; | |
763 | unsigned long flags; | |
764 | ||
765 | spin_lock_irqsave(&msm_host->intr_lock, flags); | |
766 | intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); | |
767 | ||
768 | if (enable) | |
769 | intr |= mask; | |
770 | else | |
771 | intr &= ~mask; | |
772 | ||
773 | DBG("intr=%x enable=%d", intr, enable); | |
774 | ||
775 | dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); | |
776 | spin_unlock_irqrestore(&msm_host->intr_lock, flags); | |
777 | } | |
778 | ||
779 | static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) | |
780 | { | |
781 | if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) | |
782 | return BURST_MODE; | |
783 | else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) | |
784 | return NON_BURST_SYNCH_PULSE; | |
785 | ||
786 | return NON_BURST_SYNCH_EVENT; | |
787 | } | |
788 | ||
789 | static inline enum dsi_vid_dst_format dsi_get_vid_fmt( | |
790 | const enum mipi_dsi_pixel_format mipi_fmt) | |
791 | { | |
792 | switch (mipi_fmt) { | |
793 | case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; | |
794 | case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; | |
795 | case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; | |
796 | case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; | |
797 | default: return VID_DST_FORMAT_RGB888; | |
798 | } | |
799 | } | |
800 | ||
801 | static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( | |
802 | const enum mipi_dsi_pixel_format mipi_fmt) | |
803 | { | |
804 | switch (mipi_fmt) { | |
805 | case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; | |
806 | case MIPI_DSI_FMT_RGB666_PACKED: | |
cf606fe3 | 807 | case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; |
a689554b HL |
808 | case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; |
809 | default: return CMD_DST_FORMAT_RGB888; | |
810 | } | |
811 | } | |
812 | ||
813 | static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, | |
dceac340 | 814 | struct msm_dsi_phy_shared_timings *phy_shared_timings) |
a689554b HL |
815 | { |
816 | u32 flags = msm_host->mode_flags; | |
817 | enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; | |
d248b61f | 818 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
819 | u32 data = 0; |
820 | ||
821 | if (!enable) { | |
822 | dsi_write(msm_host, REG_DSI_CTRL, 0); | |
823 | return; | |
824 | } | |
825 | ||
826 | if (flags & MIPI_DSI_MODE_VIDEO) { | |
827 | if (flags & MIPI_DSI_MODE_VIDEO_HSE) | |
828 | data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; | |
829 | if (flags & MIPI_DSI_MODE_VIDEO_HFP) | |
830 | data |= DSI_VID_CFG0_HFP_POWER_STOP; | |
831 | if (flags & MIPI_DSI_MODE_VIDEO_HBP) | |
832 | data |= DSI_VID_CFG0_HBP_POWER_STOP; | |
833 | if (flags & MIPI_DSI_MODE_VIDEO_HSA) | |
834 | data |= DSI_VID_CFG0_HSA_POWER_STOP; | |
835 | /* Always set low power stop mode for BLLP | |
836 | * to let command engine send packets | |
837 | */ | |
838 | data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | | |
839 | DSI_VID_CFG0_BLLP_POWER_STOP; | |
840 | data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); | |
841 | data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); | |
842 | data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); | |
843 | dsi_write(msm_host, REG_DSI_VID_CFG0, data); | |
844 | ||
845 | /* Do not swap RGB colors */ | |
846 | data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); | |
847 | dsi_write(msm_host, REG_DSI_VID_CFG1, 0); | |
848 | } else { | |
849 | /* Do not swap RGB colors */ | |
850 | data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); | |
851 | data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); | |
852 | dsi_write(msm_host, REG_DSI_CMD_CFG0, data); | |
853 | ||
854 | data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | | |
855 | DSI_CMD_CFG1_WR_MEM_CONTINUE( | |
856 | MIPI_DCS_WRITE_MEMORY_CONTINUE); | |
857 | /* Always insert DCS command */ | |
858 | data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; | |
859 | dsi_write(msm_host, REG_DSI_CMD_CFG1, data); | |
860 | } | |
861 | ||
862 | dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, | |
863 | DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | | |
864 | DSI_CMD_DMA_CTRL_LOW_POWER); | |
865 | ||
866 | data = 0; | |
867 | /* Always assume dedicated TE pin */ | |
868 | data |= DSI_TRIG_CTRL_TE; | |
869 | data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); | |
870 | data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); | |
871 | data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); | |
d248b61f HL |
872 | if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && |
873 | (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) | |
a689554b HL |
874 | data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; |
875 | dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); | |
876 | ||
dceac340 HL |
877 | data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | |
878 | DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); | |
a689554b HL |
879 | dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); |
880 | ||
dceac340 HL |
881 | if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && |
882 | (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && | |
883 | phy_shared_timings->clk_pre_inc_by_2) | |
884 | dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, | |
885 | DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); | |
886 | ||
a689554b HL |
887 | data = 0; |
888 | if (!(flags & MIPI_DSI_MODE_EOT_PACKET)) | |
889 | data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; | |
890 | dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); | |
891 | ||
892 | /* allow only ack-err-status to generate interrupt */ | |
893 | dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); | |
894 | ||
895 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); | |
896 | ||
897 | dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); | |
898 | ||
899 | data = DSI_CTRL_CLK_EN; | |
900 | ||
901 | DBG("lane number=%d", msm_host->lanes); | |
26f7d1f4 AT |
902 | data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); |
903 | ||
904 | dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, | |
905 | DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); | |
65c5e542 AT |
906 | |
907 | if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) | |
908 | dsi_write(msm_host, REG_DSI_LANE_CTRL, | |
909 | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); | |
910 | ||
a689554b HL |
911 | data |= DSI_CTRL_ENABLE; |
912 | ||
913 | dsi_write(msm_host, REG_DSI_CTRL, data); | |
914 | } | |
915 | ||
ed9976a0 | 916 | static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi) |
a689554b HL |
917 | { |
918 | struct drm_display_mode *mode = msm_host->mode; | |
919 | u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ | |
920 | u32 h_total = mode->htotal; | |
921 | u32 v_total = mode->vtotal; | |
922 | u32 hs_end = mode->hsync_end - mode->hsync_start; | |
923 | u32 vs_end = mode->vsync_end - mode->vsync_start; | |
924 | u32 ha_start = h_total - mode->hsync_start; | |
925 | u32 ha_end = ha_start + mode->hdisplay; | |
926 | u32 va_start = v_total - mode->vsync_start; | |
927 | u32 va_end = va_start + mode->vdisplay; | |
ed9976a0 | 928 | u32 hdisplay = mode->hdisplay; |
a689554b HL |
929 | u32 wc; |
930 | ||
931 | DBG(""); | |
932 | ||
ed9976a0 CU |
933 | /* |
934 | * For dual DSI mode, the current DRM mode has | |
935 | * the complete width of the panel. Since, the complete | |
936 | * panel is driven by two DSI controllers, the horizontal | |
937 | * timings have to be split between the two dsi controllers. | |
938 | * Adjust the DSI host timing values accordingly. | |
939 | */ | |
940 | if (is_dual_dsi) { | |
941 | h_total /= 2; | |
942 | hs_end /= 2; | |
943 | ha_start /= 2; | |
944 | ha_end /= 2; | |
945 | hdisplay /= 2; | |
946 | } | |
947 | ||
a689554b HL |
948 | if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { |
949 | dsi_write(msm_host, REG_DSI_ACTIVE_H, | |
950 | DSI_ACTIVE_H_START(ha_start) | | |
951 | DSI_ACTIVE_H_END(ha_end)); | |
952 | dsi_write(msm_host, REG_DSI_ACTIVE_V, | |
953 | DSI_ACTIVE_V_START(va_start) | | |
954 | DSI_ACTIVE_V_END(va_end)); | |
955 | dsi_write(msm_host, REG_DSI_TOTAL, | |
956 | DSI_TOTAL_H_TOTAL(h_total - 1) | | |
957 | DSI_TOTAL_V_TOTAL(v_total - 1)); | |
958 | ||
959 | dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, | |
960 | DSI_ACTIVE_HSYNC_START(hs_start) | | |
961 | DSI_ACTIVE_HSYNC_END(hs_end)); | |
962 | dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); | |
963 | dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, | |
964 | DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | | |
965 | DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); | |
966 | } else { /* command mode */ | |
967 | /* image data and 1 byte write_memory_start cmd */ | |
ed9976a0 | 968 | wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; |
a689554b HL |
969 | |
970 | dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL, | |
971 | DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) | | |
972 | DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL( | |
973 | msm_host->channel) | | |
974 | DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE( | |
975 | MIPI_DSI_DCS_LONG_WRITE)); | |
976 | ||
977 | dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL, | |
ed9976a0 | 978 | DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(hdisplay) | |
a689554b HL |
979 | DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay)); |
980 | } | |
981 | } | |
982 | ||
983 | static void dsi_sw_reset(struct msm_dsi_host *msm_host) | |
984 | { | |
985 | dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); | |
986 | wmb(); /* clocks need to be enabled before reset */ | |
987 | ||
988 | dsi_write(msm_host, REG_DSI_RESET, 1); | |
989 | wmb(); /* make sure reset happen */ | |
990 | dsi_write(msm_host, REG_DSI_RESET, 0); | |
991 | } | |
992 | ||
993 | static void dsi_op_mode_config(struct msm_dsi_host *msm_host, | |
994 | bool video_mode, bool enable) | |
995 | { | |
996 | u32 dsi_ctrl; | |
997 | ||
998 | dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); | |
999 | ||
1000 | if (!enable) { | |
1001 | dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | | |
1002 | DSI_CTRL_CMD_MODE_EN); | |
1003 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | | |
1004 | DSI_IRQ_MASK_VIDEO_DONE, 0); | |
1005 | } else { | |
1006 | if (video_mode) { | |
1007 | dsi_ctrl |= DSI_CTRL_VID_MODE_EN; | |
1008 | } else { /* command mode */ | |
1009 | dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; | |
1010 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); | |
1011 | } | |
1012 | dsi_ctrl |= DSI_CTRL_ENABLE; | |
1013 | } | |
1014 | ||
1015 | dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); | |
1016 | } | |
1017 | ||
1018 | static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) | |
1019 | { | |
1020 | u32 data; | |
1021 | ||
1022 | data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); | |
1023 | ||
1024 | if (mode == 0) | |
1025 | data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; | |
1026 | else | |
1027 | data |= DSI_CMD_DMA_CTRL_LOW_POWER; | |
1028 | ||
1029 | dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); | |
1030 | } | |
1031 | ||
1032 | static void dsi_wait4video_done(struct msm_dsi_host *msm_host) | |
1033 | { | |
79ebc86c AK |
1034 | u32 ret = 0; |
1035 | struct device *dev = &msm_host->pdev->dev; | |
1036 | ||
a689554b HL |
1037 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); |
1038 | ||
1039 | reinit_completion(&msm_host->video_comp); | |
1040 | ||
79ebc86c | 1041 | ret = wait_for_completion_timeout(&msm_host->video_comp, |
a689554b HL |
1042 | msecs_to_jiffies(70)); |
1043 | ||
79ebc86c | 1044 | if (ret <= 0) |
6a41da17 | 1045 | DRM_DEV_ERROR(dev, "wait for video done timed out\n"); |
79ebc86c | 1046 | |
a689554b HL |
1047 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); |
1048 | } | |
1049 | ||
1050 | static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) | |
1051 | { | |
1052 | if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) | |
1053 | return; | |
1054 | ||
9c5638d7 | 1055 | if (msm_host->power_on && msm_host->enabled) { |
a689554b HL |
1056 | dsi_wait4video_done(msm_host); |
1057 | /* delay 4 ms to skip BLLP */ | |
1058 | usleep_range(2000, 4000); | |
1059 | } | |
1060 | } | |
1061 | ||
c4d8cfe5 SS |
1062 | int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) |
1063 | { | |
1064 | struct drm_device *dev = msm_host->dev; | |
1065 | struct msm_drm_private *priv = dev->dev_private; | |
1066 | uint64_t iova; | |
1067 | u8 *data; | |
1068 | ||
1069 | data = msm_gem_kernel_new(dev, size, MSM_BO_UNCACHED, | |
1070 | priv->kms->aspace, | |
1071 | &msm_host->tx_gem_obj, &iova); | |
1072 | ||
1073 | if (IS_ERR(data)) { | |
1074 | msm_host->tx_gem_obj = NULL; | |
1075 | return PTR_ERR(data); | |
1076 | } | |
1077 | ||
0815d774 JC |
1078 | msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); |
1079 | ||
c4d8cfe5 SS |
1080 | msm_host->tx_size = msm_host->tx_gem_obj->size; |
1081 | ||
1082 | return 0; | |
1083 | } | |
1084 | ||
1085 | int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) | |
1086 | { | |
1087 | struct drm_device *dev = msm_host->dev; | |
1088 | ||
1089 | msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, | |
1090 | &msm_host->tx_buf_paddr, GFP_KERNEL); | |
1091 | if (!msm_host->tx_buf) | |
1092 | return -ENOMEM; | |
1093 | ||
1094 | msm_host->tx_size = size; | |
1095 | ||
1096 | return 0; | |
1097 | } | |
1098 | ||
a689554b HL |
1099 | static void dsi_tx_buf_free(struct msm_dsi_host *msm_host) |
1100 | { | |
1101 | struct drm_device *dev = msm_host->dev; | |
74d3a3a7 SP |
1102 | struct msm_drm_private *priv; |
1103 | ||
1104 | /* | |
1105 | * This is possible if we're tearing down before we've had a chance to | |
1106 | * fully initialize. A very real possibility if our probe is deferred, | |
1107 | * in which case we'll hit msm_dsi_host_destroy() without having run | |
1108 | * through the dsi_tx_buf_alloc(). | |
1109 | */ | |
1110 | if (!dev) | |
1111 | return; | |
a689554b | 1112 | |
74d3a3a7 | 1113 | priv = dev->dev_private; |
a689554b | 1114 | if (msm_host->tx_gem_obj) { |
7ad0e8cf | 1115 | msm_gem_unpin_iova(msm_host->tx_gem_obj, priv->kms->aspace); |
d71b6bd8 | 1116 | drm_gem_object_put_unlocked(msm_host->tx_gem_obj); |
a689554b | 1117 | msm_host->tx_gem_obj = NULL; |
a689554b | 1118 | } |
4ff9d4cb AT |
1119 | |
1120 | if (msm_host->tx_buf) | |
1121 | dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, | |
1122 | msm_host->tx_buf_paddr); | |
a689554b HL |
1123 | } |
1124 | ||
c4d8cfe5 SS |
1125 | void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) |
1126 | { | |
1127 | return msm_gem_get_vaddr(msm_host->tx_gem_obj); | |
1128 | } | |
1129 | ||
1130 | void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) | |
1131 | { | |
1132 | return msm_host->tx_buf; | |
1133 | } | |
1134 | ||
1135 | void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) | |
1136 | { | |
1137 | msm_gem_put_vaddr(msm_host->tx_gem_obj); | |
1138 | } | |
1139 | ||
a689554b HL |
1140 | /* |
1141 | * prepare cmd buffer to be txed | |
1142 | */ | |
4ff9d4cb AT |
1143 | static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, |
1144 | const struct mipi_dsi_msg *msg) | |
a689554b | 1145 | { |
4ff9d4cb | 1146 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
1147 | struct mipi_dsi_packet packet; |
1148 | int len; | |
1149 | int ret; | |
1150 | u8 *data; | |
1151 | ||
1152 | ret = mipi_dsi_create_packet(&packet, msg); | |
1153 | if (ret) { | |
1154 | pr_err("%s: create packet failed, %d\n", __func__, ret); | |
1155 | return ret; | |
1156 | } | |
1157 | len = (packet.size + 3) & (~0x3); | |
1158 | ||
4ff9d4cb | 1159 | if (len > msm_host->tx_size) { |
a689554b HL |
1160 | pr_err("%s: packet size is too big\n", __func__); |
1161 | return -EINVAL; | |
1162 | } | |
1163 | ||
8f7ca540 SS |
1164 | data = cfg_hnd->ops->tx_buf_get(msm_host); |
1165 | if (IS_ERR(data)) { | |
1166 | ret = PTR_ERR(data); | |
1167 | pr_err("%s: get vaddr failed, %d\n", __func__, ret); | |
1168 | return ret; | |
a689554b HL |
1169 | } |
1170 | ||
1171 | /* MSM specific command format in memory */ | |
1172 | data[0] = packet.header[1]; | |
1173 | data[1] = packet.header[2]; | |
1174 | data[2] = packet.header[0]; | |
1175 | data[3] = BIT(7); /* Last packet */ | |
1176 | if (mipi_dsi_packet_format_is_long(msg->type)) | |
1177 | data[3] |= BIT(6); | |
1178 | if (msg->rx_buf && msg->rx_len) | |
1179 | data[3] |= BIT(5); | |
1180 | ||
1181 | /* Long packet */ | |
1182 | if (packet.payload && packet.payload_length) | |
1183 | memcpy(data + 4, packet.payload, packet.payload_length); | |
1184 | ||
1185 | /* Append 0xff to the end */ | |
1186 | if (packet.size < len) | |
1187 | memset(data + packet.size, 0xff, len - packet.size); | |
1188 | ||
8f7ca540 SS |
1189 | if (cfg_hnd->ops->tx_buf_put) |
1190 | cfg_hnd->ops->tx_buf_put(msm_host); | |
18f23049 | 1191 | |
a689554b HL |
1192 | return len; |
1193 | } | |
1194 | ||
1195 | /* | |
1196 | * dsi_short_read1_resp: 1 parameter | |
1197 | */ | |
1198 | static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) | |
1199 | { | |
1200 | u8 *data = msg->rx_buf; | |
1201 | if (data && (msg->rx_len >= 1)) { | |
1202 | *data = buf[1]; /* strip out dcs type */ | |
1203 | return 1; | |
1204 | } else { | |
981371f3 | 1205 | pr_err("%s: read data does not match with rx_buf len %zu\n", |
a689554b HL |
1206 | __func__, msg->rx_len); |
1207 | return -EINVAL; | |
1208 | } | |
1209 | } | |
1210 | ||
1211 | /* | |
1212 | * dsi_short_read2_resp: 2 parameter | |
1213 | */ | |
1214 | static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) | |
1215 | { | |
1216 | u8 *data = msg->rx_buf; | |
1217 | if (data && (msg->rx_len >= 2)) { | |
1218 | data[0] = buf[1]; /* strip out dcs type */ | |
1219 | data[1] = buf[2]; | |
1220 | return 2; | |
1221 | } else { | |
981371f3 | 1222 | pr_err("%s: read data does not match with rx_buf len %zu\n", |
a689554b HL |
1223 | __func__, msg->rx_len); |
1224 | return -EINVAL; | |
1225 | } | |
1226 | } | |
1227 | ||
1228 | static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) | |
1229 | { | |
1230 | /* strip out 4 byte dcs header */ | |
1231 | if (msg->rx_buf && msg->rx_len) | |
1232 | memcpy(msg->rx_buf, buf + 4, msg->rx_len); | |
1233 | ||
1234 | return msg->rx_len; | |
1235 | } | |
1236 | ||
c4d8cfe5 SS |
1237 | int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) |
1238 | { | |
1239 | struct drm_device *dev = msm_host->dev; | |
1240 | struct msm_drm_private *priv = dev->dev_private; | |
1241 | ||
1242 | if (!dma_base) | |
1243 | return -EINVAL; | |
1244 | ||
9fe041f6 | 1245 | return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, |
c4d8cfe5 SS |
1246 | priv->kms->aspace, dma_base); |
1247 | } | |
1248 | ||
1249 | int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) | |
1250 | { | |
1251 | if (!dma_base) | |
1252 | return -EINVAL; | |
1253 | ||
1254 | *dma_base = msm_host->tx_buf_paddr; | |
1255 | return 0; | |
1256 | } | |
1257 | ||
a689554b HL |
1258 | static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) |
1259 | { | |
4ff9d4cb | 1260 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b | 1261 | int ret; |
78babc16 | 1262 | uint64_t dma_base; |
a689554b HL |
1263 | bool triggered; |
1264 | ||
8f7ca540 SS |
1265 | ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); |
1266 | if (ret) { | |
1267 | pr_err("%s: failed to get iova: %d\n", __func__, ret); | |
1268 | return ret; | |
a689554b HL |
1269 | } |
1270 | ||
1271 | reinit_completion(&msm_host->dma_comp); | |
1272 | ||
1273 | dsi_wait4video_eng_busy(msm_host); | |
1274 | ||
1275 | triggered = msm_dsi_manager_cmd_xfer_trigger( | |
4ff9d4cb | 1276 | msm_host->id, dma_base, len); |
a689554b HL |
1277 | if (triggered) { |
1278 | ret = wait_for_completion_timeout(&msm_host->dma_comp, | |
1279 | msecs_to_jiffies(200)); | |
1280 | DBG("ret=%d", ret); | |
1281 | if (ret == 0) | |
1282 | ret = -ETIMEDOUT; | |
1283 | else | |
1284 | ret = len; | |
1285 | } else | |
1286 | ret = len; | |
1287 | ||
1288 | return ret; | |
1289 | } | |
1290 | ||
1291 | static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, | |
1292 | u8 *buf, int rx_byte, int pkt_size) | |
1293 | { | |
1294 | u32 *lp, *temp, data; | |
1295 | int i, j = 0, cnt; | |
a689554b HL |
1296 | u32 read_cnt; |
1297 | u8 reg[16]; | |
1298 | int repeated_bytes = 0; | |
1299 | int buf_offset = buf - msm_host->rx_buf; | |
1300 | ||
1301 | lp = (u32 *)buf; | |
1302 | temp = (u32 *)reg; | |
1303 | cnt = (rx_byte + 3) >> 2; | |
1304 | if (cnt > 4) | |
1305 | cnt = 4; /* 4 x 32 bits registers only */ | |
1306 | ||
ec1936eb HL |
1307 | if (rx_byte == 4) |
1308 | read_cnt = 4; | |
1309 | else | |
1310 | read_cnt = pkt_size + 6; | |
a689554b HL |
1311 | |
1312 | /* | |
1313 | * In case of multiple reads from the panel, after the first read, there | |
1314 | * is possibility that there are some bytes in the payload repeating in | |
1315 | * the RDBK_DATA registers. Since we read all the parameters from the | |
1316 | * panel right from the first byte for every pass. We need to skip the | |
1317 | * repeating bytes and then append the new parameters to the rx buffer. | |
1318 | */ | |
1319 | if (read_cnt > 16) { | |
1320 | int bytes_shifted; | |
1321 | /* Any data more than 16 bytes will be shifted out. | |
1322 | * The temp read buffer should already contain these bytes. | |
1323 | * The remaining bytes in read buffer are the repeated bytes. | |
1324 | */ | |
1325 | bytes_shifted = read_cnt - 16; | |
1326 | repeated_bytes = buf_offset - bytes_shifted; | |
1327 | } | |
1328 | ||
1329 | for (i = cnt - 1; i >= 0; i--) { | |
1330 | data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); | |
1331 | *temp++ = ntohl(data); /* to host byte order */ | |
1332 | DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); | |
1333 | } | |
1334 | ||
1335 | for (i = repeated_bytes; i < 16; i++) | |
1336 | buf[j++] = reg[i]; | |
1337 | ||
1338 | return j; | |
1339 | } | |
1340 | ||
1341 | static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, | |
1342 | const struct mipi_dsi_msg *msg) | |
1343 | { | |
1344 | int len, ret; | |
1345 | int bllp_len = msm_host->mode->hdisplay * | |
1346 | dsi_get_bpp(msm_host->format) / 8; | |
1347 | ||
4ff9d4cb | 1348 | len = dsi_cmd_dma_add(msm_host, msg); |
a689554b HL |
1349 | if (!len) { |
1350 | pr_err("%s: failed to add cmd type = 0x%x\n", | |
1351 | __func__, msg->type); | |
1352 | return -EINVAL; | |
1353 | } | |
1354 | ||
1355 | /* for video mode, do not send cmds more than | |
1356 | * one pixel line, since it only transmit it | |
1357 | * during BLLP. | |
1358 | */ | |
1359 | /* TODO: if the command is sent in LP mode, the bit rate is only | |
1360 | * half of esc clk rate. In this case, if the video is already | |
1361 | * actively streaming, we need to check more carefully if the | |
1362 | * command can be fit into one BLLP. | |
1363 | */ | |
1364 | if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { | |
1365 | pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", | |
1366 | __func__, len); | |
1367 | return -EINVAL; | |
1368 | } | |
1369 | ||
1370 | ret = dsi_cmd_dma_tx(msm_host, len); | |
1371 | if (ret < len) { | |
1372 | pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n", | |
1373 | __func__, msg->type, (*(u8 *)(msg->tx_buf)), len); | |
1374 | return -ECOMM; | |
1375 | } | |
1376 | ||
1377 | return len; | |
1378 | } | |
1379 | ||
1380 | static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host) | |
1381 | { | |
1382 | u32 data0, data1; | |
1383 | ||
1384 | data0 = dsi_read(msm_host, REG_DSI_CTRL); | |
1385 | data1 = data0; | |
1386 | data1 &= ~DSI_CTRL_ENABLE; | |
1387 | dsi_write(msm_host, REG_DSI_CTRL, data1); | |
1388 | /* | |
1389 | * dsi controller need to be disabled before | |
1390 | * clocks turned on | |
1391 | */ | |
1392 | wmb(); | |
1393 | ||
1394 | dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); | |
1395 | wmb(); /* make sure clocks enabled */ | |
1396 | ||
1397 | /* dsi controller can only be reset while clocks are running */ | |
1398 | dsi_write(msm_host, REG_DSI_RESET, 1); | |
1399 | wmb(); /* make sure reset happen */ | |
1400 | dsi_write(msm_host, REG_DSI_RESET, 0); | |
1401 | wmb(); /* controller out of reset */ | |
1402 | dsi_write(msm_host, REG_DSI_CTRL, data0); | |
1403 | wmb(); /* make sure dsi controller enabled again */ | |
1404 | } | |
1405 | ||
8d23ea40 AT |
1406 | static void dsi_hpd_worker(struct work_struct *work) |
1407 | { | |
1408 | struct msm_dsi_host *msm_host = | |
1409 | container_of(work, struct msm_dsi_host, hpd_work); | |
1410 | ||
1411 | drm_helper_hpd_irq_event(msm_host->dev); | |
1412 | } | |
1413 | ||
a689554b HL |
1414 | static void dsi_err_worker(struct work_struct *work) |
1415 | { | |
1416 | struct msm_dsi_host *msm_host = | |
1417 | container_of(work, struct msm_dsi_host, err_work); | |
1418 | u32 status = msm_host->err_work_state; | |
1419 | ||
ff431fa4 | 1420 | pr_err_ratelimited("%s: status=%x\n", __func__, status); |
a689554b HL |
1421 | if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) |
1422 | dsi_sw_reset_restore(msm_host); | |
1423 | ||
1424 | /* It is safe to clear here because error irq is disabled. */ | |
1425 | msm_host->err_work_state = 0; | |
1426 | ||
1427 | /* enable dsi error interrupt */ | |
1428 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); | |
1429 | } | |
1430 | ||
1431 | static void dsi_ack_err_status(struct msm_dsi_host *msm_host) | |
1432 | { | |
1433 | u32 status; | |
1434 | ||
1435 | status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); | |
1436 | ||
1437 | if (status) { | |
1438 | dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); | |
1439 | /* Writing of an extra 0 needed to clear error bits */ | |
1440 | dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); | |
1441 | msm_host->err_work_state |= DSI_ERR_STATE_ACK; | |
1442 | } | |
1443 | } | |
1444 | ||
1445 | static void dsi_timeout_status(struct msm_dsi_host *msm_host) | |
1446 | { | |
1447 | u32 status; | |
1448 | ||
1449 | status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); | |
1450 | ||
1451 | if (status) { | |
1452 | dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); | |
1453 | msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; | |
1454 | } | |
1455 | } | |
1456 | ||
1457 | static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) | |
1458 | { | |
1459 | u32 status; | |
1460 | ||
1461 | status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); | |
1462 | ||
01199361 AT |
1463 | if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | |
1464 | DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | | |
1465 | DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | | |
1466 | DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | | |
1467 | DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { | |
a689554b HL |
1468 | dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); |
1469 | msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; | |
1470 | } | |
1471 | } | |
1472 | ||
1473 | static void dsi_fifo_status(struct msm_dsi_host *msm_host) | |
1474 | { | |
1475 | u32 status; | |
1476 | ||
1477 | status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); | |
1478 | ||
1479 | /* fifo underflow, overflow */ | |
1480 | if (status) { | |
1481 | dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); | |
1482 | msm_host->err_work_state |= DSI_ERR_STATE_FIFO; | |
1483 | if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) | |
1484 | msm_host->err_work_state |= | |
1485 | DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; | |
1486 | } | |
1487 | } | |
1488 | ||
1489 | static void dsi_status(struct msm_dsi_host *msm_host) | |
1490 | { | |
1491 | u32 status; | |
1492 | ||
1493 | status = dsi_read(msm_host, REG_DSI_STATUS0); | |
1494 | ||
1495 | if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { | |
1496 | dsi_write(msm_host, REG_DSI_STATUS0, status); | |
1497 | msm_host->err_work_state |= | |
1498 | DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; | |
1499 | } | |
1500 | } | |
1501 | ||
1502 | static void dsi_clk_status(struct msm_dsi_host *msm_host) | |
1503 | { | |
1504 | u32 status; | |
1505 | ||
1506 | status = dsi_read(msm_host, REG_DSI_CLK_STATUS); | |
1507 | ||
1508 | if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { | |
1509 | dsi_write(msm_host, REG_DSI_CLK_STATUS, status); | |
1510 | msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; | |
1511 | } | |
1512 | } | |
1513 | ||
1514 | static void dsi_error(struct msm_dsi_host *msm_host) | |
1515 | { | |
1516 | /* disable dsi error interrupt */ | |
1517 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); | |
1518 | ||
1519 | dsi_clk_status(msm_host); | |
1520 | dsi_fifo_status(msm_host); | |
1521 | dsi_ack_err_status(msm_host); | |
1522 | dsi_timeout_status(msm_host); | |
1523 | dsi_status(msm_host); | |
1524 | dsi_dln0_phy_err(msm_host); | |
1525 | ||
1526 | queue_work(msm_host->workqueue, &msm_host->err_work); | |
1527 | } | |
1528 | ||
1529 | static irqreturn_t dsi_host_irq(int irq, void *ptr) | |
1530 | { | |
1531 | struct msm_dsi_host *msm_host = ptr; | |
1532 | u32 isr; | |
1533 | unsigned long flags; | |
1534 | ||
1535 | if (!msm_host->ctrl_base) | |
1536 | return IRQ_HANDLED; | |
1537 | ||
1538 | spin_lock_irqsave(&msm_host->intr_lock, flags); | |
1539 | isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); | |
1540 | dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); | |
1541 | spin_unlock_irqrestore(&msm_host->intr_lock, flags); | |
1542 | ||
1543 | DBG("isr=0x%x, id=%d", isr, msm_host->id); | |
1544 | ||
1545 | if (isr & DSI_IRQ_ERROR) | |
1546 | dsi_error(msm_host); | |
1547 | ||
1548 | if (isr & DSI_IRQ_VIDEO_DONE) | |
1549 | complete(&msm_host->video_comp); | |
1550 | ||
1551 | if (isr & DSI_IRQ_CMD_DMA_DONE) | |
1552 | complete(&msm_host->dma_comp); | |
1553 | ||
1554 | return IRQ_HANDLED; | |
1555 | } | |
1556 | ||
1557 | static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, | |
1558 | struct device *panel_device) | |
1559 | { | |
9590e69d UKK |
1560 | msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, |
1561 | "disp-enable", | |
1562 | GPIOD_OUT_LOW); | |
a689554b HL |
1563 | if (IS_ERR(msm_host->disp_en_gpio)) { |
1564 | DBG("cannot get disp-enable-gpios %ld", | |
1565 | PTR_ERR(msm_host->disp_en_gpio)); | |
9590e69d | 1566 | return PTR_ERR(msm_host->disp_en_gpio); |
a689554b HL |
1567 | } |
1568 | ||
60d05cb4 AT |
1569 | msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te", |
1570 | GPIOD_IN); | |
a689554b HL |
1571 | if (IS_ERR(msm_host->te_gpio)) { |
1572 | DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); | |
9590e69d | 1573 | return PTR_ERR(msm_host->te_gpio); |
a689554b HL |
1574 | } |
1575 | ||
1576 | return 0; | |
1577 | } | |
1578 | ||
1579 | static int dsi_host_attach(struct mipi_dsi_host *host, | |
1580 | struct mipi_dsi_device *dsi) | |
1581 | { | |
1582 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
1583 | int ret; | |
1584 | ||
26f7d1f4 AT |
1585 | if (dsi->lanes > msm_host->num_data_lanes) |
1586 | return -EINVAL; | |
1587 | ||
a689554b HL |
1588 | msm_host->channel = dsi->channel; |
1589 | msm_host->lanes = dsi->lanes; | |
1590 | msm_host->format = dsi->format; | |
1591 | msm_host->mode_flags = dsi->mode_flags; | |
1592 | ||
9c9f6f8d AT |
1593 | msm_dsi_manager_attach_dsi_device(msm_host->id, dsi->mode_flags); |
1594 | ||
a689554b HL |
1595 | /* Some gpios defined in panel DT need to be controlled by host */ |
1596 | ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); | |
1597 | if (ret) | |
1598 | return ret; | |
1599 | ||
1600 | DBG("id=%d", msm_host->id); | |
1601 | if (msm_host->dev) | |
8d23ea40 | 1602 | queue_work(msm_host->workqueue, &msm_host->hpd_work); |
a689554b HL |
1603 | |
1604 | return 0; | |
1605 | } | |
1606 | ||
1607 | static int dsi_host_detach(struct mipi_dsi_host *host, | |
1608 | struct mipi_dsi_device *dsi) | |
1609 | { | |
1610 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
1611 | ||
a9ddac9c | 1612 | msm_host->device_node = NULL; |
a689554b HL |
1613 | |
1614 | DBG("id=%d", msm_host->id); | |
1615 | if (msm_host->dev) | |
8d23ea40 | 1616 | queue_work(msm_host->workqueue, &msm_host->hpd_work); |
a689554b HL |
1617 | |
1618 | return 0; | |
1619 | } | |
1620 | ||
1621 | static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, | |
1622 | const struct mipi_dsi_msg *msg) | |
1623 | { | |
1624 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
1625 | int ret; | |
1626 | ||
1627 | if (!msg || !msm_host->power_on) | |
1628 | return -EINVAL; | |
1629 | ||
1630 | mutex_lock(&msm_host->cmd_mutex); | |
1631 | ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); | |
1632 | mutex_unlock(&msm_host->cmd_mutex); | |
1633 | ||
1634 | return ret; | |
1635 | } | |
1636 | ||
1637 | static struct mipi_dsi_host_ops dsi_host_ops = { | |
1638 | .attach = dsi_host_attach, | |
1639 | .detach = dsi_host_detach, | |
1640 | .transfer = dsi_host_transfer, | |
1641 | }; | |
1642 | ||
26f7d1f4 AT |
1643 | /* |
1644 | * List of supported physical to logical lane mappings. | |
1645 | * For example, the 2nd entry represents the following mapping: | |
1646 | * | |
1647 | * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; | |
1648 | */ | |
1649 | static const int supported_data_lane_swaps[][4] = { | |
1650 | { 0, 1, 2, 3 }, | |
1651 | { 3, 0, 1, 2 }, | |
1652 | { 2, 3, 0, 1 }, | |
1653 | { 1, 2, 3, 0 }, | |
1654 | { 0, 3, 2, 1 }, | |
1655 | { 1, 0, 3, 2 }, | |
1656 | { 2, 1, 0, 3 }, | |
1657 | { 3, 2, 1, 0 }, | |
1658 | }; | |
1659 | ||
1660 | static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, | |
1661 | struct device_node *ep) | |
1662 | { | |
1663 | struct device *dev = &msm_host->pdev->dev; | |
1664 | struct property *prop; | |
1665 | u32 lane_map[4]; | |
1666 | int ret, i, len, num_lanes; | |
1667 | ||
60282cea | 1668 | prop = of_find_property(ep, "data-lanes", &len); |
26f7d1f4 | 1669 | if (!prop) { |
6a41da17 | 1670 | DRM_DEV_DEBUG(dev, |
a1b1a4f7 AT |
1671 | "failed to find data lane mapping, using default\n"); |
1672 | return 0; | |
26f7d1f4 AT |
1673 | } |
1674 | ||
1675 | num_lanes = len / sizeof(u32); | |
1676 | ||
1677 | if (num_lanes < 1 || num_lanes > 4) { | |
6a41da17 | 1678 | DRM_DEV_ERROR(dev, "bad number of data lanes\n"); |
26f7d1f4 AT |
1679 | return -EINVAL; |
1680 | } | |
1681 | ||
1682 | msm_host->num_data_lanes = num_lanes; | |
1683 | ||
60282cea | 1684 | ret = of_property_read_u32_array(ep, "data-lanes", lane_map, |
26f7d1f4 AT |
1685 | num_lanes); |
1686 | if (ret) { | |
6a41da17 | 1687 | DRM_DEV_ERROR(dev, "failed to read lane data\n"); |
26f7d1f4 AT |
1688 | return ret; |
1689 | } | |
1690 | ||
1691 | /* | |
1692 | * compare DT specified physical-logical lane mappings with the ones | |
1693 | * supported by hardware | |
1694 | */ | |
1695 | for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { | |
1696 | const int *swap = supported_data_lane_swaps[i]; | |
1697 | int j; | |
1698 | ||
60282cea AT |
1699 | /* |
1700 | * the data-lanes array we get from DT has a logical->physical | |
1701 | * mapping. The "data lane swap" register field represents | |
1702 | * supported configurations in a physical->logical mapping. | |
1703 | * Translate the DT mapping to what we understand and find a | |
1704 | * configuration that works. | |
1705 | */ | |
26f7d1f4 | 1706 | for (j = 0; j < num_lanes; j++) { |
60282cea | 1707 | if (lane_map[j] < 0 || lane_map[j] > 3) |
6a41da17 | 1708 | DRM_DEV_ERROR(dev, "bad physical lane entry %u\n", |
60282cea AT |
1709 | lane_map[j]); |
1710 | ||
1711 | if (swap[lane_map[j]] != j) | |
26f7d1f4 AT |
1712 | break; |
1713 | } | |
1714 | ||
1715 | if (j == num_lanes) { | |
1716 | msm_host->dlane_swap = i; | |
1717 | return 0; | |
1718 | } | |
1719 | } | |
1720 | ||
1721 | return -EINVAL; | |
1722 | } | |
1723 | ||
f7009d26 AT |
1724 | static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) |
1725 | { | |
1726 | struct device *dev = &msm_host->pdev->dev; | |
1727 | struct device_node *np = dev->of_node; | |
a9ddac9c | 1728 | struct device_node *endpoint, *device_node; |
a1b1a4f7 | 1729 | int ret = 0; |
f7009d26 | 1730 | |
f7009d26 | 1731 | /* |
b9ac76f6 AT |
1732 | * Get the endpoint of the output port of the DSI host. In our case, |
1733 | * this is mapped to port number with reg = 1. Don't return an error if | |
1734 | * the remote endpoint isn't defined. It's possible that there is | |
1735 | * nothing connected to the dsi output. | |
f7009d26 | 1736 | */ |
b9ac76f6 | 1737 | endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); |
f7009d26 | 1738 | if (!endpoint) { |
6a41da17 | 1739 | DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__); |
f7009d26 AT |
1740 | return 0; |
1741 | } | |
1742 | ||
26f7d1f4 AT |
1743 | ret = dsi_host_parse_lane_data(msm_host, endpoint); |
1744 | if (ret) { | |
6a41da17 | 1745 | DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", |
26f7d1f4 | 1746 | __func__, ret); |
feb085ec | 1747 | ret = -EINVAL; |
26f7d1f4 AT |
1748 | goto err; |
1749 | } | |
1750 | ||
f7009d26 | 1751 | /* Get panel node from the output port's endpoint data */ |
86418f90 | 1752 | device_node = of_graph_get_remote_node(np, 1, 0); |
a9ddac9c | 1753 | if (!device_node) { |
6a41da17 | 1754 | DRM_DEV_DEBUG(dev, "%s: no valid device\n", __func__); |
feb085ec | 1755 | ret = -ENODEV; |
26f7d1f4 | 1756 | goto err; |
f7009d26 AT |
1757 | } |
1758 | ||
a9ddac9c | 1759 | msm_host->device_node = device_node; |
f7009d26 | 1760 | |
0c7df47f AT |
1761 | if (of_property_read_bool(np, "syscon-sfpb")) { |
1762 | msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, | |
1763 | "syscon-sfpb"); | |
1764 | if (IS_ERR(msm_host->sfpb)) { | |
6a41da17 | 1765 | DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n", |
0c7df47f | 1766 | __func__); |
26f7d1f4 | 1767 | ret = PTR_ERR(msm_host->sfpb); |
0c7df47f AT |
1768 | } |
1769 | } | |
1770 | ||
26f7d1f4 AT |
1771 | of_node_put(device_node); |
1772 | ||
1773 | err: | |
1774 | of_node_put(endpoint); | |
1775 | ||
1776 | return ret; | |
f7009d26 AT |
1777 | } |
1778 | ||
32280d66 AT |
1779 | static int dsi_host_get_id(struct msm_dsi_host *msm_host) |
1780 | { | |
1781 | struct platform_device *pdev = msm_host->pdev; | |
1782 | const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; | |
1783 | struct resource *res; | |
1784 | int i; | |
1785 | ||
1786 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); | |
1787 | if (!res) | |
1788 | return -EINVAL; | |
1789 | ||
1790 | for (i = 0; i < cfg->num_dsi; i++) { | |
1791 | if (cfg->io_start[i] == res->start) | |
1792 | return i; | |
1793 | } | |
1794 | ||
1795 | return -EINVAL; | |
1796 | } | |
1797 | ||
a689554b HL |
1798 | int msm_dsi_host_init(struct msm_dsi *msm_dsi) |
1799 | { | |
1800 | struct msm_dsi_host *msm_host = NULL; | |
1801 | struct platform_device *pdev = msm_dsi->pdev; | |
1802 | int ret; | |
1803 | ||
1804 | msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); | |
1805 | if (!msm_host) { | |
1806 | pr_err("%s: FAILED: cannot alloc dsi host\n", | |
1807 | __func__); | |
1808 | ret = -ENOMEM; | |
1809 | goto fail; | |
1810 | } | |
1811 | ||
f7009d26 | 1812 | msm_host->pdev = pdev; |
f54ca1a0 | 1813 | msm_dsi->host = &msm_host->base; |
f7009d26 AT |
1814 | |
1815 | ret = dsi_host_parse_dt(msm_host); | |
a689554b | 1816 | if (ret) { |
f7009d26 | 1817 | pr_err("%s: failed to parse dt\n", __func__); |
a689554b HL |
1818 | goto fail; |
1819 | } | |
a689554b | 1820 | |
a689554b HL |
1821 | msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL"); |
1822 | if (IS_ERR(msm_host->ctrl_base)) { | |
1823 | pr_err("%s: unable to map Dsi ctrl base\n", __func__); | |
1824 | ret = PTR_ERR(msm_host->ctrl_base); | |
1825 | goto fail; | |
1826 | } | |
1827 | ||
f6be1121 AT |
1828 | pm_runtime_enable(&pdev->dev); |
1829 | ||
d248b61f HL |
1830 | msm_host->cfg_hnd = dsi_get_config(msm_host); |
1831 | if (!msm_host->cfg_hnd) { | |
a689554b HL |
1832 | ret = -EINVAL; |
1833 | pr_err("%s: get config failed\n", __func__); | |
1834 | goto fail; | |
1835 | } | |
1836 | ||
32280d66 AT |
1837 | msm_host->id = dsi_host_get_id(msm_host); |
1838 | if (msm_host->id < 0) { | |
1839 | ret = msm_host->id; | |
1840 | pr_err("%s: unable to identify DSI host index\n", __func__); | |
1841 | goto fail; | |
1842 | } | |
1843 | ||
d248b61f HL |
1844 | /* fixup base address by io offset */ |
1845 | msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset; | |
1846 | ||
a689554b HL |
1847 | ret = dsi_regulator_init(msm_host); |
1848 | if (ret) { | |
1849 | pr_err("%s: regulator init failed\n", __func__); | |
1850 | goto fail; | |
1851 | } | |
1852 | ||
31c92767 AT |
1853 | ret = dsi_clk_init(msm_host); |
1854 | if (ret) { | |
1855 | pr_err("%s: unable to initialize dsi clks\n", __func__); | |
1856 | goto fail; | |
1857 | } | |
1858 | ||
a689554b HL |
1859 | msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); |
1860 | if (!msm_host->rx_buf) { | |
cd57b48a | 1861 | ret = -ENOMEM; |
a689554b HL |
1862 | pr_err("%s: alloc rx temp buf failed\n", __func__); |
1863 | goto fail; | |
1864 | } | |
1865 | ||
1866 | init_completion(&msm_host->dma_comp); | |
1867 | init_completion(&msm_host->video_comp); | |
1868 | mutex_init(&msm_host->dev_mutex); | |
1869 | mutex_init(&msm_host->cmd_mutex); | |
a689554b HL |
1870 | spin_lock_init(&msm_host->intr_lock); |
1871 | ||
1872 | /* setup workqueue */ | |
1873 | msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); | |
1874 | INIT_WORK(&msm_host->err_work, dsi_err_worker); | |
8d23ea40 | 1875 | INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker); |
a689554b | 1876 | |
a689554b HL |
1877 | msm_dsi->id = msm_host->id; |
1878 | ||
1879 | DBG("Dsi Host %d initialized", msm_host->id); | |
1880 | return 0; | |
1881 | ||
1882 | fail: | |
1883 | return ret; | |
1884 | } | |
1885 | ||
1886 | void msm_dsi_host_destroy(struct mipi_dsi_host *host) | |
1887 | { | |
1888 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
1889 | ||
1890 | DBG(""); | |
1891 | dsi_tx_buf_free(msm_host); | |
1892 | if (msm_host->workqueue) { | |
1893 | flush_workqueue(msm_host->workqueue); | |
1894 | destroy_workqueue(msm_host->workqueue); | |
1895 | msm_host->workqueue = NULL; | |
1896 | } | |
1897 | ||
a689554b HL |
1898 | mutex_destroy(&msm_host->cmd_mutex); |
1899 | mutex_destroy(&msm_host->dev_mutex); | |
f6be1121 AT |
1900 | |
1901 | pm_runtime_disable(&msm_host->pdev->dev); | |
a689554b HL |
1902 | } |
1903 | ||
1904 | int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, | |
1905 | struct drm_device *dev) | |
1906 | { | |
1907 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
8f7ca540 | 1908 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
1909 | struct platform_device *pdev = msm_host->pdev; |
1910 | int ret; | |
1911 | ||
1912 | msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); | |
1913 | if (msm_host->irq < 0) { | |
1914 | ret = msm_host->irq; | |
6a41da17 | 1915 | DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret); |
a689554b HL |
1916 | return ret; |
1917 | } | |
1918 | ||
1919 | ret = devm_request_irq(&pdev->dev, msm_host->irq, | |
1920 | dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, | |
1921 | "dsi_isr", msm_host); | |
1922 | if (ret < 0) { | |
6a41da17 | 1923 | DRM_DEV_ERROR(&pdev->dev, "failed to request IRQ%u: %d\n", |
a689554b HL |
1924 | msm_host->irq, ret); |
1925 | return ret; | |
1926 | } | |
1927 | ||
1928 | msm_host->dev = dev; | |
8f7ca540 | 1929 | ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); |
a689554b HL |
1930 | if (ret) { |
1931 | pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); | |
1932 | return ret; | |
1933 | } | |
1934 | ||
1935 | return 0; | |
1936 | } | |
1937 | ||
1938 | int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer) | |
1939 | { | |
1940 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
a689554b HL |
1941 | int ret; |
1942 | ||
1943 | /* Register mipi dsi host */ | |
1944 | if (!msm_host->registered) { | |
1945 | host->dev = &msm_host->pdev->dev; | |
1946 | host->ops = &dsi_host_ops; | |
1947 | ret = mipi_dsi_host_register(host); | |
1948 | if (ret) | |
1949 | return ret; | |
1950 | ||
1951 | msm_host->registered = true; | |
1952 | ||
1953 | /* If the panel driver has not been probed after host register, | |
1954 | * we should defer the host's probe. | |
1955 | * It makes sure panel is connected when fbcon detects | |
1956 | * connector status and gets the proper display mode to | |
1957 | * create framebuffer. | |
f7009d26 AT |
1958 | * Don't try to defer if there is nothing connected to the dsi |
1959 | * output | |
a689554b | 1960 | */ |
a9ddac9c | 1961 | if (check_defer && msm_host->device_node) { |
5fa8e4a2 | 1962 | if (IS_ERR(of_drm_find_panel(msm_host->device_node))) |
c118e290 AT |
1963 | if (!of_drm_find_bridge(msm_host->device_node)) |
1964 | return -EPROBE_DEFER; | |
a689554b HL |
1965 | } |
1966 | } | |
1967 | ||
1968 | return 0; | |
1969 | } | |
1970 | ||
1971 | void msm_dsi_host_unregister(struct mipi_dsi_host *host) | |
1972 | { | |
1973 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
1974 | ||
1975 | if (msm_host->registered) { | |
1976 | mipi_dsi_host_unregister(host); | |
1977 | host->dev = NULL; | |
1978 | host->ops = NULL; | |
1979 | msm_host->registered = false; | |
1980 | } | |
1981 | } | |
1982 | ||
1983 | int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, | |
1984 | const struct mipi_dsi_msg *msg) | |
1985 | { | |
1986 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
8f7ca540 | 1987 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
1988 | |
1989 | /* TODO: make sure dsi_cmd_mdp is idle. | |
1990 | * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME | |
1991 | * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. | |
1992 | * How to handle the old versions? Wait for mdp cmd done? | |
1993 | */ | |
1994 | ||
1995 | /* | |
1996 | * mdss interrupt is generated in mdp core clock domain | |
1997 | * mdp clock need to be enabled to receive dsi interrupt | |
1998 | */ | |
f6be1121 | 1999 | pm_runtime_get_sync(&msm_host->pdev->dev); |
8f7ca540 | 2000 | cfg_hnd->ops->link_clk_enable(msm_host); |
a689554b HL |
2001 | |
2002 | /* TODO: vote for bus bandwidth */ | |
2003 | ||
2004 | if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) | |
2005 | dsi_set_tx_power_mode(0, msm_host); | |
2006 | ||
2007 | msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); | |
2008 | dsi_write(msm_host, REG_DSI_CTRL, | |
2009 | msm_host->dma_cmd_ctrl_restore | | |
2010 | DSI_CTRL_CMD_MODE_EN | | |
2011 | DSI_CTRL_ENABLE); | |
2012 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); | |
2013 | ||
2014 | return 0; | |
2015 | } | |
2016 | ||
2017 | void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, | |
2018 | const struct mipi_dsi_msg *msg) | |
2019 | { | |
2020 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
8f7ca540 | 2021 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
2022 | |
2023 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); | |
2024 | dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); | |
2025 | ||
2026 | if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) | |
2027 | dsi_set_tx_power_mode(1, msm_host); | |
2028 | ||
2029 | /* TODO: unvote for bus bandwidth */ | |
2030 | ||
8f7ca540 | 2031 | cfg_hnd->ops->link_clk_disable(msm_host); |
f6be1121 | 2032 | pm_runtime_put_autosuspend(&msm_host->pdev->dev); |
a689554b HL |
2033 | } |
2034 | ||
2035 | int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, | |
2036 | const struct mipi_dsi_msg *msg) | |
2037 | { | |
2038 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2039 | ||
2040 | return dsi_cmds2buf_tx(msm_host, msg); | |
2041 | } | |
2042 | ||
2043 | int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, | |
2044 | const struct mipi_dsi_msg *msg) | |
2045 | { | |
2046 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
d248b61f | 2047 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
2048 | int data_byte, rx_byte, dlen, end; |
2049 | int short_response, diff, pkt_size, ret = 0; | |
2050 | char cmd; | |
2051 | int rlen = msg->rx_len; | |
2052 | u8 *buf; | |
2053 | ||
2054 | if (rlen <= 2) { | |
2055 | short_response = 1; | |
2056 | pkt_size = rlen; | |
2057 | rx_byte = 4; | |
2058 | } else { | |
2059 | short_response = 0; | |
2060 | data_byte = 10; /* first read */ | |
2061 | if (rlen < data_byte) | |
2062 | pkt_size = rlen; | |
2063 | else | |
2064 | pkt_size = data_byte; | |
2065 | rx_byte = data_byte + 6; /* 4 header + 2 crc */ | |
2066 | } | |
2067 | ||
2068 | buf = msm_host->rx_buf; | |
2069 | end = 0; | |
2070 | while (!end) { | |
2071 | u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; | |
2072 | struct mipi_dsi_msg max_pkt_size_msg = { | |
2073 | .channel = msg->channel, | |
2074 | .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, | |
2075 | .tx_len = 2, | |
2076 | .tx_buf = tx, | |
2077 | }; | |
2078 | ||
2079 | DBG("rlen=%d pkt_size=%d rx_byte=%d", | |
2080 | rlen, pkt_size, rx_byte); | |
2081 | ||
2082 | ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); | |
2083 | if (ret < 2) { | |
2084 | pr_err("%s: Set max pkt size failed, %d\n", | |
2085 | __func__, ret); | |
2086 | return -EINVAL; | |
2087 | } | |
2088 | ||
d248b61f HL |
2089 | if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && |
2090 | (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { | |
a689554b HL |
2091 | /* Clear the RDBK_DATA registers */ |
2092 | dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, | |
2093 | DSI_RDBK_DATA_CTRL_CLR); | |
2094 | wmb(); /* make sure the RDBK registers are cleared */ | |
2095 | dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); | |
2096 | wmb(); /* release cleared status before transfer */ | |
2097 | } | |
2098 | ||
2099 | ret = dsi_cmds2buf_tx(msm_host, msg); | |
2100 | if (ret < msg->tx_len) { | |
2101 | pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); | |
2102 | return ret; | |
2103 | } | |
2104 | ||
2105 | /* | |
2106 | * once cmd_dma_done interrupt received, | |
2107 | * return data from client is ready and stored | |
2108 | * at RDBK_DATA register already | |
2109 | * since rx fifo is 16 bytes, dcs header is kept at first loop, | |
2110 | * after that dcs header lost during shift into registers | |
2111 | */ | |
2112 | dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); | |
2113 | ||
2114 | if (dlen <= 0) | |
2115 | return 0; | |
2116 | ||
2117 | if (short_response) | |
2118 | break; | |
2119 | ||
2120 | if (rlen <= data_byte) { | |
2121 | diff = data_byte - rlen; | |
2122 | end = 1; | |
2123 | } else { | |
2124 | diff = 0; | |
2125 | rlen -= data_byte; | |
2126 | } | |
2127 | ||
2128 | if (!end) { | |
2129 | dlen -= 2; /* 2 crc */ | |
2130 | dlen -= diff; | |
2131 | buf += dlen; /* next start position */ | |
2132 | data_byte = 14; /* NOT first read */ | |
2133 | if (rlen < data_byte) | |
2134 | pkt_size += rlen; | |
2135 | else | |
2136 | pkt_size += data_byte; | |
2137 | DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); | |
2138 | } | |
2139 | } | |
2140 | ||
2141 | /* | |
2142 | * For single Long read, if the requested rlen < 10, | |
2143 | * we need to shift the start position of rx | |
2144 | * data buffer to skip the bytes which are not | |
2145 | * updated. | |
2146 | */ | |
2147 | if (pkt_size < 10 && !short_response) | |
2148 | buf = msm_host->rx_buf + (10 - rlen); | |
2149 | else | |
2150 | buf = msm_host->rx_buf; | |
2151 | ||
2152 | cmd = buf[0]; | |
2153 | switch (cmd) { | |
2154 | case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: | |
2155 | pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); | |
2156 | ret = 0; | |
651ad3f5 | 2157 | break; |
a689554b HL |
2158 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: |
2159 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: | |
2160 | ret = dsi_short_read1_resp(buf, msg); | |
2161 | break; | |
2162 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: | |
2163 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: | |
2164 | ret = dsi_short_read2_resp(buf, msg); | |
2165 | break; | |
2166 | case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: | |
2167 | case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: | |
2168 | ret = dsi_long_read_resp(buf, msg); | |
2169 | break; | |
2170 | default: | |
2171 | pr_warn("%s:Invalid response cmd\n", __func__); | |
2172 | ret = 0; | |
2173 | } | |
2174 | ||
2175 | return ret; | |
2176 | } | |
2177 | ||
4ff9d4cb AT |
2178 | void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, |
2179 | u32 len) | |
a689554b HL |
2180 | { |
2181 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2182 | ||
4ff9d4cb | 2183 | dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); |
a689554b HL |
2184 | dsi_write(msm_host, REG_DSI_DMA_LEN, len); |
2185 | dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); | |
2186 | ||
2187 | /* Make sure trigger happens */ | |
2188 | wmb(); | |
2189 | } | |
2190 | ||
9d32c498 HL |
2191 | int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, |
2192 | struct msm_dsi_pll *src_pll) | |
2193 | { | |
2194 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2195 | struct clk *byte_clk_provider, *pixel_clk_provider; | |
2196 | int ret; | |
2197 | ||
2198 | ret = msm_dsi_pll_get_clk_provider(src_pll, | |
2199 | &byte_clk_provider, &pixel_clk_provider); | |
2200 | if (ret) { | |
2201 | pr_info("%s: can't get provider from pll, don't set parent\n", | |
2202 | __func__); | |
2203 | return 0; | |
2204 | } | |
2205 | ||
2206 | ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider); | |
2207 | if (ret) { | |
2208 | pr_err("%s: can't set parent to byte_clk_src. ret=%d\n", | |
2209 | __func__, ret); | |
2210 | goto exit; | |
2211 | } | |
2212 | ||
2213 | ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider); | |
2214 | if (ret) { | |
2215 | pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n", | |
2216 | __func__, ret); | |
2217 | goto exit; | |
2218 | } | |
2219 | ||
8f7ca540 | 2220 | if (msm_host->dsi_clk_src) { |
4bfa9748 AT |
2221 | ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider); |
2222 | if (ret) { | |
2223 | pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n", | |
2224 | __func__, ret); | |
2225 | goto exit; | |
2226 | } | |
8f7ca540 | 2227 | } |
4bfa9748 | 2228 | |
8f7ca540 | 2229 | if (msm_host->esc_clk_src) { |
4bfa9748 AT |
2230 | ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider); |
2231 | if (ret) { | |
2232 | pr_err("%s: can't set parent to esc_clk_src. ret=%d\n", | |
2233 | __func__, ret); | |
2234 | goto exit; | |
2235 | } | |
2236 | } | |
2237 | ||
9d32c498 HL |
2238 | exit: |
2239 | return ret; | |
2240 | } | |
2241 | ||
34d9545b AT |
2242 | void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) |
2243 | { | |
2244 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2245 | ||
2246 | DBG(""); | |
2247 | dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); | |
2248 | /* Make sure fully reset */ | |
2249 | wmb(); | |
2250 | udelay(1000); | |
2251 | dsi_write(msm_host, REG_DSI_PHY_RESET, 0); | |
2252 | udelay(100); | |
2253 | } | |
2254 | ||
b62aa70a | 2255 | void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, |
ed9976a0 CU |
2256 | struct msm_dsi_phy_clk_request *clk_req, |
2257 | bool is_dual_dsi) | |
b62aa70a HL |
2258 | { |
2259 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
8f7ca540 | 2260 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
d4cea38e AT |
2261 | int ret; |
2262 | ||
ed9976a0 | 2263 | ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_dual_dsi); |
d4cea38e AT |
2264 | if (ret) { |
2265 | pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); | |
2266 | return; | |
2267 | } | |
b62aa70a HL |
2268 | |
2269 | clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; | |
2270 | clk_req->escclk_rate = msm_host->esc_clk_rate; | |
2271 | } | |
2272 | ||
a689554b HL |
2273 | int msm_dsi_host_enable(struct mipi_dsi_host *host) |
2274 | { | |
2275 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2276 | ||
2277 | dsi_op_mode_config(msm_host, | |
2278 | !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); | |
2279 | ||
2280 | /* TODO: clock should be turned off for command mode, | |
2281 | * and only turned on before MDP START. | |
2282 | * This part of code should be enabled once mdp driver support it. | |
2283 | */ | |
f54ca1a0 AT |
2284 | /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { |
2285 | * dsi_link_clk_disable(msm_host); | |
2286 | * pm_runtime_put_autosuspend(&msm_host->pdev->dev); | |
2287 | * } | |
2288 | */ | |
9c5638d7 | 2289 | msm_host->enabled = true; |
a689554b HL |
2290 | return 0; |
2291 | } | |
2292 | ||
2293 | int msm_dsi_host_disable(struct mipi_dsi_host *host) | |
2294 | { | |
2295 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2296 | ||
9c5638d7 | 2297 | msm_host->enabled = false; |
a689554b HL |
2298 | dsi_op_mode_config(msm_host, |
2299 | !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); | |
2300 | ||
2301 | /* Since we have disabled INTF, the video engine won't stop so that | |
2302 | * the cmd engine will be blocked. | |
2303 | * Reset to disable video engine so that we can send off cmd. | |
2304 | */ | |
2305 | dsi_sw_reset(msm_host); | |
2306 | ||
2307 | return 0; | |
2308 | } | |
2309 | ||
0c7df47f AT |
2310 | static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) |
2311 | { | |
2312 | enum sfpb_ahb_arb_master_port_en en; | |
2313 | ||
2314 | if (!msm_host->sfpb) | |
2315 | return; | |
2316 | ||
2317 | en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; | |
2318 | ||
2319 | regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, | |
2320 | SFPB_GPREG_MASTER_PORT_EN__MASK, | |
2321 | SFPB_GPREG_MASTER_PORT_EN(en)); | |
2322 | } | |
2323 | ||
b62aa70a | 2324 | int msm_dsi_host_power_on(struct mipi_dsi_host *host, |
ed9976a0 CU |
2325 | struct msm_dsi_phy_shared_timings *phy_shared_timings, |
2326 | bool is_dual_dsi) | |
a689554b HL |
2327 | { |
2328 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
8f7ca540 | 2329 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
2330 | int ret = 0; |
2331 | ||
2332 | mutex_lock(&msm_host->dev_mutex); | |
2333 | if (msm_host->power_on) { | |
2334 | DBG("dsi host already on"); | |
2335 | goto unlock_ret; | |
2336 | } | |
2337 | ||
0c7df47f AT |
2338 | msm_dsi_sfpb_config(msm_host, true); |
2339 | ||
a689554b HL |
2340 | ret = dsi_host_regulator_enable(msm_host); |
2341 | if (ret) { | |
2342 | pr_err("%s:Failed to enable vregs.ret=%d\n", | |
2343 | __func__, ret); | |
2344 | goto unlock_ret; | |
2345 | } | |
2346 | ||
f6be1121 | 2347 | pm_runtime_get_sync(&msm_host->pdev->dev); |
8f7ca540 | 2348 | ret = cfg_hnd->ops->link_clk_enable(msm_host); |
a689554b | 2349 | if (ret) { |
f54ca1a0 AT |
2350 | pr_err("%s: failed to enable link clocks. ret=%d\n", |
2351 | __func__, ret); | |
a689554b HL |
2352 | goto fail_disable_reg; |
2353 | } | |
2354 | ||
ab8909b0 HL |
2355 | ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); |
2356 | if (ret) { | |
2357 | pr_err("%s: failed to set pinctrl default state, %d\n", | |
2358 | __func__, ret); | |
2359 | goto fail_disable_clk; | |
2360 | } | |
2361 | ||
ed9976a0 | 2362 | dsi_timing_setup(msm_host, is_dual_dsi); |
a689554b | 2363 | dsi_sw_reset(msm_host); |
b62aa70a | 2364 | dsi_ctrl_config(msm_host, true, phy_shared_timings); |
a689554b HL |
2365 | |
2366 | if (msm_host->disp_en_gpio) | |
2367 | gpiod_set_value(msm_host->disp_en_gpio, 1); | |
2368 | ||
2369 | msm_host->power_on = true; | |
2370 | mutex_unlock(&msm_host->dev_mutex); | |
2371 | ||
2372 | return 0; | |
2373 | ||
ab8909b0 | 2374 | fail_disable_clk: |
8f7ca540 | 2375 | cfg_hnd->ops->link_clk_disable(msm_host); |
f54ca1a0 | 2376 | pm_runtime_put_autosuspend(&msm_host->pdev->dev); |
a689554b HL |
2377 | fail_disable_reg: |
2378 | dsi_host_regulator_disable(msm_host); | |
2379 | unlock_ret: | |
2380 | mutex_unlock(&msm_host->dev_mutex); | |
2381 | return ret; | |
2382 | } | |
2383 | ||
2384 | int msm_dsi_host_power_off(struct mipi_dsi_host *host) | |
2385 | { | |
2386 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
8f7ca540 | 2387 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
2388 | |
2389 | mutex_lock(&msm_host->dev_mutex); | |
2390 | if (!msm_host->power_on) { | |
2391 | DBG("dsi host already off"); | |
2392 | goto unlock_ret; | |
2393 | } | |
2394 | ||
dceac340 | 2395 | dsi_ctrl_config(msm_host, false, NULL); |
a689554b HL |
2396 | |
2397 | if (msm_host->disp_en_gpio) | |
2398 | gpiod_set_value(msm_host->disp_en_gpio, 0); | |
2399 | ||
ab8909b0 HL |
2400 | pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); |
2401 | ||
8f7ca540 | 2402 | cfg_hnd->ops->link_clk_disable(msm_host); |
f6be1121 | 2403 | pm_runtime_put_autosuspend(&msm_host->pdev->dev); |
a689554b HL |
2404 | |
2405 | dsi_host_regulator_disable(msm_host); | |
2406 | ||
0c7df47f AT |
2407 | msm_dsi_sfpb_config(msm_host, false); |
2408 | ||
a689554b HL |
2409 | DBG("-"); |
2410 | ||
2411 | msm_host->power_on = false; | |
2412 | ||
2413 | unlock_ret: | |
2414 | mutex_unlock(&msm_host->dev_mutex); | |
2415 | return 0; | |
2416 | } | |
2417 | ||
2418 | int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, | |
63f8f3ba | 2419 | const struct drm_display_mode *mode) |
a689554b HL |
2420 | { |
2421 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2422 | ||
2423 | if (msm_host->mode) { | |
2424 | drm_mode_destroy(msm_host->dev, msm_host->mode); | |
2425 | msm_host->mode = NULL; | |
2426 | } | |
2427 | ||
2428 | msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); | |
2abe1f25 | 2429 | if (!msm_host->mode) { |
a689554b | 2430 | pr_err("%s: cannot duplicate mode\n", __func__); |
2abe1f25 | 2431 | return -ENOMEM; |
a689554b HL |
2432 | } |
2433 | ||
2434 | return 0; | |
2435 | } | |
2436 | ||
2437 | struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host, | |
2438 | unsigned long *panel_flags) | |
2439 | { | |
2440 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2441 | struct drm_panel *panel; | |
2442 | ||
a9ddac9c | 2443 | panel = of_drm_find_panel(msm_host->device_node); |
a689554b HL |
2444 | if (panel_flags) |
2445 | *panel_flags = msm_host->mode_flags; | |
2446 | ||
2447 | return panel; | |
2448 | } | |
2449 | ||
c118e290 AT |
2450 | struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host) |
2451 | { | |
2452 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2453 | ||
2454 | return of_drm_find_bridge(msm_host->device_node); | |
2455 | } |