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97fb5e8d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
a689554b HL |
2 | /* |
3 | * Copyright (c) 2015, The Linux Foundation. All rights reserved. | |
a689554b HL |
4 | */ |
5 | ||
6 | #include <linux/clk.h> | |
7 | #include <linux/delay.h> | |
feea39a8 | 8 | #include <linux/dma-mapping.h> |
a689554b | 9 | #include <linux/err.h> |
964a0754 | 10 | #include <linux/gpio/consumer.h> |
a689554b | 11 | #include <linux/interrupt.h> |
feea39a8 | 12 | #include <linux/mfd/syscon.h> |
a689554b | 13 | #include <linux/of_device.h> |
feea39a8 | 14 | #include <linux/of_graph.h> |
a689554b | 15 | #include <linux/of_irq.h> |
ab8909b0 | 16 | #include <linux/pinctrl/consumer.h> |
32d3e0fe | 17 | #include <linux/pm_opp.h> |
feea39a8 | 18 | #include <linux/regmap.h> |
a689554b HL |
19 | #include <linux/regulator/consumer.h> |
20 | #include <linux/spinlock.h> | |
feea39a8 | 21 | |
a689554b HL |
22 | #include <video/mipi_display.h> |
23 | ||
24 | #include "dsi.h" | |
25 | #include "dsi.xml.h" | |
0c7df47f | 26 | #include "sfpb.xml.h" |
d248b61f | 27 | #include "dsi_cfg.h" |
f59f62d5 | 28 | #include "msm_kms.h" |
8f642378 | 29 | #include "msm_gem.h" |
5ac17838 | 30 | #include "phy/dsi_phy.h" |
a689554b | 31 | |
78e31c42 JH |
32 | #define DSI_RESET_TOGGLE_DELAY_MS 20 |
33 | ||
a689554b HL |
34 | static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) |
35 | { | |
36 | u32 ver; | |
a689554b HL |
37 | |
38 | if (!major || !minor) | |
39 | return -EINVAL; | |
40 | ||
648d5063 AT |
41 | /* |
42 | * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 | |
a689554b | 43 | * makes all other registers 4-byte shifted down. |
648d5063 AT |
44 | * |
45 | * In order to identify between DSI6G(v3) and beyond, and DSIv2 and | |
46 | * older, we read the DSI_VERSION register without any shift(offset | |
47 | * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In | |
48 | * the case of DSI6G, this has to be zero (the offset points to a | |
49 | * scratch register which we never touch) | |
a689554b | 50 | */ |
648d5063 AT |
51 | |
52 | ver = msm_readl(base + REG_DSI_VERSION); | |
53 | if (ver) { | |
54 | /* older dsi host, there is no register shift */ | |
a689554b HL |
55 | ver = FIELD(ver, DSI_VERSION_MAJOR); |
56 | if (ver <= MSM_DSI_VER_MAJOR_V2) { | |
57 | /* old versions */ | |
58 | *major = ver; | |
59 | *minor = 0; | |
60 | return 0; | |
61 | } else { | |
62 | return -EINVAL; | |
63 | } | |
64 | } else { | |
648d5063 AT |
65 | /* |
66 | * newer host, offset 0 has 6G_HW_VERSION, the rest of the | |
67 | * registers are shifted down, read DSI_VERSION again with | |
68 | * the shifted offset | |
69 | */ | |
a689554b HL |
70 | ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); |
71 | ver = FIELD(ver, DSI_VERSION_MAJOR); | |
72 | if (ver == MSM_DSI_VER_MAJOR_6G) { | |
73 | /* 6G version */ | |
74 | *major = ver; | |
648d5063 | 75 | *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); |
a689554b HL |
76 | return 0; |
77 | } else { | |
78 | return -EINVAL; | |
79 | } | |
80 | } | |
81 | } | |
82 | ||
83 | #define DSI_ERR_STATE_ACK 0x0000 | |
84 | #define DSI_ERR_STATE_TIMEOUT 0x0001 | |
85 | #define DSI_ERR_STATE_DLN0_PHY 0x0002 | |
86 | #define DSI_ERR_STATE_FIFO 0x0004 | |
87 | #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 | |
88 | #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 | |
89 | #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 | |
90 | ||
91 | #define DSI_CLK_CTRL_ENABLE_CLKS \ | |
92 | (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ | |
93 | DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ | |
94 | DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ | |
95 | DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) | |
96 | ||
97 | struct msm_dsi_host { | |
98 | struct mipi_dsi_host base; | |
99 | ||
100 | struct platform_device *pdev; | |
101 | struct drm_device *dev; | |
102 | ||
103 | int id; | |
104 | ||
105 | void __iomem *ctrl_base; | |
bac2c6a6 | 106 | phys_addr_t ctrl_size; |
ec31abf6 | 107 | struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; |
6e0eb52e AT |
108 | |
109 | struct clk *bus_clks[DSI_BUS_CLK_MAX]; | |
110 | ||
a689554b HL |
111 | struct clk *byte_clk; |
112 | struct clk *esc_clk; | |
113 | struct clk *pixel_clk; | |
9d32c498 HL |
114 | struct clk *byte_clk_src; |
115 | struct clk *pixel_clk_src; | |
c1d97083 | 116 | struct clk *byte_intf_clk; |
9d32c498 | 117 | |
b16927f5 JZ |
118 | unsigned long byte_clk_rate; |
119 | unsigned long pixel_clk_rate; | |
120 | unsigned long esc_clk_rate; | |
4bfa9748 AT |
121 | |
122 | /* DSI v2 specific clocks */ | |
123 | struct clk *src_clk; | |
124 | struct clk *esc_clk_src; | |
125 | struct clk *dsi_clk_src; | |
126 | ||
b16927f5 | 127 | unsigned long src_clk_rate; |
a689554b HL |
128 | |
129 | struct gpio_desc *disp_en_gpio; | |
130 | struct gpio_desc *te_gpio; | |
131 | ||
d248b61f | 132 | const struct msm_dsi_cfg_handler *cfg_hnd; |
a689554b HL |
133 | |
134 | struct completion dma_comp; | |
135 | struct completion video_comp; | |
136 | struct mutex dev_mutex; | |
137 | struct mutex cmd_mutex; | |
a689554b HL |
138 | spinlock_t intr_lock; /* Protect interrupt ctrl register */ |
139 | ||
140 | u32 err_work_state; | |
141 | struct work_struct err_work; | |
8d23ea40 | 142 | struct work_struct hpd_work; |
a689554b HL |
143 | struct workqueue_struct *workqueue; |
144 | ||
4ff9d4cb | 145 | /* DSI 6G TX buffer*/ |
a689554b | 146 | struct drm_gem_object *tx_gem_obj; |
4ff9d4cb AT |
147 | |
148 | /* DSI v2 TX buffer */ | |
149 | void *tx_buf; | |
150 | dma_addr_t tx_buf_paddr; | |
151 | ||
152 | int tx_size; | |
153 | ||
a689554b HL |
154 | u8 *rx_buf; |
155 | ||
0c7df47f AT |
156 | struct regmap *sfpb; |
157 | ||
a689554b HL |
158 | struct drm_display_mode *mode; |
159 | ||
a9ddac9c AT |
160 | /* connected device info */ |
161 | struct device_node *device_node; | |
a689554b HL |
162 | unsigned int channel; |
163 | unsigned int lanes; | |
164 | enum mipi_dsi_pixel_format format; | |
165 | unsigned long mode_flags; | |
166 | ||
26f7d1f4 AT |
167 | /* lane data parsed via DT */ |
168 | int dlane_swap; | |
169 | int num_data_lanes; | |
170 | ||
5ac17838 JM |
171 | /* from phy DT */ |
172 | bool cphy_mode; | |
173 | ||
a689554b HL |
174 | u32 dma_cmd_ctrl_restore; |
175 | ||
176 | bool registered; | |
177 | bool power_on; | |
9c5638d7 | 178 | bool enabled; |
a689554b HL |
179 | int irq; |
180 | }; | |
181 | ||
182 | static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt) | |
183 | { | |
184 | switch (fmt) { | |
185 | case MIPI_DSI_FMT_RGB565: return 16; | |
186 | case MIPI_DSI_FMT_RGB666_PACKED: return 18; | |
187 | case MIPI_DSI_FMT_RGB666: | |
188 | case MIPI_DSI_FMT_RGB888: | |
189 | default: return 24; | |
190 | } | |
191 | } | |
192 | ||
193 | static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) | |
194 | { | |
d248b61f | 195 | return msm_readl(msm_host->ctrl_base + reg); |
a689554b HL |
196 | } |
197 | static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) | |
198 | { | |
d248b61f | 199 | msm_writel(data, msm_host->ctrl_base + reg); |
a689554b HL |
200 | } |
201 | ||
202 | static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host); | |
203 | static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host); | |
204 | ||
d248b61f HL |
205 | static const struct msm_dsi_cfg_handler *dsi_get_config( |
206 | struct msm_dsi_host *msm_host) | |
a689554b | 207 | { |
d248b61f | 208 | const struct msm_dsi_cfg_handler *cfg_hnd = NULL; |
31c92767 | 209 | struct device *dev = &msm_host->pdev->dev; |
31c92767 | 210 | struct clk *ahb_clk; |
d248b61f | 211 | int ret; |
a689554b HL |
212 | u32 major = 0, minor = 0; |
213 | ||
29a1157c | 214 | ahb_clk = msm_clk_get(msm_host->pdev, "iface"); |
31c92767 AT |
215 | if (IS_ERR(ahb_clk)) { |
216 | pr_err("%s: cannot get interface clock\n", __func__); | |
b93cc4b2 | 217 | goto exit; |
31c92767 AT |
218 | } |
219 | ||
f6be1121 AT |
220 | pm_runtime_get_sync(dev); |
221 | ||
31c92767 | 222 | ret = clk_prepare_enable(ahb_clk); |
a689554b HL |
223 | if (ret) { |
224 | pr_err("%s: unable to enable ahb_clk\n", __func__); | |
b93cc4b2 | 225 | goto runtime_put; |
a689554b HL |
226 | } |
227 | ||
228 | ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); | |
a689554b HL |
229 | if (ret) { |
230 | pr_err("%s: Invalid version\n", __func__); | |
d248b61f | 231 | goto disable_clks; |
a689554b HL |
232 | } |
233 | ||
d248b61f | 234 | cfg_hnd = msm_dsi_cfg_get(major, minor); |
a689554b | 235 | |
d248b61f HL |
236 | DBG("%s: Version %x:%x\n", __func__, major, minor); |
237 | ||
238 | disable_clks: | |
31c92767 | 239 | clk_disable_unprepare(ahb_clk); |
b93cc4b2 | 240 | runtime_put: |
a18a0ea0 | 241 | pm_runtime_put_sync(dev); |
d248b61f HL |
242 | exit: |
243 | return cfg_hnd; | |
a689554b HL |
244 | } |
245 | ||
246 | static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) | |
247 | { | |
248 | return container_of(host, struct msm_dsi_host, base); | |
249 | } | |
250 | ||
251 | static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host) | |
252 | { | |
253 | struct regulator_bulk_data *s = msm_host->supplies; | |
d248b61f HL |
254 | const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; |
255 | int num = msm_host->cfg_hnd->cfg->reg_cfg.num; | |
a689554b HL |
256 | int i; |
257 | ||
258 | DBG(""); | |
259 | for (i = num - 1; i >= 0; i--) | |
260 | if (regs[i].disable_load >= 0) | |
2c33ce00 DA |
261 | regulator_set_load(s[i].consumer, |
262 | regs[i].disable_load); | |
a689554b HL |
263 | |
264 | regulator_bulk_disable(num, s); | |
265 | } | |
266 | ||
267 | static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host) | |
268 | { | |
269 | struct regulator_bulk_data *s = msm_host->supplies; | |
d248b61f HL |
270 | const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; |
271 | int num = msm_host->cfg_hnd->cfg->reg_cfg.num; | |
a689554b HL |
272 | int ret, i; |
273 | ||
274 | DBG(""); | |
275 | for (i = 0; i < num; i++) { | |
276 | if (regs[i].enable_load >= 0) { | |
2c33ce00 DA |
277 | ret = regulator_set_load(s[i].consumer, |
278 | regs[i].enable_load); | |
a689554b HL |
279 | if (ret < 0) { |
280 | pr_err("regulator %d set op mode failed, %d\n", | |
281 | i, ret); | |
282 | goto fail; | |
283 | } | |
284 | } | |
285 | } | |
286 | ||
287 | ret = regulator_bulk_enable(num, s); | |
288 | if (ret < 0) { | |
289 | pr_err("regulator enable failed, %d\n", ret); | |
290 | goto fail; | |
291 | } | |
292 | ||
293 | return 0; | |
294 | ||
295 | fail: | |
296 | for (i--; i >= 0; i--) | |
2c33ce00 | 297 | regulator_set_load(s[i].consumer, regs[i].disable_load); |
a689554b HL |
298 | return ret; |
299 | } | |
300 | ||
301 | static int dsi_regulator_init(struct msm_dsi_host *msm_host) | |
302 | { | |
303 | struct regulator_bulk_data *s = msm_host->supplies; | |
d248b61f HL |
304 | const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; |
305 | int num = msm_host->cfg_hnd->cfg->reg_cfg.num; | |
a689554b HL |
306 | int i, ret; |
307 | ||
308 | for (i = 0; i < num; i++) | |
309 | s[i].supply = regs[i].name; | |
310 | ||
311 | ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s); | |
312 | if (ret < 0) { | |
313 | pr_err("%s: failed to init regulator, ret=%d\n", | |
314 | __func__, ret); | |
315 | return ret; | |
316 | } | |
317 | ||
a689554b HL |
318 | return 0; |
319 | } | |
320 | ||
c4d8cfe5 SS |
321 | int dsi_clk_init_v2(struct msm_dsi_host *msm_host) |
322 | { | |
323 | struct platform_device *pdev = msm_host->pdev; | |
324 | int ret = 0; | |
325 | ||
326 | msm_host->src_clk = msm_clk_get(pdev, "src"); | |
327 | ||
328 | if (IS_ERR(msm_host->src_clk)) { | |
329 | ret = PTR_ERR(msm_host->src_clk); | |
330 | pr_err("%s: can't find src clock. ret=%d\n", | |
331 | __func__, ret); | |
332 | msm_host->src_clk = NULL; | |
333 | return ret; | |
334 | } | |
335 | ||
336 | msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk); | |
337 | if (!msm_host->esc_clk_src) { | |
338 | ret = -ENODEV; | |
339 | pr_err("%s: can't get esc clock parent. ret=%d\n", | |
340 | __func__, ret); | |
341 | return ret; | |
342 | } | |
343 | ||
344 | msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk); | |
345 | if (!msm_host->dsi_clk_src) { | |
346 | ret = -ENODEV; | |
347 | pr_err("%s: can't get src clock parent. ret=%d\n", | |
348 | __func__, ret); | |
349 | } | |
350 | ||
351 | return ret; | |
352 | } | |
353 | ||
354 | int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) | |
355 | { | |
356 | struct platform_device *pdev = msm_host->pdev; | |
357 | int ret = 0; | |
358 | ||
359 | msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); | |
360 | if (IS_ERR(msm_host->byte_intf_clk)) { | |
361 | ret = PTR_ERR(msm_host->byte_intf_clk); | |
362 | pr_err("%s: can't find byte_intf clock. ret=%d\n", | |
363 | __func__, ret); | |
364 | } | |
365 | ||
366 | return ret; | |
367 | } | |
368 | ||
a689554b HL |
369 | static int dsi_clk_init(struct msm_dsi_host *msm_host) |
370 | { | |
db9a3750 | 371 | struct platform_device *pdev = msm_host->pdev; |
4bfa9748 AT |
372 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
373 | const struct msm_dsi_config *cfg = cfg_hnd->cfg; | |
6e0eb52e AT |
374 | int i, ret = 0; |
375 | ||
376 | /* get bus clocks */ | |
377 | for (i = 0; i < cfg->num_bus_clks; i++) { | |
db9a3750 | 378 | msm_host->bus_clks[i] = msm_clk_get(pdev, |
6e0eb52e AT |
379 | cfg->bus_clk_names[i]); |
380 | if (IS_ERR(msm_host->bus_clks[i])) { | |
381 | ret = PTR_ERR(msm_host->bus_clks[i]); | |
db9a3750 | 382 | pr_err("%s: Unable to get %s clock, ret = %d\n", |
6e0eb52e AT |
383 | __func__, cfg->bus_clk_names[i], ret); |
384 | goto exit; | |
385 | } | |
a689554b HL |
386 | } |
387 | ||
6e0eb52e | 388 | /* get link and source clocks */ |
db9a3750 | 389 | msm_host->byte_clk = msm_clk_get(pdev, "byte"); |
a689554b HL |
390 | if (IS_ERR(msm_host->byte_clk)) { |
391 | ret = PTR_ERR(msm_host->byte_clk); | |
db9a3750 | 392 | pr_err("%s: can't find dsi_byte clock. ret=%d\n", |
a689554b HL |
393 | __func__, ret); |
394 | msm_host->byte_clk = NULL; | |
395 | goto exit; | |
396 | } | |
397 | ||
db9a3750 | 398 | msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); |
a689554b HL |
399 | if (IS_ERR(msm_host->pixel_clk)) { |
400 | ret = PTR_ERR(msm_host->pixel_clk); | |
db9a3750 | 401 | pr_err("%s: can't find dsi_pixel clock. ret=%d\n", |
a689554b HL |
402 | __func__, ret); |
403 | msm_host->pixel_clk = NULL; | |
404 | goto exit; | |
405 | } | |
406 | ||
db9a3750 | 407 | msm_host->esc_clk = msm_clk_get(pdev, "core"); |
a689554b HL |
408 | if (IS_ERR(msm_host->esc_clk)) { |
409 | ret = PTR_ERR(msm_host->esc_clk); | |
db9a3750 | 410 | pr_err("%s: can't find dsi_esc clock. ret=%d\n", |
a689554b HL |
411 | __func__, ret); |
412 | msm_host->esc_clk = NULL; | |
413 | goto exit; | |
414 | } | |
415 | ||
e6c4c78c | 416 | msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk); |
5fb9b797 SP |
417 | if (IS_ERR(msm_host->byte_clk_src)) { |
418 | ret = PTR_ERR(msm_host->byte_clk_src); | |
db9a3750 | 419 | pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret); |
9d32c498 HL |
420 | goto exit; |
421 | } | |
422 | ||
e6c4c78c | 423 | msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk); |
5fb9b797 SP |
424 | if (IS_ERR(msm_host->pixel_clk_src)) { |
425 | ret = PTR_ERR(msm_host->pixel_clk_src); | |
db9a3750 | 426 | pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret); |
4bfa9748 | 427 | goto exit; |
9d32c498 HL |
428 | } |
429 | ||
8f7ca540 SS |
430 | if (cfg_hnd->ops->clk_init_ver) |
431 | ret = cfg_hnd->ops->clk_init_ver(msm_host); | |
a689554b HL |
432 | exit: |
433 | return ret; | |
434 | } | |
435 | ||
436 | static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host) | |
437 | { | |
6e0eb52e AT |
438 | const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; |
439 | int i, ret; | |
a689554b HL |
440 | |
441 | DBG("id=%d", msm_host->id); | |
442 | ||
6e0eb52e AT |
443 | for (i = 0; i < cfg->num_bus_clks; i++) { |
444 | ret = clk_prepare_enable(msm_host->bus_clks[i]); | |
445 | if (ret) { | |
446 | pr_err("%s: failed to enable bus clock %d ret %d\n", | |
447 | __func__, i, ret); | |
448 | goto err; | |
449 | } | |
a689554b HL |
450 | } |
451 | ||
452 | return 0; | |
6e0eb52e | 453 | err: |
c8f01ffc | 454 | while (--i >= 0) |
6e0eb52e | 455 | clk_disable_unprepare(msm_host->bus_clks[i]); |
a689554b | 456 | |
a689554b HL |
457 | return ret; |
458 | } | |
459 | ||
460 | static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host) | |
461 | { | |
6e0eb52e AT |
462 | const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; |
463 | int i; | |
464 | ||
a689554b | 465 | DBG(""); |
6e0eb52e AT |
466 | |
467 | for (i = cfg->num_bus_clks - 1; i >= 0; i--) | |
468 | clk_disable_unprepare(msm_host->bus_clks[i]); | |
a689554b HL |
469 | } |
470 | ||
f54ca1a0 AT |
471 | int msm_dsi_runtime_suspend(struct device *dev) |
472 | { | |
473 | struct platform_device *pdev = to_platform_device(dev); | |
474 | struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); | |
475 | struct mipi_dsi_host *host = msm_dsi->host; | |
476 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
477 | ||
478 | if (!msm_host->cfg_hnd) | |
479 | return 0; | |
480 | ||
481 | dsi_bus_clk_disable(msm_host); | |
482 | ||
483 | return 0; | |
484 | } | |
485 | ||
486 | int msm_dsi_runtime_resume(struct device *dev) | |
487 | { | |
488 | struct platform_device *pdev = to_platform_device(dev); | |
489 | struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); | |
490 | struct mipi_dsi_host *host = msm_dsi->host; | |
491 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
492 | ||
493 | if (!msm_host->cfg_hnd) | |
494 | return 0; | |
495 | ||
496 | return dsi_bus_clk_enable(msm_host); | |
497 | } | |
498 | ||
6b16f05a | 499 | int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) |
a689554b | 500 | { |
b16927f5 | 501 | unsigned long byte_intf_rate; |
a689554b HL |
502 | int ret; |
503 | ||
b16927f5 | 504 | DBG("Set clk rates: pclk=%d, byteclk=%lu", |
a689554b HL |
505 | msm_host->mode->clock, msm_host->byte_clk_rate); |
506 | ||
32d3e0fe RN |
507 | ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, |
508 | msm_host->byte_clk_rate); | |
a689554b | 509 | if (ret) { |
32d3e0fe | 510 | pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret); |
6b16f05a | 511 | return ret; |
a689554b HL |
512 | } |
513 | ||
ed9976a0 | 514 | ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); |
a689554b HL |
515 | if (ret) { |
516 | pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); | |
6b16f05a | 517 | return ret; |
a689554b HL |
518 | } |
519 | ||
c1d97083 | 520 | if (msm_host->byte_intf_clk) { |
5ac17838 JM |
521 | /* For CPHY, byte_intf_clk is same as byte_clk */ |
522 | if (msm_host->cphy_mode) | |
523 | byte_intf_rate = msm_host->byte_clk_rate; | |
524 | else | |
525 | byte_intf_rate = msm_host->byte_clk_rate / 2; | |
526 | ||
527 | ret = clk_set_rate(msm_host->byte_intf_clk, byte_intf_rate); | |
c1d97083 AT |
528 | if (ret) { |
529 | pr_err("%s: Failed to set rate byte intf clk, %d\n", | |
530 | __func__, ret); | |
6b16f05a | 531 | return ret; |
c1d97083 AT |
532 | } |
533 | } | |
534 | ||
6b16f05a RC |
535 | return 0; |
536 | } | |
537 | ||
538 | ||
539 | int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) | |
540 | { | |
541 | int ret; | |
542 | ||
a689554b HL |
543 | ret = clk_prepare_enable(msm_host->esc_clk); |
544 | if (ret) { | |
545 | pr_err("%s: Failed to enable dsi esc clk\n", __func__); | |
546 | goto error; | |
547 | } | |
548 | ||
549 | ret = clk_prepare_enable(msm_host->byte_clk); | |
550 | if (ret) { | |
551 | pr_err("%s: Failed to enable dsi byte clk\n", __func__); | |
552 | goto byte_clk_err; | |
553 | } | |
554 | ||
555 | ret = clk_prepare_enable(msm_host->pixel_clk); | |
556 | if (ret) { | |
557 | pr_err("%s: Failed to enable dsi pixel clk\n", __func__); | |
558 | goto pixel_clk_err; | |
559 | } | |
560 | ||
c1d97083 AT |
561 | if (msm_host->byte_intf_clk) { |
562 | ret = clk_prepare_enable(msm_host->byte_intf_clk); | |
563 | if (ret) { | |
564 | pr_err("%s: Failed to enable byte intf clk\n", | |
565 | __func__); | |
566 | goto byte_intf_clk_err; | |
567 | } | |
568 | } | |
569 | ||
a689554b HL |
570 | return 0; |
571 | ||
c1d97083 AT |
572 | byte_intf_clk_err: |
573 | clk_disable_unprepare(msm_host->pixel_clk); | |
a689554b HL |
574 | pixel_clk_err: |
575 | clk_disable_unprepare(msm_host->byte_clk); | |
576 | byte_clk_err: | |
577 | clk_disable_unprepare(msm_host->esc_clk); | |
578 | error: | |
579 | return ret; | |
580 | } | |
581 | ||
6b16f05a | 582 | int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) |
a689554b | 583 | { |
4bfa9748 AT |
584 | int ret; |
585 | ||
b16927f5 | 586 | DBG("Set clk rates: pclk=%d, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu", |
4bfa9748 AT |
587 | msm_host->mode->clock, msm_host->byte_clk_rate, |
588 | msm_host->esc_clk_rate, msm_host->src_clk_rate); | |
589 | ||
590 | ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); | |
591 | if (ret) { | |
592 | pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); | |
6b16f05a | 593 | return ret; |
4bfa9748 AT |
594 | } |
595 | ||
596 | ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); | |
597 | if (ret) { | |
598 | pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); | |
6b16f05a | 599 | return ret; |
4bfa9748 AT |
600 | } |
601 | ||
602 | ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); | |
603 | if (ret) { | |
604 | pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); | |
6b16f05a | 605 | return ret; |
4bfa9748 AT |
606 | } |
607 | ||
ed9976a0 | 608 | ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); |
4bfa9748 AT |
609 | if (ret) { |
610 | pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); | |
6b16f05a | 611 | return ret; |
4bfa9748 AT |
612 | } |
613 | ||
6b16f05a RC |
614 | return 0; |
615 | } | |
616 | ||
617 | int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) | |
618 | { | |
619 | int ret; | |
620 | ||
4bfa9748 AT |
621 | ret = clk_prepare_enable(msm_host->byte_clk); |
622 | if (ret) { | |
623 | pr_err("%s: Failed to enable dsi byte clk\n", __func__); | |
624 | goto error; | |
625 | } | |
626 | ||
627 | ret = clk_prepare_enable(msm_host->esc_clk); | |
628 | if (ret) { | |
629 | pr_err("%s: Failed to enable dsi esc clk\n", __func__); | |
630 | goto esc_clk_err; | |
631 | } | |
632 | ||
633 | ret = clk_prepare_enable(msm_host->src_clk); | |
634 | if (ret) { | |
635 | pr_err("%s: Failed to enable dsi src clk\n", __func__); | |
636 | goto src_clk_err; | |
637 | } | |
638 | ||
639 | ret = clk_prepare_enable(msm_host->pixel_clk); | |
640 | if (ret) { | |
641 | pr_err("%s: Failed to enable dsi pixel clk\n", __func__); | |
642 | goto pixel_clk_err; | |
643 | } | |
644 | ||
645 | return 0; | |
646 | ||
647 | pixel_clk_err: | |
648 | clk_disable_unprepare(msm_host->src_clk); | |
649 | src_clk_err: | |
a689554b | 650 | clk_disable_unprepare(msm_host->esc_clk); |
4bfa9748 | 651 | esc_clk_err: |
a689554b | 652 | clk_disable_unprepare(msm_host->byte_clk); |
4bfa9748 AT |
653 | error: |
654 | return ret; | |
655 | } | |
656 | ||
c4d8cfe5 SS |
657 | void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) |
658 | { | |
32d3e0fe RN |
659 | /* Drop the performance state vote */ |
660 | dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); | |
c4d8cfe5 SS |
661 | clk_disable_unprepare(msm_host->esc_clk); |
662 | clk_disable_unprepare(msm_host->pixel_clk); | |
663 | if (msm_host->byte_intf_clk) | |
664 | clk_disable_unprepare(msm_host->byte_intf_clk); | |
665 | clk_disable_unprepare(msm_host->byte_clk); | |
666 | } | |
667 | ||
668 | void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) | |
669 | { | |
670 | clk_disable_unprepare(msm_host->pixel_clk); | |
671 | clk_disable_unprepare(msm_host->src_clk); | |
672 | clk_disable_unprepare(msm_host->esc_clk); | |
673 | clk_disable_unprepare(msm_host->byte_clk); | |
674 | } | |
675 | ||
b16927f5 | 676 | static unsigned long dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_bonded_dsi) |
c4d8cfe5 SS |
677 | { |
678 | struct drm_display_mode *mode = msm_host->mode; | |
b16927f5 | 679 | unsigned long pclk_rate; |
c4d8cfe5 SS |
680 | |
681 | pclk_rate = mode->clock * 1000; | |
ed9976a0 CU |
682 | |
683 | /* | |
6183606d | 684 | * For bonded DSI mode, the current DRM mode has the complete width of the |
ed9976a0 | 685 | * panel. Since, the complete panel is driven by two DSI controllers, |
a6bcddbc | 686 | * the clock rates have to be split between the two dsi controllers. |
ed9976a0 CU |
687 | * Adjust the byte and pixel clock rates for each dsi host accordingly. |
688 | */ | |
6183606d | 689 | if (is_bonded_dsi) |
ed9976a0 CU |
690 | pclk_rate /= 2; |
691 | ||
a6bcddbc SP |
692 | return pclk_rate; |
693 | } | |
694 | ||
6183606d | 695 | static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi) |
a6bcddbc SP |
696 | { |
697 | u8 lanes = msm_host->lanes; | |
698 | u32 bpp = dsi_get_bpp(msm_host->format); | |
b16927f5 | 699 | unsigned long pclk_rate = dsi_get_pclk_rate(msm_host, is_bonded_dsi); |
a6bcddbc SP |
700 | u64 pclk_bpp = (u64)pclk_rate * bpp; |
701 | ||
702 | if (lanes == 0) { | |
c4d8cfe5 | 703 | pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); |
a6bcddbc | 704 | lanes = 1; |
c4d8cfe5 SS |
705 | } |
706 | ||
5ac17838 JM |
707 | /* CPHY "byte_clk" is in units of 16 bits */ |
708 | if (msm_host->cphy_mode) | |
709 | do_div(pclk_bpp, (16 * lanes)); | |
710 | else | |
711 | do_div(pclk_bpp, (8 * lanes)); | |
c4d8cfe5 | 712 | |
a6bcddbc SP |
713 | msm_host->pixel_clk_rate = pclk_rate; |
714 | msm_host->byte_clk_rate = pclk_bpp; | |
715 | ||
b16927f5 | 716 | DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate, |
a6bcddbc SP |
717 | msm_host->byte_clk_rate); |
718 | ||
719 | } | |
720 | ||
6183606d | 721 | int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi) |
a6bcddbc SP |
722 | { |
723 | if (!msm_host->mode) { | |
724 | pr_err("%s: mode not set\n", __func__); | |
725 | return -EINVAL; | |
726 | } | |
c4d8cfe5 | 727 | |
6183606d | 728 | dsi_calc_pclk(msm_host, is_bonded_dsi); |
a6bcddbc | 729 | msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); |
c4d8cfe5 SS |
730 | return 0; |
731 | } | |
732 | ||
6183606d | 733 | int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) |
c4d8cfe5 | 734 | { |
c4d8cfe5 | 735 | u32 bpp = dsi_get_bpp(msm_host->format); |
2d0b10fc | 736 | u64 pclk_bpp; |
c4d8cfe5 SS |
737 | unsigned int esc_mhz, esc_div; |
738 | unsigned long byte_mhz; | |
739 | ||
6183606d | 740 | dsi_calc_pclk(msm_host, is_bonded_dsi); |
c4d8cfe5 | 741 | |
6183606d | 742 | pclk_bpp = (u64)dsi_get_pclk_rate(msm_host, is_bonded_dsi) * bpp; |
a6bcddbc SP |
743 | do_div(pclk_bpp, 8); |
744 | msm_host->src_clk_rate = pclk_bpp; | |
c4d8cfe5 SS |
745 | |
746 | /* | |
747 | * esc clock is byte clock followed by a 4 bit divider, | |
748 | * we need to find an escape clock frequency within the | |
749 | * mipi DSI spec range within the maximum divider limit | |
750 | * We iterate here between an escape clock frequencey | |
751 | * between 20 Mhz to 5 Mhz and pick up the first one | |
752 | * that can be supported by our divider | |
753 | */ | |
754 | ||
755 | byte_mhz = msm_host->byte_clk_rate / 1000000; | |
756 | ||
757 | for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { | |
758 | esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); | |
759 | ||
760 | /* | |
761 | * TODO: Ideally, we shouldn't know what sort of divider | |
762 | * is available in mmss_cc, we're just assuming that | |
763 | * it'll always be a 4 bit divider. Need to come up with | |
764 | * a better way here. | |
765 | */ | |
766 | if (esc_div >= 1 && esc_div <= 16) | |
767 | break; | |
768 | } | |
769 | ||
770 | if (esc_mhz < 5) | |
771 | return -EINVAL; | |
772 | ||
773 | msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; | |
774 | ||
b16927f5 | 775 | DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate, |
c4d8cfe5 SS |
776 | msm_host->src_clk_rate); |
777 | ||
778 | return 0; | |
779 | } | |
780 | ||
a689554b HL |
781 | static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) |
782 | { | |
783 | u32 intr; | |
784 | unsigned long flags; | |
785 | ||
786 | spin_lock_irqsave(&msm_host->intr_lock, flags); | |
787 | intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); | |
788 | ||
789 | if (enable) | |
790 | intr |= mask; | |
791 | else | |
792 | intr &= ~mask; | |
793 | ||
794 | DBG("intr=%x enable=%d", intr, enable); | |
795 | ||
796 | dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); | |
797 | spin_unlock_irqrestore(&msm_host->intr_lock, flags); | |
798 | } | |
799 | ||
800 | static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) | |
801 | { | |
802 | if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) | |
803 | return BURST_MODE; | |
804 | else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) | |
805 | return NON_BURST_SYNCH_PULSE; | |
806 | ||
807 | return NON_BURST_SYNCH_EVENT; | |
808 | } | |
809 | ||
810 | static inline enum dsi_vid_dst_format dsi_get_vid_fmt( | |
811 | const enum mipi_dsi_pixel_format mipi_fmt) | |
812 | { | |
813 | switch (mipi_fmt) { | |
814 | case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; | |
815 | case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; | |
816 | case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; | |
817 | case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; | |
818 | default: return VID_DST_FORMAT_RGB888; | |
819 | } | |
820 | } | |
821 | ||
822 | static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( | |
823 | const enum mipi_dsi_pixel_format mipi_fmt) | |
824 | { | |
825 | switch (mipi_fmt) { | |
826 | case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; | |
827 | case MIPI_DSI_FMT_RGB666_PACKED: | |
cf606fe3 | 828 | case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; |
a689554b HL |
829 | case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; |
830 | default: return CMD_DST_FORMAT_RGB888; | |
831 | } | |
832 | } | |
833 | ||
834 | static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, | |
858c595a | 835 | struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy) |
a689554b HL |
836 | { |
837 | u32 flags = msm_host->mode_flags; | |
838 | enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; | |
d248b61f | 839 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
e3ff6881 | 840 | u32 data = 0, lane_ctrl = 0; |
a689554b HL |
841 | |
842 | if (!enable) { | |
843 | dsi_write(msm_host, REG_DSI_CTRL, 0); | |
844 | return; | |
845 | } | |
846 | ||
847 | if (flags & MIPI_DSI_MODE_VIDEO) { | |
848 | if (flags & MIPI_DSI_MODE_VIDEO_HSE) | |
849 | data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; | |
0f3b68b6 | 850 | if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP) |
a689554b | 851 | data |= DSI_VID_CFG0_HFP_POWER_STOP; |
0f3b68b6 | 852 | if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP) |
a689554b | 853 | data |= DSI_VID_CFG0_HBP_POWER_STOP; |
0f3b68b6 | 854 | if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA) |
a689554b HL |
855 | data |= DSI_VID_CFG0_HSA_POWER_STOP; |
856 | /* Always set low power stop mode for BLLP | |
857 | * to let command engine send packets | |
858 | */ | |
859 | data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | | |
860 | DSI_VID_CFG0_BLLP_POWER_STOP; | |
861 | data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); | |
862 | data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); | |
863 | data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); | |
864 | dsi_write(msm_host, REG_DSI_VID_CFG0, data); | |
865 | ||
866 | /* Do not swap RGB colors */ | |
867 | data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); | |
868 | dsi_write(msm_host, REG_DSI_VID_CFG1, 0); | |
869 | } else { | |
870 | /* Do not swap RGB colors */ | |
871 | data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); | |
872 | data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); | |
873 | dsi_write(msm_host, REG_DSI_CMD_CFG0, data); | |
874 | ||
875 | data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | | |
876 | DSI_CMD_CFG1_WR_MEM_CONTINUE( | |
877 | MIPI_DCS_WRITE_MEMORY_CONTINUE); | |
878 | /* Always insert DCS command */ | |
879 | data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; | |
880 | dsi_write(msm_host, REG_DSI_CMD_CFG1, data); | |
881 | } | |
882 | ||
883 | dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, | |
884 | DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | | |
885 | DSI_CMD_DMA_CTRL_LOW_POWER); | |
886 | ||
887 | data = 0; | |
888 | /* Always assume dedicated TE pin */ | |
889 | data |= DSI_TRIG_CTRL_TE; | |
890 | data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); | |
891 | data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); | |
892 | data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); | |
d248b61f HL |
893 | if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && |
894 | (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) | |
a689554b HL |
895 | data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; |
896 | dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); | |
897 | ||
dceac340 HL |
898 | data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | |
899 | DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); | |
a689554b HL |
900 | dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); |
901 | ||
dceac340 HL |
902 | if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && |
903 | (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && | |
904 | phy_shared_timings->clk_pre_inc_by_2) | |
905 | dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, | |
906 | DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); | |
907 | ||
a689554b | 908 | data = 0; |
0f3b68b6 | 909 | if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET)) |
a689554b HL |
910 | data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; |
911 | dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); | |
912 | ||
913 | /* allow only ack-err-status to generate interrupt */ | |
914 | dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); | |
915 | ||
916 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); | |
917 | ||
918 | dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); | |
919 | ||
920 | data = DSI_CTRL_CLK_EN; | |
921 | ||
922 | DBG("lane number=%d", msm_host->lanes); | |
26f7d1f4 AT |
923 | data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); |
924 | ||
925 | dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, | |
926 | DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); | |
65c5e542 | 927 | |
e3ff6881 H |
928 | if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { |
929 | lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL); | |
858c595a DB |
930 | |
931 | if (msm_dsi_phy_set_continuous_clock(phy, enable)) | |
932 | lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY; | |
933 | ||
65c5e542 | 934 | dsi_write(msm_host, REG_DSI_LANE_CTRL, |
e3ff6881 H |
935 | lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); |
936 | } | |
65c5e542 | 937 | |
a689554b HL |
938 | data |= DSI_CTRL_ENABLE; |
939 | ||
940 | dsi_write(msm_host, REG_DSI_CTRL, data); | |
5ac17838 JM |
941 | |
942 | if (msm_host->cphy_mode) | |
943 | dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0)); | |
a689554b HL |
944 | } |
945 | ||
6183606d | 946 | static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) |
a689554b HL |
947 | { |
948 | struct drm_display_mode *mode = msm_host->mode; | |
949 | u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ | |
950 | u32 h_total = mode->htotal; | |
951 | u32 v_total = mode->vtotal; | |
952 | u32 hs_end = mode->hsync_end - mode->hsync_start; | |
953 | u32 vs_end = mode->vsync_end - mode->vsync_start; | |
954 | u32 ha_start = h_total - mode->hsync_start; | |
955 | u32 ha_end = ha_start + mode->hdisplay; | |
956 | u32 va_start = v_total - mode->vsync_start; | |
957 | u32 va_end = va_start + mode->vdisplay; | |
ed9976a0 | 958 | u32 hdisplay = mode->hdisplay; |
a689554b HL |
959 | u32 wc; |
960 | ||
961 | DBG(""); | |
962 | ||
ed9976a0 | 963 | /* |
6183606d | 964 | * For bonded DSI mode, the current DRM mode has |
ed9976a0 CU |
965 | * the complete width of the panel. Since, the complete |
966 | * panel is driven by two DSI controllers, the horizontal | |
967 | * timings have to be split between the two dsi controllers. | |
968 | * Adjust the DSI host timing values accordingly. | |
969 | */ | |
6183606d | 970 | if (is_bonded_dsi) { |
ed9976a0 CU |
971 | h_total /= 2; |
972 | hs_end /= 2; | |
973 | ha_start /= 2; | |
974 | ha_end /= 2; | |
975 | hdisplay /= 2; | |
976 | } | |
977 | ||
a689554b HL |
978 | if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { |
979 | dsi_write(msm_host, REG_DSI_ACTIVE_H, | |
980 | DSI_ACTIVE_H_START(ha_start) | | |
981 | DSI_ACTIVE_H_END(ha_end)); | |
982 | dsi_write(msm_host, REG_DSI_ACTIVE_V, | |
983 | DSI_ACTIVE_V_START(va_start) | | |
984 | DSI_ACTIVE_V_END(va_end)); | |
985 | dsi_write(msm_host, REG_DSI_TOTAL, | |
986 | DSI_TOTAL_H_TOTAL(h_total - 1) | | |
987 | DSI_TOTAL_V_TOTAL(v_total - 1)); | |
988 | ||
989 | dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, | |
990 | DSI_ACTIVE_HSYNC_START(hs_start) | | |
991 | DSI_ACTIVE_HSYNC_END(hs_end)); | |
992 | dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); | |
993 | dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, | |
994 | DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | | |
995 | DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); | |
996 | } else { /* command mode */ | |
997 | /* image data and 1 byte write_memory_start cmd */ | |
ed9976a0 | 998 | wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; |
a689554b | 999 | |
c28c82e9 RC |
1000 | dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, |
1001 | DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | | |
1002 | DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( | |
a689554b | 1003 | msm_host->channel) | |
c28c82e9 | 1004 | DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( |
a689554b HL |
1005 | MIPI_DSI_DCS_LONG_WRITE)); |
1006 | ||
c28c82e9 RC |
1007 | dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, |
1008 | DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | | |
1009 | DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); | |
a689554b HL |
1010 | } |
1011 | } | |
1012 | ||
1013 | static void dsi_sw_reset(struct msm_dsi_host *msm_host) | |
1014 | { | |
1015 | dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); | |
1016 | wmb(); /* clocks need to be enabled before reset */ | |
1017 | ||
1018 | dsi_write(msm_host, REG_DSI_RESET, 1); | |
78e31c42 | 1019 | msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ |
a689554b HL |
1020 | dsi_write(msm_host, REG_DSI_RESET, 0); |
1021 | } | |
1022 | ||
1023 | static void dsi_op_mode_config(struct msm_dsi_host *msm_host, | |
1024 | bool video_mode, bool enable) | |
1025 | { | |
1026 | u32 dsi_ctrl; | |
1027 | ||
1028 | dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); | |
1029 | ||
1030 | if (!enable) { | |
1031 | dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | | |
1032 | DSI_CTRL_CMD_MODE_EN); | |
1033 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | | |
1034 | DSI_IRQ_MASK_VIDEO_DONE, 0); | |
1035 | } else { | |
1036 | if (video_mode) { | |
1037 | dsi_ctrl |= DSI_CTRL_VID_MODE_EN; | |
1038 | } else { /* command mode */ | |
1039 | dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; | |
1040 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); | |
1041 | } | |
1042 | dsi_ctrl |= DSI_CTRL_ENABLE; | |
1043 | } | |
1044 | ||
1045 | dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); | |
1046 | } | |
1047 | ||
1048 | static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) | |
1049 | { | |
1050 | u32 data; | |
1051 | ||
1052 | data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); | |
1053 | ||
1054 | if (mode == 0) | |
1055 | data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; | |
1056 | else | |
1057 | data |= DSI_CMD_DMA_CTRL_LOW_POWER; | |
1058 | ||
1059 | dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); | |
1060 | } | |
1061 | ||
1062 | static void dsi_wait4video_done(struct msm_dsi_host *msm_host) | |
1063 | { | |
79ebc86c AK |
1064 | u32 ret = 0; |
1065 | struct device *dev = &msm_host->pdev->dev; | |
1066 | ||
a689554b HL |
1067 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); |
1068 | ||
1069 | reinit_completion(&msm_host->video_comp); | |
1070 | ||
79ebc86c | 1071 | ret = wait_for_completion_timeout(&msm_host->video_comp, |
a689554b HL |
1072 | msecs_to_jiffies(70)); |
1073 | ||
9a4a153b | 1074 | if (ret == 0) |
6a41da17 | 1075 | DRM_DEV_ERROR(dev, "wait for video done timed out\n"); |
79ebc86c | 1076 | |
a689554b HL |
1077 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); |
1078 | } | |
1079 | ||
1080 | static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) | |
1081 | { | |
1082 | if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) | |
1083 | return; | |
1084 | ||
9c5638d7 | 1085 | if (msm_host->power_on && msm_host->enabled) { |
a689554b HL |
1086 | dsi_wait4video_done(msm_host); |
1087 | /* delay 4 ms to skip BLLP */ | |
1088 | usleep_range(2000, 4000); | |
1089 | } | |
1090 | } | |
1091 | ||
c4d8cfe5 SS |
1092 | int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) |
1093 | { | |
1094 | struct drm_device *dev = msm_host->dev; | |
1095 | struct msm_drm_private *priv = dev->dev_private; | |
1096 | uint64_t iova; | |
1097 | u8 *data; | |
1098 | ||
a5fc7aa9 | 1099 | data = msm_gem_kernel_new(dev, size, MSM_BO_WC, |
c4d8cfe5 SS |
1100 | priv->kms->aspace, |
1101 | &msm_host->tx_gem_obj, &iova); | |
1102 | ||
1103 | if (IS_ERR(data)) { | |
1104 | msm_host->tx_gem_obj = NULL; | |
1105 | return PTR_ERR(data); | |
1106 | } | |
1107 | ||
0815d774 JC |
1108 | msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); |
1109 | ||
c4d8cfe5 SS |
1110 | msm_host->tx_size = msm_host->tx_gem_obj->size; |
1111 | ||
1112 | return 0; | |
1113 | } | |
1114 | ||
1115 | int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) | |
1116 | { | |
1117 | struct drm_device *dev = msm_host->dev; | |
1118 | ||
1119 | msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, | |
1120 | &msm_host->tx_buf_paddr, GFP_KERNEL); | |
1121 | if (!msm_host->tx_buf) | |
1122 | return -ENOMEM; | |
1123 | ||
1124 | msm_host->tx_size = size; | |
1125 | ||
1126 | return 0; | |
1127 | } | |
1128 | ||
a689554b HL |
1129 | static void dsi_tx_buf_free(struct msm_dsi_host *msm_host) |
1130 | { | |
1131 | struct drm_device *dev = msm_host->dev; | |
74d3a3a7 SP |
1132 | struct msm_drm_private *priv; |
1133 | ||
1134 | /* | |
1135 | * This is possible if we're tearing down before we've had a chance to | |
1136 | * fully initialize. A very real possibility if our probe is deferred, | |
1137 | * in which case we'll hit msm_dsi_host_destroy() without having run | |
1138 | * through the dsi_tx_buf_alloc(). | |
1139 | */ | |
1140 | if (!dev) | |
1141 | return; | |
a689554b | 1142 | |
74d3a3a7 | 1143 | priv = dev->dev_private; |
a689554b | 1144 | if (msm_host->tx_gem_obj) { |
7ad0e8cf | 1145 | msm_gem_unpin_iova(msm_host->tx_gem_obj, priv->kms->aspace); |
f7d33950 | 1146 | drm_gem_object_put(msm_host->tx_gem_obj); |
a689554b | 1147 | msm_host->tx_gem_obj = NULL; |
a689554b | 1148 | } |
4ff9d4cb AT |
1149 | |
1150 | if (msm_host->tx_buf) | |
1151 | dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, | |
1152 | msm_host->tx_buf_paddr); | |
a689554b HL |
1153 | } |
1154 | ||
c4d8cfe5 SS |
1155 | void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) |
1156 | { | |
1157 | return msm_gem_get_vaddr(msm_host->tx_gem_obj); | |
1158 | } | |
1159 | ||
1160 | void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) | |
1161 | { | |
1162 | return msm_host->tx_buf; | |
1163 | } | |
1164 | ||
1165 | void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) | |
1166 | { | |
1167 | msm_gem_put_vaddr(msm_host->tx_gem_obj); | |
1168 | } | |
1169 | ||
a689554b HL |
1170 | /* |
1171 | * prepare cmd buffer to be txed | |
1172 | */ | |
4ff9d4cb AT |
1173 | static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, |
1174 | const struct mipi_dsi_msg *msg) | |
a689554b | 1175 | { |
4ff9d4cb | 1176 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
1177 | struct mipi_dsi_packet packet; |
1178 | int len; | |
1179 | int ret; | |
1180 | u8 *data; | |
1181 | ||
1182 | ret = mipi_dsi_create_packet(&packet, msg); | |
1183 | if (ret) { | |
1184 | pr_err("%s: create packet failed, %d\n", __func__, ret); | |
1185 | return ret; | |
1186 | } | |
1187 | len = (packet.size + 3) & (~0x3); | |
1188 | ||
4ff9d4cb | 1189 | if (len > msm_host->tx_size) { |
a689554b HL |
1190 | pr_err("%s: packet size is too big\n", __func__); |
1191 | return -EINVAL; | |
1192 | } | |
1193 | ||
8f7ca540 SS |
1194 | data = cfg_hnd->ops->tx_buf_get(msm_host); |
1195 | if (IS_ERR(data)) { | |
1196 | ret = PTR_ERR(data); | |
1197 | pr_err("%s: get vaddr failed, %d\n", __func__, ret); | |
1198 | return ret; | |
a689554b HL |
1199 | } |
1200 | ||
1201 | /* MSM specific command format in memory */ | |
1202 | data[0] = packet.header[1]; | |
1203 | data[1] = packet.header[2]; | |
1204 | data[2] = packet.header[0]; | |
1205 | data[3] = BIT(7); /* Last packet */ | |
1206 | if (mipi_dsi_packet_format_is_long(msg->type)) | |
1207 | data[3] |= BIT(6); | |
1208 | if (msg->rx_buf && msg->rx_len) | |
1209 | data[3] |= BIT(5); | |
1210 | ||
1211 | /* Long packet */ | |
1212 | if (packet.payload && packet.payload_length) | |
1213 | memcpy(data + 4, packet.payload, packet.payload_length); | |
1214 | ||
1215 | /* Append 0xff to the end */ | |
1216 | if (packet.size < len) | |
1217 | memset(data + packet.size, 0xff, len - packet.size); | |
1218 | ||
8f7ca540 SS |
1219 | if (cfg_hnd->ops->tx_buf_put) |
1220 | cfg_hnd->ops->tx_buf_put(msm_host); | |
18f23049 | 1221 | |
a689554b HL |
1222 | return len; |
1223 | } | |
1224 | ||
1225 | /* | |
1226 | * dsi_short_read1_resp: 1 parameter | |
1227 | */ | |
1228 | static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) | |
1229 | { | |
1230 | u8 *data = msg->rx_buf; | |
1231 | if (data && (msg->rx_len >= 1)) { | |
1232 | *data = buf[1]; /* strip out dcs type */ | |
1233 | return 1; | |
1234 | } else { | |
981371f3 | 1235 | pr_err("%s: read data does not match with rx_buf len %zu\n", |
a689554b HL |
1236 | __func__, msg->rx_len); |
1237 | return -EINVAL; | |
1238 | } | |
1239 | } | |
1240 | ||
1241 | /* | |
1242 | * dsi_short_read2_resp: 2 parameter | |
1243 | */ | |
1244 | static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) | |
1245 | { | |
1246 | u8 *data = msg->rx_buf; | |
1247 | if (data && (msg->rx_len >= 2)) { | |
1248 | data[0] = buf[1]; /* strip out dcs type */ | |
1249 | data[1] = buf[2]; | |
1250 | return 2; | |
1251 | } else { | |
981371f3 | 1252 | pr_err("%s: read data does not match with rx_buf len %zu\n", |
a689554b HL |
1253 | __func__, msg->rx_len); |
1254 | return -EINVAL; | |
1255 | } | |
1256 | } | |
1257 | ||
1258 | static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) | |
1259 | { | |
1260 | /* strip out 4 byte dcs header */ | |
1261 | if (msg->rx_buf && msg->rx_len) | |
1262 | memcpy(msg->rx_buf, buf + 4, msg->rx_len); | |
1263 | ||
1264 | return msg->rx_len; | |
1265 | } | |
1266 | ||
c4d8cfe5 SS |
1267 | int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) |
1268 | { | |
1269 | struct drm_device *dev = msm_host->dev; | |
1270 | struct msm_drm_private *priv = dev->dev_private; | |
1271 | ||
1272 | if (!dma_base) | |
1273 | return -EINVAL; | |
1274 | ||
9fe041f6 | 1275 | return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, |
c4d8cfe5 SS |
1276 | priv->kms->aspace, dma_base); |
1277 | } | |
1278 | ||
1279 | int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) | |
1280 | { | |
1281 | if (!dma_base) | |
1282 | return -EINVAL; | |
1283 | ||
1284 | *dma_base = msm_host->tx_buf_paddr; | |
1285 | return 0; | |
1286 | } | |
1287 | ||
a689554b HL |
1288 | static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) |
1289 | { | |
4ff9d4cb | 1290 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b | 1291 | int ret; |
78babc16 | 1292 | uint64_t dma_base; |
a689554b HL |
1293 | bool triggered; |
1294 | ||
8f7ca540 SS |
1295 | ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); |
1296 | if (ret) { | |
1297 | pr_err("%s: failed to get iova: %d\n", __func__, ret); | |
1298 | return ret; | |
a689554b HL |
1299 | } |
1300 | ||
1301 | reinit_completion(&msm_host->dma_comp); | |
1302 | ||
1303 | dsi_wait4video_eng_busy(msm_host); | |
1304 | ||
1305 | triggered = msm_dsi_manager_cmd_xfer_trigger( | |
4ff9d4cb | 1306 | msm_host->id, dma_base, len); |
a689554b HL |
1307 | if (triggered) { |
1308 | ret = wait_for_completion_timeout(&msm_host->dma_comp, | |
1309 | msecs_to_jiffies(200)); | |
1310 | DBG("ret=%d", ret); | |
1311 | if (ret == 0) | |
1312 | ret = -ETIMEDOUT; | |
1313 | else | |
1314 | ret = len; | |
1315 | } else | |
1316 | ret = len; | |
1317 | ||
1318 | return ret; | |
1319 | } | |
1320 | ||
1321 | static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, | |
1322 | u8 *buf, int rx_byte, int pkt_size) | |
1323 | { | |
2e3cc607 | 1324 | u32 *temp, data; |
a689554b | 1325 | int i, j = 0, cnt; |
a689554b HL |
1326 | u32 read_cnt; |
1327 | u8 reg[16]; | |
1328 | int repeated_bytes = 0; | |
1329 | int buf_offset = buf - msm_host->rx_buf; | |
1330 | ||
a689554b HL |
1331 | temp = (u32 *)reg; |
1332 | cnt = (rx_byte + 3) >> 2; | |
1333 | if (cnt > 4) | |
1334 | cnt = 4; /* 4 x 32 bits registers only */ | |
1335 | ||
ec1936eb HL |
1336 | if (rx_byte == 4) |
1337 | read_cnt = 4; | |
1338 | else | |
1339 | read_cnt = pkt_size + 6; | |
a689554b HL |
1340 | |
1341 | /* | |
1342 | * In case of multiple reads from the panel, after the first read, there | |
1343 | * is possibility that there are some bytes in the payload repeating in | |
1344 | * the RDBK_DATA registers. Since we read all the parameters from the | |
1345 | * panel right from the first byte for every pass. We need to skip the | |
1346 | * repeating bytes and then append the new parameters to the rx buffer. | |
1347 | */ | |
1348 | if (read_cnt > 16) { | |
1349 | int bytes_shifted; | |
1350 | /* Any data more than 16 bytes will be shifted out. | |
1351 | * The temp read buffer should already contain these bytes. | |
1352 | * The remaining bytes in read buffer are the repeated bytes. | |
1353 | */ | |
1354 | bytes_shifted = read_cnt - 16; | |
1355 | repeated_bytes = buf_offset - bytes_shifted; | |
1356 | } | |
1357 | ||
1358 | for (i = cnt - 1; i >= 0; i--) { | |
1359 | data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); | |
1360 | *temp++ = ntohl(data); /* to host byte order */ | |
1361 | DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); | |
1362 | } | |
1363 | ||
1364 | for (i = repeated_bytes; i < 16; i++) | |
1365 | buf[j++] = reg[i]; | |
1366 | ||
1367 | return j; | |
1368 | } | |
1369 | ||
1370 | static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, | |
1371 | const struct mipi_dsi_msg *msg) | |
1372 | { | |
1373 | int len, ret; | |
1374 | int bllp_len = msm_host->mode->hdisplay * | |
1375 | dsi_get_bpp(msm_host->format) / 8; | |
1376 | ||
4ff9d4cb | 1377 | len = dsi_cmd_dma_add(msm_host, msg); |
a689554b HL |
1378 | if (!len) { |
1379 | pr_err("%s: failed to add cmd type = 0x%x\n", | |
1380 | __func__, msg->type); | |
1381 | return -EINVAL; | |
1382 | } | |
1383 | ||
1384 | /* for video mode, do not send cmds more than | |
1385 | * one pixel line, since it only transmit it | |
1386 | * during BLLP. | |
1387 | */ | |
1388 | /* TODO: if the command is sent in LP mode, the bit rate is only | |
1389 | * half of esc clk rate. In this case, if the video is already | |
1390 | * actively streaming, we need to check more carefully if the | |
1391 | * command can be fit into one BLLP. | |
1392 | */ | |
1393 | if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { | |
1394 | pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", | |
1395 | __func__, len); | |
1396 | return -EINVAL; | |
1397 | } | |
1398 | ||
1399 | ret = dsi_cmd_dma_tx(msm_host, len); | |
1400 | if (ret < len) { | |
1401 | pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d\n", | |
1402 | __func__, msg->type, (*(u8 *)(msg->tx_buf)), len); | |
1403 | return -ECOMM; | |
1404 | } | |
1405 | ||
1406 | return len; | |
1407 | } | |
1408 | ||
1409 | static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host) | |
1410 | { | |
1411 | u32 data0, data1; | |
1412 | ||
1413 | data0 = dsi_read(msm_host, REG_DSI_CTRL); | |
1414 | data1 = data0; | |
1415 | data1 &= ~DSI_CTRL_ENABLE; | |
1416 | dsi_write(msm_host, REG_DSI_CTRL, data1); | |
1417 | /* | |
1418 | * dsi controller need to be disabled before | |
1419 | * clocks turned on | |
1420 | */ | |
1421 | wmb(); | |
1422 | ||
1423 | dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); | |
1424 | wmb(); /* make sure clocks enabled */ | |
1425 | ||
1426 | /* dsi controller can only be reset while clocks are running */ | |
1427 | dsi_write(msm_host, REG_DSI_RESET, 1); | |
78e31c42 | 1428 | msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ |
a689554b HL |
1429 | dsi_write(msm_host, REG_DSI_RESET, 0); |
1430 | wmb(); /* controller out of reset */ | |
1431 | dsi_write(msm_host, REG_DSI_CTRL, data0); | |
1432 | wmb(); /* make sure dsi controller enabled again */ | |
1433 | } | |
1434 | ||
8d23ea40 AT |
1435 | static void dsi_hpd_worker(struct work_struct *work) |
1436 | { | |
1437 | struct msm_dsi_host *msm_host = | |
1438 | container_of(work, struct msm_dsi_host, hpd_work); | |
1439 | ||
1440 | drm_helper_hpd_irq_event(msm_host->dev); | |
1441 | } | |
1442 | ||
a689554b HL |
1443 | static void dsi_err_worker(struct work_struct *work) |
1444 | { | |
1445 | struct msm_dsi_host *msm_host = | |
1446 | container_of(work, struct msm_dsi_host, err_work); | |
1447 | u32 status = msm_host->err_work_state; | |
1448 | ||
ff431fa4 | 1449 | pr_err_ratelimited("%s: status=%x\n", __func__, status); |
a689554b HL |
1450 | if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) |
1451 | dsi_sw_reset_restore(msm_host); | |
1452 | ||
1453 | /* It is safe to clear here because error irq is disabled. */ | |
1454 | msm_host->err_work_state = 0; | |
1455 | ||
1456 | /* enable dsi error interrupt */ | |
1457 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); | |
1458 | } | |
1459 | ||
1460 | static void dsi_ack_err_status(struct msm_dsi_host *msm_host) | |
1461 | { | |
1462 | u32 status; | |
1463 | ||
1464 | status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); | |
1465 | ||
1466 | if (status) { | |
1467 | dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); | |
1468 | /* Writing of an extra 0 needed to clear error bits */ | |
1469 | dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); | |
1470 | msm_host->err_work_state |= DSI_ERR_STATE_ACK; | |
1471 | } | |
1472 | } | |
1473 | ||
1474 | static void dsi_timeout_status(struct msm_dsi_host *msm_host) | |
1475 | { | |
1476 | u32 status; | |
1477 | ||
1478 | status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); | |
1479 | ||
1480 | if (status) { | |
1481 | dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); | |
1482 | msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; | |
1483 | } | |
1484 | } | |
1485 | ||
1486 | static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) | |
1487 | { | |
1488 | u32 status; | |
1489 | ||
1490 | status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); | |
1491 | ||
01199361 AT |
1492 | if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | |
1493 | DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | | |
1494 | DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | | |
1495 | DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | | |
1496 | DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { | |
a689554b HL |
1497 | dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); |
1498 | msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; | |
1499 | } | |
1500 | } | |
1501 | ||
1502 | static void dsi_fifo_status(struct msm_dsi_host *msm_host) | |
1503 | { | |
1504 | u32 status; | |
1505 | ||
1506 | status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); | |
1507 | ||
1508 | /* fifo underflow, overflow */ | |
1509 | if (status) { | |
1510 | dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); | |
1511 | msm_host->err_work_state |= DSI_ERR_STATE_FIFO; | |
1512 | if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) | |
1513 | msm_host->err_work_state |= | |
1514 | DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; | |
1515 | } | |
1516 | } | |
1517 | ||
1518 | static void dsi_status(struct msm_dsi_host *msm_host) | |
1519 | { | |
1520 | u32 status; | |
1521 | ||
1522 | status = dsi_read(msm_host, REG_DSI_STATUS0); | |
1523 | ||
1524 | if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { | |
1525 | dsi_write(msm_host, REG_DSI_STATUS0, status); | |
1526 | msm_host->err_work_state |= | |
1527 | DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; | |
1528 | } | |
1529 | } | |
1530 | ||
1531 | static void dsi_clk_status(struct msm_dsi_host *msm_host) | |
1532 | { | |
1533 | u32 status; | |
1534 | ||
1535 | status = dsi_read(msm_host, REG_DSI_CLK_STATUS); | |
1536 | ||
1537 | if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { | |
1538 | dsi_write(msm_host, REG_DSI_CLK_STATUS, status); | |
1539 | msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; | |
1540 | } | |
1541 | } | |
1542 | ||
1543 | static void dsi_error(struct msm_dsi_host *msm_host) | |
1544 | { | |
1545 | /* disable dsi error interrupt */ | |
1546 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); | |
1547 | ||
1548 | dsi_clk_status(msm_host); | |
1549 | dsi_fifo_status(msm_host); | |
1550 | dsi_ack_err_status(msm_host); | |
1551 | dsi_timeout_status(msm_host); | |
1552 | dsi_status(msm_host); | |
1553 | dsi_dln0_phy_err(msm_host); | |
1554 | ||
1555 | queue_work(msm_host->workqueue, &msm_host->err_work); | |
1556 | } | |
1557 | ||
1558 | static irqreturn_t dsi_host_irq(int irq, void *ptr) | |
1559 | { | |
1560 | struct msm_dsi_host *msm_host = ptr; | |
1561 | u32 isr; | |
1562 | unsigned long flags; | |
1563 | ||
1564 | if (!msm_host->ctrl_base) | |
1565 | return IRQ_HANDLED; | |
1566 | ||
1567 | spin_lock_irqsave(&msm_host->intr_lock, flags); | |
1568 | isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); | |
1569 | dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); | |
1570 | spin_unlock_irqrestore(&msm_host->intr_lock, flags); | |
1571 | ||
1572 | DBG("isr=0x%x, id=%d", isr, msm_host->id); | |
1573 | ||
1574 | if (isr & DSI_IRQ_ERROR) | |
1575 | dsi_error(msm_host); | |
1576 | ||
1577 | if (isr & DSI_IRQ_VIDEO_DONE) | |
1578 | complete(&msm_host->video_comp); | |
1579 | ||
1580 | if (isr & DSI_IRQ_CMD_DMA_DONE) | |
1581 | complete(&msm_host->dma_comp); | |
1582 | ||
1583 | return IRQ_HANDLED; | |
1584 | } | |
1585 | ||
1586 | static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, | |
1587 | struct device *panel_device) | |
1588 | { | |
9590e69d UKK |
1589 | msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, |
1590 | "disp-enable", | |
1591 | GPIOD_OUT_LOW); | |
a689554b HL |
1592 | if (IS_ERR(msm_host->disp_en_gpio)) { |
1593 | DBG("cannot get disp-enable-gpios %ld", | |
1594 | PTR_ERR(msm_host->disp_en_gpio)); | |
9590e69d | 1595 | return PTR_ERR(msm_host->disp_en_gpio); |
a689554b HL |
1596 | } |
1597 | ||
60d05cb4 AT |
1598 | msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te", |
1599 | GPIOD_IN); | |
a689554b HL |
1600 | if (IS_ERR(msm_host->te_gpio)) { |
1601 | DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); | |
9590e69d | 1602 | return PTR_ERR(msm_host->te_gpio); |
a689554b HL |
1603 | } |
1604 | ||
1605 | return 0; | |
1606 | } | |
1607 | ||
1608 | static int dsi_host_attach(struct mipi_dsi_host *host, | |
1609 | struct mipi_dsi_device *dsi) | |
1610 | { | |
1611 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
1612 | int ret; | |
1613 | ||
26f7d1f4 AT |
1614 | if (dsi->lanes > msm_host->num_data_lanes) |
1615 | return -EINVAL; | |
1616 | ||
a689554b HL |
1617 | msm_host->channel = dsi->channel; |
1618 | msm_host->lanes = dsi->lanes; | |
1619 | msm_host->format = dsi->format; | |
1620 | msm_host->mode_flags = dsi->mode_flags; | |
1621 | ||
a689554b HL |
1622 | /* Some gpios defined in panel DT need to be controlled by host */ |
1623 | ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); | |
1624 | if (ret) | |
1625 | return ret; | |
1626 | ||
1627 | DBG("id=%d", msm_host->id); | |
1628 | if (msm_host->dev) | |
8d23ea40 | 1629 | queue_work(msm_host->workqueue, &msm_host->hpd_work); |
a689554b HL |
1630 | |
1631 | return 0; | |
1632 | } | |
1633 | ||
1634 | static int dsi_host_detach(struct mipi_dsi_host *host, | |
1635 | struct mipi_dsi_device *dsi) | |
1636 | { | |
1637 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
1638 | ||
a9ddac9c | 1639 | msm_host->device_node = NULL; |
a689554b HL |
1640 | |
1641 | DBG("id=%d", msm_host->id); | |
1642 | if (msm_host->dev) | |
8d23ea40 | 1643 | queue_work(msm_host->workqueue, &msm_host->hpd_work); |
a689554b HL |
1644 | |
1645 | return 0; | |
1646 | } | |
1647 | ||
1648 | static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, | |
1649 | const struct mipi_dsi_msg *msg) | |
1650 | { | |
1651 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
1652 | int ret; | |
1653 | ||
1654 | if (!msg || !msm_host->power_on) | |
1655 | return -EINVAL; | |
1656 | ||
1657 | mutex_lock(&msm_host->cmd_mutex); | |
1658 | ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); | |
1659 | mutex_unlock(&msm_host->cmd_mutex); | |
1660 | ||
1661 | return ret; | |
1662 | } | |
1663 | ||
8b6947a8 | 1664 | static const struct mipi_dsi_host_ops dsi_host_ops = { |
a689554b HL |
1665 | .attach = dsi_host_attach, |
1666 | .detach = dsi_host_detach, | |
1667 | .transfer = dsi_host_transfer, | |
1668 | }; | |
1669 | ||
26f7d1f4 AT |
1670 | /* |
1671 | * List of supported physical to logical lane mappings. | |
1672 | * For example, the 2nd entry represents the following mapping: | |
1673 | * | |
1674 | * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; | |
1675 | */ | |
1676 | static const int supported_data_lane_swaps[][4] = { | |
1677 | { 0, 1, 2, 3 }, | |
1678 | { 3, 0, 1, 2 }, | |
1679 | { 2, 3, 0, 1 }, | |
1680 | { 1, 2, 3, 0 }, | |
1681 | { 0, 3, 2, 1 }, | |
1682 | { 1, 0, 3, 2 }, | |
1683 | { 2, 1, 0, 3 }, | |
1684 | { 3, 2, 1, 0 }, | |
1685 | }; | |
1686 | ||
1687 | static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, | |
1688 | struct device_node *ep) | |
1689 | { | |
1690 | struct device *dev = &msm_host->pdev->dev; | |
1691 | struct property *prop; | |
1692 | u32 lane_map[4]; | |
1693 | int ret, i, len, num_lanes; | |
1694 | ||
60282cea | 1695 | prop = of_find_property(ep, "data-lanes", &len); |
26f7d1f4 | 1696 | if (!prop) { |
6a41da17 | 1697 | DRM_DEV_DEBUG(dev, |
a1b1a4f7 | 1698 | "failed to find data lane mapping, using default\n"); |
796984f6 PC |
1699 | /* Set the number of date lanes to 4 by default. */ |
1700 | msm_host->num_data_lanes = 4; | |
a1b1a4f7 | 1701 | return 0; |
26f7d1f4 AT |
1702 | } |
1703 | ||
1704 | num_lanes = len / sizeof(u32); | |
1705 | ||
1706 | if (num_lanes < 1 || num_lanes > 4) { | |
6a41da17 | 1707 | DRM_DEV_ERROR(dev, "bad number of data lanes\n"); |
26f7d1f4 AT |
1708 | return -EINVAL; |
1709 | } | |
1710 | ||
1711 | msm_host->num_data_lanes = num_lanes; | |
1712 | ||
60282cea | 1713 | ret = of_property_read_u32_array(ep, "data-lanes", lane_map, |
26f7d1f4 AT |
1714 | num_lanes); |
1715 | if (ret) { | |
6a41da17 | 1716 | DRM_DEV_ERROR(dev, "failed to read lane data\n"); |
26f7d1f4 AT |
1717 | return ret; |
1718 | } | |
1719 | ||
1720 | /* | |
1721 | * compare DT specified physical-logical lane mappings with the ones | |
1722 | * supported by hardware | |
1723 | */ | |
1724 | for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { | |
1725 | const int *swap = supported_data_lane_swaps[i]; | |
1726 | int j; | |
1727 | ||
60282cea AT |
1728 | /* |
1729 | * the data-lanes array we get from DT has a logical->physical | |
1730 | * mapping. The "data lane swap" register field represents | |
1731 | * supported configurations in a physical->logical mapping. | |
1732 | * Translate the DT mapping to what we understand and find a | |
1733 | * configuration that works. | |
1734 | */ | |
26f7d1f4 | 1735 | for (j = 0; j < num_lanes; j++) { |
60282cea | 1736 | if (lane_map[j] < 0 || lane_map[j] > 3) |
6a41da17 | 1737 | DRM_DEV_ERROR(dev, "bad physical lane entry %u\n", |
60282cea AT |
1738 | lane_map[j]); |
1739 | ||
1740 | if (swap[lane_map[j]] != j) | |
26f7d1f4 AT |
1741 | break; |
1742 | } | |
1743 | ||
1744 | if (j == num_lanes) { | |
1745 | msm_host->dlane_swap = i; | |
1746 | return 0; | |
1747 | } | |
1748 | } | |
1749 | ||
1750 | return -EINVAL; | |
1751 | } | |
1752 | ||
f7009d26 AT |
1753 | static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) |
1754 | { | |
1755 | struct device *dev = &msm_host->pdev->dev; | |
1756 | struct device_node *np = dev->of_node; | |
a9ddac9c | 1757 | struct device_node *endpoint, *device_node; |
a1b1a4f7 | 1758 | int ret = 0; |
f7009d26 | 1759 | |
f7009d26 | 1760 | /* |
b9ac76f6 AT |
1761 | * Get the endpoint of the output port of the DSI host. In our case, |
1762 | * this is mapped to port number with reg = 1. Don't return an error if | |
1763 | * the remote endpoint isn't defined. It's possible that there is | |
1764 | * nothing connected to the dsi output. | |
f7009d26 | 1765 | */ |
b9ac76f6 | 1766 | endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); |
f7009d26 | 1767 | if (!endpoint) { |
6a41da17 | 1768 | DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__); |
f7009d26 AT |
1769 | return 0; |
1770 | } | |
1771 | ||
26f7d1f4 AT |
1772 | ret = dsi_host_parse_lane_data(msm_host, endpoint); |
1773 | if (ret) { | |
6a41da17 | 1774 | DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", |
26f7d1f4 | 1775 | __func__, ret); |
feb085ec | 1776 | ret = -EINVAL; |
26f7d1f4 AT |
1777 | goto err; |
1778 | } | |
1779 | ||
f7009d26 | 1780 | /* Get panel node from the output port's endpoint data */ |
86418f90 | 1781 | device_node = of_graph_get_remote_node(np, 1, 0); |
a9ddac9c | 1782 | if (!device_node) { |
6a41da17 | 1783 | DRM_DEV_DEBUG(dev, "%s: no valid device\n", __func__); |
feb085ec | 1784 | ret = -ENODEV; |
26f7d1f4 | 1785 | goto err; |
f7009d26 AT |
1786 | } |
1787 | ||
a9ddac9c | 1788 | msm_host->device_node = device_node; |
f7009d26 | 1789 | |
0c7df47f AT |
1790 | if (of_property_read_bool(np, "syscon-sfpb")) { |
1791 | msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, | |
1792 | "syscon-sfpb"); | |
1793 | if (IS_ERR(msm_host->sfpb)) { | |
6a41da17 | 1794 | DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n", |
0c7df47f | 1795 | __func__); |
26f7d1f4 | 1796 | ret = PTR_ERR(msm_host->sfpb); |
0c7df47f AT |
1797 | } |
1798 | } | |
1799 | ||
26f7d1f4 AT |
1800 | of_node_put(device_node); |
1801 | ||
1802 | err: | |
1803 | of_node_put(endpoint); | |
1804 | ||
1805 | return ret; | |
f7009d26 AT |
1806 | } |
1807 | ||
32280d66 AT |
1808 | static int dsi_host_get_id(struct msm_dsi_host *msm_host) |
1809 | { | |
1810 | struct platform_device *pdev = msm_host->pdev; | |
1811 | const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; | |
1812 | struct resource *res; | |
1813 | int i; | |
1814 | ||
1815 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); | |
1816 | if (!res) | |
1817 | return -EINVAL; | |
1818 | ||
1819 | for (i = 0; i < cfg->num_dsi; i++) { | |
1820 | if (cfg->io_start[i] == res->start) | |
1821 | return i; | |
1822 | } | |
1823 | ||
1824 | return -EINVAL; | |
1825 | } | |
1826 | ||
a689554b HL |
1827 | int msm_dsi_host_init(struct msm_dsi *msm_dsi) |
1828 | { | |
1829 | struct msm_dsi_host *msm_host = NULL; | |
1830 | struct platform_device *pdev = msm_dsi->pdev; | |
1831 | int ret; | |
1832 | ||
1833 | msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); | |
1834 | if (!msm_host) { | |
a689554b HL |
1835 | ret = -ENOMEM; |
1836 | goto fail; | |
1837 | } | |
1838 | ||
f7009d26 | 1839 | msm_host->pdev = pdev; |
f54ca1a0 | 1840 | msm_dsi->host = &msm_host->base; |
f7009d26 AT |
1841 | |
1842 | ret = dsi_host_parse_dt(msm_host); | |
a689554b | 1843 | if (ret) { |
f7009d26 | 1844 | pr_err("%s: failed to parse dt\n", __func__); |
a689554b HL |
1845 | goto fail; |
1846 | } | |
a689554b | 1847 | |
bac2c6a6 | 1848 | msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", "DSI CTRL", &msm_host->ctrl_size); |
a689554b HL |
1849 | if (IS_ERR(msm_host->ctrl_base)) { |
1850 | pr_err("%s: unable to map Dsi ctrl base\n", __func__); | |
1851 | ret = PTR_ERR(msm_host->ctrl_base); | |
1852 | goto fail; | |
1853 | } | |
1854 | ||
f6be1121 AT |
1855 | pm_runtime_enable(&pdev->dev); |
1856 | ||
d248b61f HL |
1857 | msm_host->cfg_hnd = dsi_get_config(msm_host); |
1858 | if (!msm_host->cfg_hnd) { | |
a689554b HL |
1859 | ret = -EINVAL; |
1860 | pr_err("%s: get config failed\n", __func__); | |
1861 | goto fail; | |
1862 | } | |
1863 | ||
32280d66 AT |
1864 | msm_host->id = dsi_host_get_id(msm_host); |
1865 | if (msm_host->id < 0) { | |
1866 | ret = msm_host->id; | |
1867 | pr_err("%s: unable to identify DSI host index\n", __func__); | |
1868 | goto fail; | |
1869 | } | |
1870 | ||
d248b61f HL |
1871 | /* fixup base address by io offset */ |
1872 | msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset; | |
1873 | ||
a689554b HL |
1874 | ret = dsi_regulator_init(msm_host); |
1875 | if (ret) { | |
1876 | pr_err("%s: regulator init failed\n", __func__); | |
1877 | goto fail; | |
1878 | } | |
1879 | ||
31c92767 AT |
1880 | ret = dsi_clk_init(msm_host); |
1881 | if (ret) { | |
1882 | pr_err("%s: unable to initialize dsi clks\n", __func__); | |
1883 | goto fail; | |
1884 | } | |
1885 | ||
a689554b HL |
1886 | msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); |
1887 | if (!msm_host->rx_buf) { | |
cd57b48a | 1888 | ret = -ENOMEM; |
a689554b HL |
1889 | pr_err("%s: alloc rx temp buf failed\n", __func__); |
1890 | goto fail; | |
1891 | } | |
1892 | ||
11120e93 YL |
1893 | ret = devm_pm_opp_set_clkname(&pdev->dev, "byte"); |
1894 | if (ret) | |
1895 | return ret; | |
32d3e0fe | 1896 | /* OPP table is optional */ |
11120e93 | 1897 | ret = devm_pm_opp_of_add_table(&pdev->dev); |
6400a8e8 | 1898 | if (ret && ret != -ENODEV) { |
32d3e0fe | 1899 | dev_err(&pdev->dev, "invalid OPP table in device tree\n"); |
32d3e0fe RN |
1900 | return ret; |
1901 | } | |
1902 | ||
a249caba DB |
1903 | msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); |
1904 | if (msm_host->irq < 0) { | |
1905 | ret = msm_host->irq; | |
1906 | dev_err(&pdev->dev, "failed to get irq: %d\n", ret); | |
1907 | return ret; | |
1908 | } | |
1909 | ||
1910 | /* do not autoenable, will be enabled later */ | |
1911 | ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq, | |
5ea873cd | 1912 | IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN, |
a249caba DB |
1913 | "dsi_isr", msm_host); |
1914 | if (ret < 0) { | |
1915 | dev_err(&pdev->dev, "failed to request IRQ%u: %d\n", | |
1916 | msm_host->irq, ret); | |
1917 | return ret; | |
1918 | } | |
1919 | ||
a689554b HL |
1920 | init_completion(&msm_host->dma_comp); |
1921 | init_completion(&msm_host->video_comp); | |
1922 | mutex_init(&msm_host->dev_mutex); | |
1923 | mutex_init(&msm_host->cmd_mutex); | |
a689554b HL |
1924 | spin_lock_init(&msm_host->intr_lock); |
1925 | ||
1926 | /* setup workqueue */ | |
1927 | msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); | |
1928 | INIT_WORK(&msm_host->err_work, dsi_err_worker); | |
8d23ea40 | 1929 | INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker); |
a689554b | 1930 | |
a689554b HL |
1931 | msm_dsi->id = msm_host->id; |
1932 | ||
1933 | DBG("Dsi Host %d initialized", msm_host->id); | |
1934 | return 0; | |
1935 | ||
1936 | fail: | |
1937 | return ret; | |
1938 | } | |
1939 | ||
1940 | void msm_dsi_host_destroy(struct mipi_dsi_host *host) | |
1941 | { | |
1942 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
1943 | ||
1944 | DBG(""); | |
1945 | dsi_tx_buf_free(msm_host); | |
1946 | if (msm_host->workqueue) { | |
1947 | flush_workqueue(msm_host->workqueue); | |
1948 | destroy_workqueue(msm_host->workqueue); | |
1949 | msm_host->workqueue = NULL; | |
1950 | } | |
1951 | ||
a689554b HL |
1952 | mutex_destroy(&msm_host->cmd_mutex); |
1953 | mutex_destroy(&msm_host->dev_mutex); | |
f6be1121 AT |
1954 | |
1955 | pm_runtime_disable(&msm_host->pdev->dev); | |
a689554b HL |
1956 | } |
1957 | ||
1958 | int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, | |
1959 | struct drm_device *dev) | |
1960 | { | |
1961 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
8f7ca540 | 1962 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
1963 | int ret; |
1964 | ||
a689554b | 1965 | msm_host->dev = dev; |
8f7ca540 | 1966 | ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); |
a689554b HL |
1967 | if (ret) { |
1968 | pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); | |
1969 | return ret; | |
1970 | } | |
1971 | ||
1972 | return 0; | |
1973 | } | |
1974 | ||
1975 | int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer) | |
1976 | { | |
1977 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
a689554b HL |
1978 | int ret; |
1979 | ||
1980 | /* Register mipi dsi host */ | |
1981 | if (!msm_host->registered) { | |
1982 | host->dev = &msm_host->pdev->dev; | |
1983 | host->ops = &dsi_host_ops; | |
1984 | ret = mipi_dsi_host_register(host); | |
1985 | if (ret) | |
1986 | return ret; | |
1987 | ||
1988 | msm_host->registered = true; | |
1989 | ||
1990 | /* If the panel driver has not been probed after host register, | |
1991 | * we should defer the host's probe. | |
1992 | * It makes sure panel is connected when fbcon detects | |
1993 | * connector status and gets the proper display mode to | |
1994 | * create framebuffer. | |
f7009d26 AT |
1995 | * Don't try to defer if there is nothing connected to the dsi |
1996 | * output | |
a689554b | 1997 | */ |
a9ddac9c | 1998 | if (check_defer && msm_host->device_node) { |
5fa8e4a2 | 1999 | if (IS_ERR(of_drm_find_panel(msm_host->device_node))) |
c118e290 AT |
2000 | if (!of_drm_find_bridge(msm_host->device_node)) |
2001 | return -EPROBE_DEFER; | |
a689554b HL |
2002 | } |
2003 | } | |
2004 | ||
2005 | return 0; | |
2006 | } | |
2007 | ||
2008 | void msm_dsi_host_unregister(struct mipi_dsi_host *host) | |
2009 | { | |
2010 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2011 | ||
2012 | if (msm_host->registered) { | |
2013 | mipi_dsi_host_unregister(host); | |
2014 | host->dev = NULL; | |
2015 | host->ops = NULL; | |
2016 | msm_host->registered = false; | |
2017 | } | |
2018 | } | |
2019 | ||
2020 | int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, | |
2021 | const struct mipi_dsi_msg *msg) | |
2022 | { | |
2023 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
8f7ca540 | 2024 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
2025 | |
2026 | /* TODO: make sure dsi_cmd_mdp is idle. | |
2027 | * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME | |
2028 | * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. | |
2029 | * How to handle the old versions? Wait for mdp cmd done? | |
2030 | */ | |
2031 | ||
2032 | /* | |
2033 | * mdss interrupt is generated in mdp core clock domain | |
2034 | * mdp clock need to be enabled to receive dsi interrupt | |
2035 | */ | |
f6be1121 | 2036 | pm_runtime_get_sync(&msm_host->pdev->dev); |
6b16f05a | 2037 | cfg_hnd->ops->link_clk_set_rate(msm_host); |
8f7ca540 | 2038 | cfg_hnd->ops->link_clk_enable(msm_host); |
a689554b HL |
2039 | |
2040 | /* TODO: vote for bus bandwidth */ | |
2041 | ||
2042 | if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) | |
2043 | dsi_set_tx_power_mode(0, msm_host); | |
2044 | ||
2045 | msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); | |
2046 | dsi_write(msm_host, REG_DSI_CTRL, | |
2047 | msm_host->dma_cmd_ctrl_restore | | |
2048 | DSI_CTRL_CMD_MODE_EN | | |
2049 | DSI_CTRL_ENABLE); | |
2050 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); | |
2051 | ||
2052 | return 0; | |
2053 | } | |
2054 | ||
2055 | void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, | |
2056 | const struct mipi_dsi_msg *msg) | |
2057 | { | |
2058 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
8f7ca540 | 2059 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
2060 | |
2061 | dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); | |
2062 | dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); | |
2063 | ||
2064 | if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) | |
2065 | dsi_set_tx_power_mode(1, msm_host); | |
2066 | ||
2067 | /* TODO: unvote for bus bandwidth */ | |
2068 | ||
8f7ca540 | 2069 | cfg_hnd->ops->link_clk_disable(msm_host); |
f6be1121 | 2070 | pm_runtime_put_autosuspend(&msm_host->pdev->dev); |
a689554b HL |
2071 | } |
2072 | ||
2073 | int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, | |
2074 | const struct mipi_dsi_msg *msg) | |
2075 | { | |
2076 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2077 | ||
2078 | return dsi_cmds2buf_tx(msm_host, msg); | |
2079 | } | |
2080 | ||
2081 | int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, | |
2082 | const struct mipi_dsi_msg *msg) | |
2083 | { | |
2084 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
d248b61f | 2085 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
2086 | int data_byte, rx_byte, dlen, end; |
2087 | int short_response, diff, pkt_size, ret = 0; | |
2088 | char cmd; | |
2089 | int rlen = msg->rx_len; | |
2090 | u8 *buf; | |
2091 | ||
2092 | if (rlen <= 2) { | |
2093 | short_response = 1; | |
2094 | pkt_size = rlen; | |
2095 | rx_byte = 4; | |
2096 | } else { | |
2097 | short_response = 0; | |
2098 | data_byte = 10; /* first read */ | |
2099 | if (rlen < data_byte) | |
2100 | pkt_size = rlen; | |
2101 | else | |
2102 | pkt_size = data_byte; | |
2103 | rx_byte = data_byte + 6; /* 4 header + 2 crc */ | |
2104 | } | |
2105 | ||
2106 | buf = msm_host->rx_buf; | |
2107 | end = 0; | |
2108 | while (!end) { | |
2109 | u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; | |
2110 | struct mipi_dsi_msg max_pkt_size_msg = { | |
2111 | .channel = msg->channel, | |
2112 | .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, | |
2113 | .tx_len = 2, | |
2114 | .tx_buf = tx, | |
2115 | }; | |
2116 | ||
2117 | DBG("rlen=%d pkt_size=%d rx_byte=%d", | |
2118 | rlen, pkt_size, rx_byte); | |
2119 | ||
2120 | ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); | |
2121 | if (ret < 2) { | |
2122 | pr_err("%s: Set max pkt size failed, %d\n", | |
2123 | __func__, ret); | |
2124 | return -EINVAL; | |
2125 | } | |
2126 | ||
d248b61f HL |
2127 | if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && |
2128 | (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { | |
a689554b HL |
2129 | /* Clear the RDBK_DATA registers */ |
2130 | dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, | |
2131 | DSI_RDBK_DATA_CTRL_CLR); | |
2132 | wmb(); /* make sure the RDBK registers are cleared */ | |
2133 | dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); | |
2134 | wmb(); /* release cleared status before transfer */ | |
2135 | } | |
2136 | ||
2137 | ret = dsi_cmds2buf_tx(msm_host, msg); | |
2138 | if (ret < msg->tx_len) { | |
2139 | pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); | |
2140 | return ret; | |
2141 | } | |
2142 | ||
2143 | /* | |
2144 | * once cmd_dma_done interrupt received, | |
2145 | * return data from client is ready and stored | |
2146 | * at RDBK_DATA register already | |
2147 | * since rx fifo is 16 bytes, dcs header is kept at first loop, | |
2148 | * after that dcs header lost during shift into registers | |
2149 | */ | |
2150 | dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); | |
2151 | ||
2152 | if (dlen <= 0) | |
2153 | return 0; | |
2154 | ||
2155 | if (short_response) | |
2156 | break; | |
2157 | ||
2158 | if (rlen <= data_byte) { | |
2159 | diff = data_byte - rlen; | |
2160 | end = 1; | |
2161 | } else { | |
2162 | diff = 0; | |
2163 | rlen -= data_byte; | |
2164 | } | |
2165 | ||
2166 | if (!end) { | |
2167 | dlen -= 2; /* 2 crc */ | |
2168 | dlen -= diff; | |
2169 | buf += dlen; /* next start position */ | |
2170 | data_byte = 14; /* NOT first read */ | |
2171 | if (rlen < data_byte) | |
2172 | pkt_size += rlen; | |
2173 | else | |
2174 | pkt_size += data_byte; | |
2175 | DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); | |
2176 | } | |
2177 | } | |
2178 | ||
2179 | /* | |
2180 | * For single Long read, if the requested rlen < 10, | |
2181 | * we need to shift the start position of rx | |
2182 | * data buffer to skip the bytes which are not | |
2183 | * updated. | |
2184 | */ | |
2185 | if (pkt_size < 10 && !short_response) | |
2186 | buf = msm_host->rx_buf + (10 - rlen); | |
2187 | else | |
2188 | buf = msm_host->rx_buf; | |
2189 | ||
2190 | cmd = buf[0]; | |
2191 | switch (cmd) { | |
2192 | case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: | |
2193 | pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); | |
2194 | ret = 0; | |
651ad3f5 | 2195 | break; |
a689554b HL |
2196 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: |
2197 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: | |
2198 | ret = dsi_short_read1_resp(buf, msg); | |
2199 | break; | |
2200 | case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: | |
2201 | case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: | |
2202 | ret = dsi_short_read2_resp(buf, msg); | |
2203 | break; | |
2204 | case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: | |
2205 | case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: | |
2206 | ret = dsi_long_read_resp(buf, msg); | |
2207 | break; | |
2208 | default: | |
2209 | pr_warn("%s:Invalid response cmd\n", __func__); | |
2210 | ret = 0; | |
2211 | } | |
2212 | ||
2213 | return ret; | |
2214 | } | |
2215 | ||
4ff9d4cb AT |
2216 | void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, |
2217 | u32 len) | |
a689554b HL |
2218 | { |
2219 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2220 | ||
4ff9d4cb | 2221 | dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); |
a689554b HL |
2222 | dsi_write(msm_host, REG_DSI_DMA_LEN, len); |
2223 | dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); | |
2224 | ||
2225 | /* Make sure trigger happens */ | |
2226 | wmb(); | |
2227 | } | |
2228 | ||
9d32c498 | 2229 | int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, |
5d134596 | 2230 | struct msm_dsi_phy *src_phy) |
9d32c498 HL |
2231 | { |
2232 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2233 | struct clk *byte_clk_provider, *pixel_clk_provider; | |
2234 | int ret; | |
2235 | ||
5ac17838 JM |
2236 | msm_host->cphy_mode = src_phy->cphy_mode; |
2237 | ||
5d134596 | 2238 | ret = msm_dsi_phy_get_clk_provider(src_phy, |
9d32c498 HL |
2239 | &byte_clk_provider, &pixel_clk_provider); |
2240 | if (ret) { | |
2241 | pr_info("%s: can't get provider from pll, don't set parent\n", | |
2242 | __func__); | |
2243 | return 0; | |
2244 | } | |
2245 | ||
2246 | ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider); | |
2247 | if (ret) { | |
2248 | pr_err("%s: can't set parent to byte_clk_src. ret=%d\n", | |
2249 | __func__, ret); | |
2250 | goto exit; | |
2251 | } | |
2252 | ||
2253 | ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider); | |
2254 | if (ret) { | |
2255 | pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n", | |
2256 | __func__, ret); | |
2257 | goto exit; | |
2258 | } | |
2259 | ||
8f7ca540 | 2260 | if (msm_host->dsi_clk_src) { |
4bfa9748 AT |
2261 | ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider); |
2262 | if (ret) { | |
2263 | pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n", | |
2264 | __func__, ret); | |
2265 | goto exit; | |
2266 | } | |
8f7ca540 | 2267 | } |
4bfa9748 | 2268 | |
8f7ca540 | 2269 | if (msm_host->esc_clk_src) { |
4bfa9748 AT |
2270 | ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider); |
2271 | if (ret) { | |
2272 | pr_err("%s: can't set parent to esc_clk_src. ret=%d\n", | |
2273 | __func__, ret); | |
2274 | goto exit; | |
2275 | } | |
2276 | } | |
2277 | ||
9d32c498 HL |
2278 | exit: |
2279 | return ret; | |
2280 | } | |
2281 | ||
34d9545b AT |
2282 | void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) |
2283 | { | |
2284 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2285 | ||
2286 | DBG(""); | |
2287 | dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); | |
2288 | /* Make sure fully reset */ | |
2289 | wmb(); | |
2290 | udelay(1000); | |
2291 | dsi_write(msm_host, REG_DSI_PHY_RESET, 0); | |
2292 | udelay(100); | |
2293 | } | |
2294 | ||
b62aa70a | 2295 | void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, |
ed9976a0 | 2296 | struct msm_dsi_phy_clk_request *clk_req, |
6183606d | 2297 | bool is_bonded_dsi) |
b62aa70a HL |
2298 | { |
2299 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
8f7ca540 | 2300 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
d4cea38e AT |
2301 | int ret; |
2302 | ||
6183606d | 2303 | ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi); |
d4cea38e AT |
2304 | if (ret) { |
2305 | pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); | |
2306 | return; | |
2307 | } | |
b62aa70a | 2308 | |
5ac17838 JM |
2309 | /* CPHY transmits 16 bits over 7 clock cycles |
2310 | * "byte_clk" is in units of 16-bits (see dsi_calc_pclk), | |
2311 | * so multiply by 7 to get the "bitclk rate" | |
2312 | */ | |
2313 | if (msm_host->cphy_mode) | |
2314 | clk_req->bitclk_rate = msm_host->byte_clk_rate * 7; | |
2315 | else | |
2316 | clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; | |
b62aa70a HL |
2317 | clk_req->escclk_rate = msm_host->esc_clk_rate; |
2318 | } | |
2319 | ||
a249caba DB |
2320 | void msm_dsi_host_enable_irq(struct mipi_dsi_host *host) |
2321 | { | |
2322 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2323 | ||
2324 | enable_irq(msm_host->irq); | |
2325 | } | |
2326 | ||
2327 | void msm_dsi_host_disable_irq(struct mipi_dsi_host *host) | |
2328 | { | |
2329 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2330 | ||
2331 | disable_irq(msm_host->irq); | |
2332 | } | |
2333 | ||
a689554b HL |
2334 | int msm_dsi_host_enable(struct mipi_dsi_host *host) |
2335 | { | |
2336 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2337 | ||
2338 | dsi_op_mode_config(msm_host, | |
2339 | !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); | |
2340 | ||
2341 | /* TODO: clock should be turned off for command mode, | |
2342 | * and only turned on before MDP START. | |
2343 | * This part of code should be enabled once mdp driver support it. | |
2344 | */ | |
f54ca1a0 AT |
2345 | /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { |
2346 | * dsi_link_clk_disable(msm_host); | |
2347 | * pm_runtime_put_autosuspend(&msm_host->pdev->dev); | |
2348 | * } | |
2349 | */ | |
9c5638d7 | 2350 | msm_host->enabled = true; |
a689554b HL |
2351 | return 0; |
2352 | } | |
2353 | ||
2354 | int msm_dsi_host_disable(struct mipi_dsi_host *host) | |
2355 | { | |
2356 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2357 | ||
9c5638d7 | 2358 | msm_host->enabled = false; |
a689554b HL |
2359 | dsi_op_mode_config(msm_host, |
2360 | !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); | |
2361 | ||
2362 | /* Since we have disabled INTF, the video engine won't stop so that | |
2363 | * the cmd engine will be blocked. | |
2364 | * Reset to disable video engine so that we can send off cmd. | |
2365 | */ | |
2366 | dsi_sw_reset(msm_host); | |
2367 | ||
2368 | return 0; | |
2369 | } | |
2370 | ||
0c7df47f AT |
2371 | static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) |
2372 | { | |
2373 | enum sfpb_ahb_arb_master_port_en en; | |
2374 | ||
2375 | if (!msm_host->sfpb) | |
2376 | return; | |
2377 | ||
2378 | en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; | |
2379 | ||
2380 | regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, | |
2381 | SFPB_GPREG_MASTER_PORT_EN__MASK, | |
2382 | SFPB_GPREG_MASTER_PORT_EN(en)); | |
2383 | } | |
2384 | ||
b62aa70a | 2385 | int msm_dsi_host_power_on(struct mipi_dsi_host *host, |
ed9976a0 | 2386 | struct msm_dsi_phy_shared_timings *phy_shared_timings, |
858c595a | 2387 | bool is_bonded_dsi, struct msm_dsi_phy *phy) |
a689554b HL |
2388 | { |
2389 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
8f7ca540 | 2390 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
2391 | int ret = 0; |
2392 | ||
2393 | mutex_lock(&msm_host->dev_mutex); | |
2394 | if (msm_host->power_on) { | |
2395 | DBG("dsi host already on"); | |
2396 | goto unlock_ret; | |
2397 | } | |
2398 | ||
0c7df47f AT |
2399 | msm_dsi_sfpb_config(msm_host, true); |
2400 | ||
a689554b HL |
2401 | ret = dsi_host_regulator_enable(msm_host); |
2402 | if (ret) { | |
2403 | pr_err("%s:Failed to enable vregs.ret=%d\n", | |
2404 | __func__, ret); | |
2405 | goto unlock_ret; | |
2406 | } | |
2407 | ||
f6be1121 | 2408 | pm_runtime_get_sync(&msm_host->pdev->dev); |
6b16f05a RC |
2409 | ret = cfg_hnd->ops->link_clk_set_rate(msm_host); |
2410 | if (!ret) | |
2411 | ret = cfg_hnd->ops->link_clk_enable(msm_host); | |
a689554b | 2412 | if (ret) { |
f54ca1a0 AT |
2413 | pr_err("%s: failed to enable link clocks. ret=%d\n", |
2414 | __func__, ret); | |
a689554b HL |
2415 | goto fail_disable_reg; |
2416 | } | |
2417 | ||
ab8909b0 HL |
2418 | ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); |
2419 | if (ret) { | |
2420 | pr_err("%s: failed to set pinctrl default state, %d\n", | |
2421 | __func__, ret); | |
2422 | goto fail_disable_clk; | |
2423 | } | |
2424 | ||
6183606d | 2425 | dsi_timing_setup(msm_host, is_bonded_dsi); |
a689554b | 2426 | dsi_sw_reset(msm_host); |
858c595a | 2427 | dsi_ctrl_config(msm_host, true, phy_shared_timings, phy); |
a689554b HL |
2428 | |
2429 | if (msm_host->disp_en_gpio) | |
2430 | gpiod_set_value(msm_host->disp_en_gpio, 1); | |
2431 | ||
2432 | msm_host->power_on = true; | |
2433 | mutex_unlock(&msm_host->dev_mutex); | |
2434 | ||
2435 | return 0; | |
2436 | ||
ab8909b0 | 2437 | fail_disable_clk: |
8f7ca540 | 2438 | cfg_hnd->ops->link_clk_disable(msm_host); |
f54ca1a0 | 2439 | pm_runtime_put_autosuspend(&msm_host->pdev->dev); |
a689554b HL |
2440 | fail_disable_reg: |
2441 | dsi_host_regulator_disable(msm_host); | |
2442 | unlock_ret: | |
2443 | mutex_unlock(&msm_host->dev_mutex); | |
2444 | return ret; | |
2445 | } | |
2446 | ||
2447 | int msm_dsi_host_power_off(struct mipi_dsi_host *host) | |
2448 | { | |
2449 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
8f7ca540 | 2450 | const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; |
a689554b HL |
2451 | |
2452 | mutex_lock(&msm_host->dev_mutex); | |
2453 | if (!msm_host->power_on) { | |
2454 | DBG("dsi host already off"); | |
2455 | goto unlock_ret; | |
2456 | } | |
2457 | ||
858c595a | 2458 | dsi_ctrl_config(msm_host, false, NULL, NULL); |
a689554b HL |
2459 | |
2460 | if (msm_host->disp_en_gpio) | |
2461 | gpiod_set_value(msm_host->disp_en_gpio, 0); | |
2462 | ||
ab8909b0 HL |
2463 | pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); |
2464 | ||
8f7ca540 | 2465 | cfg_hnd->ops->link_clk_disable(msm_host); |
f6be1121 | 2466 | pm_runtime_put_autosuspend(&msm_host->pdev->dev); |
a689554b HL |
2467 | |
2468 | dsi_host_regulator_disable(msm_host); | |
2469 | ||
0c7df47f AT |
2470 | msm_dsi_sfpb_config(msm_host, false); |
2471 | ||
a689554b HL |
2472 | DBG("-"); |
2473 | ||
2474 | msm_host->power_on = false; | |
2475 | ||
2476 | unlock_ret: | |
2477 | mutex_unlock(&msm_host->dev_mutex); | |
2478 | return 0; | |
2479 | } | |
2480 | ||
2481 | int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, | |
63f8f3ba | 2482 | const struct drm_display_mode *mode) |
a689554b HL |
2483 | { |
2484 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2485 | ||
2486 | if (msm_host->mode) { | |
2487 | drm_mode_destroy(msm_host->dev, msm_host->mode); | |
2488 | msm_host->mode = NULL; | |
2489 | } | |
2490 | ||
2491 | msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); | |
2abe1f25 | 2492 | if (!msm_host->mode) { |
a689554b | 2493 | pr_err("%s: cannot duplicate mode\n", __func__); |
2abe1f25 | 2494 | return -ENOMEM; |
a689554b HL |
2495 | } |
2496 | ||
2497 | return 0; | |
2498 | } | |
2499 | ||
e3a91f89 | 2500 | struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host) |
a689554b | 2501 | { |
e3a91f89 SP |
2502 | return of_drm_find_panel(to_msm_dsi_host(host)->device_node); |
2503 | } | |
a689554b | 2504 | |
e3a91f89 SP |
2505 | unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) |
2506 | { | |
2507 | return to_msm_dsi_host(host)->mode_flags; | |
a689554b HL |
2508 | } |
2509 | ||
c118e290 AT |
2510 | struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host) |
2511 | { | |
2512 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2513 | ||
2514 | return of_drm_find_bridge(msm_host->device_node); | |
2515 | } | |
98659487 | 2516 | |
eb9d6c7e | 2517 | void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host) |
9d30a4bc AK |
2518 | { |
2519 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
9d30a4bc AK |
2520 | |
2521 | pm_runtime_get_sync(&msm_host->pdev->dev); | |
2522 | ||
bac2c6a6 | 2523 | msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size, |
9d30a4bc AK |
2524 | msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id); |
2525 | ||
2526 | pm_runtime_put_sync(&msm_host->pdev->dev); | |
2527 | } | |
5e2a72d4 AK |
2528 | |
2529 | static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host) | |
2530 | { | |
2531 | u32 reg; | |
2532 | ||
2533 | reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); | |
2534 | ||
2535 | dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff); | |
2536 | /* draw checkered rectangle pattern */ | |
2537 | dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL, | |
2538 | DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN); | |
2539 | /* use 24-bit RGB test pttern */ | |
2540 | dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG, | |
2541 | DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) | | |
2542 | DSI_TPG_VIDEO_CONFIG_RGB); | |
2543 | ||
2544 | reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN); | |
2545 | dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); | |
2546 | ||
2547 | DBG("Video test pattern setup done\n"); | |
2548 | } | |
2549 | ||
2550 | static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host) | |
2551 | { | |
2552 | u32 reg; | |
2553 | ||
2554 | reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); | |
2555 | ||
2556 | /* initial value for test pattern */ | |
2557 | dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff); | |
2558 | ||
2559 | reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN); | |
2560 | ||
2561 | dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg); | |
2562 | /* draw checkered rectangle pattern */ | |
2563 | dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2, | |
2564 | DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN); | |
2565 | ||
2566 | DBG("Cmd test pattern setup done\n"); | |
2567 | } | |
2568 | ||
2569 | void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host) | |
2570 | { | |
2571 | struct msm_dsi_host *msm_host = to_msm_dsi_host(host); | |
2572 | bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO); | |
2573 | u32 reg; | |
2574 | ||
2575 | if (is_video_mode) | |
2576 | msm_dsi_host_video_test_pattern_setup(msm_host); | |
2577 | else | |
2578 | msm_dsi_host_cmd_test_pattern_setup(msm_host); | |
2579 | ||
2580 | reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL); | |
2581 | /* enable the test pattern generator */ | |
2582 | dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN)); | |
2583 | ||
2584 | /* for command mode need to trigger one frame from tpg */ | |
2585 | if (!is_video_mode) | |
2586 | dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER, | |
2587 | DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER); | |
2588 | } |