]> git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blame - drivers/gpu/drm/msm/dsi/dsi_phy.c
projects / mirror_ubuntu-zesty-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/msm/dsi: Add support for msm8x94
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / msm / dsi / dsi_phy.c
CommitLineData
a689554b
HL		 1/*
2 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
ec31abf6
HL		 14#include <linux/platform_device.h>
15#include <linux/regulator/consumer.h>
16
a689554b
HL		 17#include "dsi.h"
18#include "dsi.xml.h"
19
20#define dsi_phy_read(offset) msm_readl((offset))
21#define dsi_phy_write(offset, data) msm_writel((data), (offset))
22
ec31abf6 23struct dsi_phy_ops {
13351cd1 24 int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
ec31abf6
HL		 25 const unsigned long bit_rate, const unsigned long esc_rate);
26 int (*disable)(struct msm_dsi_phy *phy);
27};
28
29struct dsi_phy_cfg {
30 enum msm_dsi_phy_type type;
31 struct dsi_reg_config reg_cfg;
32 struct dsi_phy_ops ops;
13351cd1
HL		 33
34 /* Each cell {phy_id, pll_id} of the truth table indicates
35 * if the source PLL is on the right side of the PHY.
36 * Fill default H/W values in illegal cells, eg. cell {0, 1}.
37 */
38 bool src_pll_truthtable[DSI_MAX][DSI_MAX];
ec31abf6
HL		 39};
40
a689554b
HL		 41struct dsi_dphy_timing {
42 u32 clk_pre;
43 u32 clk_post;
44 u32 clk_zero;
45 u32 clk_trail;
46 u32 clk_prepare;
47 u32 hs_exit;
48 u32 hs_zero;
49 u32 hs_prepare;
50 u32 hs_trail;
51 u32 hs_rqst;
52 u32 ta_go;
53 u32 ta_sure;
54 u32 ta_get;
55};
56
57struct msm_dsi_phy {
9d32c498 58 struct platform_device *pdev;
a689554b
HL		 59 void __iomem *base;
60 void __iomem *reg_base;
61 int id;
9d32c498
HL		 62
63 struct clk *ahb_clk;
ec31abf6 64 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
9d32c498 65
a689554b 66 struct dsi_dphy_timing timing;
ec31abf6 67 const struct dsi_phy_cfg *cfg;
9d32c498 68
dcefc117
HL		 69 bool regulator_ldo_mode;
70
9d32c498 71 struct msm_dsi_pll *pll;
a689554b
HL		 72};
73
ec31abf6
HL		 74static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)
75{
76 struct regulator_bulk_data *s = phy->supplies;
77 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
78 struct device *dev = &phy->pdev->dev;
79 int num = phy->cfg->reg_cfg.num;
80 int i, ret;
81
82 for (i = 0; i < num; i++)
83 s[i].supply = regs[i].name;
84
85 ret = devm_regulator_bulk_get(&phy->pdev->dev, num, s);
86 if (ret < 0) {
87 dev_err(dev, "%s: failed to init regulator, ret=%d\n",
88 __func__, ret);
89 return ret;
90 }
91
92 for (i = 0; i < num; i++) {
93 if ((regs[i].min_voltage >= 0) && (regs[i].max_voltage >= 0)) {
94 ret = regulator_set_voltage(s[i].consumer,
95 regs[i].min_voltage, regs[i].max_voltage);
96 if (ret < 0) {
97 dev_err(dev,
98 "regulator %d set voltage failed, %d\n",
99 i, ret);
100 return ret;
101 }
102 }
103 }
104
105 return 0;
106}
107
108static void dsi_phy_regulator_disable(struct msm_dsi_phy *phy)
109{
110 struct regulator_bulk_data *s = phy->supplies;
111 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
112 int num = phy->cfg->reg_cfg.num;
113 int i;
114
115 DBG("");
116 for (i = num - 1; i >= 0; i--)
117 if (regs[i].disable_load >= 0)
118 regulator_set_load(s[i].consumer,
119 regs[i].disable_load);
120
121 regulator_bulk_disable(num, s);
122}
123
124static int dsi_phy_regulator_enable(struct msm_dsi_phy *phy)
125{
126 struct regulator_bulk_data *s = phy->supplies;
127 const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
128 struct device *dev = &phy->pdev->dev;
129 int num = phy->cfg->reg_cfg.num;
130 int ret, i;
131
132 DBG("");
133 for (i = 0; i < num; i++) {
134 if (regs[i].enable_load >= 0) {
135 ret = regulator_set_load(s[i].consumer,
136 regs[i].enable_load);
137 if (ret < 0) {
138 dev_err(dev,
139 "regulator %d set op mode failed, %d\n",
140 i, ret);
141 goto fail;
142 }
143 }
144 }
145
146 ret = regulator_bulk_enable(num, s);
147 if (ret < 0) {
148 dev_err(dev, "regulator enable failed, %d\n", ret);
149 goto fail;
150 }
151
152 return 0;
153
154fail:
155 for (i--; i >= 0; i--)
156 regulator_set_load(s[i].consumer, regs[i].disable_load);
157 return ret;
158}
159
13351cd1
HL		 160static void dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg)
161{
162 int phy_id = phy->id;
163
164 if ((phy_id >= DSI_MAX) || (pll_id >= DSI_MAX))
165 return;
166
167 if (phy->cfg->src_pll_truthtable[phy_id][pll_id])
168 dsi_phy_write(phy->base + reg, 0x01);
169 else
170 dsi_phy_write(phy->base + reg, 0x00);
171}
172
a689554b
HL		 173#define S_DIV_ROUND_UP(n, d) \
174 (((n) >= 0) ? (((n) + (d) - 1) / (d)) : (((n) - (d) + 1) / (d)))
175
176static inline s32 linear_inter(s32 tmax, s32 tmin, s32 percent,
177 s32 min_result, bool even)
178{
179 s32 v;
180 v = (tmax - tmin) * percent;
181 v = S_DIV_ROUND_UP(v, 100) + tmin;
182 if (even && (v & 0x1))
183 return max_t(s32, min_result, v - 1);
184 else
185 return max_t(s32, min_result, v);
186}
187
188static void dsi_dphy_timing_calc_clk_zero(struct dsi_dphy_timing *timing,
189 s32 ui, s32 coeff, s32 pcnt)
190{
191 s32 tmax, tmin, clk_z;
192 s32 temp;
193
194 /* reset */
195 temp = 300 * coeff - ((timing->clk_prepare >> 1) + 1) * 2 * ui;
196 tmin = S_DIV_ROUND_UP(temp, ui) - 2;
197 if (tmin > 255) {
198 tmax = 511;
199 clk_z = linear_inter(2 * tmin, tmin, pcnt, 0, true);
200 } else {
201 tmax = 255;
202 clk_z = linear_inter(tmax, tmin, pcnt, 0, true);
203 }
204
205 /* adjust */
206 temp = (timing->hs_rqst + timing->clk_prepare + clk_z) & 0x7;
207 timing->clk_zero = clk_z + 8 - temp;
208}
209
210static int dsi_dphy_timing_calc(struct dsi_dphy_timing *timing,
211 const unsigned long bit_rate, const unsigned long esc_rate)
212{
213 s32 ui, lpx;
214 s32 tmax, tmin;
215 s32 pcnt0 = 10;
216 s32 pcnt1 = (bit_rate > 1200000000) ? 15 : 10;
217 s32 pcnt2 = 10;
218 s32 pcnt3 = (bit_rate > 180000000) ? 10 : 40;
219 s32 coeff = 1000; /* Precision, should avoid overflow */
220 s32 temp;
221
222 if (!bit_rate || !esc_rate)
223 return -EINVAL;
224
225 ui = mult_frac(NSEC_PER_MSEC, coeff, bit_rate / 1000);
226 lpx = mult_frac(NSEC_PER_MSEC, coeff, esc_rate / 1000);
227
228 tmax = S_DIV_ROUND_UP(95 * coeff, ui) - 2;
229 tmin = S_DIV_ROUND_UP(38 * coeff, ui) - 2;
230 timing->clk_prepare = linear_inter(tmax, tmin, pcnt0, 0, true);
231
232 temp = lpx / ui;
233 if (temp & 0x1)
234 timing->hs_rqst = temp;
235 else
236 timing->hs_rqst = max_t(s32, 0, temp - 2);
237
238 /* Calculate clk_zero after clk_prepare and hs_rqst */
239 dsi_dphy_timing_calc_clk_zero(timing, ui, coeff, pcnt2);
240
241 temp = 105 * coeff + 12 * ui - 20 * coeff;
242 tmax = S_DIV_ROUND_UP(temp, ui) - 2;
243 tmin = S_DIV_ROUND_UP(60 * coeff, ui) - 2;
244 timing->clk_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
245
246 temp = 85 * coeff + 6 * ui;
247 tmax = S_DIV_ROUND_UP(temp, ui) - 2;
248 temp = 40 * coeff + 4 * ui;
249 tmin = S_DIV_ROUND_UP(temp, ui) - 2;
250 timing->hs_prepare = linear_inter(tmax, tmin, pcnt1, 0, true);
251
252 tmax = 255;
253 temp = ((timing->hs_prepare >> 1) + 1) * 2 * ui + 2 * ui;
254 temp = 145 * coeff + 10 * ui - temp;
255 tmin = S_DIV_ROUND_UP(temp, ui) - 2;
256 timing->hs_zero = linear_inter(tmax, tmin, pcnt2, 24, true);
257
258 temp = 105 * coeff + 12 * ui - 20 * coeff;
259 tmax = S_DIV_ROUND_UP(temp, ui) - 2;
260 temp = 60 * coeff + 4 * ui;
261 tmin = DIV_ROUND_UP(temp, ui) - 2;
262 timing->hs_trail = linear_inter(tmax, tmin, pcnt3, 0, true);
263
264 tmax = 255;
265 tmin = S_DIV_ROUND_UP(100 * coeff, ui) - 2;
266 timing->hs_exit = linear_inter(tmax, tmin, pcnt2, 0, true);
267
268 tmax = 63;
269 temp = ((timing->hs_exit >> 1) + 1) * 2 * ui;
270 temp = 60 * coeff + 52 * ui - 24 * ui - temp;
271 tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1;
272 timing->clk_post = linear_inter(tmax, tmin, pcnt2, 0, false);
273
274 tmax = 63;
275 temp = ((timing->clk_prepare >> 1) + 1) * 2 * ui;
276 temp += ((timing->clk_zero >> 1) + 1) * 2 * ui;
277 temp += 8 * ui + lpx;
278 tmin = S_DIV_ROUND_UP(temp, 8 * ui) - 1;
279 if (tmin > tmax) {
280 temp = linear_inter(2 * tmax, tmin, pcnt2, 0, false) >> 1;
281 timing->clk_pre = temp >> 1;
282 temp = (2 * tmax - tmin) * pcnt2;
283 } else {
284 timing->clk_pre = linear_inter(tmax, tmin, pcnt2, 0, false);
285 }
286
287 timing->ta_go = 3;
288 timing->ta_sure = 0;
289 timing->ta_get = 4;
290
291 DBG("PHY timings: %d, %d, %d, %d, %d, %d, %d, %d, %d, %d",
292 timing->clk_pre, timing->clk_post, timing->clk_zero,
293 timing->clk_trail, timing->clk_prepare, timing->hs_exit,
294 timing->hs_zero, timing->hs_prepare, timing->hs_trail,
295 timing->hs_rqst);
296
297 return 0;
298}
299
300static void dsi_28nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
301{
302 void __iomem *base = phy->reg_base;
303
304 if (!enable) {
305 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 0);
306 return;
307 }
308
309 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x0);
310 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG, 1);
311 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_5, 0);
312 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_3, 0);
313 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_2, 0x3);
314 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_1, 0x9);
315 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_0, 0x7);
316 dsi_phy_write(base + REG_DSI_28nm_PHY_REGULATOR_CTRL_4, 0x20);
317}
318
13351cd1 319static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
a689554b
HL		 320 const unsigned long bit_rate, const unsigned long esc_rate)
321{
322 struct dsi_dphy_timing *timing = &phy->timing;
323 int i;
324 void __iomem *base = phy->base;
325
326 DBG("");
327
328 if (dsi_dphy_timing_calc(timing, bit_rate, esc_rate)) {
329 pr_err("%s: D-PHY timing calculation failed\n", __func__);
330 return -EINVAL;
331 }
332
333 dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_0, 0xff);
334
335 dsi_28nm_phy_regulator_ctrl(phy, true);
336
337 dsi_phy_write(base + REG_DSI_28nm_PHY_LDO_CNTRL, 0x00);
338
339 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_0,
340 DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero));
341 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_1,
342 DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail));
343 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_2,
344 DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare));
345 if (timing->clk_zero & BIT(8))
346 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_3,
347 DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8);
348 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_4,
349 DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));
350 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_5,
351 DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero));
352 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_6,
353 DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare));
354 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_7,
355 DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail));
356 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_8,
357 DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst));
358 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_9,
359 DSI_28nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
360 DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure));
361 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_10,
362 DSI_28nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get));
363 dsi_phy_write(base + REG_DSI_28nm_PHY_TIMING_CTRL_11,
364 DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0));
365
366 dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_1, 0x00);
367 dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f);
368
369 dsi_phy_write(base + REG_DSI_28nm_PHY_STRENGTH_1, 0x6);
370
371 for (i = 0; i < 4; i++) {
372 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_0(i), 0);
373 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_1(i), 0);
374 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_2(i), 0);
375 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_3(i), 0);
376 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_DATAPATH(i), 0);
377 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_DEBUG_SEL(i), 0);
378 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_0(i), 0x1);
379 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_TEST_STR_1(i), 0x97);
380 }
381 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(0), 0);
382 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(1), 0x5);
383 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(2), 0xa);
384 dsi_phy_write(base + REG_DSI_28nm_PHY_LN_CFG_4(3), 0xf);
385
386 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_CFG_1, 0xc0);
387 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR0, 0x1);
388 dsi_phy_write(base + REG_DSI_28nm_PHY_LNCK_TEST_STR1, 0xbb);
389
390 dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f);
391
13351cd1 392 dsi_phy_set_src_pll(phy, src_pll_id, REG_DSI_28nm_PHY_GLBL_TEST_CTRL);
a689554b
HL		 393
394 return 0;
395}
396
397static int dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
398{
399 dsi_phy_write(phy->base + REG_DSI_28nm_PHY_CTRL_0, 0);
400 dsi_28nm_phy_regulator_ctrl(phy, false);
401
402 /*
403 * Wait for the registers writes to complete in order to
404 * ensure that the phy is completely disabled
405 */
406 wmb();
407
408 return 0;
409}
410
dcefc117
HL		 411static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
412{
413 void __iomem *base = phy->reg_base;
414
415 if (!enable) {
416 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0);
417 return;
418 }
419
420 if (phy->regulator_ldo_mode) {
421 dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x1d);
422 return;
423 }
424
425 /* non LDO mode */
426 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_1, 0x03);
427 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_2, 0x03);
428 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_3, 0x00);
429 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_4, 0x20);
430 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG, 0x01);
431 dsi_phy_write(phy->base + REG_DSI_20nm_PHY_LDO_CNTRL, 0x00);
432 dsi_phy_write(base + REG_DSI_20nm_PHY_REGULATOR_CTRL_0, 0x03);
433}
434
435static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
436 const unsigned long bit_rate, const unsigned long esc_rate)
437{
438 struct dsi_dphy_timing *timing = &phy->timing;
439 int i;
440 void __iomem *base = phy->base;
441 u32 cfg_4[4] = {0x20, 0x40, 0x20, 0x00};
442
443 DBG("");
444
445 if (dsi_dphy_timing_calc(timing, bit_rate, esc_rate)) {
446 pr_err("%s: D-PHY timing calculation failed\n", __func__);
447 return -EINVAL;
448 }
449
450 dsi_20nm_phy_regulator_ctrl(phy, true);
451
452 dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff);
453
454 dsi_phy_set_src_pll(phy, src_pll_id, REG_DSI_20nm_PHY_GLBL_TEST_CTRL);
455
456 for (i = 0; i < 4; i++) {
457 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i),
458 (i >> 1) * 0x40);
459 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_0(i), 0x01);
460 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_TEST_STR_1(i), 0x46);
461 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_0(i), 0x02);
462 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_1(i), 0xa0);
463 dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_4(i), cfg_4[i]);
464 }
465
466 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_3, 0x80);
467 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR0, 0x01);
468 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_TEST_STR1, 0x46);
469 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_0, 0x00);
470 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_1, 0xa0);
471 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_2, 0x00);
472 dsi_phy_write(base + REG_DSI_20nm_PHY_LNCK_CFG_4, 0x00);
473
474 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_0,
475 DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(timing->clk_zero));
476 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_1,
477 DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(timing->clk_trail));
478 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_2,
479 DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(timing->clk_prepare));
480 if (timing->clk_zero & BIT(8))
481 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_3,
482 DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8);
483 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_4,
484 DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(timing->hs_exit));
485 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_5,
486 DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(timing->hs_zero));
487 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_6,
488 DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(timing->hs_prepare));
489 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_7,
490 DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(timing->hs_trail));
491 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_8,
492 DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(timing->hs_rqst));
493 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_9,
494 DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(timing->ta_go) |
495 DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(timing->ta_sure));
496 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_10,
497 DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(timing->ta_get));
498 dsi_phy_write(base + REG_DSI_20nm_PHY_TIMING_CTRL_11,
499 DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(0));
500
501 dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_1, 0x00);
502
503 dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_1, 0x06);
504
505 /* make sure everything is written before enable */
506 wmb();
507 dsi_phy_write(base + REG_DSI_20nm_PHY_CTRL_0, 0x7f);
508
509 return 0;
510}
511
512static int dsi_20nm_phy_disable(struct msm_dsi_phy *phy)
513{
514 dsi_phy_write(phy->base + REG_DSI_20nm_PHY_CTRL_0, 0);
515 dsi_20nm_phy_regulator_ctrl(phy, false);
516
517 return 0;
518}
519
9d32c498
HL		 520static int dsi_phy_enable_resource(struct msm_dsi_phy *phy)
521{
522 int ret;
523
524 pm_runtime_get_sync(&phy->pdev->dev);
525
526 ret = clk_prepare_enable(phy->ahb_clk);
527 if (ret) {
528 pr_err("%s: can't enable ahb clk, %d\n", __func__, ret);
529 pm_runtime_put_sync(&phy->pdev->dev);
530 }
531
532 return ret;
533}
534
535static void dsi_phy_disable_resource(struct msm_dsi_phy *phy)
536{
537 clk_disable_unprepare(phy->ahb_clk);
538 pm_runtime_put_sync(&phy->pdev->dev);
539}
540
ec31abf6
HL		 541static const struct dsi_phy_cfg dsi_phy_cfgs[MSM_DSI_PHY_MAX] = {
542 [MSM_DSI_PHY_28NM_HPM] = {
543 .type = MSM_DSI_PHY_28NM_HPM,
13351cd1 544 .src_pll_truthtable = { {true, true}, {false, true} },
ec31abf6
HL		 545 .reg_cfg = {
546 .num = 1,
547 .regs = {
548 {"vddio", 1800000, 1800000, 100000, 100},
549 },
550 },
551 .ops = {
552 .enable = dsi_28nm_phy_enable,
553 .disable = dsi_28nm_phy_disable,
554 }
555 },
556 [MSM_DSI_PHY_28NM_LP] = {
557 .type = MSM_DSI_PHY_28NM_LP,
13351cd1 558 .src_pll_truthtable = { {true, true}, {true, true} },
ec31abf6
HL		 559 .reg_cfg = {
560 .num = 1,
561 .regs = {
562 {"vddio", 1800000, 1800000, 100000, 100},
563 },
564 },
565 .ops = {
566 .enable = dsi_28nm_phy_enable,
567 .disable = dsi_28nm_phy_disable,
568 }
569 },
dcefc117
HL		 570 [MSM_DSI_PHY_20NM] = {
571 .type = MSM_DSI_PHY_20NM,
572 .src_pll_truthtable = { {false, true}, {false, true} },
573 .reg_cfg = {
574 .num = 2,
575 .regs = {
576 {"vddio", 1800000, 1800000, 100000, 100},
577 {"vcca", 1000000, 1000000, 10000, 100},
578 },
579 },
580 .ops = {
581 .enable = dsi_20nm_phy_enable,
582 .disable = dsi_20nm_phy_disable,
583 }
584 },
ec31abf6
HL		 585};
586
587static const struct of_device_id dsi_phy_dt_match[] = {
588 { .compatible = "qcom,dsi-phy-28nm-hpm",
589 .data = &dsi_phy_cfgs[MSM_DSI_PHY_28NM_HPM],},
590 { .compatible = "qcom,dsi-phy-28nm-lp",
591 .data = &dsi_phy_cfgs[MSM_DSI_PHY_28NM_LP],},
dcefc117
HL		 592 { .compatible = "qcom,dsi-phy-20nm",
593 .data = &dsi_phy_cfgs[MSM_DSI_PHY_20NM],},
ec31abf6
HL		 594 {}
595};
a689554b 596
ec31abf6 597static int dsi_phy_driver_probe(struct platform_device *pdev)
a689554b
HL		 598{
599 struct msm_dsi_phy *phy;
ec31abf6 600 const struct of_device_id *match;
9d32c498 601 int ret;
a689554b
HL		 602
603 phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);
604 if (!phy)
ec31abf6
HL		 605 return -ENOMEM;
606
607 match = of_match_node(dsi_phy_dt_match, pdev->dev.of_node);
608 if (!match)
609 return -ENODEV;
610
611 phy->cfg = match->data;
612 phy->pdev = pdev;
613
614 ret = of_property_read_u32(pdev->dev.of_node,
615 "qcom,dsi-phy-index", &phy->id);
616 if (ret) {
617 dev_err(&pdev->dev,
618 "%s: PHY index not specified, ret=%d\n",
619 __func__, ret);
620 goto fail;
621 }
a689554b 622
dcefc117
HL		 623 phy->regulator_ldo_mode = of_property_read_bool(pdev->dev.of_node,
624 "qcom,dsi-phy-regulator-ldo-mode");
625
a689554b 626 phy->base = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
73dbf696 627 if (IS_ERR(phy->base)) {
ec31abf6
HL		 628 dev_err(&pdev->dev, "%s: failed to map phy base\n", __func__);
629 ret = -ENOMEM;
630 goto fail;
a689554b
HL		 631 }
632 phy->reg_base = msm_ioremap(pdev, "dsi_phy_regulator", "DSI_PHY_REG");
73dbf696 633 if (IS_ERR(phy->reg_base)) {
ec31abf6
HL		 634 dev_err(&pdev->dev,
635 "%s: failed to map phy regulator base\n", __func__);
636 ret = -ENOMEM;
637 goto fail;
a689554b
HL		 638 }
639
ec31abf6
HL		 640 ret = dsi_phy_regulator_init(phy);
641 if (ret) {
642 dev_err(&pdev->dev, "%s: failed to init regulator\n", __func__);
643 goto fail;
a689554b
HL		 644 }
645
9d32c498
HL		 646 phy->ahb_clk = devm_clk_get(&pdev->dev, "iface_clk");
647 if (IS_ERR(phy->ahb_clk)) {
648 pr_err("%s: Unable to get ahb clk\n", __func__);
ec31abf6
HL		 649 ret = PTR_ERR(phy->ahb_clk);
650 goto fail;
9d32c498
HL		 651 }
652
653 /* PLL init will call into clk_register which requires
654 * register access, so we need to enable power and ahb clock.
655 */
656 ret = dsi_phy_enable_resource(phy);
657 if (ret)
ec31abf6 658 goto fail;
9d32c498 659
ec31abf6 660 phy->pll = msm_dsi_pll_init(pdev, phy->cfg->type, phy->id);
9d32c498 661 if (!phy->pll)
ec31abf6
HL		 662 dev_info(&pdev->dev,
663 "%s: pll init failed, need separate pll clk driver\n",
9d32c498
HL		 664 __func__);
665
666 dsi_phy_disable_resource(phy);
a689554b 667
ec31abf6
HL		 668 platform_set_drvdata(pdev, phy);
669
670 return 0;
671
672fail:
673 return ret;
a689554b
HL		 674}
675
ec31abf6 676static int dsi_phy_driver_remove(struct platform_device *pdev)
9d32c498 677{
ec31abf6
HL		 678 struct msm_dsi_phy *phy = platform_get_drvdata(pdev);
679
680 if (phy && phy->pll) {
9d32c498
HL		 681 msm_dsi_pll_destroy(phy->pll);
682 phy->pll = NULL;
683 }
ec31abf6
HL		 684
685 platform_set_drvdata(pdev, NULL);
686
687 return 0;
688}
689
690static struct platform_driver dsi_phy_platform_driver = {
691 .probe = dsi_phy_driver_probe,
692 .remove = dsi_phy_driver_remove,
693 .driver = {
694 .name = "msm_dsi_phy",
695 .of_match_table = dsi_phy_dt_match,
696 },
697};
698
699void __init msm_dsi_phy_driver_register(void)
700{
701 platform_driver_register(&dsi_phy_platform_driver);
702}
703
704void __exit msm_dsi_phy_driver_unregister(void)
705{
706 platform_driver_unregister(&dsi_phy_platform_driver);
9d32c498
HL		 707}
708
13351cd1 709int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
a689554b
HL		 710 const unsigned long bit_rate, const unsigned long esc_rate)
711{
ec31abf6
HL		 712 int ret;
713
714 if (!phy || !phy->cfg->ops.enable)
a689554b 715 return -EINVAL;
ec31abf6
HL		 716
717 ret = dsi_phy_regulator_enable(phy);
718 if (ret) {
719 dev_err(&phy->pdev->dev, "%s: regulator enable failed, %d\n",
720 __func__, ret);
721 return ret;
722 }
723
13351cd1 724 return phy->cfg->ops.enable(phy, src_pll_id, bit_rate, esc_rate);
a689554b
HL		 725}
726
727int msm_dsi_phy_disable(struct msm_dsi_phy *phy)
728{
ec31abf6 729 if (!phy || !phy->cfg->ops.disable)
a689554b 730 return -EINVAL;
ec31abf6
HL		 731
732 phy->cfg->ops.disable(phy);
733 dsi_phy_regulator_disable(phy);
734
735 return 0;
a689554b
HL		 736}
737
738void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy,
739 u32 *clk_pre, u32 *clk_post)
740{
741 if (!phy)
742 return;
743 if (clk_pre)
744 *clk_pre = phy->timing.clk_pre;
745 if (clk_post)
746 *clk_post = phy->timing.clk_post;
747}
748
9d32c498
HL		 749struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy)
750{
751 if (!phy)
752 return NULL;
753
754 return phy->pll;
755}
756
ubuntu-zesty-kernel mirror