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c8afe684 RC |
1 | /* |
2 | * Copyright (C) 2013 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include <linux/gpio.h> | |
865807d0 | 19 | #include <linux/pinctrl/consumer.h> |
c8afe684 | 20 | |
dd2da6e3 | 21 | #include "msm_kms.h" |
c8afe684 RC |
22 | #include "hdmi.h" |
23 | ||
24 | struct hdmi_connector { | |
a3376e3e RC |
25 | struct drm_connector base; |
26 | struct hdmi *hdmi; | |
dada25bd | 27 | struct work_struct hpd_work; |
c8afe684 RC |
28 | }; |
29 | #define to_hdmi_connector(x) container_of(x, struct hdmi_connector, base) | |
30 | ||
da328552 SV |
31 | static void hdmi_phy_reset(struct hdmi *hdmi) |
32 | { | |
33 | unsigned int val; | |
34 | ||
35 | val = hdmi_read(hdmi, REG_HDMI_PHY_CTRL); | |
36 | ||
37 | if (val & HDMI_PHY_CTRL_SW_RESET_LOW) { | |
38 | /* pull low */ | |
39 | hdmi_write(hdmi, REG_HDMI_PHY_CTRL, | |
40 | val & ~HDMI_PHY_CTRL_SW_RESET); | |
41 | } else { | |
42 | /* pull high */ | |
43 | hdmi_write(hdmi, REG_HDMI_PHY_CTRL, | |
44 | val | HDMI_PHY_CTRL_SW_RESET); | |
45 | } | |
46 | ||
47 | if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) { | |
48 | /* pull low */ | |
49 | hdmi_write(hdmi, REG_HDMI_PHY_CTRL, | |
50 | val & ~HDMI_PHY_CTRL_SW_RESET_PLL); | |
51 | } else { | |
52 | /* pull high */ | |
53 | hdmi_write(hdmi, REG_HDMI_PHY_CTRL, | |
54 | val | HDMI_PHY_CTRL_SW_RESET_PLL); | |
55 | } | |
56 | ||
57 | msleep(100); | |
58 | ||
59 | if (val & HDMI_PHY_CTRL_SW_RESET_LOW) { | |
60 | /* pull high */ | |
61 | hdmi_write(hdmi, REG_HDMI_PHY_CTRL, | |
62 | val | HDMI_PHY_CTRL_SW_RESET); | |
63 | } else { | |
64 | /* pull low */ | |
65 | hdmi_write(hdmi, REG_HDMI_PHY_CTRL, | |
66 | val & ~HDMI_PHY_CTRL_SW_RESET); | |
67 | } | |
68 | ||
69 | if (val & HDMI_PHY_CTRL_SW_RESET_PLL_LOW) { | |
70 | /* pull high */ | |
71 | hdmi_write(hdmi, REG_HDMI_PHY_CTRL, | |
72 | val | HDMI_PHY_CTRL_SW_RESET_PLL); | |
73 | } else { | |
74 | /* pull low */ | |
75 | hdmi_write(hdmi, REG_HDMI_PHY_CTRL, | |
76 | val & ~HDMI_PHY_CTRL_SW_RESET_PLL); | |
77 | } | |
78 | } | |
79 | ||
c8afe684 RC |
80 | static int gpio_config(struct hdmi *hdmi, bool on) |
81 | { | |
5e4eb82f | 82 | struct device *dev = &hdmi->pdev->dev; |
dada25bd | 83 | const struct hdmi_platform_config *config = hdmi->config; |
c8afe684 RC |
84 | int ret; |
85 | ||
86 | if (on) { | |
87 | ret = gpio_request(config->ddc_clk_gpio, "HDMI_DDC_CLK"); | |
88 | if (ret) { | |
5e4eb82f | 89 | dev_err(dev, "'%s'(%d) gpio_request failed: %d\n", |
c8afe684 RC |
90 | "HDMI_DDC_CLK", config->ddc_clk_gpio, ret); |
91 | goto error1; | |
92 | } | |
dada25bd RC |
93 | gpio_set_value_cansleep(config->ddc_clk_gpio, 1); |
94 | ||
c8afe684 RC |
95 | ret = gpio_request(config->ddc_data_gpio, "HDMI_DDC_DATA"); |
96 | if (ret) { | |
5e4eb82f | 97 | dev_err(dev, "'%s'(%d) gpio_request failed: %d\n", |
c8afe684 RC |
98 | "HDMI_DDC_DATA", config->ddc_data_gpio, ret); |
99 | goto error2; | |
100 | } | |
dada25bd RC |
101 | gpio_set_value_cansleep(config->ddc_data_gpio, 1); |
102 | ||
c8afe684 RC |
103 | ret = gpio_request(config->hpd_gpio, "HDMI_HPD"); |
104 | if (ret) { | |
5e4eb82f | 105 | dev_err(dev, "'%s'(%d) gpio_request failed: %d\n", |
c8afe684 RC |
106 | "HDMI_HPD", config->hpd_gpio, ret); |
107 | goto error3; | |
108 | } | |
dada25bd RC |
109 | gpio_direction_input(config->hpd_gpio); |
110 | gpio_set_value_cansleep(config->hpd_gpio, 1); | |
111 | ||
112 | if (config->mux_en_gpio != -1) { | |
113 | ret = gpio_request(config->mux_en_gpio, "HDMI_MUX_EN"); | |
c8afe684 | 114 | if (ret) { |
5e4eb82f | 115 | dev_err(dev, "'%s'(%d) gpio_request failed: %d\n", |
a2fe6cdc | 116 | "HDMI_MUX_EN", config->mux_en_gpio, ret); |
c8afe684 RC |
117 | goto error4; |
118 | } | |
dada25bd RC |
119 | gpio_set_value_cansleep(config->mux_en_gpio, 1); |
120 | } | |
121 | ||
122 | if (config->mux_sel_gpio != -1) { | |
123 | ret = gpio_request(config->mux_sel_gpio, "HDMI_MUX_SEL"); | |
124 | if (ret) { | |
5e4eb82f | 125 | dev_err(dev, "'%s'(%d) gpio_request failed: %d\n", |
dada25bd RC |
126 | "HDMI_MUX_SEL", config->mux_sel_gpio, ret); |
127 | goto error5; | |
128 | } | |
129 | gpio_set_value_cansleep(config->mux_sel_gpio, 0); | |
c8afe684 | 130 | } |
1930f38a BG |
131 | |
132 | if (config->mux_lpm_gpio != -1) { | |
133 | ret = gpio_request(config->mux_lpm_gpio, | |
134 | "HDMI_MUX_LPM"); | |
135 | if (ret) { | |
5e4eb82f | 136 | dev_err(dev, |
1930f38a BG |
137 | "'%s'(%d) gpio_request failed: %d\n", |
138 | "HDMI_MUX_LPM", | |
139 | config->mux_lpm_gpio, ret); | |
140 | goto error6; | |
141 | } | |
142 | gpio_set_value_cansleep(config->mux_lpm_gpio, 1); | |
143 | } | |
c8afe684 RC |
144 | DBG("gpio on"); |
145 | } else { | |
146 | gpio_free(config->ddc_clk_gpio); | |
147 | gpio_free(config->ddc_data_gpio); | |
148 | gpio_free(config->hpd_gpio); | |
149 | ||
dada25bd RC |
150 | if (config->mux_en_gpio != -1) { |
151 | gpio_set_value_cansleep(config->mux_en_gpio, 0); | |
152 | gpio_free(config->mux_en_gpio); | |
153 | } | |
154 | ||
155 | if (config->mux_sel_gpio != -1) { | |
156 | gpio_set_value_cansleep(config->mux_sel_gpio, 1); | |
157 | gpio_free(config->mux_sel_gpio); | |
c8afe684 | 158 | } |
1930f38a BG |
159 | |
160 | if (config->mux_lpm_gpio != -1) { | |
161 | gpio_set_value_cansleep(config->mux_lpm_gpio, 0); | |
162 | gpio_free(config->mux_lpm_gpio); | |
163 | } | |
c8afe684 RC |
164 | DBG("gpio off"); |
165 | } | |
166 | ||
167 | return 0; | |
168 | ||
1930f38a BG |
169 | error6: |
170 | if (config->mux_sel_gpio != -1) | |
171 | gpio_free(config->mux_sel_gpio); | |
dada25bd RC |
172 | error5: |
173 | if (config->mux_en_gpio != -1) | |
174 | gpio_free(config->mux_en_gpio); | |
c8afe684 RC |
175 | error4: |
176 | gpio_free(config->hpd_gpio); | |
177 | error3: | |
178 | gpio_free(config->ddc_data_gpio); | |
179 | error2: | |
180 | gpio_free(config->ddc_clk_gpio); | |
181 | error1: | |
182 | return ret; | |
183 | } | |
184 | ||
185 | static int hpd_enable(struct hdmi_connector *hdmi_connector) | |
186 | { | |
a3376e3e | 187 | struct hdmi *hdmi = hdmi_connector->hdmi; |
dada25bd | 188 | const struct hdmi_platform_config *config = hdmi->config; |
5e4eb82f | 189 | struct device *dev = &hdmi->pdev->dev; |
c8afe684 | 190 | uint32_t hpd_ctrl; |
dada25bd | 191 | int i, ret; |
c6a57a50 | 192 | unsigned long flags; |
c8afe684 | 193 | |
e6d7a16f JW |
194 | for (i = 0; i < config->hpd_reg_cnt; i++) { |
195 | ret = regulator_enable(hdmi->hpd_regs[i]); | |
196 | if (ret) { | |
5e4eb82f | 197 | dev_err(dev, "failed to enable hpd regulator: %s (%d)\n", |
e6d7a16f JW |
198 | config->hpd_reg_names[i], ret); |
199 | goto fail; | |
200 | } | |
201 | } | |
202 | ||
865807d0 SV |
203 | ret = pinctrl_pm_select_default_state(dev); |
204 | if (ret) { | |
205 | dev_err(dev, "pinctrl state chg failed: %d\n", ret); | |
206 | goto fail; | |
207 | } | |
208 | ||
c8afe684 RC |
209 | ret = gpio_config(hdmi, true); |
210 | if (ret) { | |
5e4eb82f | 211 | dev_err(dev, "failed to configure GPIOs: %d\n", ret); |
c8afe684 RC |
212 | goto fail; |
213 | } | |
214 | ||
dada25bd | 215 | for (i = 0; i < config->hpd_clk_cnt; i++) { |
b77f47e7 SV |
216 | if (config->hpd_freq && config->hpd_freq[i]) { |
217 | ret = clk_set_rate(hdmi->hpd_clks[i], | |
218 | config->hpd_freq[i]); | |
219 | if (ret) | |
5e4eb82f | 220 | dev_warn(dev, "failed to set clk %s (%d)\n", |
b77f47e7 SV |
221 | config->hpd_clk_names[i], ret); |
222 | } | |
223 | ||
dada25bd RC |
224 | ret = clk_prepare_enable(hdmi->hpd_clks[i]); |
225 | if (ret) { | |
5e4eb82f | 226 | dev_err(dev, "failed to enable hpd clk: %s (%d)\n", |
dada25bd RC |
227 | config->hpd_clk_names[i], ret); |
228 | goto fail; | |
229 | } | |
c8afe684 RC |
230 | } |
231 | ||
c8afe684 | 232 | hdmi_set_mode(hdmi, false); |
da328552 | 233 | hdmi_phy_reset(hdmi); |
c8afe684 RC |
234 | hdmi_set_mode(hdmi, true); |
235 | ||
236 | hdmi_write(hdmi, REG_HDMI_USEC_REFTIMER, 0x0001001b); | |
237 | ||
238 | /* enable HPD events: */ | |
239 | hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, | |
240 | HDMI_HPD_INT_CTRL_INT_CONNECT | | |
241 | HDMI_HPD_INT_CTRL_INT_EN); | |
242 | ||
243 | /* set timeout to 4.1ms (max) for hardware debounce */ | |
c6a57a50 | 244 | spin_lock_irqsave(&hdmi->reg_lock, flags); |
c8afe684 RC |
245 | hpd_ctrl = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); |
246 | hpd_ctrl |= HDMI_HPD_CTRL_TIMEOUT(0x1fff); | |
247 | ||
248 | /* Toggle HPD circuit to trigger HPD sense */ | |
249 | hdmi_write(hdmi, REG_HDMI_HPD_CTRL, | |
250 | ~HDMI_HPD_CTRL_ENABLE & hpd_ctrl); | |
251 | hdmi_write(hdmi, REG_HDMI_HPD_CTRL, | |
252 | HDMI_HPD_CTRL_ENABLE | hpd_ctrl); | |
c6a57a50 | 253 | spin_unlock_irqrestore(&hdmi->reg_lock, flags); |
c8afe684 RC |
254 | |
255 | return 0; | |
256 | ||
257 | fail: | |
258 | return ret; | |
259 | } | |
260 | ||
e6d7a16f | 261 | static void hdp_disable(struct hdmi_connector *hdmi_connector) |
c8afe684 | 262 | { |
a3376e3e | 263 | struct hdmi *hdmi = hdmi_connector->hdmi; |
dada25bd | 264 | const struct hdmi_platform_config *config = hdmi->config; |
5e4eb82f | 265 | struct device *dev = &hdmi->pdev->dev; |
dada25bd | 266 | int i, ret = 0; |
c8afe684 RC |
267 | |
268 | /* Disable HPD interrupt */ | |
269 | hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, 0); | |
270 | ||
271 | hdmi_set_mode(hdmi, false); | |
272 | ||
dada25bd RC |
273 | for (i = 0; i < config->hpd_clk_cnt; i++) |
274 | clk_disable_unprepare(hdmi->hpd_clks[i]); | |
c8afe684 RC |
275 | |
276 | ret = gpio_config(hdmi, false); | |
e6d7a16f | 277 | if (ret) |
5e4eb82f | 278 | dev_warn(dev, "failed to unconfigure GPIOs: %d\n", ret); |
c8afe684 | 279 | |
865807d0 SV |
280 | ret = pinctrl_pm_select_sleep_state(dev); |
281 | if (ret) | |
282 | dev_warn(dev, "pinctrl state chg failed: %d\n", ret); | |
283 | ||
e6d7a16f JW |
284 | for (i = 0; i < config->hpd_reg_cnt; i++) { |
285 | ret = regulator_disable(hdmi->hpd_regs[i]); | |
286 | if (ret) | |
5e4eb82f | 287 | dev_warn(dev, "failed to disable hpd regulator: %s (%d)\n", |
e6d7a16f JW |
288 | config->hpd_reg_names[i], ret); |
289 | } | |
c8afe684 RC |
290 | } |
291 | ||
dada25bd RC |
292 | static void |
293 | hotplug_work(struct work_struct *work) | |
294 | { | |
295 | struct hdmi_connector *hdmi_connector = | |
296 | container_of(work, struct hdmi_connector, hpd_work); | |
297 | struct drm_connector *connector = &hdmi_connector->base; | |
298 | drm_helper_hpd_irq_event(connector->dev); | |
299 | } | |
300 | ||
c8afe684 RC |
301 | void hdmi_connector_irq(struct drm_connector *connector) |
302 | { | |
a3376e3e RC |
303 | struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); |
304 | struct hdmi *hdmi = hdmi_connector->hdmi; | |
c8afe684 RC |
305 | uint32_t hpd_int_status, hpd_int_ctrl; |
306 | ||
307 | /* Process HPD: */ | |
308 | hpd_int_status = hdmi_read(hdmi, REG_HDMI_HPD_INT_STATUS); | |
309 | hpd_int_ctrl = hdmi_read(hdmi, REG_HDMI_HPD_INT_CTRL); | |
310 | ||
311 | if ((hpd_int_ctrl & HDMI_HPD_INT_CTRL_INT_EN) && | |
312 | (hpd_int_status & HDMI_HPD_INT_STATUS_INT)) { | |
313 | bool detected = !!(hpd_int_status & HDMI_HPD_INT_STATUS_CABLE_DETECTED); | |
314 | ||
ff2f974e | 315 | /* ack & disable (temporarily) HPD events: */ |
c8afe684 | 316 | hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, |
ff2f974e JW |
317 | HDMI_HPD_INT_CTRL_INT_ACK); |
318 | ||
319 | DBG("status=%04x, ctrl=%04x", hpd_int_status, hpd_int_ctrl); | |
c8afe684 | 320 | |
c8afe684 RC |
321 | /* detect disconnect if we are connected or visa versa: */ |
322 | hpd_int_ctrl = HDMI_HPD_INT_CTRL_INT_EN; | |
323 | if (!detected) | |
324 | hpd_int_ctrl |= HDMI_HPD_INT_CTRL_INT_CONNECT; | |
325 | hdmi_write(hdmi, REG_HDMI_HPD_INT_CTRL, hpd_int_ctrl); | |
dada25bd | 326 | |
c6a57a50 | 327 | queue_work(hdmi->workq, &hdmi_connector->hpd_work); |
c8afe684 RC |
328 | } |
329 | } | |
330 | ||
3189650d RC |
331 | static enum drm_connector_status detect_reg(struct hdmi *hdmi) |
332 | { | |
333 | uint32_t hpd_int_status = hdmi_read(hdmi, REG_HDMI_HPD_INT_STATUS); | |
334 | return (hpd_int_status & HDMI_HPD_INT_STATUS_CABLE_DETECTED) ? | |
335 | connector_status_connected : connector_status_disconnected; | |
336 | } | |
337 | ||
338 | static enum drm_connector_status detect_gpio(struct hdmi *hdmi) | |
339 | { | |
340 | const struct hdmi_platform_config *config = hdmi->config; | |
341 | return gpio_get_value(config->hpd_gpio) ? | |
342 | connector_status_connected : | |
343 | connector_status_disconnected; | |
344 | } | |
345 | ||
c8afe684 RC |
346 | static enum drm_connector_status hdmi_connector_detect( |
347 | struct drm_connector *connector, bool force) | |
348 | { | |
a3376e3e RC |
349 | struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); |
350 | struct hdmi *hdmi = hdmi_connector->hdmi; | |
3189650d | 351 | enum drm_connector_status stat_gpio, stat_reg; |
c8afe684 RC |
352 | int retry = 20; |
353 | ||
3189650d RC |
354 | do { |
355 | stat_gpio = detect_gpio(hdmi); | |
356 | stat_reg = detect_reg(hdmi); | |
c8afe684 | 357 | |
3189650d | 358 | if (stat_gpio == stat_reg) |
dada25bd | 359 | break; |
3189650d | 360 | |
c8afe684 | 361 | mdelay(10); |
3189650d RC |
362 | } while (--retry); |
363 | ||
364 | /* the status we get from reading gpio seems to be more reliable, | |
365 | * so trust that one the most if we didn't manage to get hdmi and | |
366 | * gpio status to agree: | |
367 | */ | |
368 | if (stat_gpio != stat_reg) { | |
369 | DBG("HDMI_HPD_INT_STATUS tells us: %d", stat_reg); | |
370 | DBG("hpd gpio tells us: %d", stat_gpio); | |
c8afe684 RC |
371 | } |
372 | ||
3189650d | 373 | return stat_gpio; |
c8afe684 RC |
374 | } |
375 | ||
376 | static void hdmi_connector_destroy(struct drm_connector *connector) | |
377 | { | |
a3376e3e | 378 | struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); |
c8afe684 RC |
379 | |
380 | hdp_disable(hdmi_connector); | |
381 | ||
34ea3d38 | 382 | drm_connector_unregister(connector); |
c8afe684 RC |
383 | drm_connector_cleanup(connector); |
384 | ||
c8afe684 RC |
385 | kfree(hdmi_connector); |
386 | } | |
387 | ||
388 | static int hdmi_connector_get_modes(struct drm_connector *connector) | |
389 | { | |
a3376e3e RC |
390 | struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); |
391 | struct hdmi *hdmi = hdmi_connector->hdmi; | |
c8afe684 RC |
392 | struct edid *edid; |
393 | uint32_t hdmi_ctrl; | |
394 | int ret = 0; | |
395 | ||
396 | hdmi_ctrl = hdmi_read(hdmi, REG_HDMI_CTRL); | |
397 | hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl | HDMI_CTRL_ENABLE); | |
398 | ||
399 | edid = drm_get_edid(connector, hdmi->i2c); | |
400 | ||
401 | hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl); | |
402 | ||
c6a57a50 | 403 | hdmi->hdmi_mode = drm_detect_hdmi_monitor(edid); |
c8afe684 RC |
404 | drm_mode_connector_update_edid_property(connector, edid); |
405 | ||
406 | if (edid) { | |
407 | ret = drm_add_edid_modes(connector, edid); | |
408 | kfree(edid); | |
409 | } | |
410 | ||
411 | return ret; | |
412 | } | |
413 | ||
414 | static int hdmi_connector_mode_valid(struct drm_connector *connector, | |
415 | struct drm_display_mode *mode) | |
416 | { | |
a3376e3e | 417 | struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); |
dada25bd RC |
418 | struct hdmi *hdmi = hdmi_connector->hdmi; |
419 | const struct hdmi_platform_config *config = hdmi->config; | |
c8afe684 RC |
420 | struct msm_drm_private *priv = connector->dev->dev_private; |
421 | struct msm_kms *kms = priv->kms; | |
422 | long actual, requested; | |
423 | ||
424 | requested = 1000 * mode->clock; | |
425 | actual = kms->funcs->round_pixclk(kms, | |
a3376e3e | 426 | requested, hdmi_connector->hdmi->encoder); |
c8afe684 | 427 | |
dada25bd RC |
428 | /* for mdp5/apq8074, we manage our own pixel clk (as opposed to |
429 | * mdp4/dtv stuff where pixel clk is assigned to mdp/encoder | |
430 | * instead): | |
431 | */ | |
432 | if (config->pwr_clk_cnt > 0) | |
433 | actual = clk_round_rate(hdmi->pwr_clks[0], actual); | |
434 | ||
c8afe684 RC |
435 | DBG("requested=%ld, actual=%ld", requested, actual); |
436 | ||
437 | if (actual != requested) | |
438 | return MODE_CLOCK_RANGE; | |
439 | ||
440 | return 0; | |
441 | } | |
442 | ||
a3376e3e RC |
443 | static struct drm_encoder * |
444 | hdmi_connector_best_encoder(struct drm_connector *connector) | |
445 | { | |
446 | struct hdmi_connector *hdmi_connector = to_hdmi_connector(connector); | |
447 | return hdmi_connector->hdmi->encoder; | |
448 | } | |
449 | ||
c8afe684 | 450 | static const struct drm_connector_funcs hdmi_connector_funcs = { |
0b776d45 | 451 | .dpms = drm_atomic_helper_connector_dpms, |
c8afe684 RC |
452 | .detect = hdmi_connector_detect, |
453 | .fill_modes = drm_helper_probe_single_connector_modes, | |
454 | .destroy = hdmi_connector_destroy, | |
3e7849ef RC |
455 | .reset = drm_atomic_helper_connector_reset, |
456 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, | |
457 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, | |
c8afe684 RC |
458 | }; |
459 | ||
460 | static const struct drm_connector_helper_funcs hdmi_connector_helper_funcs = { | |
461 | .get_modes = hdmi_connector_get_modes, | |
462 | .mode_valid = hdmi_connector_mode_valid, | |
a3376e3e | 463 | .best_encoder = hdmi_connector_best_encoder, |
c8afe684 RC |
464 | }; |
465 | ||
466 | /* initialize connector */ | |
a3376e3e | 467 | struct drm_connector *hdmi_connector_init(struct hdmi *hdmi) |
c8afe684 RC |
468 | { |
469 | struct drm_connector *connector = NULL; | |
470 | struct hdmi_connector *hdmi_connector; | |
471 | int ret; | |
472 | ||
473 | hdmi_connector = kzalloc(sizeof(*hdmi_connector), GFP_KERNEL); | |
474 | if (!hdmi_connector) { | |
475 | ret = -ENOMEM; | |
476 | goto fail; | |
477 | } | |
478 | ||
d1a717bd | 479 | hdmi_connector->hdmi = hdmi; |
dada25bd | 480 | INIT_WORK(&hdmi_connector->hpd_work, hotplug_work); |
a3376e3e RC |
481 | |
482 | connector = &hdmi_connector->base; | |
c8afe684 | 483 | |
a3376e3e | 484 | drm_connector_init(hdmi->dev, connector, &hdmi_connector_funcs, |
c8afe684 RC |
485 | DRM_MODE_CONNECTOR_HDMIA); |
486 | drm_connector_helper_add(connector, &hdmi_connector_helper_funcs); | |
487 | ||
3189650d RC |
488 | connector->polled = DRM_CONNECTOR_POLL_CONNECT | |
489 | DRM_CONNECTOR_POLL_DISCONNECT; | |
c8afe684 | 490 | |
cddfaebd | 491 | connector->interlace_allowed = 0; |
c8afe684 RC |
492 | connector->doublescan_allowed = 0; |
493 | ||
34ea3d38 | 494 | drm_connector_register(connector); |
c8afe684 | 495 | |
c8afe684 RC |
496 | ret = hpd_enable(hdmi_connector); |
497 | if (ret) { | |
5e4eb82f | 498 | dev_err(&hdmi->pdev->dev, "failed to enable HPD: %d\n", ret); |
c8afe684 RC |
499 | goto fail; |
500 | } | |
501 | ||
a3376e3e | 502 | drm_mode_connector_attach_encoder(connector, hdmi->encoder); |
c8afe684 RC |
503 | |
504 | return connector; | |
505 | ||
506 | fail: | |
507 | if (connector) | |
508 | hdmi_connector_destroy(connector); | |
509 | ||
510 | return ERR_PTR(ret); | |
511 | } |