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c8afe684 RC |
1 | /* |
2 | * Copyright (C) 2013 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | #include "mdp4_kms.h" | |
19 | ||
20 | #include <drm/drm_mode.h> | |
21 | #include "drm_crtc.h" | |
22 | #include "drm_crtc_helper.h" | |
23 | #include "drm_flip_work.h" | |
24 | ||
25 | struct mdp4_crtc { | |
26 | struct drm_crtc base; | |
27 | char name[8]; | |
28 | struct drm_plane *plane; | |
a8623918 | 29 | struct drm_plane *planes[8]; |
c8afe684 RC |
30 | int id; |
31 | int ovlp; | |
32 | enum mdp4_dma dma; | |
33 | bool enabled; | |
34 | ||
35 | /* which mixer/encoder we route output to: */ | |
36 | int mixer; | |
37 | ||
38 | struct { | |
39 | spinlock_t lock; | |
40 | bool stale; | |
41 | uint32_t width, height; | |
aa1b0e59 | 42 | uint32_t x, y; |
c8afe684 RC |
43 | |
44 | /* next cursor to scan-out: */ | |
45 | uint32_t next_iova; | |
46 | struct drm_gem_object *next_bo; | |
47 | ||
48 | /* current cursor being scanned out: */ | |
49 | struct drm_gem_object *scanout_bo; | |
50 | } cursor; | |
51 | ||
52 | ||
53 | /* if there is a pending flip, these will be non-null: */ | |
54 | struct drm_pending_vblank_event *event; | |
edd4fc63 | 55 | struct msm_fence_cb pageflip_cb; |
c8afe684 | 56 | |
2a2b8fa6 RC |
57 | #define PENDING_CURSOR 0x1 |
58 | #define PENDING_FLIP 0x2 | |
59 | atomic_t pending; | |
60 | ||
b69720c0 RC |
61 | /* the fb that we logically (from PoV of KMS API) hold a ref |
62 | * to. Which we may not yet be scanning out (we may still | |
63 | * be scanning out previous in case of page_flip while waiting | |
64 | * for gpu rendering to complete: | |
65 | */ | |
c8afe684 RC |
66 | struct drm_framebuffer *fb; |
67 | ||
b69720c0 RC |
68 | /* the fb that we currently hold a scanout ref to: */ |
69 | struct drm_framebuffer *scanout_fb; | |
70 | ||
c8afe684 RC |
71 | /* for unref'ing framebuffers after scanout completes: */ |
72 | struct drm_flip_work unref_fb_work; | |
73 | ||
74 | /* for unref'ing cursor bo's after scanout completes: */ | |
75 | struct drm_flip_work unref_cursor_work; | |
76 | ||
9e0efa63 RC |
77 | struct mdp_irq vblank; |
78 | struct mdp_irq err; | |
c8afe684 RC |
79 | }; |
80 | #define to_mdp4_crtc(x) container_of(x, struct mdp4_crtc, base) | |
81 | ||
82 | static struct mdp4_kms *get_kms(struct drm_crtc *crtc) | |
83 | { | |
84 | struct msm_drm_private *priv = crtc->dev->dev_private; | |
9e0efa63 | 85 | return to_mdp4_kms(to_mdp_kms(priv->kms)); |
c8afe684 RC |
86 | } |
87 | ||
b69720c0 | 88 | static void request_pending(struct drm_crtc *crtc, uint32_t pending) |
c8afe684 RC |
89 | { |
90 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
c8afe684 | 91 | |
b69720c0 RC |
92 | atomic_or(pending, &mdp4_crtc->pending); |
93 | mdp_irq_register(&get_kms(crtc)->base, &mdp4_crtc->vblank); | |
94 | } | |
95 | ||
96 | static void crtc_flush(struct drm_crtc *crtc) | |
97 | { | |
98 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
99 | struct mdp4_kms *mdp4_kms = get_kms(crtc); | |
100 | uint32_t i, flush = 0; | |
101 | ||
102 | for (i = 0; i < ARRAY_SIZE(mdp4_crtc->planes); i++) { | |
103 | struct drm_plane *plane = mdp4_crtc->planes[i]; | |
104 | if (plane) { | |
105 | enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane); | |
106 | flush |= pipe2flush(pipe_id); | |
107 | } | |
108 | } | |
109 | flush |= ovlp2flush(mdp4_crtc->ovlp); | |
110 | ||
111 | DBG("%s: flush=%08x", mdp4_crtc->name, flush); | |
112 | ||
113 | mdp4_write(mdp4_kms, REG_MDP4_OVERLAY_FLUSH, flush); | |
114 | } | |
115 | ||
116 | static void update_fb(struct drm_crtc *crtc, struct drm_framebuffer *new_fb) | |
117 | { | |
118 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
119 | struct drm_framebuffer *old_fb = mdp4_crtc->fb; | |
c8afe684 RC |
120 | |
121 | /* grab reference to incoming scanout fb: */ | |
122 | drm_framebuffer_reference(new_fb); | |
f4510a27 | 123 | mdp4_crtc->base.primary->fb = new_fb; |
c8afe684 RC |
124 | mdp4_crtc->fb = new_fb; |
125 | ||
b69720c0 RC |
126 | if (old_fb) |
127 | drm_flip_work_queue(&mdp4_crtc->unref_fb_work, old_fb); | |
128 | } | |
129 | ||
130 | /* unlike update_fb(), take a ref to the new scanout fb *before* updating | |
131 | * plane, then call this. Needed to ensure we don't unref the buffer that | |
132 | * is actually still being scanned out. | |
133 | * | |
134 | * Note that this whole thing goes away with atomic.. since we can defer | |
135 | * calling into driver until rendering is done. | |
136 | */ | |
137 | static void update_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb) | |
138 | { | |
139 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
140 | ||
141 | /* flush updates, to make sure hw is updated to new scanout fb, | |
142 | * so that we can safely queue unref to current fb (ie. next | |
143 | * vblank we know hw is done w/ previous scanout_fb). | |
144 | */ | |
145 | crtc_flush(crtc); | |
146 | ||
147 | if (mdp4_crtc->scanout_fb) | |
148 | drm_flip_work_queue(&mdp4_crtc->unref_fb_work, | |
149 | mdp4_crtc->scanout_fb); | |
150 | ||
151 | mdp4_crtc->scanout_fb = fb; | |
152 | ||
153 | /* enable vblank to complete flip: */ | |
154 | request_pending(crtc, PENDING_FLIP); | |
c8afe684 RC |
155 | } |
156 | ||
2a2b8fa6 RC |
157 | /* if file!=NULL, this is preclose potential cancel-flip path */ |
158 | static void complete_flip(struct drm_crtc *crtc, struct drm_file *file) | |
c8afe684 RC |
159 | { |
160 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
161 | struct drm_device *dev = crtc->dev; | |
162 | struct drm_pending_vblank_event *event; | |
163 | unsigned long flags; | |
164 | ||
165 | spin_lock_irqsave(&dev->event_lock, flags); | |
166 | event = mdp4_crtc->event; | |
167 | if (event) { | |
2a2b8fa6 RC |
168 | /* if regular vblank case (!file) or if cancel-flip from |
169 | * preclose on file that requested flip, then send the | |
170 | * event: | |
171 | */ | |
172 | if (!file || (event->base.file_priv == file)) { | |
173 | mdp4_crtc->event = NULL; | |
c8afe684 | 174 | drm_send_vblank_event(dev, mdp4_crtc->id, event); |
2a2b8fa6 | 175 | } |
c8afe684 RC |
176 | } |
177 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
178 | } | |
179 | ||
edd4fc63 | 180 | static void pageflip_cb(struct msm_fence_cb *cb) |
c8afe684 RC |
181 | { |
182 | struct mdp4_crtc *mdp4_crtc = | |
edd4fc63 | 183 | container_of(cb, struct mdp4_crtc, pageflip_cb); |
c8afe684 | 184 | struct drm_crtc *crtc = &mdp4_crtc->base; |
f4510a27 | 185 | struct drm_framebuffer *fb = crtc->primary->fb; |
c8afe684 | 186 | |
2a2b8fa6 RC |
187 | if (!fb) |
188 | return; | |
189 | ||
b69720c0 | 190 | drm_framebuffer_reference(fb); |
2a2b8fa6 | 191 | mdp4_plane_set_scanout(mdp4_crtc->plane, fb); |
b69720c0 | 192 | update_scanout(crtc, fb); |
c8afe684 RC |
193 | } |
194 | ||
195 | static void unref_fb_worker(struct drm_flip_work *work, void *val) | |
196 | { | |
197 | struct mdp4_crtc *mdp4_crtc = | |
198 | container_of(work, struct mdp4_crtc, unref_fb_work); | |
199 | struct drm_device *dev = mdp4_crtc->base.dev; | |
200 | ||
201 | mutex_lock(&dev->mode_config.mutex); | |
202 | drm_framebuffer_unreference(val); | |
203 | mutex_unlock(&dev->mode_config.mutex); | |
204 | } | |
205 | ||
206 | static void unref_cursor_worker(struct drm_flip_work *work, void *val) | |
207 | { | |
208 | struct mdp4_crtc *mdp4_crtc = | |
209 | container_of(work, struct mdp4_crtc, unref_cursor_work); | |
210 | struct mdp4_kms *mdp4_kms = get_kms(&mdp4_crtc->base); | |
211 | ||
212 | msm_gem_put_iova(val, mdp4_kms->id); | |
213 | drm_gem_object_unreference_unlocked(val); | |
214 | } | |
215 | ||
216 | static void mdp4_crtc_destroy(struct drm_crtc *crtc) | |
217 | { | |
218 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
219 | ||
220 | mdp4_crtc->plane->funcs->destroy(mdp4_crtc->plane); | |
221 | ||
222 | drm_crtc_cleanup(crtc); | |
223 | drm_flip_work_cleanup(&mdp4_crtc->unref_fb_work); | |
224 | drm_flip_work_cleanup(&mdp4_crtc->unref_cursor_work); | |
225 | ||
226 | kfree(mdp4_crtc); | |
227 | } | |
228 | ||
229 | static void mdp4_crtc_dpms(struct drm_crtc *crtc, int mode) | |
230 | { | |
231 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
232 | struct mdp4_kms *mdp4_kms = get_kms(crtc); | |
233 | bool enabled = (mode == DRM_MODE_DPMS_ON); | |
234 | ||
235 | DBG("%s: mode=%d", mdp4_crtc->name, mode); | |
236 | ||
237 | if (enabled != mdp4_crtc->enabled) { | |
238 | if (enabled) { | |
239 | mdp4_enable(mdp4_kms); | |
9e0efa63 | 240 | mdp_irq_register(&mdp4_kms->base, &mdp4_crtc->err); |
c8afe684 | 241 | } else { |
9e0efa63 | 242 | mdp_irq_unregister(&mdp4_kms->base, &mdp4_crtc->err); |
c8afe684 RC |
243 | mdp4_disable(mdp4_kms); |
244 | } | |
245 | mdp4_crtc->enabled = enabled; | |
246 | } | |
247 | } | |
248 | ||
249 | static bool mdp4_crtc_mode_fixup(struct drm_crtc *crtc, | |
250 | const struct drm_display_mode *mode, | |
251 | struct drm_display_mode *adjusted_mode) | |
252 | { | |
253 | return true; | |
254 | } | |
255 | ||
256 | static void blend_setup(struct drm_crtc *crtc) | |
257 | { | |
258 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
259 | struct mdp4_kms *mdp4_kms = get_kms(crtc); | |
260 | int i, ovlp = mdp4_crtc->ovlp; | |
261 | uint32_t mixer_cfg = 0; | |
facb4f4e | 262 | static const enum mdp_mixer_stage_id stages[] = { |
a8623918 RC |
263 | STAGE_BASE, STAGE0, STAGE1, STAGE2, STAGE3, |
264 | }; | |
265 | /* statically (for now) map planes to mixer stage (z-order): */ | |
266 | static const int idxs[] = { | |
267 | [VG1] = 1, | |
268 | [VG2] = 2, | |
269 | [RGB1] = 0, | |
270 | [RGB2] = 0, | |
271 | [RGB3] = 0, | |
272 | [VG3] = 3, | |
273 | [VG4] = 4, | |
274 | ||
275 | }; | |
276 | bool alpha[4]= { false, false, false, false }; | |
c8afe684 RC |
277 | |
278 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW0(ovlp), 0); | |
279 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_LOW1(ovlp), 0); | |
280 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH0(ovlp), 0); | |
281 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_TRANSP_HIGH1(ovlp), 0); | |
282 | ||
a8623918 RC |
283 | /* TODO single register for all CRTCs, so this won't work properly |
284 | * when multiple CRTCs are active.. | |
285 | */ | |
286 | for (i = 0; i < ARRAY_SIZE(mdp4_crtc->planes); i++) { | |
287 | struct drm_plane *plane = mdp4_crtc->planes[i]; | |
288 | if (plane) { | |
289 | enum mdp4_pipe pipe_id = mdp4_plane_pipe(plane); | |
290 | int idx = idxs[pipe_id]; | |
291 | if (idx > 0) { | |
10a02eb6 RC |
292 | const struct mdp_format *format = |
293 | to_mdp_format(msm_framebuffer_format(plane->fb)); | |
a8623918 RC |
294 | alpha[idx-1] = format->alpha_enable; |
295 | } | |
296 | mixer_cfg |= mixercfg(mdp4_crtc->mixer, pipe_id, stages[idx]); | |
297 | } | |
298 | } | |
299 | ||
300 | /* this shouldn't happen.. and seems to cause underflow: */ | |
301 | WARN_ON(!mixer_cfg); | |
302 | ||
c8afe684 | 303 | for (i = 0; i < 4; i++) { |
a8623918 RC |
304 | uint32_t op; |
305 | ||
306 | if (alpha[i]) { | |
307 | op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_PIXEL) | | |
308 | MDP4_OVLP_STAGE_OP_BG_ALPHA(FG_PIXEL) | | |
309 | MDP4_OVLP_STAGE_OP_BG_INV_ALPHA; | |
310 | } else { | |
311 | op = MDP4_OVLP_STAGE_OP_FG_ALPHA(FG_CONST) | | |
312 | MDP4_OVLP_STAGE_OP_BG_ALPHA(BG_CONST); | |
313 | } | |
314 | ||
315 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_FG_ALPHA(ovlp, i), 0xff); | |
316 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_BG_ALPHA(ovlp, i), 0x00); | |
317 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_OP(ovlp, i), op); | |
318 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_CO3(ovlp, i), 1); | |
c8afe684 RC |
319 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW0(ovlp, i), 0); |
320 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_LOW1(ovlp, i), 0); | |
321 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(ovlp, i), 0); | |
322 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(ovlp, i), 0); | |
323 | } | |
324 | ||
c8afe684 RC |
325 | mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, mixer_cfg); |
326 | } | |
327 | ||
328 | static int mdp4_crtc_mode_set(struct drm_crtc *crtc, | |
329 | struct drm_display_mode *mode, | |
330 | struct drm_display_mode *adjusted_mode, | |
331 | int x, int y, | |
332 | struct drm_framebuffer *old_fb) | |
333 | { | |
334 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
335 | struct mdp4_kms *mdp4_kms = get_kms(crtc); | |
336 | enum mdp4_dma dma = mdp4_crtc->dma; | |
337 | int ret, ovlp = mdp4_crtc->ovlp; | |
338 | ||
339 | mode = adjusted_mode; | |
340 | ||
341 | DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x", | |
342 | mdp4_crtc->name, mode->base.id, mode->name, | |
343 | mode->vrefresh, mode->clock, | |
344 | mode->hdisplay, mode->hsync_start, | |
345 | mode->hsync_end, mode->htotal, | |
346 | mode->vdisplay, mode->vsync_start, | |
347 | mode->vsync_end, mode->vtotal, | |
348 | mode->type, mode->flags); | |
349 | ||
b69720c0 | 350 | /* grab extra ref for update_scanout() */ |
f4510a27 | 351 | drm_framebuffer_reference(crtc->primary->fb); |
b69720c0 | 352 | |
f4510a27 | 353 | ret = mdp4_plane_mode_set(mdp4_crtc->plane, crtc, crtc->primary->fb, |
b69720c0 RC |
354 | 0, 0, mode->hdisplay, mode->vdisplay, |
355 | x << 16, y << 16, | |
356 | mode->hdisplay << 16, mode->vdisplay << 16); | |
357 | if (ret) { | |
f4510a27 | 358 | drm_framebuffer_unreference(crtc->primary->fb); |
b69720c0 RC |
359 | dev_err(crtc->dev->dev, "%s: failed to set mode on plane: %d\n", |
360 | mdp4_crtc->name, ret); | |
361 | return ret; | |
362 | } | |
363 | ||
c8afe684 RC |
364 | mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_SIZE(dma), |
365 | MDP4_DMA_SRC_SIZE_WIDTH(mode->hdisplay) | | |
366 | MDP4_DMA_SRC_SIZE_HEIGHT(mode->vdisplay)); | |
367 | ||
368 | /* take data from pipe: */ | |
369 | mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_BASE(dma), 0); | |
370 | mdp4_write(mdp4_kms, REG_MDP4_DMA_SRC_STRIDE(dma), | |
f4510a27 | 371 | crtc->primary->fb->pitches[0]); |
c8afe684 RC |
372 | mdp4_write(mdp4_kms, REG_MDP4_DMA_DST_SIZE(dma), |
373 | MDP4_DMA_DST_SIZE_WIDTH(0) | | |
374 | MDP4_DMA_DST_SIZE_HEIGHT(0)); | |
375 | ||
376 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_BASE(ovlp), 0); | |
377 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_SIZE(ovlp), | |
378 | MDP4_OVLP_SIZE_WIDTH(mode->hdisplay) | | |
379 | MDP4_OVLP_SIZE_HEIGHT(mode->vdisplay)); | |
380 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_STRIDE(ovlp), | |
f4510a27 | 381 | crtc->primary->fb->pitches[0]); |
c8afe684 RC |
382 | |
383 | mdp4_write(mdp4_kms, REG_MDP4_OVLP_CFG(ovlp), 1); | |
384 | ||
c8afe684 RC |
385 | if (dma == DMA_E) { |
386 | mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(0), 0x00ff0000); | |
387 | mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(1), 0x00ff0000); | |
388 | mdp4_write(mdp4_kms, REG_MDP4_DMA_E_QUANT(2), 0x00ff0000); | |
389 | } | |
390 | ||
f4510a27 MR |
391 | update_fb(crtc, crtc->primary->fb); |
392 | update_scanout(crtc, crtc->primary->fb); | |
b69720c0 | 393 | |
c8afe684 RC |
394 | return 0; |
395 | } | |
396 | ||
397 | static void mdp4_crtc_prepare(struct drm_crtc *crtc) | |
398 | { | |
399 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
400 | DBG("%s", mdp4_crtc->name); | |
401 | /* make sure we hold a ref to mdp clks while setting up mode: */ | |
402 | mdp4_enable(get_kms(crtc)); | |
403 | mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); | |
404 | } | |
405 | ||
406 | static void mdp4_crtc_commit(struct drm_crtc *crtc) | |
407 | { | |
408 | mdp4_crtc_dpms(crtc, DRM_MODE_DPMS_ON); | |
409 | crtc_flush(crtc); | |
410 | /* drop the ref to mdp clk's that we got in prepare: */ | |
411 | mdp4_disable(get_kms(crtc)); | |
412 | } | |
413 | ||
414 | static int mdp4_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, | |
415 | struct drm_framebuffer *old_fb) | |
416 | { | |
417 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
418 | struct drm_plane *plane = mdp4_crtc->plane; | |
419 | struct drm_display_mode *mode = &crtc->mode; | |
b69720c0 | 420 | int ret; |
c8afe684 | 421 | |
b69720c0 | 422 | /* grab extra ref for update_scanout() */ |
f4510a27 | 423 | drm_framebuffer_reference(crtc->primary->fb); |
c8afe684 | 424 | |
f4510a27 | 425 | ret = mdp4_plane_mode_set(plane, crtc, crtc->primary->fb, |
c8afe684 RC |
426 | 0, 0, mode->hdisplay, mode->vdisplay, |
427 | x << 16, y << 16, | |
428 | mode->hdisplay << 16, mode->vdisplay << 16); | |
b69720c0 | 429 | if (ret) { |
f4510a27 | 430 | drm_framebuffer_unreference(crtc->primary->fb); |
b69720c0 RC |
431 | return ret; |
432 | } | |
433 | ||
f4510a27 MR |
434 | update_fb(crtc, crtc->primary->fb); |
435 | update_scanout(crtc, crtc->primary->fb); | |
b69720c0 RC |
436 | |
437 | return 0; | |
c8afe684 RC |
438 | } |
439 | ||
440 | static void mdp4_crtc_load_lut(struct drm_crtc *crtc) | |
441 | { | |
442 | } | |
443 | ||
444 | static int mdp4_crtc_page_flip(struct drm_crtc *crtc, | |
445 | struct drm_framebuffer *new_fb, | |
ed8d1975 KP |
446 | struct drm_pending_vblank_event *event, |
447 | uint32_t page_flip_flags) | |
c8afe684 RC |
448 | { |
449 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
450 | struct drm_device *dev = crtc->dev; | |
451 | struct drm_gem_object *obj; | |
2a2b8fa6 | 452 | unsigned long flags; |
c8afe684 RC |
453 | |
454 | if (mdp4_crtc->event) { | |
455 | dev_err(dev->dev, "already pending flip!\n"); | |
456 | return -EBUSY; | |
457 | } | |
458 | ||
459 | obj = msm_framebuffer_bo(new_fb, 0); | |
460 | ||
2a2b8fa6 | 461 | spin_lock_irqsave(&dev->event_lock, flags); |
c8afe684 | 462 | mdp4_crtc->event = event; |
2a2b8fa6 RC |
463 | spin_unlock_irqrestore(&dev->event_lock, flags); |
464 | ||
b69720c0 | 465 | update_fb(crtc, new_fb); |
c8afe684 | 466 | |
edd4fc63 | 467 | return msm_gem_queue_inactive_cb(obj, &mdp4_crtc->pageflip_cb); |
c8afe684 RC |
468 | } |
469 | ||
470 | static int mdp4_crtc_set_property(struct drm_crtc *crtc, | |
471 | struct drm_property *property, uint64_t val) | |
472 | { | |
473 | // XXX | |
474 | return -EINVAL; | |
475 | } | |
476 | ||
477 | #define CURSOR_WIDTH 64 | |
478 | #define CURSOR_HEIGHT 64 | |
479 | ||
480 | /* called from IRQ to update cursor related registers (if needed). The | |
481 | * cursor registers, other than x/y position, appear not to be double | |
482 | * buffered, and changing them other than from vblank seems to trigger | |
483 | * underflow. | |
484 | */ | |
485 | static void update_cursor(struct drm_crtc *crtc) | |
486 | { | |
487 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
aa1b0e59 | 488 | struct mdp4_kms *mdp4_kms = get_kms(crtc); |
c8afe684 RC |
489 | enum mdp4_dma dma = mdp4_crtc->dma; |
490 | unsigned long flags; | |
491 | ||
492 | spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags); | |
493 | if (mdp4_crtc->cursor.stale) { | |
c8afe684 RC |
494 | struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo; |
495 | struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo; | |
496 | uint32_t iova = mdp4_crtc->cursor.next_iova; | |
497 | ||
498 | if (next_bo) { | |
499 | /* take a obj ref + iova ref when we start scanning out: */ | |
500 | drm_gem_object_reference(next_bo); | |
501 | msm_gem_get_iova_locked(next_bo, mdp4_kms->id, &iova); | |
502 | ||
503 | /* enable cursor: */ | |
504 | mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_SIZE(dma), | |
505 | MDP4_DMA_CURSOR_SIZE_WIDTH(mdp4_crtc->cursor.width) | | |
506 | MDP4_DMA_CURSOR_SIZE_HEIGHT(mdp4_crtc->cursor.height)); | |
507 | mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), iova); | |
508 | mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma), | |
509 | MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB) | | |
510 | MDP4_DMA_CURSOR_BLEND_CONFIG_CURSOR_EN); | |
511 | } else { | |
512 | /* disable cursor: */ | |
513 | mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BASE(dma), 0); | |
514 | mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_BLEND_CONFIG(dma), | |
515 | MDP4_DMA_CURSOR_BLEND_CONFIG_FORMAT(CURSOR_ARGB)); | |
516 | } | |
517 | ||
518 | /* and drop the iova ref + obj rev when done scanning out: */ | |
519 | if (prev_bo) | |
520 | drm_flip_work_queue(&mdp4_crtc->unref_cursor_work, prev_bo); | |
521 | ||
522 | mdp4_crtc->cursor.scanout_bo = next_bo; | |
523 | mdp4_crtc->cursor.stale = false; | |
524 | } | |
aa1b0e59 RC |
525 | |
526 | mdp4_write(mdp4_kms, REG_MDP4_DMA_CURSOR_POS(dma), | |
527 | MDP4_DMA_CURSOR_POS_X(mdp4_crtc->cursor.x) | | |
528 | MDP4_DMA_CURSOR_POS_Y(mdp4_crtc->cursor.y)); | |
529 | ||
c8afe684 RC |
530 | spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags); |
531 | } | |
532 | ||
533 | static int mdp4_crtc_cursor_set(struct drm_crtc *crtc, | |
534 | struct drm_file *file_priv, uint32_t handle, | |
535 | uint32_t width, uint32_t height) | |
536 | { | |
537 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
538 | struct mdp4_kms *mdp4_kms = get_kms(crtc); | |
539 | struct drm_device *dev = crtc->dev; | |
540 | struct drm_gem_object *cursor_bo, *old_bo; | |
541 | unsigned long flags; | |
542 | uint32_t iova; | |
543 | int ret; | |
544 | ||
545 | if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) { | |
546 | dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height); | |
547 | return -EINVAL; | |
548 | } | |
549 | ||
550 | if (handle) { | |
551 | cursor_bo = drm_gem_object_lookup(dev, file_priv, handle); | |
552 | if (!cursor_bo) | |
553 | return -ENOENT; | |
554 | } else { | |
555 | cursor_bo = NULL; | |
556 | } | |
557 | ||
558 | if (cursor_bo) { | |
559 | ret = msm_gem_get_iova(cursor_bo, mdp4_kms->id, &iova); | |
560 | if (ret) | |
561 | goto fail; | |
562 | } else { | |
563 | iova = 0; | |
564 | } | |
565 | ||
566 | spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags); | |
567 | old_bo = mdp4_crtc->cursor.next_bo; | |
568 | mdp4_crtc->cursor.next_bo = cursor_bo; | |
569 | mdp4_crtc->cursor.next_iova = iova; | |
570 | mdp4_crtc->cursor.width = width; | |
571 | mdp4_crtc->cursor.height = height; | |
572 | mdp4_crtc->cursor.stale = true; | |
573 | spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags); | |
574 | ||
575 | if (old_bo) { | |
576 | /* drop our previous reference: */ | |
577 | msm_gem_put_iova(old_bo, mdp4_kms->id); | |
578 | drm_gem_object_unreference_unlocked(old_bo); | |
579 | } | |
580 | ||
aa1b0e59 | 581 | crtc_flush(crtc); |
2a2b8fa6 RC |
582 | request_pending(crtc, PENDING_CURSOR); |
583 | ||
c8afe684 RC |
584 | return 0; |
585 | ||
586 | fail: | |
587 | drm_gem_object_unreference_unlocked(cursor_bo); | |
588 | return ret; | |
589 | } | |
590 | ||
591 | static int mdp4_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
592 | { | |
593 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
aa1b0e59 | 594 | unsigned long flags; |
c8afe684 | 595 | |
aa1b0e59 RC |
596 | spin_lock_irqsave(&mdp4_crtc->cursor.lock, flags); |
597 | mdp4_crtc->cursor.x = x; | |
598 | mdp4_crtc->cursor.y = y; | |
599 | spin_unlock_irqrestore(&mdp4_crtc->cursor.lock, flags); | |
600 | ||
601 | crtc_flush(crtc); | |
602 | request_pending(crtc, PENDING_CURSOR); | |
c8afe684 RC |
603 | |
604 | return 0; | |
605 | } | |
606 | ||
607 | static const struct drm_crtc_funcs mdp4_crtc_funcs = { | |
608 | .set_config = drm_crtc_helper_set_config, | |
609 | .destroy = mdp4_crtc_destroy, | |
610 | .page_flip = mdp4_crtc_page_flip, | |
611 | .set_property = mdp4_crtc_set_property, | |
612 | .cursor_set = mdp4_crtc_cursor_set, | |
613 | .cursor_move = mdp4_crtc_cursor_move, | |
614 | }; | |
615 | ||
616 | static const struct drm_crtc_helper_funcs mdp4_crtc_helper_funcs = { | |
617 | .dpms = mdp4_crtc_dpms, | |
618 | .mode_fixup = mdp4_crtc_mode_fixup, | |
619 | .mode_set = mdp4_crtc_mode_set, | |
620 | .prepare = mdp4_crtc_prepare, | |
621 | .commit = mdp4_crtc_commit, | |
622 | .mode_set_base = mdp4_crtc_mode_set_base, | |
623 | .load_lut = mdp4_crtc_load_lut, | |
624 | }; | |
625 | ||
9e0efa63 | 626 | static void mdp4_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus) |
c8afe684 RC |
627 | { |
628 | struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, vblank); | |
629 | struct drm_crtc *crtc = &mdp4_crtc->base; | |
630 | struct msm_drm_private *priv = crtc->dev->dev_private; | |
2a2b8fa6 | 631 | unsigned pending; |
c8afe684 | 632 | |
9e0efa63 | 633 | mdp_irq_unregister(&get_kms(crtc)->base, &mdp4_crtc->vblank); |
c8afe684 | 634 | |
2a2b8fa6 RC |
635 | pending = atomic_xchg(&mdp4_crtc->pending, 0); |
636 | ||
637 | if (pending & PENDING_FLIP) { | |
638 | complete_flip(crtc, NULL); | |
639 | drm_flip_work_commit(&mdp4_crtc->unref_fb_work, priv->wq); | |
640 | } | |
641 | ||
642 | if (pending & PENDING_CURSOR) { | |
643 | update_cursor(crtc); | |
644 | drm_flip_work_commit(&mdp4_crtc->unref_cursor_work, priv->wq); | |
645 | } | |
c8afe684 RC |
646 | } |
647 | ||
9e0efa63 | 648 | static void mdp4_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus) |
c8afe684 RC |
649 | { |
650 | struct mdp4_crtc *mdp4_crtc = container_of(irq, struct mdp4_crtc, err); | |
651 | struct drm_crtc *crtc = &mdp4_crtc->base; | |
652 | DBG("%s: error: %08x", mdp4_crtc->name, irqstatus); | |
653 | crtc_flush(crtc); | |
654 | } | |
655 | ||
656 | uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc) | |
657 | { | |
658 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
659 | return mdp4_crtc->vblank.irqmask; | |
660 | } | |
661 | ||
2a2b8fa6 | 662 | void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file) |
c8afe684 | 663 | { |
2a2b8fa6 RC |
664 | DBG("cancel: %p", file); |
665 | complete_flip(crtc, file); | |
c8afe684 RC |
666 | } |
667 | ||
668 | /* set dma config, ie. the format the encoder wants. */ | |
669 | void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config) | |
670 | { | |
671 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
672 | struct mdp4_kms *mdp4_kms = get_kms(crtc); | |
673 | ||
674 | mdp4_write(mdp4_kms, REG_MDP4_DMA_CONFIG(mdp4_crtc->dma), config); | |
675 | } | |
676 | ||
677 | /* set interface for routing crtc->encoder: */ | |
678 | void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf) | |
679 | { | |
680 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
681 | struct mdp4_kms *mdp4_kms = get_kms(crtc); | |
682 | uint32_t intf_sel; | |
683 | ||
684 | intf_sel = mdp4_read(mdp4_kms, REG_MDP4_DISP_INTF_SEL); | |
685 | ||
686 | switch (mdp4_crtc->dma) { | |
687 | case DMA_P: | |
688 | intf_sel &= ~MDP4_DISP_INTF_SEL_PRIM__MASK; | |
689 | intf_sel |= MDP4_DISP_INTF_SEL_PRIM(intf); | |
690 | break; | |
691 | case DMA_S: | |
692 | intf_sel &= ~MDP4_DISP_INTF_SEL_SEC__MASK; | |
693 | intf_sel |= MDP4_DISP_INTF_SEL_SEC(intf); | |
694 | break; | |
695 | case DMA_E: | |
696 | intf_sel &= ~MDP4_DISP_INTF_SEL_EXT__MASK; | |
697 | intf_sel |= MDP4_DISP_INTF_SEL_EXT(intf); | |
698 | break; | |
699 | } | |
700 | ||
701 | if (intf == INTF_DSI_VIDEO) { | |
702 | intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_CMD; | |
703 | intf_sel |= MDP4_DISP_INTF_SEL_DSI_VIDEO; | |
704 | mdp4_crtc->mixer = 0; | |
705 | } else if (intf == INTF_DSI_CMD) { | |
706 | intf_sel &= ~MDP4_DISP_INTF_SEL_DSI_VIDEO; | |
707 | intf_sel |= MDP4_DISP_INTF_SEL_DSI_CMD; | |
708 | mdp4_crtc->mixer = 0; | |
709 | } else if (intf == INTF_LCDC_DTV){ | |
710 | mdp4_crtc->mixer = 1; | |
711 | } | |
712 | ||
713 | blend_setup(crtc); | |
714 | ||
715 | DBG("%s: intf_sel=%08x", mdp4_crtc->name, intf_sel); | |
716 | ||
717 | mdp4_write(mdp4_kms, REG_MDP4_DISP_INTF_SEL, intf_sel); | |
718 | } | |
719 | ||
a8623918 RC |
720 | static void set_attach(struct drm_crtc *crtc, enum mdp4_pipe pipe_id, |
721 | struct drm_plane *plane) | |
722 | { | |
723 | struct mdp4_crtc *mdp4_crtc = to_mdp4_crtc(crtc); | |
724 | ||
725 | BUG_ON(pipe_id >= ARRAY_SIZE(mdp4_crtc->planes)); | |
726 | ||
727 | if (mdp4_crtc->planes[pipe_id] == plane) | |
728 | return; | |
729 | ||
730 | mdp4_crtc->planes[pipe_id] = plane; | |
731 | blend_setup(crtc); | |
732 | if (mdp4_crtc->enabled && (plane != mdp4_crtc->plane)) | |
733 | crtc_flush(crtc); | |
734 | } | |
735 | ||
736 | void mdp4_crtc_attach(struct drm_crtc *crtc, struct drm_plane *plane) | |
737 | { | |
738 | set_attach(crtc, mdp4_plane_pipe(plane), plane); | |
739 | } | |
740 | ||
741 | void mdp4_crtc_detach(struct drm_crtc *crtc, struct drm_plane *plane) | |
742 | { | |
2d82d188 MR |
743 | /* don't actually detatch our primary plane: */ |
744 | if (to_mdp4_crtc(crtc)->plane == plane) | |
745 | return; | |
a8623918 RC |
746 | set_attach(crtc, mdp4_plane_pipe(plane), NULL); |
747 | } | |
748 | ||
c8afe684 RC |
749 | static const char *dma_names[] = { |
750 | "DMA_P", "DMA_S", "DMA_E", | |
751 | }; | |
752 | ||
753 | /* initialize crtc */ | |
754 | struct drm_crtc *mdp4_crtc_init(struct drm_device *dev, | |
755 | struct drm_plane *plane, int id, int ovlp_id, | |
756 | enum mdp4_dma dma_id) | |
757 | { | |
758 | struct drm_crtc *crtc = NULL; | |
759 | struct mdp4_crtc *mdp4_crtc; | |
760 | int ret; | |
761 | ||
762 | mdp4_crtc = kzalloc(sizeof(*mdp4_crtc), GFP_KERNEL); | |
763 | if (!mdp4_crtc) { | |
764 | ret = -ENOMEM; | |
765 | goto fail; | |
766 | } | |
767 | ||
768 | crtc = &mdp4_crtc->base; | |
769 | ||
770 | mdp4_crtc->plane = plane; | |
b69720c0 | 771 | mdp4_crtc->id = id; |
c8afe684 RC |
772 | |
773 | mdp4_crtc->ovlp = ovlp_id; | |
774 | mdp4_crtc->dma = dma_id; | |
775 | ||
776 | mdp4_crtc->vblank.irqmask = dma2irq(mdp4_crtc->dma); | |
777 | mdp4_crtc->vblank.irq = mdp4_crtc_vblank_irq; | |
778 | ||
779 | mdp4_crtc->err.irqmask = dma2err(mdp4_crtc->dma); | |
780 | mdp4_crtc->err.irq = mdp4_crtc_err_irq; | |
781 | ||
782 | snprintf(mdp4_crtc->name, sizeof(mdp4_crtc->name), "%s:%d", | |
783 | dma_names[dma_id], ovlp_id); | |
784 | ||
785 | spin_lock_init(&mdp4_crtc->cursor.lock); | |
786 | ||
787 | ret = drm_flip_work_init(&mdp4_crtc->unref_fb_work, 16, | |
788 | "unref fb", unref_fb_worker); | |
789 | if (ret) | |
790 | goto fail; | |
791 | ||
792 | ret = drm_flip_work_init(&mdp4_crtc->unref_cursor_work, 64, | |
793 | "unref cursor", unref_cursor_worker); | |
794 | ||
edd4fc63 | 795 | INIT_FENCE_CB(&mdp4_crtc->pageflip_cb, pageflip_cb); |
c8afe684 | 796 | |
2d82d188 | 797 | drm_crtc_init_with_planes(dev, crtc, plane, NULL, &mdp4_crtc_funcs); |
c8afe684 RC |
798 | drm_crtc_helper_add(crtc, &mdp4_crtc_helper_funcs); |
799 | ||
800 | mdp4_plane_install_properties(mdp4_crtc->plane, &crtc->base); | |
801 | ||
802 | return crtc; | |
803 | ||
804 | fail: | |
805 | if (crtc) | |
806 | mdp4_crtc_destroy(crtc); | |
807 | ||
808 | return ERR_PTR(ret); | |
809 | } |