[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / msm / mdp / mdp4 / mdp4_kms.h

/*
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <robdclark@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __MDP4_KMS_H__
#define __MDP4_KMS_H__

#include "msm_drv.h"
#include "msm_kms.h"
#include "mdp/mdp_kms.h"
#include "mdp4.xml.h"

#include "drm_panel.h"

struct mdp4_kms {
	struct mdp_kms base;

	struct drm_device *dev;

	int rev;

	/* mapper-id used to request GEM buffer mapped for scanout: */
	int id;

	void __iomem *mmio;

	struct regulator *vdd;

	struct clk *clk;
	struct clk *pclk;
	struct clk *lut_clk;
	struct clk *axi_clk;
	struct msm_gem_address_space *aspace;

	struct mdp_irq error_handler;

	bool rpm_enabled;

	/* empty/blank cursor bo to use when cursor is "disabled" */
	struct drm_gem_object *blank_cursor_bo;
	uint32_t blank_cursor_iova;
};
#define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)

/* platform config data (ie. from DT, or pdata) */
struct mdp4_platform_config {
	struct iommu_domain *iommu;
	uint32_t max_clk;
};

static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
{
	msm_writel(data, mdp4_kms->mmio + reg);
}

static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
{
	return msm_readl(mdp4_kms->mmio + reg);
}

static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
{
	switch (pipe) {
	case VG1:      return MDP4_OVERLAY_FLUSH_VG1;
	case VG2:      return MDP4_OVERLAY_FLUSH_VG2;
	case RGB1:     return MDP4_OVERLAY_FLUSH_RGB1;
	case RGB2:     return MDP4_OVERLAY_FLUSH_RGB2;
	default:       return 0;
	}
}

static inline uint32_t ovlp2flush(int ovlp)
{
	switch (ovlp) {
	case 0:        return MDP4_OVERLAY_FLUSH_OVLP0;
	case 1:        return MDP4_OVERLAY_FLUSH_OVLP1;
	default:       return 0;
	}
}

static inline uint32_t dma2irq(enum mdp4_dma dma)
{
	switch (dma) {
	case DMA_P:    return MDP4_IRQ_DMA_P_DONE;
	case DMA_S:    return MDP4_IRQ_DMA_S_DONE;
	case DMA_E:    return MDP4_IRQ_DMA_E_DONE;
	default:       return 0;
	}
}

static inline uint32_t dma2err(enum mdp4_dma dma)
{
	switch (dma) {
	case DMA_P:    return MDP4_IRQ_PRIMARY_INTF_UDERRUN;
	case DMA_S:    return 0;  // ???
	case DMA_E:    return MDP4_IRQ_EXTERNAL_INTF_UDERRUN;
	default:       return 0;
	}
}

static inline uint32_t mixercfg(uint32_t mixer_cfg, int mixer,
		enum mdp4_pipe pipe, enum mdp_mixer_stage_id stage)
{
	switch (pipe) {
	case VG1:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE0(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
		break;
	case VG2:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE1(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
		break;
	case RGB1:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE2(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
		break;
	case RGB2:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE3(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
		break;
	case RGB3:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE4(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
		break;
	case VG3:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE5(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
		break;
	case VG4:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE6(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
		break;
	default:
		WARN(1, "invalid pipe");
		break;
	}

	return mixer_cfg;
}

int mdp4_disable(struct mdp4_kms *mdp4_kms);
int mdp4_enable(struct mdp4_kms *mdp4_kms);

void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
		uint32_t old_irqmask);
void mdp4_irq_preinstall(struct msm_kms *kms);
int mdp4_irq_postinstall(struct msm_kms *kms);
void mdp4_irq_uninstall(struct msm_kms *kms);
irqreturn_t mdp4_irq(struct msm_kms *kms);
int mdp4_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
void mdp4_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);

static inline uint32_t mdp4_pipe_caps(enum mdp4_pipe pipe)
{
	switch (pipe) {
	case VG1:
	case VG2:
	case VG3:
	case VG4:
		return MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
	case RGB1:
	case RGB2:
	case RGB3:
		return MDP_PIPE_CAP_SCALE;
	default:
		return 0;
	}
}

enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane);
struct drm_plane *mdp4_plane_init(struct drm_device *dev,
		enum mdp4_pipe pipe_id, bool private_plane);

uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc);
void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config);
void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer);
void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc);
struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
		struct drm_plane *plane, int id, int ovlp_id,
		enum mdp4_dma dma_id);

long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev);

long mdp4_lcdc_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev,
		struct device_node *panel_node);

struct drm_connector *mdp4_lvds_connector_init(struct drm_device *dev,
		struct device_node *panel_node, struct drm_encoder *encoder);

#ifdef CONFIG_DRM_MSM_DSI
struct drm_encoder *mdp4_dsi_encoder_init(struct drm_device *dev);
#else
static inline struct drm_encoder *mdp4_dsi_encoder_init(struct drm_device *dev)
{
	return ERR_PTR(-ENODEV);
}
#endif

#ifdef CONFIG_COMMON_CLK
struct clk *mpd4_lvds_pll_init(struct drm_device *dev);
#else
static inline struct clk *mpd4_lvds_pll_init(struct drm_device *dev)
{
	return ERR_PTR(-ENODEV);
}
#endif

#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
static inline int match_dev_name(struct device *dev, void *data)
{
	return !strcmp(dev_name(dev), data);
}
/* bus scaling data is associated with extra pointless platform devices,
 * "dtv", etc.. this is a bit of a hack, but we need a way for encoders
 * to find their pdata to make the bus-scaling stuff work.
 */
static inline void *mdp4_find_pdata(const char *devname)
{
	struct device *dev;
	dev = bus_find_device(&platform_bus_type, NULL,
			(void *)devname, match_dev_name);
	return dev ? dev->platform_data : NULL;
}
#endif

#endif /* __MDP4_KMS_H__ */
Commit	Line	Data
c8afe684 RC	1	/*
	2	* Copyright (C) 2013 Red Hat
	3	* Author: Rob Clark <robdclark@gmail.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published by
	7	* the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#ifndef __MDP4_KMS_H__
	19	#define __MDP4_KMS_H__
	20
c8afe684	21	#include "msm_drv.h"
dd2da6e3	22	#include "msm_kms.h"
10a02eb6	23	#include "mdp/mdp_kms.h"
c8afe684 RC	24	#include "mdp4.xml.h"
c8afe684 RC	25
3e87599b RC	26	#include "drm_panel.h"
3e87599b RC	27
c8afe684	28	struct mdp4_kms {
9e0efa63	29	struct mdp_kms base;
c8afe684 RC	30
	31	struct drm_device *dev;
	32
	33	int rev;
	34
	35	/* mapper-id used to request GEM buffer mapped for scanout: */
	36	int id;
	37
	38	void __iomem *mmio;
	39
c8afe684 RC	40	struct regulator *vdd;
	41
	42	struct clk *clk;
	43	struct clk *pclk;
	44	struct clk *lut_clk;
e8abb5b5	45	struct clk *axi_clk;
667ce33e	46	struct msm_gem_address_space *aspace;
c8afe684	47
9e0efa63	48	struct mdp_irq error_handler;
7d8d9f67	49
cd792726 AT	50	bool rpm_enabled;
cd792726 AT	51
7d8d9f67 RC	52	/* empty/blank cursor bo to use when cursor is "disabled" */
	53	struct drm_gem_object *blank_cursor_bo;
	54	uint32_t blank_cursor_iova;
c8afe684 RC	55	};
	56	#define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)
	57
	58	/* platform config data (ie. from DT, or pdata) */
	59	struct mdp4_platform_config {
	60	struct iommu_domain *iommu;
	61	uint32_t max_clk;
	62	};
	63
c8afe684 RC	64	static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
	65	{
	66	msm_writel(data, mdp4_kms->mmio + reg);
	67	}
	68
	69	static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
	70	{
	71	return msm_readl(mdp4_kms->mmio + reg);
	72	}
	73
22ba8b6b	74	static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
c8afe684 RC	75	{
	76	switch (pipe) {
	77	case VG1: return MDP4_OVERLAY_FLUSH_VG1;
	78	case VG2: return MDP4_OVERLAY_FLUSH_VG2;
	79	case RGB1: return MDP4_OVERLAY_FLUSH_RGB1;
f9a1ca5c	80	case RGB2: return MDP4_OVERLAY_FLUSH_RGB2;
c8afe684 RC	81	default: return 0;
	82	}
	83	}
	84
	85	static inline uint32_t ovlp2flush(int ovlp)
	86	{
	87	switch (ovlp) {
	88	case 0: return MDP4_OVERLAY_FLUSH_OVLP0;
	89	case 1: return MDP4_OVERLAY_FLUSH_OVLP1;
	90	default: return 0;
	91	}
	92	}
	93
	94	static inline uint32_t dma2irq(enum mdp4_dma dma)
	95	{
	96	switch (dma) {
	97	case DMA_P: return MDP4_IRQ_DMA_P_DONE;
	98	case DMA_S: return MDP4_IRQ_DMA_S_DONE;
	99	case DMA_E: return MDP4_IRQ_DMA_E_DONE;
	100	default: return 0;
	101	}
	102	}
	103
	104	static inline uint32_t dma2err(enum mdp4_dma dma)
	105	{
	106	switch (dma) {
	107	case DMA_P: return MDP4_IRQ_PRIMARY_INTF_UDERRUN;
	108	case DMA_S: return 0; // ???
	109	case DMA_E: return MDP4_IRQ_EXTERNAL_INTF_UDERRUN;
	110	default: return 0;
	111	}
	112	}
	113
d65bd0e4 RC	114	static inline uint32_t mixercfg(uint32_t mixer_cfg, int mixer,
d65bd0e4 RC	115	enum mdp4_pipe pipe, enum mdp_mixer_stage_id stage)
a8623918	116	{
a8623918 RC	117	switch (pipe) {
a8623918 RC	118	case VG1:
d65bd0e4 RC	119	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK \|
	120	MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
	121	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE0(stage) \|
a8623918 RC	122	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
	123	break;
	124	case VG2:
d65bd0e4 RC	125	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK \|
	126	MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
	127	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE1(stage) \|
a8623918 RC	128	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
	129	break;
	130	case RGB1:
d65bd0e4 RC	131	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK \|
	132	MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
	133	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE2(stage) \|
a8623918 RC	134	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
	135	break;
	136	case RGB2:
d65bd0e4 RC	137	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK \|
	138	MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
	139	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE3(stage) \|
a8623918 RC	140	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
	141	break;
	142	case RGB3:
d65bd0e4 RC	143	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK \|
	144	MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
	145	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE4(stage) \|
a8623918 RC	146	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
	147	break;
	148	case VG3:
d65bd0e4 RC	149	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK \|
	150	MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
	151	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE5(stage) \|
a8623918 RC	152	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
	153	break;
	154	case VG4:
d65bd0e4 RC	155	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK \|
	156	MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
	157	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE6(stage) \|
a8623918 RC	158	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
	159	break;
	160	default:
2abd1c88	161	WARN(1, "invalid pipe");
a8623918 RC	162	break;
	163	}
	164
	165	return mixer_cfg;
	166	}
	167
c8afe684 RC	168	int mdp4_disable(struct mdp4_kms *mdp4_kms);
	169	int mdp4_enable(struct mdp4_kms *mdp4_kms);
	170
29f034d7	171	void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
29f034d7	172	uint32_t old_irqmask);
c8afe684 RC	173	void mdp4_irq_preinstall(struct msm_kms *kms);
	174	int mdp4_irq_postinstall(struct msm_kms *kms);
	175	void mdp4_irq_uninstall(struct msm_kms *kms);
	176	irqreturn_t mdp4_irq(struct msm_kms *kms);
c8afe684 RC	177	int mdp4_enable_vblank(struct msm_kms kms, struct drm_crtc crtc);
	178	void mdp4_disable_vblank(struct msm_kms kms, struct drm_crtc crtc);
	179
3498409f	180	static inline uint32_t mdp4_pipe_caps(enum mdp4_pipe pipe)
7ca12718 SV	181	{
	182	switch (pipe) {
	183	case VG1:
	184	case VG2:
	185	case VG3:
	186	case VG4:
3498409f	187	return MDP_PIPE_CAP_HFLIP \| MDP_PIPE_CAP_VFLIP \|
	188	MDP_PIPE_CAP_SCALE \| MDP_PIPE_CAP_CSC;
	189	case RGB1:
	190	case RGB2:
	191	case RGB3:
	192	return MDP_PIPE_CAP_SCALE;
7ca12718	193	default:
3498409f	194	return 0;
7ca12718 SV	195	}
	196	}
	197
22ba8b6b	198	enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane);
c8afe684	199	struct drm_plane mdp4_plane_init(struct drm_device dev,
22ba8b6b	200	enum mdp4_pipe pipe_id, bool private_plane);
c8afe684 RC	201
c8afe684 RC	202	uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc);
c8afe684	203	void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config);
d65bd0e4	204	void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer);
0a5c9aad	205	void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc);
c8afe684 RC	206	struct drm_crtc mdp4_crtc_init(struct drm_device dev,
	207	struct drm_plane *plane, int id, int ovlp_id,
	208	enum mdp4_dma dma_id);
	209
	210	long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
	211	struct drm_encoder mdp4_dtv_encoder_init(struct drm_device dev);
	212
3e87599b RC	213	long mdp4_lcdc_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
3e87599b RC	214	struct drm_encoder mdp4_lcdc_encoder_init(struct drm_device dev,
a6bf7f63	215	struct device_node *panel_node);
3e87599b RC	216
3e87599b RC	217	struct drm_connector mdp4_lvds_connector_init(struct drm_device dev,
a6bf7f63	218	struct device_node panel_node, struct drm_encoder encoder);
3e87599b	219
776638e7 VSB	220	#ifdef CONFIG_DRM_MSM_DSI
	221	struct drm_encoder mdp4_dsi_encoder_init(struct drm_device dev);
	222	#else
	223	static inline struct drm_encoder mdp4_dsi_encoder_init(struct drm_device dev)
	224	{
	225	return ERR_PTR(-ENODEV);
	226	}
	227	#endif
	228
3e87599b RC	229	#ifdef CONFIG_COMMON_CLK
	230	struct clk mpd4_lvds_pll_init(struct drm_device dev);
	231	#else
	232	static inline struct clk mpd4_lvds_pll_init(struct drm_device dev)
	233	{
	234	return ERR_PTR(-ENODEV);
	235	}
	236	#endif
	237
6490ad47	238	#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
c8afe684 RC	239	static inline int match_dev_name(struct device dev, void data)
	240	{
	241	return !strcmp(dev_name(dev), data);
	242	}
	243	/* bus scaling data is associated with extra pointless platform devices,
	244	* "dtv", etc.. this is a bit of a hack, but we need a way for encoders
	245	* to find their pdata to make the bus-scaling stuff work.
	246	*/
	247	static inline void mdp4_find_pdata(const char devname)
	248	{
	249	struct device *dev;
	250	dev = bus_find_device(&platform_bus_type, NULL,
	251	(void *)devname, match_dev_name);
	252	return dev ? dev->platform_data : NULL;
	253	}
	254	#endif
	255
	256	#endif /* __MDP4_KMS_H__ */