[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / msm / mdp / mdp4 / mdp4_kms.h

/*
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <robdclark@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __MDP4_KMS_H__
#define __MDP4_KMS_H__

#include "msm_drv.h"
#include "msm_kms.h"
#include "mdp/mdp_kms.h"
#include "mdp4.xml.h"

#include "drm_panel.h"

struct mdp4_kms {
	struct mdp_kms base;

	struct drm_device *dev;

	int rev;

	/* mapper-id used to request GEM buffer mapped for scanout: */
	int id;

	void __iomem *mmio;

	struct regulator *dsi_pll_vdda;
	struct regulator *dsi_pll_vddio;
	struct regulator *vdd;

	struct clk *clk;
	struct clk *pclk;
	struct clk *lut_clk;
	struct clk *axi_clk;

	struct mdp_irq error_handler;

	/* empty/blank cursor bo to use when cursor is "disabled" */
	struct drm_gem_object *blank_cursor_bo;
	uint32_t blank_cursor_iova;
};
#define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)

/* platform config data (ie. from DT, or pdata) */
struct mdp4_platform_config {
	struct iommu_domain *iommu;
	uint32_t max_clk;
};

static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
{
	msm_writel(data, mdp4_kms->mmio + reg);
}

static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
{
	return msm_readl(mdp4_kms->mmio + reg);
}

static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
{
	switch (pipe) {
	case VG1:      return MDP4_OVERLAY_FLUSH_VG1;
	case VG2:      return MDP4_OVERLAY_FLUSH_VG2;
	case RGB1:     return MDP4_OVERLAY_FLUSH_RGB1;
	case RGB2:     return MDP4_OVERLAY_FLUSH_RGB2;
	default:       return 0;
	}
}

static inline uint32_t ovlp2flush(int ovlp)
{
	switch (ovlp) {
	case 0:        return MDP4_OVERLAY_FLUSH_OVLP0;
	case 1:        return MDP4_OVERLAY_FLUSH_OVLP1;
	default:       return 0;
	}
}

static inline uint32_t dma2irq(enum mdp4_dma dma)
{
	switch (dma) {
	case DMA_P:    return MDP4_IRQ_DMA_P_DONE;
	case DMA_S:    return MDP4_IRQ_DMA_S_DONE;
	case DMA_E:    return MDP4_IRQ_DMA_E_DONE;
	default:       return 0;
	}
}

static inline uint32_t dma2err(enum mdp4_dma dma)
{
	switch (dma) {
	case DMA_P:    return MDP4_IRQ_PRIMARY_INTF_UDERRUN;
	case DMA_S:    return 0;  // ???
	case DMA_E:    return MDP4_IRQ_EXTERNAL_INTF_UDERRUN;
	default:       return 0;
	}
}

static inline uint32_t mixercfg(uint32_t mixer_cfg, int mixer,
		enum mdp4_pipe pipe, enum mdp_mixer_stage_id stage)
{
	switch (pipe) {
	case VG1:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE0(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
		break;
	case VG2:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE1(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
		break;
	case RGB1:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE2(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
		break;
	case RGB2:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE3(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
		break;
	case RGB3:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE4(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
		break;
	case VG3:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE5(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
		break;
	case VG4:
		mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK |
				MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
		mixer_cfg |= MDP4_LAYERMIXER_IN_CFG_PIPE6(stage) |
			COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
		break;
	default:
		WARN_ON("invalid pipe");
		break;
	}

	return mixer_cfg;
}

int mdp4_disable(struct mdp4_kms *mdp4_kms);
int mdp4_enable(struct mdp4_kms *mdp4_kms);

void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
		uint32_t old_irqmask);
void mdp4_irq_preinstall(struct msm_kms *kms);
int mdp4_irq_postinstall(struct msm_kms *kms);
void mdp4_irq_uninstall(struct msm_kms *kms);
irqreturn_t mdp4_irq(struct msm_kms *kms);
int mdp4_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);
void mdp4_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc);

static inline uint32_t mdp4_pipe_caps(enum mdp4_pipe pipe)
{
	switch (pipe) {
	case VG1:
	case VG2:
	case VG3:
	case VG4:
		return MDP_PIPE_CAP_HFLIP | MDP_PIPE_CAP_VFLIP |
				MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
	case RGB1:
	case RGB2:
	case RGB3:
		return MDP_PIPE_CAP_SCALE;
	default:
		return 0;
	}
}

enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane);
struct drm_plane *mdp4_plane_init(struct drm_device *dev,
		enum mdp4_pipe pipe_id, bool private_plane);

uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc);
void mdp4_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file);
void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config);
void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer);
void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc);
struct drm_crtc *mdp4_crtc_init(struct drm_device *dev,
		struct drm_plane *plane, int id, int ovlp_id,
		enum mdp4_dma dma_id);

long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
struct drm_encoder *mdp4_dtv_encoder_init(struct drm_device *dev);

long mdp4_lcdc_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
struct drm_encoder *mdp4_lcdc_encoder_init(struct drm_device *dev,
		struct drm_panel *panel);

struct drm_connector *mdp4_lvds_connector_init(struct drm_device *dev,
		struct drm_panel *panel, struct drm_encoder *encoder);

#ifdef CONFIG_COMMON_CLK
struct clk *mpd4_lvds_pll_init(struct drm_device *dev);
#else
static inline struct clk *mpd4_lvds_pll_init(struct drm_device *dev)
{
	return ERR_PTR(-ENODEV);
}
#endif

#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
static inline int match_dev_name(struct device *dev, void *data)
{
	return !strcmp(dev_name(dev), data);
}
/* bus scaling data is associated with extra pointless platform devices,
 * "dtv", etc.. this is a bit of a hack, but we need a way for encoders
 * to find their pdata to make the bus-scaling stuff work.
 */
static inline void *mdp4_find_pdata(const char *devname)
{
	struct device *dev;
	dev = bus_find_device(&platform_bus_type, NULL,
			(void *)devname, match_dev_name);
	return dev ? dev->platform_data : NULL;
}
#endif

#endif /* __MDP4_KMS_H__ */
Commit	Line	Data
c8afe684 RC	1	/*
	2	* Copyright (C) 2013 Red Hat
	3	* Author: Rob Clark <robdclark@gmail.com>
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License version 2 as published by
	7	* the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
	18	#ifndef __MDP4_KMS_H__
	19	#define __MDP4_KMS_H__
	20
c8afe684	21	#include "msm_drv.h"
dd2da6e3	22	#include "msm_kms.h"
10a02eb6	23	#include "mdp/mdp_kms.h"
c8afe684 RC	24	#include "mdp4.xml.h"
c8afe684 RC	25
3e87599b RC	26	#include "drm_panel.h"
3e87599b RC	27
c8afe684	28	struct mdp4_kms {
9e0efa63	29	struct mdp_kms base;
c8afe684 RC	30
	31	struct drm_device *dev;
	32
	33	int rev;
	34
	35	/* mapper-id used to request GEM buffer mapped for scanout: */
	36	int id;
	37
	38	void __iomem *mmio;
	39
	40	struct regulator *dsi_pll_vdda;
	41	struct regulator *dsi_pll_vddio;
	42	struct regulator *vdd;
	43
	44	struct clk *clk;
	45	struct clk *pclk;
	46	struct clk *lut_clk;
e8abb5b5	47	struct clk *axi_clk;
c8afe684	48
9e0efa63	49	struct mdp_irq error_handler;
7d8d9f67 RC	50
	51	/* empty/blank cursor bo to use when cursor is "disabled" */
	52	struct drm_gem_object *blank_cursor_bo;
	53	uint32_t blank_cursor_iova;
c8afe684 RC	54	};
	55	#define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)
	56
	57	/* platform config data (ie. from DT, or pdata) */
	58	struct mdp4_platform_config {
	59	struct iommu_domain *iommu;
	60	uint32_t max_clk;
	61	};
	62
c8afe684 RC	63	static inline void mdp4_write(struct mdp4_kms *mdp4_kms, u32 reg, u32 data)
	64	{
	65	msm_writel(data, mdp4_kms->mmio + reg);
	66	}
	67
	68	static inline u32 mdp4_read(struct mdp4_kms *mdp4_kms, u32 reg)
	69	{
	70	return msm_readl(mdp4_kms->mmio + reg);
	71	}
	72
22ba8b6b	73	static inline uint32_t pipe2flush(enum mdp4_pipe pipe)
c8afe684 RC	74	{
	75	switch (pipe) {
	76	case VG1: return MDP4_OVERLAY_FLUSH_VG1;
	77	case VG2: return MDP4_OVERLAY_FLUSH_VG2;
	78	case RGB1: return MDP4_OVERLAY_FLUSH_RGB1;
f9a1ca5c	79	case RGB2: return MDP4_OVERLAY_FLUSH_RGB2;
c8afe684 RC	80	default: return 0;
	81	}
	82	}
	83
	84	static inline uint32_t ovlp2flush(int ovlp)
	85	{
	86	switch (ovlp) {
	87	case 0: return MDP4_OVERLAY_FLUSH_OVLP0;
	88	case 1: return MDP4_OVERLAY_FLUSH_OVLP1;
	89	default: return 0;
	90	}
	91	}
	92
	93	static inline uint32_t dma2irq(enum mdp4_dma dma)
	94	{
	95	switch (dma) {
	96	case DMA_P: return MDP4_IRQ_DMA_P_DONE;
	97	case DMA_S: return MDP4_IRQ_DMA_S_DONE;
	98	case DMA_E: return MDP4_IRQ_DMA_E_DONE;
	99	default: return 0;
	100	}
	101	}
	102
	103	static inline uint32_t dma2err(enum mdp4_dma dma)
	104	{
	105	switch (dma) {
	106	case DMA_P: return MDP4_IRQ_PRIMARY_INTF_UDERRUN;
	107	case DMA_S: return 0; // ???
	108	case DMA_E: return MDP4_IRQ_EXTERNAL_INTF_UDERRUN;
	109	default: return 0;
	110	}
	111	}
	112
d65bd0e4 RC	113	static inline uint32_t mixercfg(uint32_t mixer_cfg, int mixer,
d65bd0e4 RC	114	enum mdp4_pipe pipe, enum mdp_mixer_stage_id stage)
a8623918	115	{
a8623918 RC	116	switch (pipe) {
a8623918 RC	117	case VG1:
d65bd0e4 RC	118	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE0__MASK \|
	119	MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
	120	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE0(stage) \|
a8623918 RC	121	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE0_MIXER1);
	122	break;
	123	case VG2:
d65bd0e4 RC	124	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE1__MASK \|
	125	MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
	126	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE1(stage) \|
a8623918 RC	127	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE1_MIXER1);
	128	break;
	129	case RGB1:
d65bd0e4 RC	130	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE2__MASK \|
	131	MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
	132	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE2(stage) \|
a8623918 RC	133	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE2_MIXER1);
	134	break;
	135	case RGB2:
d65bd0e4 RC	136	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE3__MASK \|
	137	MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
	138	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE3(stage) \|
a8623918 RC	139	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE3_MIXER1);
	140	break;
	141	case RGB3:
d65bd0e4 RC	142	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE4__MASK \|
	143	MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
	144	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE4(stage) \|
a8623918 RC	145	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE4_MIXER1);
	146	break;
	147	case VG3:
d65bd0e4 RC	148	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE5__MASK \|
	149	MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
	150	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE5(stage) \|
a8623918 RC	151	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE5_MIXER1);
	152	break;
	153	case VG4:
d65bd0e4 RC	154	mixer_cfg &= ~(MDP4_LAYERMIXER_IN_CFG_PIPE6__MASK \|
	155	MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
	156	mixer_cfg \|= MDP4_LAYERMIXER_IN_CFG_PIPE6(stage) \|
a8623918 RC	157	COND(mixer == 1, MDP4_LAYERMIXER_IN_CFG_PIPE6_MIXER1);
	158	break;
	159	default:
	160	WARN_ON("invalid pipe");
	161	break;
	162	}
	163
	164	return mixer_cfg;
	165	}
	166
c8afe684 RC	167	int mdp4_disable(struct mdp4_kms *mdp4_kms);
	168	int mdp4_enable(struct mdp4_kms *mdp4_kms);
	169
29f034d7	170	void mdp4_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
29f034d7	171	uint32_t old_irqmask);
c8afe684 RC	172	void mdp4_irq_preinstall(struct msm_kms *kms);
	173	int mdp4_irq_postinstall(struct msm_kms *kms);
	174	void mdp4_irq_uninstall(struct msm_kms *kms);
	175	irqreturn_t mdp4_irq(struct msm_kms *kms);
c8afe684 RC	176	int mdp4_enable_vblank(struct msm_kms kms, struct drm_crtc crtc);
	177	void mdp4_disable_vblank(struct msm_kms kms, struct drm_crtc crtc);
	178
3498409f	179	static inline uint32_t mdp4_pipe_caps(enum mdp4_pipe pipe)
7ca12718 SV	180	{
	181	switch (pipe) {
	182	case VG1:
	183	case VG2:
	184	case VG3:
	185	case VG4:
3498409f	186	return MDP_PIPE_CAP_HFLIP \| MDP_PIPE_CAP_VFLIP \|
	187	MDP_PIPE_CAP_SCALE \| MDP_PIPE_CAP_CSC;
	188	case RGB1:
	189	case RGB2:
	190	case RGB3:
	191	return MDP_PIPE_CAP_SCALE;
7ca12718	192	default:
3498409f	193	return 0;
7ca12718 SV	194	}
	195	}
	196
22ba8b6b	197	enum mdp4_pipe mdp4_plane_pipe(struct drm_plane *plane);
c8afe684	198	struct drm_plane mdp4_plane_init(struct drm_device dev,
22ba8b6b	199	enum mdp4_pipe pipe_id, bool private_plane);
c8afe684 RC	200
c8afe684 RC	201	uint32_t mdp4_crtc_vblank(struct drm_crtc *crtc);
2a2b8fa6	202	void mdp4_crtc_cancel_pending_flip(struct drm_crtc crtc, struct drm_file file);
c8afe684	203	void mdp4_crtc_set_config(struct drm_crtc *crtc, uint32_t config);
d65bd0e4	204	void mdp4_crtc_set_intf(struct drm_crtc *crtc, enum mdp4_intf intf, int mixer);
0a5c9aad	205	void mdp4_crtc_wait_for_commit_done(struct drm_crtc *crtc);
c8afe684 RC	206	struct drm_crtc mdp4_crtc_init(struct drm_device dev,
	207	struct drm_plane *plane, int id, int ovlp_id,
	208	enum mdp4_dma dma_id);
	209
	210	long mdp4_dtv_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
	211	struct drm_encoder mdp4_dtv_encoder_init(struct drm_device dev);
	212
3e87599b RC	213	long mdp4_lcdc_round_pixclk(struct drm_encoder *encoder, unsigned long rate);
	214	struct drm_encoder mdp4_lcdc_encoder_init(struct drm_device dev,
	215	struct drm_panel *panel);
	216
	217	struct drm_connector mdp4_lvds_connector_init(struct drm_device dev,
	218	struct drm_panel panel, struct drm_encoder encoder);
	219
	220	#ifdef CONFIG_COMMON_CLK
	221	struct clk mpd4_lvds_pll_init(struct drm_device dev);
	222	#else
	223	static inline struct clk mpd4_lvds_pll_init(struct drm_device dev)
	224	{
	225	return ERR_PTR(-ENODEV);
	226	}
	227	#endif
	228
6490ad47	229	#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
c8afe684 RC	230	static inline int match_dev_name(struct device dev, void data)
	231	{
	232	return !strcmp(dev_name(dev), data);
	233	}
	234	/* bus scaling data is associated with extra pointless platform devices,
	235	* "dtv", etc.. this is a bit of a hack, but we need a way for encoders
	236	* to find their pdata to make the bus-scaling stuff work.
	237	*/
	238	static inline void mdp4_find_pdata(const char devname)
	239	{
	240	struct device *dev;
	241	dev = bus_find_device(&platform_bus_type, NULL,
	242	(void *)devname, match_dev_name);
	243	return dev ? dev->platform_data : NULL;
	244	}
	245	#endif
	246
	247	#endif /* __MDP4_KMS_H__ */