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1 | #ifndef MDP5_XML |
2 | #define MDP5_XML | |
3 | ||
4 | /* Autogenerated file, DO NOT EDIT manually! | |
5 | ||
6 | This file was generated by the rules-ng-ng headergen tool in this git repository: | |
7 | http://github.com/freedreno/envytools/ | |
8 | git clone https://github.com/freedreno/envytools.git | |
9 | ||
10 | The rules-ng-ng source files this header was generated from are: | |
11 | - /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35) | |
12 | - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27) | |
13 | - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31) | |
14 | - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52) | |
15 | - /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13) | |
16 | - /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43) | |
17 | - /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32) | |
18 | - /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05) | |
19 | - /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12) | |
20 | - /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04) | |
21 | ||
22 | Copyright (C) 2013 by the following authors: | |
23 | - Rob Clark <robdclark@gmail.com> (robclark) | |
24 | ||
25 | Permission is hereby granted, free of charge, to any person obtaining | |
26 | a copy of this software and associated documentation files (the | |
27 | "Software"), to deal in the Software without restriction, including | |
28 | without limitation the rights to use, copy, modify, merge, publish, | |
29 | distribute, sublicense, and/or sell copies of the Software, and to | |
30 | permit persons to whom the Software is furnished to do so, subject to | |
31 | the following conditions: | |
32 | ||
33 | The above copyright notice and this permission notice (including the | |
34 | next paragraph) shall be included in all copies or substantial | |
35 | portions of the Software. | |
36 | ||
37 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
38 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
39 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | |
40 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | |
41 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | |
42 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | |
43 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
44 | */ | |
45 | ||
46 | ||
47 | enum mdp5_intf { | |
48 | INTF_DSI = 1, | |
49 | INTF_HDMI = 3, | |
50 | INTF_LCDC = 5, | |
51 | INTF_eDP = 9, | |
52 | }; | |
53 | ||
54 | enum mdp5_intfnum { | |
55 | NO_INTF = 0, | |
56 | INTF0 = 1, | |
57 | INTF1 = 2, | |
58 | INTF2 = 3, | |
59 | INTF3 = 4, | |
60 | }; | |
61 | ||
62 | enum mdp5_pipe { | |
63 | SSPP_VIG0 = 0, | |
64 | SSPP_VIG1 = 1, | |
65 | SSPP_VIG2 = 2, | |
66 | SSPP_RGB0 = 3, | |
67 | SSPP_RGB1 = 4, | |
68 | SSPP_RGB2 = 5, | |
69 | SSPP_DMA0 = 6, | |
70 | SSPP_DMA1 = 7, | |
71 | }; | |
72 | ||
73 | enum mdp5_ctl_mode { | |
74 | MODE_NONE = 0, | |
75 | MODE_ROT0 = 1, | |
76 | MODE_ROT1 = 2, | |
77 | MODE_WB0 = 3, | |
78 | MODE_WB1 = 4, | |
79 | MODE_WFD = 5, | |
80 | }; | |
81 | ||
82 | enum mdp5_pack_3d { | |
83 | PACK_3D_FRAME_INT = 0, | |
84 | PACK_3D_H_ROW_INT = 1, | |
85 | PACK_3D_V_ROW_INT = 2, | |
86 | PACK_3D_COL_INT = 3, | |
87 | }; | |
88 | ||
89 | enum mdp5_chroma_samp_type { | |
90 | CHROMA_RGB = 0, | |
91 | CHROMA_H2V1 = 1, | |
92 | CHROMA_H1V2 = 2, | |
93 | CHROMA_420 = 3, | |
94 | }; | |
95 | ||
96 | enum mdp5_scale_filter { | |
97 | SCALE_FILTER_NEAREST = 0, | |
98 | SCALE_FILTER_BIL = 1, | |
99 | SCALE_FILTER_PCMN = 2, | |
100 | SCALE_FILTER_CA = 3, | |
101 | }; | |
102 | ||
103 | enum mdp5_pipe_bwc { | |
104 | BWC_LOSSLESS = 0, | |
105 | BWC_Q_HIGH = 1, | |
106 | BWC_Q_MED = 2, | |
107 | }; | |
108 | ||
109 | enum mdp5_client_id { | |
110 | CID_UNUSED = 0, | |
111 | CID_VIG0_Y = 1, | |
112 | CID_VIG0_CR = 2, | |
113 | CID_VIG0_CB = 3, | |
114 | CID_VIG1_Y = 4, | |
115 | CID_VIG1_CR = 5, | |
116 | CID_VIG1_CB = 6, | |
117 | CID_VIG2_Y = 7, | |
118 | CID_VIG2_CR = 8, | |
119 | CID_VIG2_CB = 9, | |
120 | CID_DMA0_Y = 10, | |
121 | CID_DMA0_CR = 11, | |
122 | CID_DMA0_CB = 12, | |
123 | CID_DMA1_Y = 13, | |
124 | CID_DMA1_CR = 14, | |
125 | CID_DMA1_CB = 15, | |
126 | CID_RGB0 = 16, | |
127 | CID_RGB1 = 17, | |
128 | CID_RGB2 = 18, | |
129 | CID_MAX = 19, | |
130 | }; | |
131 | ||
132 | enum mdp5_igc_type { | |
133 | IGC_VIG = 0, | |
134 | IGC_RGB = 1, | |
135 | IGC_DMA = 2, | |
136 | IGC_DSPP = 3, | |
137 | }; | |
138 | ||
139 | #define MDP5_IRQ_INTF0_WB_ROT_COMP 0x00000001 | |
140 | #define MDP5_IRQ_INTF1_WB_ROT_COMP 0x00000002 | |
141 | #define MDP5_IRQ_INTF2_WB_ROT_COMP 0x00000004 | |
142 | #define MDP5_IRQ_INTF3_WB_ROT_COMP 0x00000008 | |
143 | #define MDP5_IRQ_INTF0_WB_WFD 0x00000010 | |
144 | #define MDP5_IRQ_INTF1_WB_WFD 0x00000020 | |
145 | #define MDP5_IRQ_INTF2_WB_WFD 0x00000040 | |
146 | #define MDP5_IRQ_INTF3_WB_WFD 0x00000080 | |
147 | #define MDP5_IRQ_INTF0_PING_PONG_COMP 0x00000100 | |
148 | #define MDP5_IRQ_INTF1_PING_PONG_COMP 0x00000200 | |
149 | #define MDP5_IRQ_INTF2_PING_PONG_COMP 0x00000400 | |
150 | #define MDP5_IRQ_INTF3_PING_PONG_COMP 0x00000800 | |
151 | #define MDP5_IRQ_INTF0_PING_PONG_RD_PTR 0x00001000 | |
152 | #define MDP5_IRQ_INTF1_PING_PONG_RD_PTR 0x00002000 | |
153 | #define MDP5_IRQ_INTF2_PING_PONG_RD_PTR 0x00004000 | |
154 | #define MDP5_IRQ_INTF3_PING_PONG_RD_PTR 0x00008000 | |
155 | #define MDP5_IRQ_INTF0_PING_PONG_WR_PTR 0x00010000 | |
156 | #define MDP5_IRQ_INTF1_PING_PONG_WR_PTR 0x00020000 | |
157 | #define MDP5_IRQ_INTF2_PING_PONG_WR_PTR 0x00040000 | |
158 | #define MDP5_IRQ_INTF3_PING_PONG_WR_PTR 0x00080000 | |
159 | #define MDP5_IRQ_INTF0_PING_PONG_AUTO_REF 0x00100000 | |
160 | #define MDP5_IRQ_INTF1_PING_PONG_AUTO_REF 0x00200000 | |
161 | #define MDP5_IRQ_INTF2_PING_PONG_AUTO_REF 0x00400000 | |
162 | #define MDP5_IRQ_INTF3_PING_PONG_AUTO_REF 0x00800000 | |
163 | #define MDP5_IRQ_INTF0_UNDER_RUN 0x01000000 | |
164 | #define MDP5_IRQ_INTF0_VSYNC 0x02000000 | |
165 | #define MDP5_IRQ_INTF1_UNDER_RUN 0x04000000 | |
166 | #define MDP5_IRQ_INTF1_VSYNC 0x08000000 | |
167 | #define MDP5_IRQ_INTF2_UNDER_RUN 0x10000000 | |
168 | #define MDP5_IRQ_INTF2_VSYNC 0x20000000 | |
169 | #define MDP5_IRQ_INTF3_UNDER_RUN 0x40000000 | |
170 | #define MDP5_IRQ_INTF3_VSYNC 0x80000000 | |
171 | #define REG_MDP5_HW_VERSION 0x00000000 | |
172 | ||
173 | #define REG_MDP5_HW_INTR_STATUS 0x00000010 | |
174 | #define MDP5_HW_INTR_STATUS_INTR_MDP 0x00000001 | |
175 | #define MDP5_HW_INTR_STATUS_INTR_DSI0 0x00000010 | |
176 | #define MDP5_HW_INTR_STATUS_INTR_DSI1 0x00000020 | |
177 | #define MDP5_HW_INTR_STATUS_INTR_HDMI 0x00000100 | |
178 | #define MDP5_HW_INTR_STATUS_INTR_EDP 0x00001000 | |
179 | ||
180 | #define REG_MDP5_MDP_VERSION 0x00000100 | |
181 | #define MDP5_MDP_VERSION_MINOR__MASK 0x00ff0000 | |
182 | #define MDP5_MDP_VERSION_MINOR__SHIFT 16 | |
183 | static inline uint32_t MDP5_MDP_VERSION_MINOR(uint32_t val) | |
184 | { | |
185 | return ((val) << MDP5_MDP_VERSION_MINOR__SHIFT) & MDP5_MDP_VERSION_MINOR__MASK; | |
186 | } | |
187 | #define MDP5_MDP_VERSION_MAJOR__MASK 0xf0000000 | |
188 | #define MDP5_MDP_VERSION_MAJOR__SHIFT 28 | |
189 | static inline uint32_t MDP5_MDP_VERSION_MAJOR(uint32_t val) | |
190 | { | |
191 | return ((val) << MDP5_MDP_VERSION_MAJOR__SHIFT) & MDP5_MDP_VERSION_MAJOR__MASK; | |
192 | } | |
193 | ||
194 | #define REG_MDP5_DISP_INTF_SEL 0x00000104 | |
195 | #define MDP5_DISP_INTF_SEL_INTF0__MASK 0x000000ff | |
196 | #define MDP5_DISP_INTF_SEL_INTF0__SHIFT 0 | |
197 | static inline uint32_t MDP5_DISP_INTF_SEL_INTF0(enum mdp5_intf val) | |
198 | { | |
199 | return ((val) << MDP5_DISP_INTF_SEL_INTF0__SHIFT) & MDP5_DISP_INTF_SEL_INTF0__MASK; | |
200 | } | |
201 | #define MDP5_DISP_INTF_SEL_INTF1__MASK 0x0000ff00 | |
202 | #define MDP5_DISP_INTF_SEL_INTF1__SHIFT 8 | |
203 | static inline uint32_t MDP5_DISP_INTF_SEL_INTF1(enum mdp5_intf val) | |
204 | { | |
205 | return ((val) << MDP5_DISP_INTF_SEL_INTF1__SHIFT) & MDP5_DISP_INTF_SEL_INTF1__MASK; | |
206 | } | |
207 | #define MDP5_DISP_INTF_SEL_INTF2__MASK 0x00ff0000 | |
208 | #define MDP5_DISP_INTF_SEL_INTF2__SHIFT 16 | |
209 | static inline uint32_t MDP5_DISP_INTF_SEL_INTF2(enum mdp5_intf val) | |
210 | { | |
211 | return ((val) << MDP5_DISP_INTF_SEL_INTF2__SHIFT) & MDP5_DISP_INTF_SEL_INTF2__MASK; | |
212 | } | |
213 | #define MDP5_DISP_INTF_SEL_INTF3__MASK 0xff000000 | |
214 | #define MDP5_DISP_INTF_SEL_INTF3__SHIFT 24 | |
215 | static inline uint32_t MDP5_DISP_INTF_SEL_INTF3(enum mdp5_intf val) | |
216 | { | |
217 | return ((val) << MDP5_DISP_INTF_SEL_INTF3__SHIFT) & MDP5_DISP_INTF_SEL_INTF3__MASK; | |
218 | } | |
219 | ||
220 | #define REG_MDP5_INTR_EN 0x00000110 | |
221 | ||
222 | #define REG_MDP5_INTR_STATUS 0x00000114 | |
223 | ||
224 | #define REG_MDP5_INTR_CLEAR 0x00000118 | |
225 | ||
226 | #define REG_MDP5_HIST_INTR_EN 0x0000011c | |
227 | ||
228 | #define REG_MDP5_HIST_INTR_STATUS 0x00000120 | |
229 | ||
230 | #define REG_MDP5_HIST_INTR_CLEAR 0x00000124 | |
231 | ||
232 | static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000180 + 0x4*i0; } | |
233 | ||
234 | static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000180 + 0x4*i0; } | |
235 | #define MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK 0x000000ff | |
236 | #define MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT 0 | |
237 | static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT0(enum mdp5_client_id val) | |
238 | { | |
239 | return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT0__MASK; | |
240 | } | |
241 | #define MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK 0x0000ff00 | |
242 | #define MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT 8 | |
243 | static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT1(enum mdp5_client_id val) | |
244 | { | |
245 | return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT1__MASK; | |
246 | } | |
247 | #define MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK 0x00ff0000 | |
248 | #define MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT 16 | |
249 | static inline uint32_t MDP5_SMP_ALLOC_W_REG_CLIENT2(enum mdp5_client_id val) | |
250 | { | |
251 | return ((val) << MDP5_SMP_ALLOC_W_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_W_REG_CLIENT2__MASK; | |
252 | } | |
253 | ||
254 | static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000230 + 0x4*i0; } | |
255 | ||
256 | static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000230 + 0x4*i0; } | |
257 | #define MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK 0x000000ff | |
258 | #define MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT 0 | |
259 | static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT0(enum mdp5_client_id val) | |
260 | { | |
261 | return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT0__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT0__MASK; | |
262 | } | |
263 | #define MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK 0x0000ff00 | |
264 | #define MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT 8 | |
265 | static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT1(enum mdp5_client_id val) | |
266 | { | |
267 | return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT1__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT1__MASK; | |
268 | } | |
269 | #define MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK 0x00ff0000 | |
270 | #define MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT 16 | |
271 | static inline uint32_t MDP5_SMP_ALLOC_R_REG_CLIENT2(enum mdp5_client_id val) | |
272 | { | |
273 | return ((val) << MDP5_SMP_ALLOC_R_REG_CLIENT2__SHIFT) & MDP5_SMP_ALLOC_R_REG_CLIENT2__MASK; | |
274 | } | |
275 | ||
276 | static inline uint32_t __offset_IGC(enum mdp5_igc_type idx) | |
277 | { | |
278 | switch (idx) { | |
279 | case IGC_VIG: return 0x00000300; | |
280 | case IGC_RGB: return 0x00000310; | |
281 | case IGC_DMA: return 0x00000320; | |
282 | case IGC_DSPP: return 0x00000400; | |
283 | default: return INVALID_IDX(idx); | |
284 | } | |
285 | } | |
286 | static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); } | |
287 | ||
288 | static inline uint32_t REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; } | |
289 | ||
290 | static inline uint32_t REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) { return 0x00000000 + __offset_IGC(i0) + 0x4*i1; } | |
291 | #define MDP5_IGC_LUT_REG_VAL__MASK 0x00000fff | |
292 | #define MDP5_IGC_LUT_REG_VAL__SHIFT 0 | |
293 | static inline uint32_t MDP5_IGC_LUT_REG_VAL(uint32_t val) | |
294 | { | |
295 | return ((val) << MDP5_IGC_LUT_REG_VAL__SHIFT) & MDP5_IGC_LUT_REG_VAL__MASK; | |
296 | } | |
297 | #define MDP5_IGC_LUT_REG_INDEX_UPDATE 0x02000000 | |
298 | #define MDP5_IGC_LUT_REG_DISABLE_PIPE_0 0x10000000 | |
299 | #define MDP5_IGC_LUT_REG_DISABLE_PIPE_1 0x20000000 | |
300 | #define MDP5_IGC_LUT_REG_DISABLE_PIPE_2 0x40000000 | |
301 | ||
302 | static inline uint32_t REG_MDP5_CTL(uint32_t i0) { return 0x00000600 + 0x100*i0; } | |
303 | ||
304 | static inline uint32_t REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) { return 0x00000600 + 0x100*i0 + 0x4*i1; } | |
305 | ||
306 | static inline uint32_t REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) { return 0x00000600 + 0x100*i0 + 0x4*i1; } | |
307 | #define MDP5_CTL_LAYER_REG_VIG0__MASK 0x00000007 | |
308 | #define MDP5_CTL_LAYER_REG_VIG0__SHIFT 0 | |
309 | static inline uint32_t MDP5_CTL_LAYER_REG_VIG0(enum mdp_mixer_stage_id val) | |
310 | { | |
311 | return ((val) << MDP5_CTL_LAYER_REG_VIG0__SHIFT) & MDP5_CTL_LAYER_REG_VIG0__MASK; | |
312 | } | |
313 | #define MDP5_CTL_LAYER_REG_VIG1__MASK 0x00000038 | |
314 | #define MDP5_CTL_LAYER_REG_VIG1__SHIFT 3 | |
315 | static inline uint32_t MDP5_CTL_LAYER_REG_VIG1(enum mdp_mixer_stage_id val) | |
316 | { | |
317 | return ((val) << MDP5_CTL_LAYER_REG_VIG1__SHIFT) & MDP5_CTL_LAYER_REG_VIG1__MASK; | |
318 | } | |
319 | #define MDP5_CTL_LAYER_REG_VIG2__MASK 0x000001c0 | |
320 | #define MDP5_CTL_LAYER_REG_VIG2__SHIFT 6 | |
321 | static inline uint32_t MDP5_CTL_LAYER_REG_VIG2(enum mdp_mixer_stage_id val) | |
322 | { | |
323 | return ((val) << MDP5_CTL_LAYER_REG_VIG2__SHIFT) & MDP5_CTL_LAYER_REG_VIG2__MASK; | |
324 | } | |
325 | #define MDP5_CTL_LAYER_REG_RGB0__MASK 0x00000e00 | |
326 | #define MDP5_CTL_LAYER_REG_RGB0__SHIFT 9 | |
327 | static inline uint32_t MDP5_CTL_LAYER_REG_RGB0(enum mdp_mixer_stage_id val) | |
328 | { | |
329 | return ((val) << MDP5_CTL_LAYER_REG_RGB0__SHIFT) & MDP5_CTL_LAYER_REG_RGB0__MASK; | |
330 | } | |
331 | #define MDP5_CTL_LAYER_REG_RGB1__MASK 0x00007000 | |
332 | #define MDP5_CTL_LAYER_REG_RGB1__SHIFT 12 | |
333 | static inline uint32_t MDP5_CTL_LAYER_REG_RGB1(enum mdp_mixer_stage_id val) | |
334 | { | |
335 | return ((val) << MDP5_CTL_LAYER_REG_RGB1__SHIFT) & MDP5_CTL_LAYER_REG_RGB1__MASK; | |
336 | } | |
337 | #define MDP5_CTL_LAYER_REG_RGB2__MASK 0x00038000 | |
338 | #define MDP5_CTL_LAYER_REG_RGB2__SHIFT 15 | |
339 | static inline uint32_t MDP5_CTL_LAYER_REG_RGB2(enum mdp_mixer_stage_id val) | |
340 | { | |
341 | return ((val) << MDP5_CTL_LAYER_REG_RGB2__SHIFT) & MDP5_CTL_LAYER_REG_RGB2__MASK; | |
342 | } | |
343 | #define MDP5_CTL_LAYER_REG_DMA0__MASK 0x001c0000 | |
344 | #define MDP5_CTL_LAYER_REG_DMA0__SHIFT 18 | |
345 | static inline uint32_t MDP5_CTL_LAYER_REG_DMA0(enum mdp_mixer_stage_id val) | |
346 | { | |
347 | return ((val) << MDP5_CTL_LAYER_REG_DMA0__SHIFT) & MDP5_CTL_LAYER_REG_DMA0__MASK; | |
348 | } | |
349 | #define MDP5_CTL_LAYER_REG_DMA1__MASK 0x00e00000 | |
350 | #define MDP5_CTL_LAYER_REG_DMA1__SHIFT 21 | |
351 | static inline uint32_t MDP5_CTL_LAYER_REG_DMA1(enum mdp_mixer_stage_id val) | |
352 | { | |
353 | return ((val) << MDP5_CTL_LAYER_REG_DMA1__SHIFT) & MDP5_CTL_LAYER_REG_DMA1__MASK; | |
354 | } | |
355 | #define MDP5_CTL_LAYER_REG_BORDER_COLOR 0x01000000 | |
356 | #define MDP5_CTL_LAYER_REG_CURSOR_OUT 0x02000000 | |
357 | ||
358 | static inline uint32_t REG_MDP5_CTL_OP(uint32_t i0) { return 0x00000614 + 0x100*i0; } | |
359 | #define MDP5_CTL_OP_MODE__MASK 0x0000000f | |
360 | #define MDP5_CTL_OP_MODE__SHIFT 0 | |
361 | static inline uint32_t MDP5_CTL_OP_MODE(enum mdp5_ctl_mode val) | |
362 | { | |
363 | return ((val) << MDP5_CTL_OP_MODE__SHIFT) & MDP5_CTL_OP_MODE__MASK; | |
364 | } | |
365 | #define MDP5_CTL_OP_INTF_NUM__MASK 0x00000070 | |
366 | #define MDP5_CTL_OP_INTF_NUM__SHIFT 4 | |
367 | static inline uint32_t MDP5_CTL_OP_INTF_NUM(enum mdp5_intfnum val) | |
368 | { | |
369 | return ((val) << MDP5_CTL_OP_INTF_NUM__SHIFT) & MDP5_CTL_OP_INTF_NUM__MASK; | |
370 | } | |
371 | #define MDP5_CTL_OP_CMD_MODE 0x00020000 | |
372 | #define MDP5_CTL_OP_PACK_3D_ENABLE 0x00080000 | |
373 | #define MDP5_CTL_OP_PACK_3D__MASK 0x00300000 | |
374 | #define MDP5_CTL_OP_PACK_3D__SHIFT 20 | |
375 | static inline uint32_t MDP5_CTL_OP_PACK_3D(enum mdp5_pack_3d val) | |
376 | { | |
377 | return ((val) << MDP5_CTL_OP_PACK_3D__SHIFT) & MDP5_CTL_OP_PACK_3D__MASK; | |
378 | } | |
379 | ||
380 | static inline uint32_t REG_MDP5_CTL_FLUSH(uint32_t i0) { return 0x00000618 + 0x100*i0; } | |
381 | #define MDP5_CTL_FLUSH_VIG0 0x00000001 | |
382 | #define MDP5_CTL_FLUSH_VIG1 0x00000002 | |
383 | #define MDP5_CTL_FLUSH_VIG2 0x00000004 | |
384 | #define MDP5_CTL_FLUSH_RGB0 0x00000008 | |
385 | #define MDP5_CTL_FLUSH_RGB1 0x00000010 | |
386 | #define MDP5_CTL_FLUSH_RGB2 0x00000020 | |
387 | #define MDP5_CTL_FLUSH_LM0 0x00000040 | |
388 | #define MDP5_CTL_FLUSH_LM1 0x00000080 | |
389 | #define MDP5_CTL_FLUSH_LM2 0x00000100 | |
390 | #define MDP5_CTL_FLUSH_DMA0 0x00000800 | |
391 | #define MDP5_CTL_FLUSH_DMA1 0x00001000 | |
392 | #define MDP5_CTL_FLUSH_DSPP0 0x00002000 | |
393 | #define MDP5_CTL_FLUSH_DSPP1 0x00004000 | |
394 | #define MDP5_CTL_FLUSH_DSPP2 0x00008000 | |
395 | #define MDP5_CTL_FLUSH_CTL 0x00020000 | |
396 | ||
397 | static inline uint32_t REG_MDP5_CTL_START(uint32_t i0) { return 0x0000061c + 0x100*i0; } | |
398 | ||
399 | static inline uint32_t REG_MDP5_CTL_PACK_3D(uint32_t i0) { return 0x00000620 + 0x100*i0; } | |
400 | ||
401 | static inline uint32_t REG_MDP5_PIPE(enum mdp5_pipe i0) { return 0x00001200 + 0x400*i0; } | |
402 | ||
403 | static inline uint32_t REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) { return 0x000014c4 + 0x400*i0; } | |
404 | ||
405 | static inline uint32_t REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) { return 0x000014f0 + 0x400*i0; } | |
406 | ||
407 | static inline uint32_t REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) { return 0x00001500 + 0x400*i0; } | |
408 | ||
409 | static inline uint32_t REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) { return 0x00001200 + 0x400*i0; } | |
410 | #define MDP5_PIPE_SRC_SIZE_HEIGHT__MASK 0xffff0000 | |
411 | #define MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT 16 | |
412 | static inline uint32_t MDP5_PIPE_SRC_SIZE_HEIGHT(uint32_t val) | |
413 | { | |
414 | return ((val) << MDP5_PIPE_SRC_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_SIZE_HEIGHT__MASK; | |
415 | } | |
416 | #define MDP5_PIPE_SRC_SIZE_WIDTH__MASK 0x0000ffff | |
417 | #define MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT 0 | |
418 | static inline uint32_t MDP5_PIPE_SRC_SIZE_WIDTH(uint32_t val) | |
419 | { | |
420 | return ((val) << MDP5_PIPE_SRC_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_SIZE_WIDTH__MASK; | |
421 | } | |
422 | ||
423 | static inline uint32_t REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) { return 0x00001204 + 0x400*i0; } | |
424 | #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK 0xffff0000 | |
425 | #define MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT 16 | |
426 | static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(uint32_t val) | |
427 | { | |
428 | return ((val) << MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_HEIGHT__MASK; | |
429 | } | |
430 | #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK 0x0000ffff | |
431 | #define MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT 0 | |
432 | static inline uint32_t MDP5_PIPE_SRC_IMG_SIZE_WIDTH(uint32_t val) | |
433 | { | |
434 | return ((val) << MDP5_PIPE_SRC_IMG_SIZE_WIDTH__SHIFT) & MDP5_PIPE_SRC_IMG_SIZE_WIDTH__MASK; | |
435 | } | |
436 | ||
437 | static inline uint32_t REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) { return 0x00001208 + 0x400*i0; } | |
438 | #define MDP5_PIPE_SRC_XY_Y__MASK 0xffff0000 | |
439 | #define MDP5_PIPE_SRC_XY_Y__SHIFT 16 | |
440 | static inline uint32_t MDP5_PIPE_SRC_XY_Y(uint32_t val) | |
441 | { | |
442 | return ((val) << MDP5_PIPE_SRC_XY_Y__SHIFT) & MDP5_PIPE_SRC_XY_Y__MASK; | |
443 | } | |
444 | #define MDP5_PIPE_SRC_XY_X__MASK 0x0000ffff | |
445 | #define MDP5_PIPE_SRC_XY_X__SHIFT 0 | |
446 | static inline uint32_t MDP5_PIPE_SRC_XY_X(uint32_t val) | |
447 | { | |
448 | return ((val) << MDP5_PIPE_SRC_XY_X__SHIFT) & MDP5_PIPE_SRC_XY_X__MASK; | |
449 | } | |
450 | ||
451 | static inline uint32_t REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) { return 0x0000120c + 0x400*i0; } | |
452 | #define MDP5_PIPE_OUT_SIZE_HEIGHT__MASK 0xffff0000 | |
453 | #define MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT 16 | |
454 | static inline uint32_t MDP5_PIPE_OUT_SIZE_HEIGHT(uint32_t val) | |
455 | { | |
456 | return ((val) << MDP5_PIPE_OUT_SIZE_HEIGHT__SHIFT) & MDP5_PIPE_OUT_SIZE_HEIGHT__MASK; | |
457 | } | |
458 | #define MDP5_PIPE_OUT_SIZE_WIDTH__MASK 0x0000ffff | |
459 | #define MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT 0 | |
460 | static inline uint32_t MDP5_PIPE_OUT_SIZE_WIDTH(uint32_t val) | |
461 | { | |
462 | return ((val) << MDP5_PIPE_OUT_SIZE_WIDTH__SHIFT) & MDP5_PIPE_OUT_SIZE_WIDTH__MASK; | |
463 | } | |
464 | ||
465 | static inline uint32_t REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) { return 0x00001210 + 0x400*i0; } | |
466 | #define MDP5_PIPE_OUT_XY_Y__MASK 0xffff0000 | |
467 | #define MDP5_PIPE_OUT_XY_Y__SHIFT 16 | |
468 | static inline uint32_t MDP5_PIPE_OUT_XY_Y(uint32_t val) | |
469 | { | |
470 | return ((val) << MDP5_PIPE_OUT_XY_Y__SHIFT) & MDP5_PIPE_OUT_XY_Y__MASK; | |
471 | } | |
472 | #define MDP5_PIPE_OUT_XY_X__MASK 0x0000ffff | |
473 | #define MDP5_PIPE_OUT_XY_X__SHIFT 0 | |
474 | static inline uint32_t MDP5_PIPE_OUT_XY_X(uint32_t val) | |
475 | { | |
476 | return ((val) << MDP5_PIPE_OUT_XY_X__SHIFT) & MDP5_PIPE_OUT_XY_X__MASK; | |
477 | } | |
478 | ||
479 | static inline uint32_t REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) { return 0x00001214 + 0x400*i0; } | |
480 | ||
481 | static inline uint32_t REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) { return 0x00001218 + 0x400*i0; } | |
482 | ||
483 | static inline uint32_t REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) { return 0x0000121c + 0x400*i0; } | |
484 | ||
485 | static inline uint32_t REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) { return 0x00001220 + 0x400*i0; } | |
486 | ||
487 | static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) { return 0x00001224 + 0x400*i0; } | |
488 | #define MDP5_PIPE_SRC_STRIDE_A_P0__MASK 0x0000ffff | |
489 | #define MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT 0 | |
490 | static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P0(uint32_t val) | |
491 | { | |
492 | return ((val) << MDP5_PIPE_SRC_STRIDE_A_P0__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P0__MASK; | |
493 | } | |
494 | #define MDP5_PIPE_SRC_STRIDE_A_P1__MASK 0xffff0000 | |
495 | #define MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT 16 | |
496 | static inline uint32_t MDP5_PIPE_SRC_STRIDE_A_P1(uint32_t val) | |
497 | { | |
498 | return ((val) << MDP5_PIPE_SRC_STRIDE_A_P1__SHIFT) & MDP5_PIPE_SRC_STRIDE_A_P1__MASK; | |
499 | } | |
500 | ||
501 | static inline uint32_t REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) { return 0x00001228 + 0x400*i0; } | |
502 | #define MDP5_PIPE_SRC_STRIDE_B_P2__MASK 0x0000ffff | |
503 | #define MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT 0 | |
504 | static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P2(uint32_t val) | |
505 | { | |
506 | return ((val) << MDP5_PIPE_SRC_STRIDE_B_P2__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P2__MASK; | |
507 | } | |
508 | #define MDP5_PIPE_SRC_STRIDE_B_P3__MASK 0xffff0000 | |
509 | #define MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT 16 | |
510 | static inline uint32_t MDP5_PIPE_SRC_STRIDE_B_P3(uint32_t val) | |
511 | { | |
512 | return ((val) << MDP5_PIPE_SRC_STRIDE_B_P3__SHIFT) & MDP5_PIPE_SRC_STRIDE_B_P3__MASK; | |
513 | } | |
514 | ||
515 | static inline uint32_t REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) { return 0x0000122c + 0x400*i0; } | |
516 | ||
517 | static inline uint32_t REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) { return 0x00001230 + 0x400*i0; } | |
518 | #define MDP5_PIPE_SRC_FORMAT_G_BPC__MASK 0x00000003 | |
519 | #define MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT 0 | |
520 | static inline uint32_t MDP5_PIPE_SRC_FORMAT_G_BPC(enum mdp_bpc val) | |
521 | { | |
522 | return ((val) << MDP5_PIPE_SRC_FORMAT_G_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_G_BPC__MASK; | |
523 | } | |
524 | #define MDP5_PIPE_SRC_FORMAT_B_BPC__MASK 0x0000000c | |
525 | #define MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT 2 | |
526 | static inline uint32_t MDP5_PIPE_SRC_FORMAT_B_BPC(enum mdp_bpc val) | |
527 | { | |
528 | return ((val) << MDP5_PIPE_SRC_FORMAT_B_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_B_BPC__MASK; | |
529 | } | |
530 | #define MDP5_PIPE_SRC_FORMAT_R_BPC__MASK 0x00000030 | |
531 | #define MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT 4 | |
532 | static inline uint32_t MDP5_PIPE_SRC_FORMAT_R_BPC(enum mdp_bpc val) | |
533 | { | |
534 | return ((val) << MDP5_PIPE_SRC_FORMAT_R_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_R_BPC__MASK; | |
535 | } | |
536 | #define MDP5_PIPE_SRC_FORMAT_A_BPC__MASK 0x000000c0 | |
537 | #define MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT 6 | |
538 | static inline uint32_t MDP5_PIPE_SRC_FORMAT_A_BPC(enum mdp_bpc_alpha val) | |
539 | { | |
540 | return ((val) << MDP5_PIPE_SRC_FORMAT_A_BPC__SHIFT) & MDP5_PIPE_SRC_FORMAT_A_BPC__MASK; | |
541 | } | |
542 | #define MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE 0x00000100 | |
543 | #define MDP5_PIPE_SRC_FORMAT_CPP__MASK 0x00000600 | |
544 | #define MDP5_PIPE_SRC_FORMAT_CPP__SHIFT 9 | |
545 | static inline uint32_t MDP5_PIPE_SRC_FORMAT_CPP(uint32_t val) | |
546 | { | |
547 | return ((val) << MDP5_PIPE_SRC_FORMAT_CPP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CPP__MASK; | |
548 | } | |
549 | #define MDP5_PIPE_SRC_FORMAT_ROT90 0x00000800 | |
550 | #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK 0x00003000 | |
551 | #define MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT 12 | |
552 | static inline uint32_t MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(uint32_t val) | |
553 | { | |
554 | return ((val) << MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__SHIFT) & MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT__MASK; | |
555 | } | |
556 | #define MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT 0x00020000 | |
557 | #define MDP5_PIPE_SRC_FORMAT_UNPACK_ALIGN_MSB 0x00040000 | |
558 | #define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK 0x00780000 | |
559 | #define MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT 19 | |
560 | static inline uint32_t MDP5_PIPE_SRC_FORMAT_NUM_PLANES(uint32_t val) | |
561 | { | |
562 | return ((val) << MDP5_PIPE_SRC_FORMAT_NUM_PLANES__SHIFT) & MDP5_PIPE_SRC_FORMAT_NUM_PLANES__MASK; | |
563 | } | |
564 | #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK 0x01800000 | |
565 | #define MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT 23 | |
566 | static inline uint32_t MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(enum mdp5_chroma_samp_type val) | |
567 | { | |
568 | return ((val) << MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__SHIFT) & MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP__MASK; | |
569 | } | |
570 | ||
571 | static inline uint32_t REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) { return 0x00001234 + 0x400*i0; } | |
572 | #define MDP5_PIPE_SRC_UNPACK_ELEM0__MASK 0x000000ff | |
573 | #define MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT 0 | |
574 | static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM0(uint32_t val) | |
575 | { | |
576 | return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM0__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM0__MASK; | |
577 | } | |
578 | #define MDP5_PIPE_SRC_UNPACK_ELEM1__MASK 0x0000ff00 | |
579 | #define MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT 8 | |
580 | static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM1(uint32_t val) | |
581 | { | |
582 | return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM1__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM1__MASK; | |
583 | } | |
584 | #define MDP5_PIPE_SRC_UNPACK_ELEM2__MASK 0x00ff0000 | |
585 | #define MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT 16 | |
586 | static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM2(uint32_t val) | |
587 | { | |
588 | return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM2__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM2__MASK; | |
589 | } | |
590 | #define MDP5_PIPE_SRC_UNPACK_ELEM3__MASK 0xff000000 | |
591 | #define MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT 24 | |
592 | static inline uint32_t MDP5_PIPE_SRC_UNPACK_ELEM3(uint32_t val) | |
593 | { | |
594 | return ((val) << MDP5_PIPE_SRC_UNPACK_ELEM3__SHIFT) & MDP5_PIPE_SRC_UNPACK_ELEM3__MASK; | |
595 | } | |
596 | ||
597 | static inline uint32_t REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) { return 0x00001238 + 0x400*i0; } | |
598 | #define MDP5_PIPE_SRC_OP_MODE_BWC_EN 0x00000001 | |
599 | #define MDP5_PIPE_SRC_OP_MODE_BWC__MASK 0x00000006 | |
600 | #define MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT 1 | |
601 | static inline uint32_t MDP5_PIPE_SRC_OP_MODE_BWC(enum mdp5_pipe_bwc val) | |
602 | { | |
603 | return ((val) << MDP5_PIPE_SRC_OP_MODE_BWC__SHIFT) & MDP5_PIPE_SRC_OP_MODE_BWC__MASK; | |
604 | } | |
605 | #define MDP5_PIPE_SRC_OP_MODE_FLIP_LR 0x00002000 | |
606 | #define MDP5_PIPE_SRC_OP_MODE_FLIP_UD 0x00004000 | |
607 | #define MDP5_PIPE_SRC_OP_MODE_IGC_EN 0x00010000 | |
608 | #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_0 0x00020000 | |
609 | #define MDP5_PIPE_SRC_OP_MODE_IGC_ROM_1 0x00040000 | |
610 | #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE 0x00400000 | |
611 | #define MDP5_PIPE_SRC_OP_MODE_DEINTERLACE_ODD 0x00800000 | |
612 | ||
613 | static inline uint32_t REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) { return 0x0000123c + 0x400*i0; } | |
614 | ||
615 | static inline uint32_t REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) { return 0x00001248 + 0x400*i0; } | |
616 | ||
617 | static inline uint32_t REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) { return 0x0000124c + 0x400*i0; } | |
618 | ||
619 | static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) { return 0x00001250 + 0x400*i0; } | |
620 | ||
621 | static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) { return 0x00001254 + 0x400*i0; } | |
622 | ||
623 | static inline uint32_t REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) { return 0x00001258 + 0x400*i0; } | |
624 | ||
625 | static inline uint32_t REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) { return 0x00001270 + 0x400*i0; } | |
626 | ||
627 | static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) { return 0x000012a4 + 0x400*i0; } | |
628 | ||
629 | static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) { return 0x000012a8 + 0x400*i0; } | |
630 | ||
631 | static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) { return 0x000012ac + 0x400*i0; } | |
632 | ||
633 | static inline uint32_t REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) { return 0x000012b0 + 0x400*i0; } | |
634 | ||
635 | static inline uint32_t REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) { return 0x000012b4 + 0x400*i0; } | |
636 | #define MDP5_PIPE_DECIMATION_VERT__MASK 0x000000ff | |
637 | #define MDP5_PIPE_DECIMATION_VERT__SHIFT 0 | |
638 | static inline uint32_t MDP5_PIPE_DECIMATION_VERT(uint32_t val) | |
639 | { | |
640 | return ((val) << MDP5_PIPE_DECIMATION_VERT__SHIFT) & MDP5_PIPE_DECIMATION_VERT__MASK; | |
641 | } | |
642 | #define MDP5_PIPE_DECIMATION_HORZ__MASK 0x0000ff00 | |
643 | #define MDP5_PIPE_DECIMATION_HORZ__SHIFT 8 | |
644 | static inline uint32_t MDP5_PIPE_DECIMATION_HORZ(uint32_t val) | |
645 | { | |
646 | return ((val) << MDP5_PIPE_DECIMATION_HORZ__SHIFT) & MDP5_PIPE_DECIMATION_HORZ__MASK; | |
647 | } | |
648 | ||
649 | static inline uint32_t REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) { return 0x00001404 + 0x400*i0; } | |
650 | #define MDP5_PIPE_SCALE_CONFIG_SCALEX_EN 0x00000001 | |
651 | #define MDP5_PIPE_SCALE_CONFIG_SCALEY_EN 0x00000002 | |
652 | #define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK 0x00000300 | |
653 | #define MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT 8 | |
654 | static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER(enum mdp5_scale_filter val) | |
655 | { | |
656 | return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_MIN_FILTER__MASK; | |
657 | } | |
658 | #define MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK 0x00000c00 | |
659 | #define MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT 10 | |
660 | static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER(enum mdp5_scale_filter val) | |
661 | { | |
662 | return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MIN_FILTER__MASK; | |
663 | } | |
664 | #define MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK 0x00003000 | |
665 | #define MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT 12 | |
666 | static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER(enum mdp5_scale_filter val) | |
667 | { | |
668 | return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_CR_FILTER__MASK; | |
669 | } | |
670 | #define MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__MASK 0x0000c000 | |
671 | #define MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__SHIFT 14 | |
672 | static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER(enum mdp5_scale_filter val) | |
673 | { | |
674 | return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_CR_FILTER__MASK; | |
675 | } | |
676 | #define MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__MASK 0x00030000 | |
677 | #define MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__SHIFT 16 | |
678 | static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER(enum mdp5_scale_filter val) | |
679 | { | |
680 | return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEX_MAX_FILTER__MASK; | |
681 | } | |
682 | #define MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK 0x000c0000 | |
683 | #define MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT 18 | |
684 | static inline uint32_t MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER(enum mdp5_scale_filter val) | |
685 | { | |
686 | return ((val) << MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__SHIFT) & MDP5_PIPE_SCALE_CONFIG_SCALEY_MAX_FILTER__MASK; | |
687 | } | |
688 | ||
689 | static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) { return 0x00001410 + 0x400*i0; } | |
690 | ||
691 | static inline uint32_t REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) { return 0x00001414 + 0x400*i0; } | |
692 | ||
693 | static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) { return 0x00001420 + 0x400*i0; } | |
694 | ||
695 | static inline uint32_t REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) { return 0x00001424 + 0x400*i0; } | |
696 | ||
697 | static inline uint32_t REG_MDP5_LM(uint32_t i0) { return 0x00003200 + 0x400*i0; } | |
698 | ||
699 | static inline uint32_t REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) { return 0x00003200 + 0x400*i0; } | |
700 | #define MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA 0x00000002 | |
701 | #define MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA 0x00000004 | |
702 | #define MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA 0x00000008 | |
703 | #define MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA 0x00000010 | |
704 | ||
705 | static inline uint32_t REG_MDP5_LM_OUT_SIZE(uint32_t i0) { return 0x00003204 + 0x400*i0; } | |
706 | #define MDP5_LM_OUT_SIZE_HEIGHT__MASK 0xffff0000 | |
707 | #define MDP5_LM_OUT_SIZE_HEIGHT__SHIFT 16 | |
708 | static inline uint32_t MDP5_LM_OUT_SIZE_HEIGHT(uint32_t val) | |
709 | { | |
710 | return ((val) << MDP5_LM_OUT_SIZE_HEIGHT__SHIFT) & MDP5_LM_OUT_SIZE_HEIGHT__MASK; | |
711 | } | |
712 | #define MDP5_LM_OUT_SIZE_WIDTH__MASK 0x0000ffff | |
713 | #define MDP5_LM_OUT_SIZE_WIDTH__SHIFT 0 | |
714 | static inline uint32_t MDP5_LM_OUT_SIZE_WIDTH(uint32_t val) | |
715 | { | |
716 | return ((val) << MDP5_LM_OUT_SIZE_WIDTH__SHIFT) & MDP5_LM_OUT_SIZE_WIDTH__MASK; | |
717 | } | |
718 | ||
719 | static inline uint32_t REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) { return 0x00003208 + 0x400*i0; } | |
720 | ||
721 | static inline uint32_t REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) { return 0x00003210 + 0x400*i0; } | |
722 | ||
723 | static inline uint32_t REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) { return 0x00003220 + 0x400*i0 + 0x30*i1; } | |
724 | ||
725 | static inline uint32_t REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) { return 0x00003220 + 0x400*i0 + 0x30*i1; } | |
726 | #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK 0x00000003 | |
727 | #define MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT 0 | |
728 | static inline uint32_t MDP5_LM_BLEND_OP_MODE_FG_ALPHA(enum mdp_alpha_type val) | |
729 | { | |
730 | return ((val) << MDP5_LM_BLEND_OP_MODE_FG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_FG_ALPHA__MASK; | |
731 | } | |
732 | #define MDP5_LM_BLEND_OP_MODE_FG_INV_ALPHA 0x00000004 | |
733 | #define MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA 0x00000008 | |
734 | #define MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA 0x00000010 | |
735 | #define MDP5_LM_BLEND_OP_MODE_FG_TRANSP_EN 0x00000020 | |
736 | #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK 0x00000300 | |
737 | #define MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT 8 | |
738 | static inline uint32_t MDP5_LM_BLEND_OP_MODE_BG_ALPHA(enum mdp_alpha_type val) | |
739 | { | |
740 | return ((val) << MDP5_LM_BLEND_OP_MODE_BG_ALPHA__SHIFT) & MDP5_LM_BLEND_OP_MODE_BG_ALPHA__MASK; | |
741 | } | |
742 | #define MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA 0x00000400 | |
743 | #define MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA 0x00000800 | |
744 | #define MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA 0x00001000 | |
745 | #define MDP5_LM_BLEND_OP_MODE_BG_TRANSP_EN 0x00002000 | |
746 | ||
747 | static inline uint32_t REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00003224 + 0x400*i0 + 0x30*i1; } | |
748 | ||
749 | static inline uint32_t REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) { return 0x00003228 + 0x400*i0 + 0x30*i1; } | |
750 | ||
751 | static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000322c + 0x400*i0 + 0x30*i1; } | |
752 | ||
753 | static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00003230 + 0x400*i0 + 0x30*i1; } | |
754 | ||
755 | static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00003234 + 0x400*i0 + 0x30*i1; } | |
756 | ||
757 | static inline uint32_t REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00003238 + 0x400*i0 + 0x30*i1; } | |
758 | ||
759 | static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) { return 0x0000323c + 0x400*i0 + 0x30*i1; } | |
760 | ||
761 | static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) { return 0x00003240 + 0x400*i0 + 0x30*i1; } | |
762 | ||
763 | static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) { return 0x00003244 + 0x400*i0 + 0x30*i1; } | |
764 | ||
765 | static inline uint32_t REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) { return 0x00003248 + 0x400*i0 + 0x30*i1; } | |
766 | ||
767 | static inline uint32_t REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) { return 0x000032e0 + 0x400*i0; } | |
768 | ||
769 | static inline uint32_t REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) { return 0x000032e4 + 0x400*i0; } | |
770 | ||
771 | static inline uint32_t REG_MDP5_LM_CURSOR_XY(uint32_t i0) { return 0x000032e8 + 0x400*i0; } | |
772 | ||
773 | static inline uint32_t REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) { return 0x000032dc + 0x400*i0; } | |
774 | ||
775 | static inline uint32_t REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) { return 0x000032ec + 0x400*i0; } | |
776 | ||
777 | static inline uint32_t REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) { return 0x000032f0 + 0x400*i0; } | |
778 | ||
779 | static inline uint32_t REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) { return 0x000032f4 + 0x400*i0; } | |
780 | ||
781 | static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) { return 0x000032f8 + 0x400*i0; } | |
782 | ||
783 | static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) { return 0x000032fc + 0x400*i0; } | |
784 | ||
785 | static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) { return 0x00003300 + 0x400*i0; } | |
786 | ||
787 | static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) { return 0x00003304 + 0x400*i0; } | |
788 | ||
789 | static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) { return 0x00003308 + 0x400*i0; } | |
790 | ||
791 | static inline uint32_t REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) { return 0x0000330c + 0x400*i0; } | |
792 | ||
793 | static inline uint32_t REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) { return 0x00003310 + 0x400*i0; } | |
794 | ||
795 | static inline uint32_t REG_MDP5_DSPP(uint32_t i0) { return 0x00004600 + 0x400*i0; } | |
796 | ||
797 | static inline uint32_t REG_MDP5_DSPP_OP_MODE(uint32_t i0) { return 0x00004600 + 0x400*i0; } | |
798 | #define MDP5_DSPP_OP_MODE_IGC_LUT_EN 0x00000001 | |
799 | #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK 0x0000000e | |
800 | #define MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT 1 | |
801 | static inline uint32_t MDP5_DSPP_OP_MODE_IGC_TBL_IDX(uint32_t val) | |
802 | { | |
803 | return ((val) << MDP5_DSPP_OP_MODE_IGC_TBL_IDX__SHIFT) & MDP5_DSPP_OP_MODE_IGC_TBL_IDX__MASK; | |
804 | } | |
805 | #define MDP5_DSPP_OP_MODE_PCC_EN 0x00000010 | |
806 | #define MDP5_DSPP_OP_MODE_DITHER_EN 0x00000100 | |
807 | #define MDP5_DSPP_OP_MODE_HIST_EN 0x00010000 | |
808 | #define MDP5_DSPP_OP_MODE_AUTO_CLEAR 0x00020000 | |
809 | #define MDP5_DSPP_OP_MODE_HIST_LUT_EN 0x00080000 | |
810 | #define MDP5_DSPP_OP_MODE_PA_EN 0x00100000 | |
811 | #define MDP5_DSPP_OP_MODE_GAMUT_EN 0x00800000 | |
812 | #define MDP5_DSPP_OP_MODE_GAMUT_ORDER 0x01000000 | |
813 | ||
814 | static inline uint32_t REG_MDP5_DSPP_PCC_BASE(uint32_t i0) { return 0x00004630 + 0x400*i0; } | |
815 | ||
816 | static inline uint32_t REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) { return 0x00004750 + 0x400*i0; } | |
817 | ||
818 | static inline uint32_t REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) { return 0x00004810 + 0x400*i0; } | |
819 | ||
820 | static inline uint32_t REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) { return 0x00004830 + 0x400*i0; } | |
821 | ||
822 | static inline uint32_t REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) { return 0x00004834 + 0x400*i0; } | |
823 | ||
824 | static inline uint32_t REG_MDP5_DSPP_PA_BASE(uint32_t i0) { return 0x00004838 + 0x400*i0; } | |
825 | ||
826 | static inline uint32_t REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) { return 0x000048dc + 0x400*i0; } | |
827 | ||
828 | static inline uint32_t REG_MDP5_DSPP_GC_BASE(uint32_t i0) { return 0x000048b0 + 0x400*i0; } | |
829 | ||
830 | static inline uint32_t REG_MDP5_INTF(uint32_t i0) { return 0x00012500 + 0x200*i0; } | |
831 | ||
832 | static inline uint32_t REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) { return 0x00012500 + 0x200*i0; } | |
833 | ||
834 | static inline uint32_t REG_MDP5_INTF_CONFIG(uint32_t i0) { return 0x00012504 + 0x200*i0; } | |
835 | ||
836 | static inline uint32_t REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) { return 0x00012508 + 0x200*i0; } | |
837 | #define MDP5_INTF_HSYNC_CTL_PULSEW__MASK 0x0000ffff | |
838 | #define MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT 0 | |
839 | static inline uint32_t MDP5_INTF_HSYNC_CTL_PULSEW(uint32_t val) | |
840 | { | |
841 | return ((val) << MDP5_INTF_HSYNC_CTL_PULSEW__SHIFT) & MDP5_INTF_HSYNC_CTL_PULSEW__MASK; | |
842 | } | |
843 | #define MDP5_INTF_HSYNC_CTL_PERIOD__MASK 0xffff0000 | |
844 | #define MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT 16 | |
845 | static inline uint32_t MDP5_INTF_HSYNC_CTL_PERIOD(uint32_t val) | |
846 | { | |
847 | return ((val) << MDP5_INTF_HSYNC_CTL_PERIOD__SHIFT) & MDP5_INTF_HSYNC_CTL_PERIOD__MASK; | |
848 | } | |
849 | ||
850 | static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) { return 0x0001250c + 0x200*i0; } | |
851 | ||
852 | static inline uint32_t REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) { return 0x00012510 + 0x200*i0; } | |
853 | ||
854 | static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) { return 0x00012514 + 0x200*i0; } | |
855 | ||
856 | static inline uint32_t REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) { return 0x00012518 + 0x200*i0; } | |
857 | ||
858 | static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) { return 0x0001251c + 0x200*i0; } | |
859 | ||
860 | static inline uint32_t REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) { return 0x00012520 + 0x200*i0; } | |
861 | ||
862 | static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) { return 0x00012524 + 0x200*i0; } | |
863 | ||
864 | static inline uint32_t REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) { return 0x00012528 + 0x200*i0; } | |
865 | ||
866 | static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) { return 0x0001252c + 0x200*i0; } | |
867 | #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK 0x7fffffff | |
868 | #define MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT 0 | |
869 | static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F0_VAL(uint32_t val) | |
870 | { | |
871 | return ((val) << MDP5_INTF_ACTIVE_VSTART_F0_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F0_VAL__MASK; | |
872 | } | |
873 | #define MDP5_INTF_ACTIVE_VSTART_F0_ACTIVE_V_ENABLE 0x80000000 | |
874 | ||
875 | static inline uint32_t REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) { return 0x00012530 + 0x200*i0; } | |
876 | #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK 0x7fffffff | |
877 | #define MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT 0 | |
878 | static inline uint32_t MDP5_INTF_ACTIVE_VSTART_F1_VAL(uint32_t val) | |
879 | { | |
880 | return ((val) << MDP5_INTF_ACTIVE_VSTART_F1_VAL__SHIFT) & MDP5_INTF_ACTIVE_VSTART_F1_VAL__MASK; | |
881 | } | |
882 | ||
883 | static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) { return 0x00012534 + 0x200*i0; } | |
884 | ||
885 | static inline uint32_t REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) { return 0x00012538 + 0x200*i0; } | |
886 | ||
887 | static inline uint32_t REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) { return 0x0001253c + 0x200*i0; } | |
888 | #define MDP5_INTF_DISPLAY_HCTL_START__MASK 0x0000ffff | |
889 | #define MDP5_INTF_DISPLAY_HCTL_START__SHIFT 0 | |
890 | static inline uint32_t MDP5_INTF_DISPLAY_HCTL_START(uint32_t val) | |
891 | { | |
892 | return ((val) << MDP5_INTF_DISPLAY_HCTL_START__SHIFT) & MDP5_INTF_DISPLAY_HCTL_START__MASK; | |
893 | } | |
894 | #define MDP5_INTF_DISPLAY_HCTL_END__MASK 0xffff0000 | |
895 | #define MDP5_INTF_DISPLAY_HCTL_END__SHIFT 16 | |
896 | static inline uint32_t MDP5_INTF_DISPLAY_HCTL_END(uint32_t val) | |
897 | { | |
898 | return ((val) << MDP5_INTF_DISPLAY_HCTL_END__SHIFT) & MDP5_INTF_DISPLAY_HCTL_END__MASK; | |
899 | } | |
900 | ||
901 | static inline uint32_t REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) { return 0x00012540 + 0x200*i0; } | |
902 | #define MDP5_INTF_ACTIVE_HCTL_START__MASK 0x00007fff | |
903 | #define MDP5_INTF_ACTIVE_HCTL_START__SHIFT 0 | |
904 | static inline uint32_t MDP5_INTF_ACTIVE_HCTL_START(uint32_t val) | |
905 | { | |
906 | return ((val) << MDP5_INTF_ACTIVE_HCTL_START__SHIFT) & MDP5_INTF_ACTIVE_HCTL_START__MASK; | |
907 | } | |
908 | #define MDP5_INTF_ACTIVE_HCTL_END__MASK 0x7fff0000 | |
909 | #define MDP5_INTF_ACTIVE_HCTL_END__SHIFT 16 | |
910 | static inline uint32_t MDP5_INTF_ACTIVE_HCTL_END(uint32_t val) | |
911 | { | |
912 | return ((val) << MDP5_INTF_ACTIVE_HCTL_END__SHIFT) & MDP5_INTF_ACTIVE_HCTL_END__MASK; | |
913 | } | |
914 | #define MDP5_INTF_ACTIVE_HCTL_ACTIVE_H_ENABLE 0x80000000 | |
915 | ||
916 | static inline uint32_t REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) { return 0x00012544 + 0x200*i0; } | |
917 | ||
918 | static inline uint32_t REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) { return 0x00012548 + 0x200*i0; } | |
919 | ||
920 | static inline uint32_t REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) { return 0x0001254c + 0x200*i0; } | |
921 | ||
922 | static inline uint32_t REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) { return 0x00012550 + 0x200*i0; } | |
923 | #define MDP5_INTF_POLARITY_CTL_HSYNC_LOW 0x00000001 | |
924 | #define MDP5_INTF_POLARITY_CTL_VSYNC_LOW 0x00000002 | |
925 | #define MDP5_INTF_POLARITY_CTL_DATA_EN_LOW 0x00000004 | |
926 | ||
927 | static inline uint32_t REG_MDP5_INTF_TEST_CTL(uint32_t i0) { return 0x00012554 + 0x200*i0; } | |
928 | ||
929 | static inline uint32_t REG_MDP5_INTF_TP_COLOR0(uint32_t i0) { return 0x00012558 + 0x200*i0; } | |
930 | ||
931 | static inline uint32_t REG_MDP5_INTF_TP_COLOR1(uint32_t i0) { return 0x0001255c + 0x200*i0; } | |
932 | ||
933 | static inline uint32_t REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) { return 0x00012584 + 0x200*i0; } | |
934 | ||
935 | static inline uint32_t REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) { return 0x00012590 + 0x200*i0; } | |
936 | ||
937 | static inline uint32_t REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) { return 0x000125a8 + 0x200*i0; } | |
938 | ||
939 | static inline uint32_t REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) { return 0x000125ac + 0x200*i0; } | |
940 | ||
941 | static inline uint32_t REG_MDP5_INTF_LINE_COUNT(uint32_t i0) { return 0x000125b0 + 0x200*i0; } | |
942 | ||
943 | static inline uint32_t REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) { return 0x000125f0 + 0x200*i0; } | |
944 | ||
945 | static inline uint32_t REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) { return 0x000125f4 + 0x200*i0; } | |
946 | ||
947 | static inline uint32_t REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) { return 0x000125f8 + 0x200*i0; } | |
948 | ||
949 | static inline uint32_t REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) { return 0x00012600 + 0x200*i0; } | |
950 | ||
951 | static inline uint32_t REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) { return 0x00012604 + 0x200*i0; } | |
952 | ||
953 | static inline uint32_t REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) { return 0x00012608 + 0x200*i0; } | |
954 | ||
955 | static inline uint32_t REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) { return 0x0001260c + 0x200*i0; } | |
956 | ||
957 | static inline uint32_t REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) { return 0x00012610 + 0x200*i0; } | |
958 | ||
959 | static inline uint32_t REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) { return 0x00012614 + 0x200*i0; } | |
960 | ||
961 | static inline uint32_t REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) { return 0x00012618 + 0x200*i0; } | |
962 | ||
963 | static inline uint32_t REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) { return 0x0001261c + 0x200*i0; } | |
964 | ||
965 | static inline uint32_t REG_MDP5_AD(uint32_t i0) { return 0x00013100 + 0x200*i0; } | |
966 | ||
967 | static inline uint32_t REG_MDP5_AD_BYPASS(uint32_t i0) { return 0x00013100 + 0x200*i0; } | |
968 | ||
969 | static inline uint32_t REG_MDP5_AD_CTRL_0(uint32_t i0) { return 0x00013104 + 0x200*i0; } | |
970 | ||
971 | static inline uint32_t REG_MDP5_AD_CTRL_1(uint32_t i0) { return 0x00013108 + 0x200*i0; } | |
972 | ||
973 | static inline uint32_t REG_MDP5_AD_FRAME_SIZE(uint32_t i0) { return 0x0001310c + 0x200*i0; } | |
974 | ||
975 | static inline uint32_t REG_MDP5_AD_CON_CTRL_0(uint32_t i0) { return 0x00013110 + 0x200*i0; } | |
976 | ||
977 | static inline uint32_t REG_MDP5_AD_CON_CTRL_1(uint32_t i0) { return 0x00013114 + 0x200*i0; } | |
978 | ||
979 | static inline uint32_t REG_MDP5_AD_STR_MAN(uint32_t i0) { return 0x00013118 + 0x200*i0; } | |
980 | ||
981 | static inline uint32_t REG_MDP5_AD_VAR(uint32_t i0) { return 0x0001311c + 0x200*i0; } | |
982 | ||
983 | static inline uint32_t REG_MDP5_AD_DITH(uint32_t i0) { return 0x00013120 + 0x200*i0; } | |
984 | ||
985 | static inline uint32_t REG_MDP5_AD_DITH_CTRL(uint32_t i0) { return 0x00013124 + 0x200*i0; } | |
986 | ||
987 | static inline uint32_t REG_MDP5_AD_AMP_LIM(uint32_t i0) { return 0x00013128 + 0x200*i0; } | |
988 | ||
989 | static inline uint32_t REG_MDP5_AD_SLOPE(uint32_t i0) { return 0x0001312c + 0x200*i0; } | |
990 | ||
991 | static inline uint32_t REG_MDP5_AD_BW_LVL(uint32_t i0) { return 0x00013130 + 0x200*i0; } | |
992 | ||
993 | static inline uint32_t REG_MDP5_AD_LOGO_POS(uint32_t i0) { return 0x00013134 + 0x200*i0; } | |
994 | ||
995 | static inline uint32_t REG_MDP5_AD_LUT_FI(uint32_t i0) { return 0x00013138 + 0x200*i0; } | |
996 | ||
997 | static inline uint32_t REG_MDP5_AD_LUT_CC(uint32_t i0) { return 0x0001317c + 0x200*i0; } | |
998 | ||
999 | static inline uint32_t REG_MDP5_AD_STR_LIM(uint32_t i0) { return 0x000131c8 + 0x200*i0; } | |
1000 | ||
1001 | static inline uint32_t REG_MDP5_AD_CALIB_AB(uint32_t i0) { return 0x000131cc + 0x200*i0; } | |
1002 | ||
1003 | static inline uint32_t REG_MDP5_AD_CALIB_CD(uint32_t i0) { return 0x000131d0 + 0x200*i0; } | |
1004 | ||
1005 | static inline uint32_t REG_MDP5_AD_MODE_SEL(uint32_t i0) { return 0x000131d4 + 0x200*i0; } | |
1006 | ||
1007 | static inline uint32_t REG_MDP5_AD_TFILT_CTRL(uint32_t i0) { return 0x000131d8 + 0x200*i0; } | |
1008 | ||
1009 | static inline uint32_t REG_MDP5_AD_BL_MINMAX(uint32_t i0) { return 0x000131dc + 0x200*i0; } | |
1010 | ||
1011 | static inline uint32_t REG_MDP5_AD_BL(uint32_t i0) { return 0x000131e0 + 0x200*i0; } | |
1012 | ||
1013 | static inline uint32_t REG_MDP5_AD_BL_MAX(uint32_t i0) { return 0x000131e8 + 0x200*i0; } | |
1014 | ||
1015 | static inline uint32_t REG_MDP5_AD_AL(uint32_t i0) { return 0x000131ec + 0x200*i0; } | |
1016 | ||
1017 | static inline uint32_t REG_MDP5_AD_AL_MIN(uint32_t i0) { return 0x000131f0 + 0x200*i0; } | |
1018 | ||
1019 | static inline uint32_t REG_MDP5_AD_AL_FILT(uint32_t i0) { return 0x000131f4 + 0x200*i0; } | |
1020 | ||
1021 | static inline uint32_t REG_MDP5_AD_CFG_BUF(uint32_t i0) { return 0x000131f8 + 0x200*i0; } | |
1022 | ||
1023 | static inline uint32_t REG_MDP5_AD_LUT_AL(uint32_t i0) { return 0x00013200 + 0x200*i0; } | |
1024 | ||
1025 | static inline uint32_t REG_MDP5_AD_TARG_STR(uint32_t i0) { return 0x00013244 + 0x200*i0; } | |
1026 | ||
1027 | static inline uint32_t REG_MDP5_AD_START_CALC(uint32_t i0) { return 0x00013248 + 0x200*i0; } | |
1028 | ||
1029 | static inline uint32_t REG_MDP5_AD_STR_OUT(uint32_t i0) { return 0x0001324c + 0x200*i0; } | |
1030 | ||
1031 | static inline uint32_t REG_MDP5_AD_BL_OUT(uint32_t i0) { return 0x00013254 + 0x200*i0; } | |
1032 | ||
1033 | static inline uint32_t REG_MDP5_AD_CALC_DONE(uint32_t i0) { return 0x00013258 + 0x200*i0; } | |
1034 | ||
1035 | ||
1036 | #endif /* MDP5_XML */ |