[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / msm / mdp / mdp5 / mdp5_cfg.h

/*
 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __MDP5_CFG_H__
#define __MDP5_CFG_H__

#include "msm_drv.h"

/*
 * mdp5_cfg
 *
 * This module configures the dynamic offsets used by mdp5.xml.h
 * (initialized in mdp5_cfg.c)
 */
extern const struct mdp5_cfg_hw *mdp5_cfg;

#define MAX_CTL			8
#define MAX_BASES		8
#define MAX_SMP_BLOCKS		44
#define MAX_CLIENTS		32

typedef DECLARE_BITMAP(mdp5_smp_state_t, MAX_SMP_BLOCKS);

#define MDP5_SUB_BLOCK_DEFINITION \
	int count; \
	uint32_t base[MAX_BASES]

struct mdp5_sub_block {
	MDP5_SUB_BLOCK_DEFINITION;
};

struct mdp5_lm_block {
	MDP5_SUB_BLOCK_DEFINITION;
	uint32_t nb_stages;		/* number of stages per blender */
	uint32_t max_width;		/* Maximum output resolution */
	uint32_t max_height;
};

struct mdp5_pipe_block {
	MDP5_SUB_BLOCK_DEFINITION;
	uint32_t caps;			/* pipe capabilities */
};

struct mdp5_ctl_block {
	MDP5_SUB_BLOCK_DEFINITION;
	uint32_t flush_hw_mask;		/* FLUSH register's hardware mask */
};

struct mdp5_smp_block {
	int mmb_count;			/* number of SMP MMBs */
	int mmb_size;			/* MMB: size in bytes */
	uint32_t clients[MAX_CLIENTS];	/* SMP port allocation /pipe */
	mdp5_smp_state_t reserved_state;/* SMP MMBs statically allocated */
	uint8_t reserved[MAX_CLIENTS];	/* # of MMBs allocated per client */
};

struct mdp5_mdp_block {
	MDP5_SUB_BLOCK_DEFINITION;
	uint32_t caps;			/* MDP capabilities: MDP_CAP_xxx bits */
};

#define MDP5_INTF_NUM_MAX	5

struct mdp5_intf_block {
	uint32_t base[MAX_BASES];
	u32 connect[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
};

struct mdp5_cfg_hw {
	char  *name;

	struct mdp5_mdp_block mdp;
	struct mdp5_smp_block smp;
	struct mdp5_ctl_block ctl;
	struct mdp5_pipe_block pipe_vig;
	struct mdp5_pipe_block pipe_rgb;
	struct mdp5_pipe_block pipe_dma;
	struct mdp5_lm_block  lm;
	struct mdp5_sub_block dspp;
	struct mdp5_sub_block ad;
	struct mdp5_sub_block pp;
	struct mdp5_sub_block dsc;
	struct mdp5_sub_block cdm;
	struct mdp5_intf_block intf;

	uint32_t max_clk;
};

/* platform config data (ie. from DT, or pdata) */
struct mdp5_cfg_platform {
	struct iommu_domain *iommu;
};

struct mdp5_cfg {
	const struct mdp5_cfg_hw *hw;
	struct mdp5_cfg_platform platform;
};

struct mdp5_kms;
struct mdp5_cfg_handler;

const struct mdp5_cfg_hw *mdp5_cfg_get_hw_config(struct mdp5_cfg_handler *cfg_hnd);
struct mdp5_cfg *mdp5_cfg_get_config(struct mdp5_cfg_handler *cfg_hnd);
int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_hnd);

#define mdp5_cfg_intf_is_virtual(intf_type) ({	\
	typeof(intf_type) __val = (intf_type);	\
	(__val) >= INTF_VIRTUAL ? true : false; })

struct mdp5_cfg_handler *mdp5_cfg_init(struct mdp5_kms *mdp5_kms,
		uint32_t major, uint32_t minor);
void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_hnd);

#endif /* __MDP5_CFG_H__ */
Commit	Line	Data
2e362e17 SV	1	/*
	2	* Copyright (c) 2014 The Linux Foundation. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 and
	6	* only version 2 as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope that it will be useful,
	9	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	10	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	11	* GNU General Public License for more details.
	12	*/
	13
	14	#ifndef __MDP5_CFG_H__
	15	#define __MDP5_CFG_H__
	16
	17	#include "msm_drv.h"
	18
	19	/*
	20	* mdp5_cfg
	21	*
	22	* This module configures the dynamic offsets used by mdp5.xml.h
	23	* (initialized in mdp5_cfg.c)
	24	*/
	25	extern const struct mdp5_cfg_hw *mdp5_cfg;
	26
0deed25b	27	#define MAX_CTL 8
2e362e17 SV	28	#define MAX_BASES 8
	29	#define MAX_SMP_BLOCKS 44
	30	#define MAX_CLIENTS 32
	31
	32	typedef DECLARE_BITMAP(mdp5_smp_state_t, MAX_SMP_BLOCKS);
	33
	34	#define MDP5_SUB_BLOCK_DEFINITION \
	35	int count; \
	36	uint32_t base[MAX_BASES]
	37
	38	struct mdp5_sub_block {
	39	MDP5_SUB_BLOCK_DEFINITION;
	40	};
	41
	42	struct mdp5_lm_block {
	43	MDP5_SUB_BLOCK_DEFINITION;
	44	uint32_t nb_stages; /* number of stages per blender */
9b7a9fc2 HL	45	uint32_t max_width; /* Maximum output resolution */
9b7a9fc2 HL	46	uint32_t max_height;
2e362e17 SV	47	};
2e362e17 SV	48
3498409f	49	struct mdp5_pipe_block {
	50	MDP5_SUB_BLOCK_DEFINITION;
	51	uint32_t caps; /* pipe capabilities */
	52	};
	53
389b09a1 SV	54	struct mdp5_ctl_block {
	55	MDP5_SUB_BLOCK_DEFINITION;
	56	uint32_t flush_hw_mask; /* FLUSH register's hardware mask */
	57	};
	58
2e362e17 SV	59	struct mdp5_smp_block {
	60	int mmb_count; /* number of SMP MMBs */
	61	int mmb_size; /* MMB: size in bytes */
6fa6acdf	62	uint32_t clients[MAX_CLIENTS]; /* SMP port allocation /pipe */
2e362e17	63	mdp5_smp_state_t reserved_state;/* SMP MMBs statically allocated */
60fb49ca	64	uint8_t reserved[MAX_CLIENTS]; /* # of MMBs allocated per client */
2e362e17 SV	65	};
2e362e17 SV	66
d879eb5a SV	67	struct mdp5_mdp_block {
	68	MDP5_SUB_BLOCK_DEFINITION;
	69	uint32_t caps; /* MDP capabilities: MDP_CAP_xxx bits */
	70	};
	71
67ac0a2d SV	72	#define MDP5_INTF_NUM_MAX 5
67ac0a2d SV	73
fe34464d SV	74	struct mdp5_intf_block {
	75	uint32_t base[MAX_BASES];
	76	u32 connect[MDP5_INTF_NUM_MAX]; /* array of enum mdp5_intf_type */
	77	};
	78
2e362e17 SV	79	struct mdp5_cfg_hw {
	80	char *name;
	81
d879eb5a	82	struct mdp5_mdp_block mdp;
2e362e17	83	struct mdp5_smp_block smp;
389b09a1	84	struct mdp5_ctl_block ctl;
3498409f	85	struct mdp5_pipe_block pipe_vig;
	86	struct mdp5_pipe_block pipe_rgb;
	87	struct mdp5_pipe_block pipe_dma;
2e362e17 SV	88	struct mdp5_lm_block lm;
	89	struct mdp5_sub_block dspp;
	90	struct mdp5_sub_block ad;
38305907	91	struct mdp5_sub_block pp;
d879eb5a SV	92	struct mdp5_sub_block dsc;
d879eb5a SV	93	struct mdp5_sub_block cdm;
fe34464d	94	struct mdp5_intf_block intf;
67ac0a2d	95
2e362e17 SV	96	uint32_t max_clk;
	97	};
	98
	99	/* platform config data (ie. from DT, or pdata) */
	100	struct mdp5_cfg_platform {
	101	struct iommu_domain *iommu;
	102	};
	103
	104	struct mdp5_cfg {
	105	const struct mdp5_cfg_hw *hw;
	106	struct mdp5_cfg_platform platform;
	107	};
	108
	109	struct mdp5_kms;
42238da8	110	struct mdp5_cfg_handler;
2e362e17	111
42238da8 RC	112	const struct mdp5_cfg_hw mdp5_cfg_get_hw_config(struct mdp5_cfg_handler cfg_hnd);
	113	struct mdp5_cfg mdp5_cfg_get_config(struct mdp5_cfg_handler cfg_hnd);
	114	int mdp5_cfg_get_hw_rev(struct mdp5_cfg_handler *cfg_hnd);
2e362e17	115
d145dd78 SV	116	#define mdp5_cfg_intf_is_virtual(intf_type) ({ \
	117	typeof(intf_type) __val = (intf_type); \
	118	(__val) >= INTF_VIRTUAL ? true : false; })
	119
42238da8 RC	120	struct mdp5_cfg_handler mdp5_cfg_init(struct mdp5_kms mdp5_kms,
	121	uint32_t major, uint32_t minor);
	122	void mdp5_cfg_destroy(struct mdp5_cfg_handler *cfg_hnd);
2e362e17 SV	123
2e362e17 SV	124	#endif /* __MDP5_CFG_H__ */