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06c0dd96 | 1 | /* |
68cdbed9 | 2 | * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved. |
06c0dd96 RC |
3 | * Copyright (C) 2013 Red Hat |
4 | * Author: Rob Clark <robdclark@gmail.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published by | |
8 | * the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
13 | * more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along with | |
16 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
17 | */ | |
18 | ||
ed851963 | 19 | #include <linux/sort.h> |
06c0dd96 | 20 | #include <drm/drm_mode.h> |
78f27b1c MY |
21 | #include <drm/drm_crtc.h> |
22 | #include <drm/drm_crtc_helper.h> | |
23 | #include <drm/drm_flip_work.h> | |
24 | ||
25 | #include "mdp5_kms.h" | |
06c0dd96 | 26 | |
e172d10a BG |
27 | #define CURSOR_WIDTH 64 |
28 | #define CURSOR_HEIGHT 64 | |
29 | ||
06c0dd96 RC |
30 | struct mdp5_crtc { |
31 | struct drm_crtc base; | |
06c0dd96 RC |
32 | int id; |
33 | bool enabled; | |
34 | ||
adfc0e63 | 35 | spinlock_t lm_lock; /* protect REG_MDP5_LM_* registers */ |
0deed25b | 36 | |
06c0dd96 RC |
37 | /* if there is a pending flip, these will be non-null: */ |
38 | struct drm_pending_vblank_event *event; | |
06c0dd96 | 39 | |
0a5c9aad HL |
40 | /* Bits have been flushed at the last commit, |
41 | * used to decide if a vsync has happened since last commit. | |
42 | */ | |
43 | u32 flushed_mask; | |
44 | ||
06c0dd96 RC |
45 | #define PENDING_CURSOR 0x1 |
46 | #define PENDING_FLIP 0x2 | |
47 | atomic_t pending; | |
48 | ||
e172d10a BG |
49 | /* for unref'ing cursor bo's after scanout completes: */ |
50 | struct drm_flip_work unref_cursor_work; | |
51 | ||
06c0dd96 RC |
52 | struct mdp_irq vblank; |
53 | struct mdp_irq err; | |
68cdbed9 HL |
54 | struct mdp_irq pp_done; |
55 | ||
56 | struct completion pp_completion; | |
57 | ||
e172d10a BG |
58 | struct { |
59 | /* protect REG_MDP5_LM_CURSOR* registers and cursor scanout_bo*/ | |
60 | spinlock_t lock; | |
61 | ||
62 | /* current cursor being scanned out: */ | |
63 | struct drm_gem_object *scanout_bo; | |
58560890 RC |
64 | uint32_t width, height; |
65 | uint32_t x, y; | |
e172d10a | 66 | } cursor; |
06c0dd96 RC |
67 | }; |
68 | #define to_mdp5_crtc(x) container_of(x, struct mdp5_crtc, base) | |
69 | ||
70 | static struct mdp5_kms *get_kms(struct drm_crtc *crtc) | |
71 | { | |
72 | struct msm_drm_private *priv = crtc->dev->dev_private; | |
73 | return to_mdp5_kms(to_mdp_kms(priv->kms)); | |
74 | } | |
75 | ||
76 | static void request_pending(struct drm_crtc *crtc, uint32_t pending) | |
77 | { | |
78 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
79 | ||
80 | atomic_or(pending, &mdp5_crtc->pending); | |
81 | mdp_irq_register(&get_kms(crtc)->base, &mdp5_crtc->vblank); | |
82 | } | |
83 | ||
68cdbed9 HL |
84 | static void request_pp_done_pending(struct drm_crtc *crtc) |
85 | { | |
86 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
87 | reinit_completion(&mdp5_crtc->pp_completion); | |
88 | } | |
89 | ||
0a5c9aad | 90 | static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask) |
0deed25b | 91 | { |
0ddc3a63 AT |
92 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
93 | struct mdp5_ctl *ctl = mdp5_cstate->ctl; | |
f316b25a | 94 | struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; |
0deed25b | 95 | |
cee26588 | 96 | DBG("%s: flush=%08x", crtc->name, flush_mask); |
f316b25a | 97 | return mdp5_ctl_commit(ctl, pipeline, flush_mask); |
0deed25b SV |
98 | } |
99 | ||
100 | /* | |
101 | * flush updates, to make sure hw is updated to new scanout fb, | |
102 | * so that we can safely queue unref to current fb (ie. next | |
103 | * vblank we know hw is done w/ previous scanout_fb). | |
104 | */ | |
0a5c9aad | 105 | static u32 crtc_flush_all(struct drm_crtc *crtc) |
06c0dd96 | 106 | { |
0ddc3a63 | 107 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
b7621b2a | 108 | struct mdp5_hw_mixer *mixer, *r_mixer; |
a8cecf33 | 109 | struct drm_plane *plane; |
0deed25b SV |
110 | uint32_t flush_mask = 0; |
111 | ||
ba0312a6 | 112 | /* this should not happen: */ |
0ddc3a63 | 113 | if (WARN_ON(!mdp5_cstate->ctl)) |
0a5c9aad | 114 | return 0; |
06c0dd96 | 115 | |
93b02beb | 116 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
0deed25b | 117 | flush_mask |= mdp5_plane_get_flush(plane); |
06c0dd96 | 118 | } |
389b09a1 | 119 | |
0ddc3a63 | 120 | mixer = mdp5_cstate->pipeline.mixer; |
adfc0e63 | 121 | flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm); |
a8cecf33 | 122 | |
b7621b2a AT |
123 | r_mixer = mdp5_cstate->pipeline.r_mixer; |
124 | if (r_mixer) | |
125 | flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm); | |
126 | ||
0a5c9aad | 127 | return crtc_flush(crtc, flush_mask); |
06c0dd96 RC |
128 | } |
129 | ||
06c0dd96 RC |
130 | /* if file!=NULL, this is preclose potential cancel-flip path */ |
131 | static void complete_flip(struct drm_crtc *crtc, struct drm_file *file) | |
132 | { | |
0ddc3a63 | 133 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
f316b25a | 134 | struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; |
06c0dd96 | 135 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); |
0ddc3a63 | 136 | struct mdp5_ctl *ctl = mdp5_cstate->ctl; |
06c0dd96 RC |
137 | struct drm_device *dev = crtc->dev; |
138 | struct drm_pending_vblank_event *event; | |
a8cecf33 | 139 | unsigned long flags; |
06c0dd96 RC |
140 | |
141 | spin_lock_irqsave(&dev->event_lock, flags); | |
142 | event = mdp5_crtc->event; | |
143 | if (event) { | |
02efb359 DV |
144 | mdp5_crtc->event = NULL; |
145 | DBG("%s: send event: %p", crtc->name, event); | |
146 | drm_crtc_send_vblank_event(crtc, event); | |
06c0dd96 RC |
147 | } |
148 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
149 | ||
0ddc3a63 | 150 | if (ctl && !crtc->state->enable) { |
e5989ee1 | 151 | /* set STAGE_UNUSED for all layers */ |
b7621b2a | 152 | mdp5_ctl_blend(ctl, pipeline, NULL, NULL, 0, 0); |
0ddc3a63 AT |
153 | /* XXX: What to do here? */ |
154 | /* mdp5_crtc->ctl = NULL; */ | |
ba0312a6 | 155 | } |
06c0dd96 RC |
156 | } |
157 | ||
e172d10a BG |
158 | static void unref_cursor_worker(struct drm_flip_work *work, void *val) |
159 | { | |
160 | struct mdp5_crtc *mdp5_crtc = | |
161 | container_of(work, struct mdp5_crtc, unref_cursor_work); | |
162 | struct mdp5_kms *mdp5_kms = get_kms(&mdp5_crtc->base); | |
f59f62d5 | 163 | struct msm_kms *kms = &mdp5_kms->base.base; |
e172d10a | 164 | |
8bdcd949 | 165 | msm_gem_put_iova(val, kms->aspace); |
e172d10a BG |
166 | drm_gem_object_unreference_unlocked(val); |
167 | } | |
168 | ||
06c0dd96 RC |
169 | static void mdp5_crtc_destroy(struct drm_crtc *crtc) |
170 | { | |
171 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
172 | ||
06c0dd96 | 173 | drm_crtc_cleanup(crtc); |
e172d10a | 174 | drm_flip_work_cleanup(&mdp5_crtc->unref_cursor_work); |
06c0dd96 RC |
175 | |
176 | kfree(mdp5_crtc); | |
177 | } | |
178 | ||
829200ac AT |
179 | static inline u32 mdp5_lm_use_fg_alpha_mask(enum mdp_mixer_stage_id stage) |
180 | { | |
181 | switch (stage) { | |
182 | case STAGE0: return MDP5_LM_BLEND_COLOR_OUT_STAGE0_FG_ALPHA; | |
183 | case STAGE1: return MDP5_LM_BLEND_COLOR_OUT_STAGE1_FG_ALPHA; | |
184 | case STAGE2: return MDP5_LM_BLEND_COLOR_OUT_STAGE2_FG_ALPHA; | |
185 | case STAGE3: return MDP5_LM_BLEND_COLOR_OUT_STAGE3_FG_ALPHA; | |
186 | case STAGE4: return MDP5_LM_BLEND_COLOR_OUT_STAGE4_FG_ALPHA; | |
187 | case STAGE5: return MDP5_LM_BLEND_COLOR_OUT_STAGE5_FG_ALPHA; | |
188 | case STAGE6: return MDP5_LM_BLEND_COLOR_OUT_STAGE6_FG_ALPHA; | |
189 | default: | |
190 | return 0; | |
191 | } | |
192 | } | |
193 | ||
b7621b2a AT |
194 | /* |
195 | * left/right pipe offsets for the stage array used in blend_setup() | |
196 | */ | |
197 | #define PIPE_LEFT 0 | |
198 | #define PIPE_RIGHT 1 | |
199 | ||
0deed25b SV |
200 | /* |
201 | * blend_setup() - blend all the planes of a CRTC | |
202 | * | |
12987781 | 203 | * If no base layer is available, border will be enabled as the base layer. |
204 | * Otherwise all layers will be blended based on their stage calculated | |
205 | * in mdp5_crtc_atomic_check. | |
0deed25b | 206 | */ |
06c0dd96 RC |
207 | static void blend_setup(struct drm_crtc *crtc) |
208 | { | |
209 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
0ddc3a63 | 210 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
f316b25a | 211 | struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; |
06c0dd96 | 212 | struct mdp5_kms *mdp5_kms = get_kms(crtc); |
0deed25b SV |
213 | struct drm_plane *plane; |
214 | const struct mdp5_cfg_hw *hw_cfg; | |
12987781 | 215 | struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL}; |
216 | const struct mdp_format *format; | |
f316b25a | 217 | struct mdp5_hw_mixer *mixer = pipeline->mixer; |
adfc0e63 | 218 | uint32_t lm = mixer->lm; |
b7621b2a AT |
219 | struct mdp5_hw_mixer *r_mixer = pipeline->r_mixer; |
220 | uint32_t r_lm = r_mixer ? r_mixer->lm : 0; | |
0ddc3a63 | 221 | struct mdp5_ctl *ctl = mdp5_cstate->ctl; |
12987781 | 222 | uint32_t blend_op, fg_alpha, bg_alpha, ctl_blend_flags = 0; |
0deed25b | 223 | unsigned long flags; |
b7621b2a AT |
224 | enum mdp5_pipe stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { SSPP_NONE }; |
225 | enum mdp5_pipe r_stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { SSPP_NONE }; | |
12987781 | 226 | int i, plane_cnt = 0; |
829200ac AT |
227 | bool bg_alpha_enabled = false; |
228 | u32 mixer_op_mode = 0; | |
ed78560d | 229 | u32 val; |
12987781 | 230 | #define blender(stage) ((stage) - STAGE0) |
06c0dd96 | 231 | |
42238da8 | 232 | hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); |
06c0dd96 | 233 | |
0deed25b SV |
234 | spin_lock_irqsave(&mdp5_crtc->lm_lock, flags); |
235 | ||
236 | /* ctl could be released already when we are shutting down: */ | |
0ddc3a63 AT |
237 | /* XXX: Can this happen now? */ |
238 | if (!ctl) | |
0deed25b SV |
239 | goto out; |
240 | ||
12987781 | 241 | /* Collect all plane information */ |
93b02beb | 242 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
bf8dc0a0 AT |
243 | enum mdp5_pipe right_pipe; |
244 | ||
12987781 | 245 | pstate = to_mdp5_plane_state(plane->state); |
246 | pstates[pstate->stage] = pstate; | |
b7621b2a AT |
247 | stage[pstate->stage][PIPE_LEFT] = mdp5_plane_pipe(plane); |
248 | /* | |
249 | * if we have a right mixer, stage the same pipe as we | |
250 | * have on the left mixer | |
251 | */ | |
252 | if (r_mixer) | |
253 | r_stage[pstate->stage][PIPE_LEFT] = | |
254 | mdp5_plane_pipe(plane); | |
bf8dc0a0 AT |
255 | /* |
256 | * if we have a right pipe (i.e, the plane comprises of 2 | |
257 | * hwpipes, then stage the right pipe on the right side of both | |
258 | * the layer mixers | |
259 | */ | |
260 | right_pipe = mdp5_plane_right_pipe(plane); | |
261 | if (right_pipe) { | |
262 | stage[pstate->stage][PIPE_RIGHT] = right_pipe; | |
263 | r_stage[pstate->stage][PIPE_RIGHT] = right_pipe; | |
264 | } | |
b7621b2a | 265 | |
12987781 | 266 | plane_cnt++; |
267 | } | |
06c0dd96 | 268 | |
1455adbd | 269 | if (!pstates[STAGE_BASE]) { |
12987781 | 270 | ctl_blend_flags |= MDP5_CTL_BLEND_OP_FLAG_BORDER_OUT; |
271 | DBG("Border Color is enabled"); | |
829200ac AT |
272 | } else if (plane_cnt) { |
273 | format = to_mdp_format(msm_framebuffer_format(pstates[STAGE_BASE]->base.fb)); | |
274 | ||
275 | if (format->alpha_enable) | |
276 | bg_alpha_enabled = true; | |
12987781 | 277 | } |
278 | ||
279 | /* The reset for blending */ | |
280 | for (i = STAGE0; i <= STAGE_MAX; i++) { | |
281 | if (!pstates[i]) | |
282 | continue; | |
283 | ||
284 | format = to_mdp_format( | |
285 | msm_framebuffer_format(pstates[i]->base.fb)); | |
286 | plane = pstates[i]->base.plane; | |
287 | blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) | | |
288 | MDP5_LM_BLEND_OP_MODE_BG_ALPHA(BG_CONST); | |
289 | fg_alpha = pstates[i]->alpha; | |
290 | bg_alpha = 0xFF - pstates[i]->alpha; | |
829200ac AT |
291 | |
292 | if (!format->alpha_enable && bg_alpha_enabled) | |
293 | mixer_op_mode = 0; | |
294 | else | |
295 | mixer_op_mode |= mdp5_lm_use_fg_alpha_mask(i); | |
296 | ||
12987781 | 297 | DBG("Stage %d fg_alpha %x bg_alpha %x", i, fg_alpha, bg_alpha); |
298 | ||
299 | if (format->alpha_enable && pstates[i]->premultiplied) { | |
300 | blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_CONST) | | |
301 | MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL); | |
302 | if (fg_alpha != 0xff) { | |
303 | bg_alpha = fg_alpha; | |
304 | blend_op |= | |
305 | MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA | | |
306 | MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA; | |
307 | } else { | |
308 | blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA; | |
309 | } | |
310 | } else if (format->alpha_enable) { | |
311 | blend_op = MDP5_LM_BLEND_OP_MODE_FG_ALPHA(FG_PIXEL) | | |
312 | MDP5_LM_BLEND_OP_MODE_BG_ALPHA(FG_PIXEL); | |
313 | if (fg_alpha != 0xff) { | |
314 | bg_alpha = fg_alpha; | |
315 | blend_op |= | |
316 | MDP5_LM_BLEND_OP_MODE_FG_MOD_ALPHA | | |
317 | MDP5_LM_BLEND_OP_MODE_FG_INV_MOD_ALPHA | | |
318 | MDP5_LM_BLEND_OP_MODE_BG_MOD_ALPHA | | |
319 | MDP5_LM_BLEND_OP_MODE_BG_INV_MOD_ALPHA; | |
320 | } else { | |
321 | blend_op |= MDP5_LM_BLEND_OP_MODE_BG_INV_ALPHA; | |
322 | } | |
323 | } | |
0deed25b | 324 | |
12987781 | 325 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(lm, |
326 | blender(i)), blend_op); | |
0deed25b | 327 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(lm, |
12987781 | 328 | blender(i)), fg_alpha); |
0deed25b | 329 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(lm, |
12987781 | 330 | blender(i)), bg_alpha); |
b7621b2a AT |
331 | if (r_mixer) { |
332 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_OP_MODE(r_lm, | |
333 | blender(i)), blend_op); | |
334 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_FG_ALPHA(r_lm, | |
335 | blender(i)), fg_alpha); | |
336 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_BG_ALPHA(r_lm, | |
337 | blender(i)), bg_alpha); | |
338 | } | |
0deed25b SV |
339 | } |
340 | ||
ed78560d AT |
341 | val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm)); |
342 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), | |
343 | val | mixer_op_mode); | |
344 | if (r_mixer) { | |
345 | val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm)); | |
b7621b2a | 346 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), |
ed78560d AT |
347 | val | mixer_op_mode); |
348 | } | |
829200ac | 349 | |
b7621b2a AT |
350 | mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt, |
351 | ctl_blend_flags); | |
0deed25b SV |
352 | out: |
353 | spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags); | |
06c0dd96 RC |
354 | } |
355 | ||
ed851963 | 356 | static void mdp5_crtc_mode_set_nofb(struct drm_crtc *crtc) |
06c0dd96 RC |
357 | { |
358 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
0ddc3a63 | 359 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
06c0dd96 | 360 | struct mdp5_kms *mdp5_kms = get_kms(crtc); |
0ddc3a63 | 361 | struct mdp5_hw_mixer *mixer = mdp5_cstate->pipeline.mixer; |
b7621b2a | 362 | struct mdp5_hw_mixer *r_mixer = mdp5_cstate->pipeline.r_mixer; |
adfc0e63 | 363 | uint32_t lm = mixer->lm; |
ed78560d | 364 | u32 mixer_width, val; |
0deed25b | 365 | unsigned long flags; |
ed851963 RC |
366 | struct drm_display_mode *mode; |
367 | ||
368 | if (WARN_ON(!crtc->state)) | |
369 | return; | |
06c0dd96 | 370 | |
ed851963 | 371 | mode = &crtc->state->adjusted_mode; |
06c0dd96 RC |
372 | |
373 | DBG("%s: set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x", | |
cee26588 | 374 | crtc->name, mode->base.id, mode->name, |
06c0dd96 RC |
375 | mode->vrefresh, mode->clock, |
376 | mode->hdisplay, mode->hsync_start, | |
377 | mode->hsync_end, mode->htotal, | |
378 | mode->vdisplay, mode->vsync_start, | |
379 | mode->vsync_end, mode->vtotal, | |
380 | mode->type, mode->flags); | |
381 | ||
ed78560d AT |
382 | mixer_width = mode->hdisplay; |
383 | if (r_mixer) | |
384 | mixer_width /= 2; | |
385 | ||
0deed25b | 386 | spin_lock_irqsave(&mdp5_crtc->lm_lock, flags); |
adfc0e63 | 387 | mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(lm), |
ed78560d | 388 | MDP5_LM_OUT_SIZE_WIDTH(mixer_width) | |
06c0dd96 | 389 | MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay)); |
ed78560d AT |
390 | |
391 | /* Assign mixer to LEFT side in source split mode */ | |
392 | val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm)); | |
393 | val &= ~MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT; | |
394 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(lm), val); | |
395 | ||
396 | if (r_mixer) { | |
397 | u32 r_lm = r_mixer->lm; | |
398 | ||
399 | mdp5_write(mdp5_kms, REG_MDP5_LM_OUT_SIZE(r_lm), | |
400 | MDP5_LM_OUT_SIZE_WIDTH(mixer_width) | | |
b7621b2a | 401 | MDP5_LM_OUT_SIZE_HEIGHT(mode->vdisplay)); |
ed78560d AT |
402 | |
403 | /* Assign mixer to RIGHT side in source split mode */ | |
404 | val = mdp5_read(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm)); | |
405 | val |= MDP5_LM_BLEND_COLOR_OUT_SPLIT_LEFT_RIGHT; | |
406 | mdp5_write(mdp5_kms, REG_MDP5_LM_BLEND_COLOR_OUT(r_lm), val); | |
407 | } | |
408 | ||
0deed25b | 409 | spin_unlock_irqrestore(&mdp5_crtc->lm_lock, flags); |
06c0dd96 RC |
410 | } |
411 | ||
0b776d45 | 412 | static void mdp5_crtc_disable(struct drm_crtc *crtc) |
06c0dd96 RC |
413 | { |
414 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
0ddc3a63 | 415 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
0b776d45 RC |
416 | struct mdp5_kms *mdp5_kms = get_kms(crtc); |
417 | ||
cee26588 | 418 | DBG("%s", crtc->name); |
0b776d45 RC |
419 | |
420 | if (WARN_ON(!mdp5_crtc->enabled)) | |
421 | return; | |
422 | ||
0ddc3a63 | 423 | if (mdp5_cstate->cmd_mode) |
68cdbed9 HL |
424 | mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->pp_done); |
425 | ||
0b776d45 RC |
426 | mdp_irq_unregister(&mdp5_kms->base, &mdp5_crtc->err); |
427 | mdp5_disable(mdp5_kms); | |
428 | ||
429 | mdp5_crtc->enabled = false; | |
06c0dd96 RC |
430 | } |
431 | ||
0b20a0f8 LP |
432 | static void mdp5_crtc_atomic_enable(struct drm_crtc *crtc, |
433 | struct drm_crtc_state *old_state) | |
06c0dd96 | 434 | { |
ed851963 | 435 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); |
0ddc3a63 | 436 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
0b776d45 RC |
437 | struct mdp5_kms *mdp5_kms = get_kms(crtc); |
438 | ||
cee26588 | 439 | DBG("%s", crtc->name); |
0b776d45 RC |
440 | |
441 | if (WARN_ON(mdp5_crtc->enabled)) | |
442 | return; | |
443 | ||
444 | mdp5_enable(mdp5_kms); | |
445 | mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->err); | |
446 | ||
0ddc3a63 | 447 | if (mdp5_cstate->cmd_mode) |
68cdbed9 HL |
448 | mdp_irq_register(&mdp5_kms->base, &mdp5_crtc->pp_done); |
449 | ||
0b776d45 | 450 | mdp5_crtc->enabled = true; |
06c0dd96 RC |
451 | } |
452 | ||
894558ec | 453 | int mdp5_crtc_setup_pipeline(struct drm_crtc *crtc, |
8480adac AT |
454 | struct drm_crtc_state *new_crtc_state, |
455 | bool need_right_mixer) | |
894558ec AT |
456 | { |
457 | struct mdp5_crtc_state *mdp5_cstate = | |
458 | to_mdp5_crtc_state(new_crtc_state); | |
459 | struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; | |
bcb877b7 | 460 | struct mdp5_interface *intf; |
894558ec AT |
461 | bool new_mixer = false; |
462 | ||
463 | new_mixer = !pipeline->mixer; | |
464 | ||
8480adac AT |
465 | if ((need_right_mixer && !pipeline->r_mixer) || |
466 | (!need_right_mixer && pipeline->r_mixer)) | |
467 | new_mixer = true; | |
468 | ||
894558ec AT |
469 | if (new_mixer) { |
470 | struct mdp5_hw_mixer *old_mixer = pipeline->mixer; | |
8480adac AT |
471 | struct mdp5_hw_mixer *old_r_mixer = pipeline->r_mixer; |
472 | u32 caps; | |
473 | int ret; | |
474 | ||
475 | caps = MDP_LM_CAP_DISPLAY; | |
476 | if (need_right_mixer) | |
477 | caps |= MDP_LM_CAP_PAIR; | |
894558ec | 478 | |
8480adac AT |
479 | ret = mdp5_mixer_assign(new_crtc_state->state, crtc, caps, |
480 | &pipeline->mixer, need_right_mixer ? | |
481 | &pipeline->r_mixer : NULL); | |
482 | if (ret) | |
483 | return ret; | |
894558ec AT |
484 | |
485 | mdp5_mixer_release(new_crtc_state->state, old_mixer); | |
8480adac AT |
486 | if (old_r_mixer) { |
487 | mdp5_mixer_release(new_crtc_state->state, old_r_mixer); | |
488 | if (!need_right_mixer) | |
489 | pipeline->r_mixer = NULL; | |
490 | } | |
894558ec AT |
491 | } |
492 | ||
bcb877b7 AT |
493 | /* |
494 | * these should have been already set up in the encoder's atomic | |
495 | * check (called by drm_atomic_helper_check_modeset) | |
496 | */ | |
497 | intf = pipeline->intf; | |
498 | ||
499 | mdp5_cstate->err_irqmask = intf2err(intf->num); | |
500 | mdp5_cstate->vblank_irqmask = intf2vblank(pipeline->mixer, intf); | |
501 | ||
502 | if ((intf->type == INTF_DSI) && | |
503 | (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)) { | |
504 | mdp5_cstate->pp_done_irqmask = lm2ppdone(pipeline->mixer); | |
505 | mdp5_cstate->cmd_mode = true; | |
506 | } else { | |
507 | mdp5_cstate->pp_done_irqmask = 0; | |
508 | mdp5_cstate->cmd_mode = false; | |
509 | } | |
510 | ||
894558ec AT |
511 | return 0; |
512 | } | |
513 | ||
ed851963 RC |
514 | struct plane_state { |
515 | struct drm_plane *plane; | |
516 | struct mdp5_plane_state *state; | |
517 | }; | |
518 | ||
519 | static int pstate_cmp(const void *a, const void *b) | |
06c0dd96 | 520 | { |
ed851963 RC |
521 | struct plane_state *pa = (struct plane_state *)a; |
522 | struct plane_state *pb = (struct plane_state *)b; | |
523 | return pa->state->zpos - pb->state->zpos; | |
06c0dd96 RC |
524 | } |
525 | ||
1455adbd RC |
526 | /* is there a helper for this? */ |
527 | static bool is_fullscreen(struct drm_crtc_state *cstate, | |
528 | struct drm_plane_state *pstate) | |
529 | { | |
530 | return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) && | |
531 | ((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) && | |
532 | ((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay); | |
533 | } | |
534 | ||
359ae862 AT |
535 | enum mdp_mixer_stage_id get_start_stage(struct drm_crtc *crtc, |
536 | struct drm_crtc_state *new_crtc_state, | |
537 | struct drm_plane_state *bpstate) | |
538 | { | |
539 | struct mdp5_crtc_state *mdp5_cstate = | |
540 | to_mdp5_crtc_state(new_crtc_state); | |
541 | ||
542 | /* | |
543 | * if we're in source split mode, it's mandatory to have | |
544 | * border out on the base stage | |
545 | */ | |
546 | if (mdp5_cstate->pipeline.r_mixer) | |
547 | return STAGE0; | |
548 | ||
549 | /* if the bottom-most layer is not fullscreen, we need to use | |
550 | * it for solid-color: | |
551 | */ | |
552 | if (!is_fullscreen(new_crtc_state, bpstate)) | |
553 | return STAGE0; | |
554 | ||
555 | return STAGE_BASE; | |
556 | } | |
557 | ||
ed851963 RC |
558 | static int mdp5_crtc_atomic_check(struct drm_crtc *crtc, |
559 | struct drm_crtc_state *state) | |
0deed25b | 560 | { |
ed851963 RC |
561 | struct mdp5_kms *mdp5_kms = get_kms(crtc); |
562 | struct drm_plane *plane; | |
563 | struct drm_device *dev = crtc->dev; | |
12987781 | 564 | struct plane_state pstates[STAGE_MAX + 1]; |
565 | const struct mdp5_cfg_hw *hw_cfg; | |
2f196b7c | 566 | const struct drm_plane_state *pstate; |
8480adac | 567 | const struct drm_display_mode *mode = &state->adjusted_mode; |
5798c8e0 | 568 | bool cursor_plane = false; |
8480adac | 569 | bool need_right_mixer = false; |
359ae862 | 570 | int cnt = 0, i; |
894558ec | 571 | int ret; |
359ae862 | 572 | enum mdp_mixer_stage_id start; |
0deed25b | 573 | |
cee26588 | 574 | DBG("%s: check", crtc->name); |
0deed25b | 575 | |
2f196b7c | 576 | drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { |
ed851963 RC |
577 | pstates[cnt].plane = plane; |
578 | pstates[cnt].state = to_mdp5_plane_state(pstate); | |
579 | ||
8480adac AT |
580 | /* |
581 | * if any plane on this crtc uses 2 hwpipes, then we need | |
582 | * the crtc to have a right hwmixer. | |
583 | */ | |
584 | if (pstates[cnt].state->r_hwpipe) | |
585 | need_right_mixer = true; | |
ed851963 | 586 | cnt++; |
5798c8e0 AT |
587 | |
588 | if (plane->type == DRM_PLANE_TYPE_CURSOR) | |
589 | cursor_plane = true; | |
ed851963 RC |
590 | } |
591 | ||
359ae862 AT |
592 | /* bail out early if there aren't any planes */ |
593 | if (!cnt) | |
594 | return 0; | |
595 | ||
8480adac AT |
596 | hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg); |
597 | ||
598 | /* | |
599 | * we need a right hwmixer if the mode's width is greater than a single | |
600 | * LM's max width | |
601 | */ | |
602 | if (mode->hdisplay > hw_cfg->lm.max_width) | |
603 | need_right_mixer = true; | |
604 | ||
605 | ret = mdp5_crtc_setup_pipeline(crtc, state, need_right_mixer); | |
894558ec AT |
606 | if (ret) { |
607 | dev_err(dev->dev, "couldn't assign mixers %d\n", ret); | |
608 | return ret; | |
609 | } | |
610 | ||
12987781 | 611 | /* assign a stage based on sorted zpos property */ |
ed851963 RC |
612 | sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); |
613 | ||
5798c8e0 AT |
614 | /* trigger a warning if cursor isn't the highest zorder */ |
615 | WARN_ON(cursor_plane && | |
616 | (pstates[cnt - 1].plane->type != DRM_PLANE_TYPE_CURSOR)); | |
617 | ||
359ae862 AT |
618 | start = get_start_stage(crtc, state, &pstates[0].state->base); |
619 | ||
1455adbd RC |
620 | /* verify that there are not too many planes attached to crtc |
621 | * and that we don't have conflicting mixer stages: | |
622 | */ | |
359ae862 AT |
623 | if ((cnt + start - 1) >= hw_cfg->lm.nb_stages) { |
624 | dev_err(dev->dev, "too many planes! cnt=%d, start stage=%d\n", | |
625 | cnt, start); | |
1455adbd RC |
626 | return -EINVAL; |
627 | } | |
628 | ||
ed851963 | 629 | for (i = 0; i < cnt; i++) { |
5798c8e0 AT |
630 | if (cursor_plane && (i == (cnt - 1))) |
631 | pstates[i].state->stage = hw_cfg->lm.nb_stages; | |
632 | else | |
359ae862 | 633 | pstates[i].state->stage = start + i; |
cee26588 | 634 | DBG("%s: assign pipe %s on stage=%d", crtc->name, |
4a0f012d | 635 | pstates[i].plane->name, |
ed851963 RC |
636 | pstates[i].state->stage); |
637 | } | |
638 | ||
639 | return 0; | |
0deed25b SV |
640 | } |
641 | ||
613d2b27 ML |
642 | static void mdp5_crtc_atomic_begin(struct drm_crtc *crtc, |
643 | struct drm_crtc_state *old_crtc_state) | |
ed851963 | 644 | { |
cee26588 | 645 | DBG("%s: begin", crtc->name); |
ed851963 | 646 | } |
0deed25b | 647 | |
613d2b27 ML |
648 | static void mdp5_crtc_atomic_flush(struct drm_crtc *crtc, |
649 | struct drm_crtc_state *old_crtc_state) | |
06c0dd96 RC |
650 | { |
651 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
0ddc3a63 | 652 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
06c0dd96 | 653 | struct drm_device *dev = crtc->dev; |
06c0dd96 RC |
654 | unsigned long flags; |
655 | ||
cee26588 | 656 | DBG("%s: event: %p", crtc->name, crtc->state->event); |
06c0dd96 | 657 | |
ed851963 | 658 | WARN_ON(mdp5_crtc->event); |
06c0dd96 RC |
659 | |
660 | spin_lock_irqsave(&dev->event_lock, flags); | |
ed851963 | 661 | mdp5_crtc->event = crtc->state->event; |
06c0dd96 RC |
662 | spin_unlock_irqrestore(&dev->event_lock, flags); |
663 | ||
ba0312a6 SV |
664 | /* |
665 | * If no CTL has been allocated in mdp5_crtc_atomic_check(), | |
666 | * it means we are trying to flush a CRTC whose state is disabled: | |
667 | * nothing else needs to be done. | |
668 | */ | |
0ddc3a63 AT |
669 | /* XXX: Can this happen now ? */ |
670 | if (unlikely(!mdp5_cstate->ctl)) | |
ba0312a6 SV |
671 | return; |
672 | ||
ed851963 | 673 | blend_setup(crtc); |
0a5c9aad | 674 | |
68cdbed9 HL |
675 | /* PP_DONE irq is only used by command mode for now. |
676 | * It is better to request pending before FLUSH and START trigger | |
677 | * to make sure no pp_done irq missed. | |
678 | * This is safe because no pp_done will happen before SW trigger | |
679 | * in command mode. | |
680 | */ | |
0ddc3a63 | 681 | if (mdp5_cstate->cmd_mode) |
68cdbed9 HL |
682 | request_pp_done_pending(crtc); |
683 | ||
0a5c9aad HL |
684 | mdp5_crtc->flushed_mask = crtc_flush_all(crtc); |
685 | ||
0ddc3a63 AT |
686 | /* XXX are we leaking out state here? */ |
687 | mdp5_crtc->vblank.irqmask = mdp5_cstate->vblank_irqmask; | |
688 | mdp5_crtc->err.irqmask = mdp5_cstate->err_irqmask; | |
689 | mdp5_crtc->pp_done.irqmask = mdp5_cstate->pp_done_irqmask; | |
690 | ||
ed851963 | 691 | request_pending(crtc, PENDING_FLIP); |
06c0dd96 RC |
692 | } |
693 | ||
58560890 RC |
694 | static void get_roi(struct drm_crtc *crtc, uint32_t *roi_w, uint32_t *roi_h) |
695 | { | |
696 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
697 | uint32_t xres = crtc->mode.hdisplay; | |
698 | uint32_t yres = crtc->mode.vdisplay; | |
699 | ||
700 | /* | |
701 | * Cursor Region Of Interest (ROI) is a plane read from cursor | |
702 | * buffer to render. The ROI region is determined by the visibility of | |
703 | * the cursor point. In the default Cursor image the cursor point will | |
704 | * be at the top left of the cursor image, unless it is specified | |
705 | * otherwise using hotspot feature. | |
706 | * | |
707 | * If the cursor point reaches the right (xres - x < cursor.width) or | |
708 | * bottom (yres - y < cursor.height) boundary of the screen, then ROI | |
709 | * width and ROI height need to be evaluated to crop the cursor image | |
710 | * accordingly. | |
711 | * (xres-x) will be new cursor width when x > (xres - cursor.width) | |
712 | * (yres-y) will be new cursor height when y > (yres - cursor.height) | |
713 | */ | |
714 | *roi_w = min(mdp5_crtc->cursor.width, xres - | |
715 | mdp5_crtc->cursor.x); | |
716 | *roi_h = min(mdp5_crtc->cursor.height, yres - | |
717 | mdp5_crtc->cursor.y); | |
718 | } | |
719 | ||
e172d10a BG |
720 | static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, |
721 | struct drm_file *file, uint32_t handle, | |
722 | uint32_t width, uint32_t height) | |
723 | { | |
724 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
0ddc3a63 | 725 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
f316b25a | 726 | struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; |
e172d10a BG |
727 | struct drm_device *dev = crtc->dev; |
728 | struct mdp5_kms *mdp5_kms = get_kms(crtc); | |
f59f62d5 | 729 | struct msm_kms *kms = &mdp5_kms->base.base; |
389b09a1 | 730 | struct drm_gem_object *cursor_bo, *old_bo = NULL; |
78babc16 RC |
731 | uint32_t blendcfg, stride; |
732 | uint64_t cursor_addr; | |
0ddc3a63 | 733 | struct mdp5_ctl *ctl; |
d13b33fa | 734 | int ret, lm; |
e172d10a BG |
735 | enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL; |
736 | uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); | |
58560890 | 737 | uint32_t roi_w, roi_h; |
389b09a1 | 738 | bool cursor_enable = true; |
e172d10a BG |
739 | unsigned long flags; |
740 | ||
741 | if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) { | |
742 | dev_err(dev->dev, "bad cursor size: %dx%d\n", width, height); | |
743 | return -EINVAL; | |
744 | } | |
745 | ||
0ddc3a63 AT |
746 | ctl = mdp5_cstate->ctl; |
747 | if (!ctl) | |
e172d10a BG |
748 | return -EINVAL; |
749 | ||
b7621b2a AT |
750 | /* don't support LM cursors when we we have source split enabled */ |
751 | if (mdp5_cstate->pipeline.r_mixer) | |
752 | return -EINVAL; | |
753 | ||
e172d10a BG |
754 | if (!handle) { |
755 | DBG("Cursor off"); | |
389b09a1 SV |
756 | cursor_enable = false; |
757 | goto set_cursor; | |
e172d10a BG |
758 | } |
759 | ||
a8ad0bd8 | 760 | cursor_bo = drm_gem_object_lookup(file, handle); |
e172d10a BG |
761 | if (!cursor_bo) |
762 | return -ENOENT; | |
763 | ||
8bdcd949 | 764 | ret = msm_gem_get_iova(cursor_bo, kms->aspace, &cursor_addr); |
e172d10a BG |
765 | if (ret) |
766 | return -EINVAL; | |
767 | ||
0ddc3a63 | 768 | lm = mdp5_cstate->pipeline.mixer->lm; |
d13b33fa | 769 | stride = width * drm_format_plane_cpp(DRM_FORMAT_ARGB8888, 0); |
e172d10a BG |
770 | |
771 | spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); | |
772 | old_bo = mdp5_crtc->cursor.scanout_bo; | |
773 | ||
58560890 RC |
774 | mdp5_crtc->cursor.scanout_bo = cursor_bo; |
775 | mdp5_crtc->cursor.width = width; | |
776 | mdp5_crtc->cursor.height = height; | |
777 | ||
778 | get_roi(crtc, &roi_w, &roi_h); | |
779 | ||
e172d10a BG |
780 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_STRIDE(lm), stride); |
781 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_FORMAT(lm), | |
782 | MDP5_LM_CURSOR_FORMAT_FORMAT(CURSOR_FMT_ARGB8888)); | |
783 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_IMG_SIZE(lm), | |
784 | MDP5_LM_CURSOR_IMG_SIZE_SRC_H(height) | | |
785 | MDP5_LM_CURSOR_IMG_SIZE_SRC_W(width)); | |
786 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm), | |
58560890 RC |
787 | MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) | |
788 | MDP5_LM_CURSOR_SIZE_ROI_W(roi_w)); | |
e172d10a BG |
789 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BASE_ADDR(lm), cursor_addr); |
790 | ||
e172d10a | 791 | blendcfg = MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_EN; |
e172d10a BG |
792 | blendcfg |= MDP5_LM_CURSOR_BLEND_CONFIG_BLEND_ALPHA_SEL(cur_alpha); |
793 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_BLEND_CONFIG(lm), blendcfg); | |
794 | ||
e172d10a BG |
795 | spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags); |
796 | ||
389b09a1 | 797 | set_cursor: |
f316b25a | 798 | ret = mdp5_ctl_set_cursor(ctl, pipeline, 0, cursor_enable); |
389b09a1 SV |
799 | if (ret) { |
800 | dev_err(dev->dev, "failed to %sable cursor: %d\n", | |
801 | cursor_enable ? "en" : "dis", ret); | |
e172d10a | 802 | goto end; |
389b09a1 | 803 | } |
e172d10a | 804 | |
e172d10a BG |
805 | crtc_flush(crtc, flush_mask); |
806 | ||
807 | end: | |
808 | if (old_bo) { | |
809 | drm_flip_work_queue(&mdp5_crtc->unref_cursor_work, old_bo); | |
810 | /* enable vblank to complete cursor work: */ | |
811 | request_pending(crtc, PENDING_CURSOR); | |
812 | } | |
813 | return ret; | |
814 | } | |
815 | ||
816 | static int mdp5_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) | |
817 | { | |
818 | struct mdp5_kms *mdp5_kms = get_kms(crtc); | |
819 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
0ddc3a63 AT |
820 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
821 | uint32_t lm = mdp5_cstate->pipeline.mixer->lm; | |
e172d10a | 822 | uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); |
e172d10a BG |
823 | uint32_t roi_w; |
824 | uint32_t roi_h; | |
825 | unsigned long flags; | |
826 | ||
b7621b2a AT |
827 | /* don't support LM cursors when we we have source split enabled */ |
828 | if (mdp5_cstate->pipeline.r_mixer) | |
829 | return -EINVAL; | |
830 | ||
ba0312a6 SV |
831 | /* In case the CRTC is disabled, just drop the cursor update */ |
832 | if (unlikely(!crtc->state->enable)) | |
833 | return 0; | |
834 | ||
58560890 RC |
835 | mdp5_crtc->cursor.x = x = max(x, 0); |
836 | mdp5_crtc->cursor.y = y = max(y, 0); | |
e172d10a | 837 | |
58560890 | 838 | get_roi(crtc, &roi_w, &roi_h); |
e172d10a BG |
839 | |
840 | spin_lock_irqsave(&mdp5_crtc->cursor.lock, flags); | |
adfc0e63 | 841 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_SIZE(lm), |
e172d10a BG |
842 | MDP5_LM_CURSOR_SIZE_ROI_H(roi_h) | |
843 | MDP5_LM_CURSOR_SIZE_ROI_W(roi_w)); | |
adfc0e63 | 844 | mdp5_write(mdp5_kms, REG_MDP5_LM_CURSOR_START_XY(lm), |
e172d10a BG |
845 | MDP5_LM_CURSOR_START_XY_Y_START(y) | |
846 | MDP5_LM_CURSOR_START_XY_X_START(x)); | |
847 | spin_unlock_irqrestore(&mdp5_crtc->cursor.lock, flags); | |
848 | ||
849 | crtc_flush(crtc, flush_mask); | |
850 | ||
851 | return 0; | |
852 | } | |
853 | ||
c1e2a130 AT |
854 | static void |
855 | mdp5_crtc_atomic_print_state(struct drm_printer *p, | |
856 | const struct drm_crtc_state *state) | |
857 | { | |
858 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state); | |
859 | struct mdp5_pipeline *pipeline = &mdp5_cstate->pipeline; | |
b7621b2a | 860 | struct mdp5_kms *mdp5_kms = get_kms(state->crtc); |
c1e2a130 AT |
861 | |
862 | if (WARN_ON(!pipeline)) | |
863 | return; | |
864 | ||
865 | drm_printf(p, "\thwmixer=%s\n", pipeline->mixer ? | |
866 | pipeline->mixer->name : "(null)"); | |
b7621b2a AT |
867 | |
868 | if (mdp5_kms->caps & MDP_CAP_SRC_SPLIT) | |
869 | drm_printf(p, "\tright hwmixer=%s\n", pipeline->r_mixer ? | |
870 | pipeline->r_mixer->name : "(null)"); | |
c1e2a130 AT |
871 | } |
872 | ||
873 | static void mdp5_crtc_reset(struct drm_crtc *crtc) | |
874 | { | |
875 | struct mdp5_crtc_state *mdp5_cstate; | |
876 | ||
877 | if (crtc->state) { | |
878 | __drm_atomic_helper_crtc_destroy_state(crtc->state); | |
879 | kfree(to_mdp5_crtc_state(crtc->state)); | |
880 | } | |
881 | ||
882 | mdp5_cstate = kzalloc(sizeof(*mdp5_cstate), GFP_KERNEL); | |
883 | ||
884 | if (mdp5_cstate) { | |
885 | mdp5_cstate->base.crtc = crtc; | |
886 | crtc->state = &mdp5_cstate->base; | |
887 | } | |
888 | } | |
889 | ||
890 | static struct drm_crtc_state * | |
891 | mdp5_crtc_duplicate_state(struct drm_crtc *crtc) | |
892 | { | |
893 | struct mdp5_crtc_state *mdp5_cstate; | |
894 | ||
895 | if (WARN_ON(!crtc->state)) | |
896 | return NULL; | |
897 | ||
898 | mdp5_cstate = kmemdup(to_mdp5_crtc_state(crtc->state), | |
899 | sizeof(*mdp5_cstate), GFP_KERNEL); | |
900 | if (!mdp5_cstate) | |
901 | return NULL; | |
902 | ||
903 | __drm_atomic_helper_crtc_duplicate_state(crtc, &mdp5_cstate->base); | |
904 | ||
905 | return &mdp5_cstate->base; | |
906 | } | |
907 | ||
908 | static void mdp5_crtc_destroy_state(struct drm_crtc *crtc, struct drm_crtc_state *state) | |
909 | { | |
910 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(state); | |
911 | ||
912 | __drm_atomic_helper_crtc_destroy_state(state); | |
913 | ||
914 | kfree(mdp5_cstate); | |
915 | } | |
916 | ||
06c0dd96 | 917 | static const struct drm_crtc_funcs mdp5_crtc_funcs = { |
ed851963 | 918 | .set_config = drm_atomic_helper_set_config, |
06c0dd96 | 919 | .destroy = mdp5_crtc_destroy, |
ed851963 | 920 | .page_flip = drm_atomic_helper_page_flip, |
4103eef9 | 921 | .set_property = drm_atomic_helper_crtc_set_property, |
c1e2a130 AT |
922 | .reset = mdp5_crtc_reset, |
923 | .atomic_duplicate_state = mdp5_crtc_duplicate_state, | |
924 | .atomic_destroy_state = mdp5_crtc_destroy_state, | |
e172d10a BG |
925 | .cursor_set = mdp5_crtc_cursor_set, |
926 | .cursor_move = mdp5_crtc_cursor_move, | |
c1e2a130 | 927 | .atomic_print_state = mdp5_crtc_atomic_print_state, |
06c0dd96 RC |
928 | }; |
929 | ||
5798c8e0 AT |
930 | static const struct drm_crtc_funcs mdp5_crtc_no_lm_cursor_funcs = { |
931 | .set_config = drm_atomic_helper_set_config, | |
932 | .destroy = mdp5_crtc_destroy, | |
933 | .page_flip = drm_atomic_helper_page_flip, | |
934 | .set_property = drm_atomic_helper_crtc_set_property, | |
c1e2a130 AT |
935 | .reset = mdp5_crtc_reset, |
936 | .atomic_duplicate_state = mdp5_crtc_duplicate_state, | |
937 | .atomic_destroy_state = mdp5_crtc_destroy_state, | |
938 | .atomic_print_state = mdp5_crtc_atomic_print_state, | |
5798c8e0 AT |
939 | }; |
940 | ||
06c0dd96 | 941 | static const struct drm_crtc_helper_funcs mdp5_crtc_helper_funcs = { |
ed851963 | 942 | .mode_set_nofb = mdp5_crtc_mode_set_nofb, |
5db0f6e8 | 943 | .disable = mdp5_crtc_disable, |
ed851963 RC |
944 | .atomic_check = mdp5_crtc_atomic_check, |
945 | .atomic_begin = mdp5_crtc_atomic_begin, | |
946 | .atomic_flush = mdp5_crtc_atomic_flush, | |
0b20a0f8 | 947 | .atomic_enable = mdp5_crtc_atomic_enable, |
06c0dd96 RC |
948 | }; |
949 | ||
950 | static void mdp5_crtc_vblank_irq(struct mdp_irq *irq, uint32_t irqstatus) | |
951 | { | |
952 | struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, vblank); | |
953 | struct drm_crtc *crtc = &mdp5_crtc->base; | |
e172d10a | 954 | struct msm_drm_private *priv = crtc->dev->dev_private; |
06c0dd96 RC |
955 | unsigned pending; |
956 | ||
957 | mdp_irq_unregister(&get_kms(crtc)->base, &mdp5_crtc->vblank); | |
958 | ||
959 | pending = atomic_xchg(&mdp5_crtc->pending, 0); | |
960 | ||
961 | if (pending & PENDING_FLIP) { | |
962 | complete_flip(crtc, NULL); | |
06c0dd96 | 963 | } |
e172d10a BG |
964 | |
965 | if (pending & PENDING_CURSOR) | |
966 | drm_flip_work_commit(&mdp5_crtc->unref_cursor_work, priv->wq); | |
06c0dd96 RC |
967 | } |
968 | ||
969 | static void mdp5_crtc_err_irq(struct mdp_irq *irq, uint32_t irqstatus) | |
970 | { | |
971 | struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, err); | |
0deed25b | 972 | |
cee26588 | 973 | DBG("%s: error: %08x", mdp5_crtc->base.name, irqstatus); |
06c0dd96 RC |
974 | } |
975 | ||
68cdbed9 HL |
976 | static void mdp5_crtc_pp_done_irq(struct mdp_irq *irq, uint32_t irqstatus) |
977 | { | |
978 | struct mdp5_crtc *mdp5_crtc = container_of(irq, struct mdp5_crtc, | |
979 | pp_done); | |
980 | ||
981 | complete(&mdp5_crtc->pp_completion); | |
982 | } | |
983 | ||
984 | static void mdp5_crtc_wait_for_pp_done(struct drm_crtc *crtc) | |
985 | { | |
986 | struct drm_device *dev = crtc->dev; | |
987 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
0ddc3a63 | 988 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
68cdbed9 HL |
989 | int ret; |
990 | ||
991 | ret = wait_for_completion_timeout(&mdp5_crtc->pp_completion, | |
992 | msecs_to_jiffies(50)); | |
993 | if (ret == 0) | |
adfc0e63 | 994 | dev_warn(dev->dev, "pp done time out, lm=%d\n", |
0ddc3a63 | 995 | mdp5_cstate->pipeline.mixer->lm); |
68cdbed9 HL |
996 | } |
997 | ||
0a5c9aad HL |
998 | static void mdp5_crtc_wait_for_flush_done(struct drm_crtc *crtc) |
999 | { | |
1000 | struct drm_device *dev = crtc->dev; | |
1001 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
0ddc3a63 AT |
1002 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
1003 | struct mdp5_ctl *ctl = mdp5_cstate->ctl; | |
0a5c9aad HL |
1004 | int ret; |
1005 | ||
1006 | /* Should not call this function if crtc is disabled. */ | |
0ddc3a63 | 1007 | if (!ctl) |
0a5c9aad HL |
1008 | return; |
1009 | ||
1010 | ret = drm_crtc_vblank_get(crtc); | |
1011 | if (ret) | |
1012 | return; | |
1013 | ||
1014 | ret = wait_event_timeout(dev->vblank[drm_crtc_index(crtc)].queue, | |
0ddc3a63 | 1015 | ((mdp5_ctl_get_commit_status(ctl) & |
0a5c9aad HL |
1016 | mdp5_crtc->flushed_mask) == 0), |
1017 | msecs_to_jiffies(50)); | |
1018 | if (ret <= 0) | |
1019 | dev_warn(dev->dev, "vblank time out, crtc=%d\n", mdp5_crtc->id); | |
1020 | ||
1021 | mdp5_crtc->flushed_mask = 0; | |
1022 | ||
1023 | drm_crtc_vblank_put(crtc); | |
1024 | } | |
1025 | ||
06c0dd96 RC |
1026 | uint32_t mdp5_crtc_vblank(struct drm_crtc *crtc) |
1027 | { | |
1028 | struct mdp5_crtc *mdp5_crtc = to_mdp5_crtc(crtc); | |
1029 | return mdp5_crtc->vblank.irqmask; | |
1030 | } | |
1031 | ||
f316b25a | 1032 | void mdp5_crtc_set_pipeline(struct drm_crtc *crtc) |
06c0dd96 | 1033 | { |
0ddc3a63 | 1034 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
06c0dd96 | 1035 | struct mdp5_kms *mdp5_kms = get_kms(crtc); |
0a5c9aad | 1036 | |
0ddc3a63 | 1037 | /* should this be done elsewhere ? */ |
8bc1fe92 | 1038 | mdp_irq_update(&mdp5_kms->base); |
06c0dd96 | 1039 | |
f316b25a | 1040 | mdp5_ctl_set_pipeline(mdp5_cstate->ctl, &mdp5_cstate->pipeline); |
0deed25b | 1041 | } |
06c0dd96 | 1042 | |
10967a06 AT |
1043 | struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc) |
1044 | { | |
0ddc3a63 | 1045 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
10967a06 | 1046 | |
0ddc3a63 | 1047 | return mdp5_cstate->ctl; |
10967a06 AT |
1048 | } |
1049 | ||
adfc0e63 | 1050 | struct mdp5_hw_mixer *mdp5_crtc_get_mixer(struct drm_crtc *crtc) |
0deed25b | 1051 | { |
0ddc3a63 AT |
1052 | struct mdp5_crtc_state *mdp5_cstate; |
1053 | ||
1054 | if (WARN_ON(!crtc)) | |
1055 | return ERR_PTR(-EINVAL); | |
1056 | ||
1057 | mdp5_cstate = to_mdp5_crtc_state(crtc->state); | |
1058 | ||
1059 | return WARN_ON(!mdp5_cstate->pipeline.mixer) ? | |
1060 | ERR_PTR(-EINVAL) : mdp5_cstate->pipeline.mixer; | |
389b09a1 | 1061 | } |
0deed25b | 1062 | |
f316b25a AT |
1063 | struct mdp5_pipeline *mdp5_crtc_get_pipeline(struct drm_crtc *crtc) |
1064 | { | |
1065 | struct mdp5_crtc_state *mdp5_cstate; | |
1066 | ||
1067 | if (WARN_ON(!crtc)) | |
1068 | return ERR_PTR(-EINVAL); | |
1069 | ||
1070 | mdp5_cstate = to_mdp5_crtc_state(crtc->state); | |
1071 | ||
1072 | return &mdp5_cstate->pipeline; | |
1073 | } | |
1074 | ||
0a5c9aad HL |
1075 | void mdp5_crtc_wait_for_commit_done(struct drm_crtc *crtc) |
1076 | { | |
0ddc3a63 | 1077 | struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc->state); |
68cdbed9 | 1078 | |
0ddc3a63 | 1079 | if (mdp5_cstate->cmd_mode) |
68cdbed9 HL |
1080 | mdp5_crtc_wait_for_pp_done(crtc); |
1081 | else | |
1082 | mdp5_crtc_wait_for_flush_done(crtc); | |
0a5c9aad HL |
1083 | } |
1084 | ||
06c0dd96 RC |
1085 | /* initialize crtc */ |
1086 | struct drm_crtc *mdp5_crtc_init(struct drm_device *dev, | |
5798c8e0 AT |
1087 | struct drm_plane *plane, |
1088 | struct drm_plane *cursor_plane, int id) | |
06c0dd96 RC |
1089 | { |
1090 | struct drm_crtc *crtc = NULL; | |
1091 | struct mdp5_crtc *mdp5_crtc; | |
06c0dd96 RC |
1092 | |
1093 | mdp5_crtc = kzalloc(sizeof(*mdp5_crtc), GFP_KERNEL); | |
d7f8db53 BB |
1094 | if (!mdp5_crtc) |
1095 | return ERR_PTR(-ENOMEM); | |
06c0dd96 RC |
1096 | |
1097 | crtc = &mdp5_crtc->base; | |
1098 | ||
06c0dd96 | 1099 | mdp5_crtc->id = id; |
0deed25b SV |
1100 | |
1101 | spin_lock_init(&mdp5_crtc->lm_lock); | |
e172d10a | 1102 | spin_lock_init(&mdp5_crtc->cursor.lock); |
68cdbed9 | 1103 | init_completion(&mdp5_crtc->pp_completion); |
06c0dd96 RC |
1104 | |
1105 | mdp5_crtc->vblank.irq = mdp5_crtc_vblank_irq; | |
1106 | mdp5_crtc->err.irq = mdp5_crtc_err_irq; | |
0ddc3a63 | 1107 | mdp5_crtc->pp_done.irq = mdp5_crtc_pp_done_irq; |
06c0dd96 | 1108 | |
5798c8e0 AT |
1109 | if (cursor_plane) |
1110 | drm_crtc_init_with_planes(dev, crtc, plane, cursor_plane, | |
1111 | &mdp5_crtc_no_lm_cursor_funcs, NULL); | |
1112 | else | |
1113 | drm_crtc_init_with_planes(dev, crtc, plane, NULL, | |
1114 | &mdp5_crtc_funcs, NULL); | |
e172d10a BG |
1115 | |
1116 | drm_flip_work_init(&mdp5_crtc->unref_cursor_work, | |
1117 | "unref cursor", unref_cursor_worker); | |
1118 | ||
06c0dd96 | 1119 | drm_crtc_helper_add(crtc, &mdp5_crtc_helper_funcs); |
a8cecf33 | 1120 | plane->crtc = crtc; |
06c0dd96 | 1121 | |
06c0dd96 | 1122 | return crtc; |
06c0dd96 | 1123 | } |