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06c0dd96 RC |
1 | /* |
2 | * Copyright (C) 2013 Red Hat | |
3 | * Author: Rob Clark <robdclark@gmail.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published by | |
7 | * the Free Software Foundation. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
12 | * more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License along with | |
15 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | ||
19 | #include "msm_drv.h" | |
20 | #include "msm_mmu.h" | |
21 | #include "mdp5_kms.h" | |
22 | ||
23 | static struct mdp5_platform_config *mdp5_get_config(struct platform_device *dev); | |
24 | ||
25 | static int mdp5_hw_init(struct msm_kms *kms) | |
26 | { | |
27 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
28 | struct drm_device *dev = mdp5_kms->dev; | |
29 | uint32_t version, major, minor; | |
30 | int ret = 0; | |
31 | ||
32 | pm_runtime_get_sync(dev->dev); | |
33 | ||
34 | mdp5_enable(mdp5_kms); | |
35 | version = mdp5_read(mdp5_kms, REG_MDP5_MDP_VERSION); | |
36 | mdp5_disable(mdp5_kms); | |
37 | ||
38 | major = FIELD(version, MDP5_MDP_VERSION_MAJOR); | |
39 | minor = FIELD(version, MDP5_MDP_VERSION_MINOR); | |
40 | ||
41 | DBG("found MDP5 version v%d.%d", major, minor); | |
42 | ||
43 | if ((major != 1) || ((minor != 0) && (minor != 2))) { | |
44 | dev_err(dev->dev, "unexpected MDP version: v%d.%d\n", | |
45 | major, minor); | |
46 | ret = -ENXIO; | |
47 | goto out; | |
48 | } | |
49 | ||
50 | mdp5_kms->rev = minor; | |
51 | ||
52 | /* Magic unknown register writes: | |
53 | * | |
54 | * W VBIF:0x004 00000001 (mdss_mdp.c:839) | |
55 | * W MDP5:0x2e0 0xe9 (mdss_mdp.c:839) | |
56 | * W MDP5:0x2e4 0x55 (mdss_mdp.c:839) | |
57 | * W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839) | |
58 | * W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839) | |
59 | * W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839) | |
60 | * W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839) | |
61 | * W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839) | |
62 | * W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839) | |
63 | * | |
64 | * Downstream fbdev driver gets these register offsets/values | |
65 | * from DT.. not really sure what these registers are or if | |
66 | * different values for different boards/SoC's, etc. I guess | |
67 | * they are the golden registers. | |
68 | * | |
69 | * Not setting these does not seem to cause any problem. But | |
70 | * we may be getting lucky with the bootloader initializing | |
71 | * them for us. OTOH, if we can always count on the bootloader | |
72 | * setting the golden registers, then perhaps we don't need to | |
73 | * care. | |
74 | */ | |
75 | ||
76 | mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0); | |
77 | mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(0), 0); | |
78 | mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(1), 0); | |
79 | mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(2), 0); | |
80 | mdp5_write(mdp5_kms, REG_MDP5_CTL_OP(3), 0); | |
81 | ||
82 | out: | |
83 | pm_runtime_put_sync(dev->dev); | |
84 | ||
85 | return ret; | |
86 | } | |
87 | ||
88 | static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate, | |
89 | struct drm_encoder *encoder) | |
90 | { | |
91 | return rate; | |
92 | } | |
93 | ||
94 | static void mdp5_preclose(struct msm_kms *kms, struct drm_file *file) | |
95 | { | |
96 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
97 | struct msm_drm_private *priv = mdp5_kms->dev->dev_private; | |
98 | unsigned i; | |
99 | ||
100 | for (i = 0; i < priv->num_crtcs; i++) | |
101 | mdp5_crtc_cancel_pending_flip(priv->crtcs[i], file); | |
102 | } | |
103 | ||
104 | static void mdp5_destroy(struct msm_kms *kms) | |
105 | { | |
106 | struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms)); | |
107 | kfree(mdp5_kms); | |
108 | } | |
109 | ||
110 | static const struct mdp_kms_funcs kms_funcs = { | |
111 | .base = { | |
112 | .hw_init = mdp5_hw_init, | |
113 | .irq_preinstall = mdp5_irq_preinstall, | |
114 | .irq_postinstall = mdp5_irq_postinstall, | |
115 | .irq_uninstall = mdp5_irq_uninstall, | |
116 | .irq = mdp5_irq, | |
117 | .enable_vblank = mdp5_enable_vblank, | |
118 | .disable_vblank = mdp5_disable_vblank, | |
119 | .get_format = mdp_get_format, | |
120 | .round_pixclk = mdp5_round_pixclk, | |
121 | .preclose = mdp5_preclose, | |
122 | .destroy = mdp5_destroy, | |
123 | }, | |
124 | .set_irqmask = mdp5_set_irqmask, | |
125 | }; | |
126 | ||
127 | int mdp5_disable(struct mdp5_kms *mdp5_kms) | |
128 | { | |
129 | DBG(""); | |
130 | ||
131 | clk_disable_unprepare(mdp5_kms->ahb_clk); | |
132 | clk_disable_unprepare(mdp5_kms->axi_clk); | |
133 | clk_disable_unprepare(mdp5_kms->core_clk); | |
134 | clk_disable_unprepare(mdp5_kms->lut_clk); | |
135 | ||
136 | return 0; | |
137 | } | |
138 | ||
139 | int mdp5_enable(struct mdp5_kms *mdp5_kms) | |
140 | { | |
141 | DBG(""); | |
142 | ||
143 | clk_prepare_enable(mdp5_kms->ahb_clk); | |
144 | clk_prepare_enable(mdp5_kms->axi_clk); | |
145 | clk_prepare_enable(mdp5_kms->core_clk); | |
146 | clk_prepare_enable(mdp5_kms->lut_clk); | |
147 | ||
148 | return 0; | |
149 | } | |
150 | ||
151 | static int modeset_init(struct mdp5_kms *mdp5_kms) | |
152 | { | |
153 | static const enum mdp5_pipe crtcs[] = { | |
154 | SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, | |
155 | }; | |
156 | struct drm_device *dev = mdp5_kms->dev; | |
157 | struct msm_drm_private *priv = dev->dev_private; | |
158 | struct drm_encoder *encoder; | |
159 | int i, ret; | |
160 | ||
161 | /* construct CRTCs: */ | |
162 | for (i = 0; i < ARRAY_SIZE(crtcs); i++) { | |
163 | struct drm_plane *plane; | |
164 | struct drm_crtc *crtc; | |
165 | ||
166 | plane = mdp5_plane_init(dev, crtcs[i], true); | |
167 | if (IS_ERR(plane)) { | |
168 | ret = PTR_ERR(plane); | |
169 | dev_err(dev->dev, "failed to construct plane for %s (%d)\n", | |
170 | pipe2name(crtcs[i]), ret); | |
171 | goto fail; | |
172 | } | |
173 | ||
174 | crtc = mdp5_crtc_init(dev, plane, i); | |
175 | if (IS_ERR(crtc)) { | |
176 | ret = PTR_ERR(crtc); | |
177 | dev_err(dev->dev, "failed to construct crtc for %s (%d)\n", | |
178 | pipe2name(crtcs[i]), ret); | |
179 | goto fail; | |
180 | } | |
181 | priv->crtcs[priv->num_crtcs++] = crtc; | |
182 | } | |
183 | ||
184 | /* Construct encoder for HDMI: */ | |
185 | encoder = mdp5_encoder_init(dev, 3, INTF_HDMI); | |
186 | if (IS_ERR(encoder)) { | |
187 | dev_err(dev->dev, "failed to construct encoder\n"); | |
188 | ret = PTR_ERR(encoder); | |
189 | goto fail; | |
190 | } | |
191 | ||
192 | /* NOTE: the vsync and error irq's are actually associated with | |
193 | * the INTF/encoder.. the easiest way to deal with this (ie. what | |
194 | * we do now) is assume a fixed relationship between crtc's and | |
195 | * encoders. I'm not sure if there is ever a need to more freely | |
196 | * assign crtcs to encoders, but if there is then we need to take | |
197 | * care of error and vblank irq's that the crtc has registered, | |
198 | * and also update user-requested vblank_mask. | |
199 | */ | |
200 | encoder->possible_crtcs = BIT(0); | |
201 | mdp5_crtc_set_intf(priv->crtcs[0], 3, INTF_HDMI); | |
202 | ||
203 | priv->encoders[priv->num_encoders++] = encoder; | |
204 | ||
205 | /* Construct bridge/connector for HDMI: */ | |
206 | mdp5_kms->hdmi = hdmi_init(dev, encoder); | |
207 | if (IS_ERR(mdp5_kms->hdmi)) { | |
208 | ret = PTR_ERR(mdp5_kms->hdmi); | |
209 | dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret); | |
210 | goto fail; | |
211 | } | |
212 | ||
213 | return 0; | |
214 | ||
215 | fail: | |
216 | return ret; | |
217 | } | |
218 | ||
219 | static const char *iommu_ports[] = { | |
220 | "mdp_0", | |
221 | }; | |
222 | ||
223 | static int get_clk(struct platform_device *pdev, struct clk **clkp, | |
224 | const char *name) | |
225 | { | |
226 | struct device *dev = &pdev->dev; | |
227 | struct clk *clk = devm_clk_get(dev, name); | |
228 | if (IS_ERR(clk)) { | |
229 | dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk)); | |
230 | return PTR_ERR(clk); | |
231 | } | |
232 | *clkp = clk; | |
233 | return 0; | |
234 | } | |
235 | ||
236 | struct msm_kms *mdp5_kms_init(struct drm_device *dev) | |
237 | { | |
238 | struct platform_device *pdev = dev->platformdev; | |
239 | struct mdp5_platform_config *config = mdp5_get_config(pdev); | |
240 | struct mdp5_kms *mdp5_kms; | |
241 | struct msm_kms *kms = NULL; | |
242 | struct msm_mmu *mmu; | |
243 | int ret; | |
244 | ||
245 | mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL); | |
246 | if (!mdp5_kms) { | |
247 | dev_err(dev->dev, "failed to allocate kms\n"); | |
248 | ret = -ENOMEM; | |
249 | goto fail; | |
250 | } | |
251 | ||
252 | mdp_kms_init(&mdp5_kms->base, &kms_funcs); | |
253 | ||
254 | kms = &mdp5_kms->base.base; | |
255 | ||
256 | mdp5_kms->dev = dev; | |
257 | mdp5_kms->smp_blk_cnt = config->smp_blk_cnt; | |
258 | ||
259 | mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5"); | |
260 | if (IS_ERR(mdp5_kms->mmio)) { | |
261 | ret = PTR_ERR(mdp5_kms->mmio); | |
262 | goto fail; | |
263 | } | |
264 | ||
265 | mdp5_kms->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF"); | |
266 | if (IS_ERR(mdp5_kms->vbif)) { | |
267 | ret = PTR_ERR(mdp5_kms->vbif); | |
268 | goto fail; | |
269 | } | |
270 | ||
271 | mdp5_kms->vdd = devm_regulator_get(&pdev->dev, "vdd"); | |
272 | if (IS_ERR(mdp5_kms->vdd)) { | |
273 | ret = PTR_ERR(mdp5_kms->vdd); | |
274 | goto fail; | |
275 | } | |
276 | ||
277 | ret = regulator_enable(mdp5_kms->vdd); | |
278 | if (ret) { | |
279 | dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret); | |
280 | goto fail; | |
281 | } | |
282 | ||
283 | ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk") || | |
284 | get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk") || | |
285 | get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src") || | |
286 | get_clk(pdev, &mdp5_kms->core_clk, "core_clk") || | |
287 | get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk") || | |
288 | get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk"); | |
289 | if (ret) | |
290 | goto fail; | |
291 | ||
292 | ret = clk_set_rate(mdp5_kms->src_clk, config->max_clk); | |
293 | ||
294 | /* make sure things are off before attaching iommu (bootloader could | |
295 | * have left things on, in which case we'll start getting faults if | |
296 | * we don't disable): | |
297 | */ | |
298 | mdp5_enable(mdp5_kms); | |
299 | mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(0), 0); | |
300 | mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(1), 0); | |
301 | mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(2), 0); | |
302 | mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(3), 0); | |
303 | mdp5_disable(mdp5_kms); | |
304 | mdelay(16); | |
305 | ||
306 | if (config->iommu) { | |
307 | mmu = msm_iommu_new(dev, config->iommu); | |
308 | if (IS_ERR(mmu)) { | |
309 | ret = PTR_ERR(mmu); | |
310 | goto fail; | |
311 | } | |
312 | ret = mmu->funcs->attach(mmu, iommu_ports, | |
313 | ARRAY_SIZE(iommu_ports)); | |
314 | if (ret) | |
315 | goto fail; | |
316 | } else { | |
317 | dev_info(dev->dev, "no iommu, fallback to phys " | |
318 | "contig buffers for scanout\n"); | |
319 | mmu = NULL; | |
320 | } | |
321 | ||
322 | mdp5_kms->id = msm_register_mmu(dev, mmu); | |
323 | if (mdp5_kms->id < 0) { | |
324 | ret = mdp5_kms->id; | |
325 | dev_err(dev->dev, "failed to register mdp5 iommu: %d\n", ret); | |
326 | goto fail; | |
327 | } | |
328 | ||
329 | ret = modeset_init(mdp5_kms); | |
330 | if (ret) { | |
331 | dev_err(dev->dev, "modeset_init failed: %d\n", ret); | |
332 | goto fail; | |
333 | } | |
334 | ||
335 | return kms; | |
336 | ||
337 | fail: | |
338 | if (kms) | |
339 | mdp5_destroy(kms); | |
340 | return ERR_PTR(ret); | |
341 | } | |
342 | ||
343 | static struct mdp5_platform_config *mdp5_get_config(struct platform_device *dev) | |
344 | { | |
345 | static struct mdp5_platform_config config = {}; | |
346 | #ifdef CONFIG_OF | |
347 | /* TODO */ | |
348 | #endif | |
349 | return &config; | |
350 | } |