[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / msm / mdp / mdp5 / mdp5_kms.c

/*
 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
 * Copyright (C) 2013 Red Hat
 * Author: Rob Clark <robdclark@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */


#include "msm_drv.h"
#include "msm_mmu.h"
#include "mdp5_kms.h"

static const char *iommu_ports[] = {
		"mdp_0",
};

static int mdp5_hw_init(struct msm_kms *kms)
{
	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	struct drm_device *dev = mdp5_kms->dev;
	unsigned long flags;

	pm_runtime_get_sync(dev->dev);

	/* Magic unknown register writes:
	 *
	 *    W VBIF:0x004 00000001      (mdss_mdp.c:839)
	 *    W MDP5:0x2e0 0xe9          (mdss_mdp.c:839)
	 *    W MDP5:0x2e4 0x55          (mdss_mdp.c:839)
	 *    W MDP5:0x3ac 0xc0000ccc    (mdss_mdp.c:839)
	 *    W MDP5:0x3b4 0xc0000ccc    (mdss_mdp.c:839)
	 *    W MDP5:0x3bc 0xcccccc      (mdss_mdp.c:839)
	 *    W MDP5:0x4a8 0xcccc0c0     (mdss_mdp.c:839)
	 *    W MDP5:0x4b0 0xccccc0c0    (mdss_mdp.c:839)
	 *    W MDP5:0x4b8 0xccccc000    (mdss_mdp.c:839)
	 *
	 * Downstream fbdev driver gets these register offsets/values
	 * from DT.. not really sure what these registers are or if
	 * different values for different boards/SoC's, etc.  I guess
	 * they are the golden registers.
	 *
	 * Not setting these does not seem to cause any problem.  But
	 * we may be getting lucky with the bootloader initializing
	 * them for us.  OTOH, if we can always count on the bootloader
	 * setting the golden registers, then perhaps we don't need to
	 * care.
	 */

	spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
	mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);
	spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);

	mdp5_ctlm_hw_reset(mdp5_kms->ctlm);

	pm_runtime_put_sync(dev->dev);

	return 0;
}

static void mdp5_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state)
{
	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	mdp5_enable(mdp5_kms);
}

static void mdp5_complete_commit(struct msm_kms *kms, struct drm_atomic_state *state)
{
	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	mdp5_disable(mdp5_kms);
}

static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
		struct drm_encoder *encoder)
{
	return rate;
}

static void mdp5_preclose(struct msm_kms *kms, struct drm_file *file)
{
	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	struct msm_drm_private *priv = mdp5_kms->dev->dev_private;
	unsigned i;

	for (i = 0; i < priv->num_crtcs; i++)
		mdp5_crtc_cancel_pending_flip(priv->crtcs[i], file);
}

static void mdp5_destroy(struct msm_kms *kms)
{
	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	struct msm_mmu *mmu = mdp5_kms->mmu;

	mdp5_irq_domain_fini(mdp5_kms);

	if (mmu) {
		mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports));
		mmu->funcs->destroy(mmu);
	}

	if (mdp5_kms->ctlm)
		mdp5_ctlm_destroy(mdp5_kms->ctlm);
	if (mdp5_kms->smp)
		mdp5_smp_destroy(mdp5_kms->smp);
	if (mdp5_kms->cfg)
		mdp5_cfg_destroy(mdp5_kms->cfg);

	kfree(mdp5_kms);
}

static const struct mdp_kms_funcs kms_funcs = {
	.base = {
		.hw_init         = mdp5_hw_init,
		.irq_preinstall  = mdp5_irq_preinstall,
		.irq_postinstall = mdp5_irq_postinstall,
		.irq_uninstall   = mdp5_irq_uninstall,
		.irq             = mdp5_irq,
		.enable_vblank   = mdp5_enable_vblank,
		.disable_vblank  = mdp5_disable_vblank,
		.prepare_commit  = mdp5_prepare_commit,
		.complete_commit = mdp5_complete_commit,
		.get_format      = mdp_get_format,
		.round_pixclk    = mdp5_round_pixclk,
		.preclose        = mdp5_preclose,
		.destroy         = mdp5_destroy,
	},
	.set_irqmask         = mdp5_set_irqmask,
};

int mdp5_disable(struct mdp5_kms *mdp5_kms)
{
	DBG("");

	clk_disable_unprepare(mdp5_kms->ahb_clk);
	clk_disable_unprepare(mdp5_kms->axi_clk);
	clk_disable_unprepare(mdp5_kms->core_clk);
	clk_disable_unprepare(mdp5_kms->lut_clk);

	return 0;
}

int mdp5_enable(struct mdp5_kms *mdp5_kms)
{
	DBG("");

	clk_prepare_enable(mdp5_kms->ahb_clk);
	clk_prepare_enable(mdp5_kms->axi_clk);
	clk_prepare_enable(mdp5_kms->core_clk);
	clk_prepare_enable(mdp5_kms->lut_clk);

	return 0;
}

static int modeset_init(struct mdp5_kms *mdp5_kms)
{
	static const enum mdp5_pipe crtcs[] = {
			SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
	};
	static const enum mdp5_pipe pub_planes[] = {
			SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,
	};
	struct drm_device *dev = mdp5_kms->dev;
	struct msm_drm_private *priv = dev->dev_private;
	struct drm_encoder *encoder;
	const struct mdp5_cfg_hw *hw_cfg;
	int i, ret;

	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);

	/* register our interrupt-controller for hdmi/eDP/dsi/etc
	 * to use for irqs routed through mdp:
	 */
	ret = mdp5_irq_domain_init(mdp5_kms);
	if (ret)
		goto fail;

	/* construct CRTCs and their private planes: */
	for (i = 0; i < hw_cfg->pipe_rgb.count; i++) {
		struct drm_plane *plane;
		struct drm_crtc *crtc;

		plane = mdp5_plane_init(dev, crtcs[i], true,
				hw_cfg->pipe_rgb.base[i]);
		if (IS_ERR(plane)) {
			ret = PTR_ERR(plane);
			dev_err(dev->dev, "failed to construct plane for %s (%d)\n",
					pipe2name(crtcs[i]), ret);
			goto fail;
		}

		crtc  = mdp5_crtc_init(dev, plane, i);
		if (IS_ERR(crtc)) {
			ret = PTR_ERR(crtc);
			dev_err(dev->dev, "failed to construct crtc for %s (%d)\n",
					pipe2name(crtcs[i]), ret);
			goto fail;
		}
		priv->crtcs[priv->num_crtcs++] = crtc;
	}

	/* Construct public planes: */
	for (i = 0; i < hw_cfg->pipe_vig.count; i++) {
		struct drm_plane *plane;

		plane = mdp5_plane_init(dev, pub_planes[i], false,
				hw_cfg->pipe_vig.base[i]);
		if (IS_ERR(plane)) {
			ret = PTR_ERR(plane);
			dev_err(dev->dev, "failed to construct %s plane: %d\n",
					pipe2name(pub_planes[i]), ret);
			goto fail;
		}
	}

	if (priv->hdmi) {
		struct mdp5_interface intf = {
				.num	= 3,
				.type	= INTF_HDMI,
				.mode	= MDP5_INTF_MODE_NONE,
		};

		/* Construct encoder for HDMI: */
		encoder = mdp5_encoder_init(dev, &intf);
		if (IS_ERR(encoder)) {
			dev_err(dev->dev, "failed to construct encoder\n");
			ret = PTR_ERR(encoder);
			goto fail;
		}

		encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;;
		priv->encoders[priv->num_encoders++] = encoder;

		ret = hdmi_modeset_init(priv->hdmi, dev, encoder);
		if (ret) {
			dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret);
			goto fail;
		}
	}

	if (priv->edp) {
		struct mdp5_interface intf = {
				.num	= 0,
				.type	= INTF_eDP,
				.mode	= MDP5_INTF_MODE_NONE,
		};

		/* Construct encoder for eDP: */
		encoder = mdp5_encoder_init(dev, &intf);
		if (IS_ERR(encoder)) {
			dev_err(dev->dev, "failed to construct eDP encoder\n");
			ret = PTR_ERR(encoder);
			goto fail;
		}

		encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
		priv->encoders[priv->num_encoders++] = encoder;

		/* Construct bridge/connector for eDP: */
		ret = msm_edp_modeset_init(priv->edp, dev, encoder);
		if (ret) {
			dev_err(dev->dev, "failed to initialize eDP: %d\n",
									ret);
			goto fail;
		}
	}

	return 0;

fail:
	return ret;
}

static void read_hw_revision(struct mdp5_kms *mdp5_kms,
		uint32_t *major, uint32_t *minor)
{
	uint32_t version;

	mdp5_enable(mdp5_kms);
	version = mdp5_read(mdp5_kms, REG_MDP5_MDP_VERSION);
	mdp5_disable(mdp5_kms);

	*major = FIELD(version, MDP5_MDP_VERSION_MAJOR);
	*minor = FIELD(version, MDP5_MDP_VERSION_MINOR);

	DBG("MDP5 version v%d.%d", *major, *minor);
}

static int get_clk(struct platform_device *pdev, struct clk **clkp,
		const char *name)
{
	struct device *dev = &pdev->dev;
	struct clk *clk = devm_clk_get(dev, name);
	if (IS_ERR(clk)) {
		dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
		return PTR_ERR(clk);
	}
	*clkp = clk;
	return 0;
}

struct msm_kms *mdp5_kms_init(struct drm_device *dev)
{
	struct platform_device *pdev = dev->platformdev;
	struct mdp5_cfg *config;
	struct mdp5_kms *mdp5_kms;
	struct msm_kms *kms = NULL;
	struct msm_mmu *mmu;
	uint32_t major, minor;
	int i, ret;

	mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL);
	if (!mdp5_kms) {
		dev_err(dev->dev, "failed to allocate kms\n");
		ret = -ENOMEM;
		goto fail;
	}

	spin_lock_init(&mdp5_kms->resource_lock);

	mdp_kms_init(&mdp5_kms->base, &kms_funcs);

	kms = &mdp5_kms->base.base;

	mdp5_kms->dev = dev;

	mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
	if (IS_ERR(mdp5_kms->mmio)) {
		ret = PTR_ERR(mdp5_kms->mmio);
		goto fail;
	}

	mdp5_kms->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF");
	if (IS_ERR(mdp5_kms->vbif)) {
		ret = PTR_ERR(mdp5_kms->vbif);
		goto fail;
	}

	mdp5_kms->vdd = devm_regulator_get(&pdev->dev, "vdd");
	if (IS_ERR(mdp5_kms->vdd)) {
		ret = PTR_ERR(mdp5_kms->vdd);
		goto fail;
	}

	ret = regulator_enable(mdp5_kms->vdd);
	if (ret) {
		dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
		goto fail;
	}

	ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk");
	if (ret)
		goto fail;
	ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk");
	if (ret)
		goto fail;
	ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src");
	if (ret)
		goto fail;
	ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk");
	if (ret)
		goto fail;
	ret = get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk");
	if (ret)
		goto fail;
	ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk");
	if (ret)
		goto fail;

	/* we need to set a default rate before enabling.  Set a safe
	 * rate first, then figure out hw revision, and then set a
	 * more optimal rate:
	 */
	clk_set_rate(mdp5_kms->src_clk, 200000000);

	read_hw_revision(mdp5_kms, &major, &minor);

	mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor);
	if (IS_ERR(mdp5_kms->cfg)) {
		ret = PTR_ERR(mdp5_kms->cfg);
		mdp5_kms->cfg = NULL;
		goto fail;
	}

	config = mdp5_cfg_get_config(mdp5_kms->cfg);

	/* TODO: compute core clock rate at runtime */
	clk_set_rate(mdp5_kms->src_clk, config->hw->max_clk);

	mdp5_kms->smp = mdp5_smp_init(mdp5_kms->dev, &config->hw->smp);
	if (IS_ERR(mdp5_kms->smp)) {
		ret = PTR_ERR(mdp5_kms->smp);
		mdp5_kms->smp = NULL;
		goto fail;
	}

	mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, config->hw);
	if (IS_ERR(mdp5_kms->ctlm)) {
		ret = PTR_ERR(mdp5_kms->ctlm);
		mdp5_kms->ctlm = NULL;
		goto fail;
	}

	/* make sure things are off before attaching iommu (bootloader could
	 * have left things on, in which case we'll start getting faults if
	 * we don't disable):
	 */
	mdp5_enable(mdp5_kms);
	for (i = 0; i < config->hw->intf.count; i++)
		mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
	mdp5_disable(mdp5_kms);
	mdelay(16);

	if (config->platform.iommu) {
		mmu = msm_iommu_new(&pdev->dev, config->platform.iommu);
		if (IS_ERR(mmu)) {
			ret = PTR_ERR(mmu);
			dev_err(dev->dev, "failed to init iommu: %d\n", ret);
			goto fail;
		}

		ret = mmu->funcs->attach(mmu, iommu_ports,
				ARRAY_SIZE(iommu_ports));
		if (ret) {
			dev_err(dev->dev, "failed to attach iommu: %d\n", ret);
			mmu->funcs->destroy(mmu);
			goto fail;
		}
	} else {
		dev_info(dev->dev, "no iommu, fallback to phys "
				"contig buffers for scanout\n");
		mmu = NULL;
	}
	mdp5_kms->mmu = mmu;

	mdp5_kms->id = msm_register_mmu(dev, mmu);
	if (mdp5_kms->id < 0) {
		ret = mdp5_kms->id;
		dev_err(dev->dev, "failed to register mdp5 iommu: %d\n", ret);
		goto fail;
	}

	ret = modeset_init(mdp5_kms);
	if (ret) {
		dev_err(dev->dev, "modeset_init failed: %d\n", ret);
		goto fail;
	}

	return kms;

fail:
	if (kms)
		mdp5_destroy(kms);
	return ERR_PTR(ret);
}
Commit	Line	Data
06c0dd96	1	/*
2e362e17	2	* Copyright (c) 2014, The Linux Foundation. All rights reserved.
06c0dd96 RC	3	* Copyright (C) 2013 Red Hat
	4	* Author: Rob Clark <robdclark@gmail.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published by
	8	* the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
	19
	20	#include "msm_drv.h"
	21	#include "msm_mmu.h"
	22	#include "mdp5_kms.h"
	23
87e956e9 SV	24	static const char *iommu_ports[] = {
	25	"mdp_0",
	26	};
	27
3d47fd47 SV	28	static int mdp5_hw_init(struct msm_kms *kms)
	29	{
	30	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	31	struct drm_device *dev = mdp5_kms->dev;
0deed25b	32	unsigned long flags;
3d47fd47 SV	33
	34	pm_runtime_get_sync(dev->dev);
	35
06c0dd96 RC	36	/* Magic unknown register writes:
	37	*
	38	* W VBIF:0x004 00000001 (mdss_mdp.c:839)
	39	* W MDP5:0x2e0 0xe9 (mdss_mdp.c:839)
	40	* W MDP5:0x2e4 0x55 (mdss_mdp.c:839)
	41	* W MDP5:0x3ac 0xc0000ccc (mdss_mdp.c:839)
	42	* W MDP5:0x3b4 0xc0000ccc (mdss_mdp.c:839)
	43	* W MDP5:0x3bc 0xcccccc (mdss_mdp.c:839)
	44	* W MDP5:0x4a8 0xcccc0c0 (mdss_mdp.c:839)
	45	* W MDP5:0x4b0 0xccccc0c0 (mdss_mdp.c:839)
	46	* W MDP5:0x4b8 0xccccc000 (mdss_mdp.c:839)
	47	*
	48	* Downstream fbdev driver gets these register offsets/values
	49	* from DT.. not really sure what these registers are or if
	50	* different values for different boards/SoC's, etc. I guess
	51	* they are the golden registers.
	52	*
	53	* Not setting these does not seem to cause any problem. But
	54	* we may be getting lucky with the bootloader initializing
	55	* them for us. OTOH, if we can always count on the bootloader
	56	* setting the golden registers, then perhaps we don't need to
	57	* care.
	58	*/
	59
0deed25b	60	spin_lock_irqsave(&mdp5_kms->resource_lock, flags);
06c0dd96	61	mdp5_write(mdp5_kms, REG_MDP5_DISP_INTF_SEL, 0);
0deed25b	62	spin_unlock_irqrestore(&mdp5_kms->resource_lock, flags);
06c0dd96	63
42238da8	64	mdp5_ctlm_hw_reset(mdp5_kms->ctlm);
3d47fd47	65
06c0dd96 RC	66	pm_runtime_put_sync(dev->dev);
06c0dd96 RC	67
3d47fd47	68	return 0;
06c0dd96 RC	69	}
06c0dd96 RC	70
0b776d45 RC	71	static void mdp5_prepare_commit(struct msm_kms kms, struct drm_atomic_state state)
	72	{
	73	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	74	mdp5_enable(mdp5_kms);
	75	}
	76
	77	static void mdp5_complete_commit(struct msm_kms kms, struct drm_atomic_state state)
	78	{
	79	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	80	mdp5_disable(mdp5_kms);
	81	}
	82
06c0dd96 RC	83	static long mdp5_round_pixclk(struct msm_kms *kms, unsigned long rate,
	84	struct drm_encoder *encoder)
	85	{
	86	return rate;
	87	}
	88
	89	static void mdp5_preclose(struct msm_kms kms, struct drm_file file)
	90	{
	91	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
	92	struct msm_drm_private *priv = mdp5_kms->dev->dev_private;
	93	unsigned i;
	94
	95	for (i = 0; i < priv->num_crtcs; i++)
	96	mdp5_crtc_cancel_pending_flip(priv->crtcs[i], file);
	97	}
	98
	99	static void mdp5_destroy(struct msm_kms *kms)
	100	{
	101	struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
87e956e9 SV	102	struct msm_mmu *mmu = mdp5_kms->mmu;
87e956e9 SV	103
f6a8eaca RC	104	mdp5_irq_domain_fini(mdp5_kms);
f6a8eaca RC	105
87e956e9 SV	106	if (mmu) {
	107	mmu->funcs->detach(mmu, iommu_ports, ARRAY_SIZE(iommu_ports));
	108	mmu->funcs->destroy(mmu);
	109	}
42238da8 RC	110
	111	if (mdp5_kms->ctlm)
	112	mdp5_ctlm_destroy(mdp5_kms->ctlm);
	113	if (mdp5_kms->smp)
	114	mdp5_smp_destroy(mdp5_kms->smp);
	115	if (mdp5_kms->cfg)
	116	mdp5_cfg_destroy(mdp5_kms->cfg);
bfcdfb0e	117
06c0dd96 RC	118	kfree(mdp5_kms);
	119	}
	120
	121	static const struct mdp_kms_funcs kms_funcs = {
	122	.base = {
	123	.hw_init = mdp5_hw_init,
	124	.irq_preinstall = mdp5_irq_preinstall,
	125	.irq_postinstall = mdp5_irq_postinstall,
	126	.irq_uninstall = mdp5_irq_uninstall,
	127	.irq = mdp5_irq,
	128	.enable_vblank = mdp5_enable_vblank,
	129	.disable_vblank = mdp5_disable_vblank,
0b776d45 RC	130	.prepare_commit = mdp5_prepare_commit,
0b776d45 RC	131	.complete_commit = mdp5_complete_commit,
06c0dd96 RC	132	.get_format = mdp_get_format,
	133	.round_pixclk = mdp5_round_pixclk,
	134	.preclose = mdp5_preclose,
	135	.destroy = mdp5_destroy,
	136	},
	137	.set_irqmask = mdp5_set_irqmask,
	138	};
	139
	140	int mdp5_disable(struct mdp5_kms *mdp5_kms)
	141	{
	142	DBG("");
	143
	144	clk_disable_unprepare(mdp5_kms->ahb_clk);
	145	clk_disable_unprepare(mdp5_kms->axi_clk);
	146	clk_disable_unprepare(mdp5_kms->core_clk);
	147	clk_disable_unprepare(mdp5_kms->lut_clk);
	148
	149	return 0;
	150	}
	151
	152	int mdp5_enable(struct mdp5_kms *mdp5_kms)
	153	{
	154	DBG("");
	155
	156	clk_prepare_enable(mdp5_kms->ahb_clk);
	157	clk_prepare_enable(mdp5_kms->axi_clk);
	158	clk_prepare_enable(mdp5_kms->core_clk);
	159	clk_prepare_enable(mdp5_kms->lut_clk);
	160
	161	return 0;
	162	}
	163
	164	static int modeset_init(struct mdp5_kms *mdp5_kms)
	165	{
	166	static const enum mdp5_pipe crtcs[] = {
3d47fd47	167	SSPP_RGB0, SSPP_RGB1, SSPP_RGB2, SSPP_RGB3,
06c0dd96	168	};
0deed25b SV	169	static const enum mdp5_pipe pub_planes[] = {
	170	SSPP_VIG0, SSPP_VIG1, SSPP_VIG2, SSPP_VIG3,
	171	};
06c0dd96 RC	172	struct drm_device *dev = mdp5_kms->dev;
	173	struct msm_drm_private *priv = dev->dev_private;
	174	struct drm_encoder *encoder;
2e362e17	175	const struct mdp5_cfg_hw *hw_cfg;
06c0dd96 RC	176	int i, ret;
06c0dd96 RC	177
42238da8	178	hw_cfg = mdp5_cfg_get_hw_config(mdp5_kms->cfg);
2e362e17	179
f6a8eaca RC	180	/* register our interrupt-controller for hdmi/eDP/dsi/etc
	181	* to use for irqs routed through mdp:
	182	*/
	183	ret = mdp5_irq_domain_init(mdp5_kms);
	184	if (ret)
	185	goto fail;
	186
0deed25b	187	/* construct CRTCs and their private planes: */
2e362e17	188	for (i = 0; i < hw_cfg->pipe_rgb.count; i++) {
06c0dd96 RC	189	struct drm_plane *plane;
	190	struct drm_crtc *crtc;
	191
0deed25b SV	192	plane = mdp5_plane_init(dev, crtcs[i], true,
0deed25b SV	193	hw_cfg->pipe_rgb.base[i]);
06c0dd96 RC	194	if (IS_ERR(plane)) {
	195	ret = PTR_ERR(plane);
	196	dev_err(dev->dev, "failed to construct plane for %s (%d)\n",
	197	pipe2name(crtcs[i]), ret);
	198	goto fail;
	199	}
	200
	201	crtc = mdp5_crtc_init(dev, plane, i);
	202	if (IS_ERR(crtc)) {
	203	ret = PTR_ERR(crtc);
	204	dev_err(dev->dev, "failed to construct crtc for %s (%d)\n",
	205	pipe2name(crtcs[i]), ret);
	206	goto fail;
	207	}
	208	priv->crtcs[priv->num_crtcs++] = crtc;
	209	}
	210
0deed25b SV	211	/* Construct public planes: */
	212	for (i = 0; i < hw_cfg->pipe_vig.count; i++) {
	213	struct drm_plane *plane;
	214
	215	plane = mdp5_plane_init(dev, pub_planes[i], false,
	216	hw_cfg->pipe_vig.base[i]);
	217	if (IS_ERR(plane)) {
	218	ret = PTR_ERR(plane);
	219	dev_err(dev->dev, "failed to construct %s plane: %d\n",
	220	pipe2name(pub_planes[i]), ret);
	221	goto fail;
	222	}
	223	}
	224
00453981	225	if (priv->hdmi) {
d145dd78 SV	226	struct mdp5_interface intf = {
	227	.num = 3,
	228	.type = INTF_HDMI,
	229	.mode = MDP5_INTF_MODE_NONE,
	230	};
	231
00453981	232	/* Construct encoder for HDMI: */
d145dd78	233	encoder = mdp5_encoder_init(dev, &intf);
00453981 HL	234	if (IS_ERR(encoder)) {
	235	dev_err(dev->dev, "failed to construct encoder\n");
	236	ret = PTR_ERR(encoder);
	237	goto fail;
	238	}
06c0dd96	239
00453981 HL	240	encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;;
00453981 HL	241	priv->encoders[priv->num_encoders++] = encoder;
06c0dd96	242
067fef37 RC	243	ret = hdmi_modeset_init(priv->hdmi, dev, encoder);
	244	if (ret) {
	245	dev_err(dev->dev, "failed to initialize HDMI: %d\n", ret);
	246	goto fail;
	247	}
06c0dd96 RC	248	}
06c0dd96 RC	249
00453981	250	if (priv->edp) {
d145dd78 SV	251	struct mdp5_interface intf = {
	252	.num = 0,
	253	.type = INTF_eDP,
	254	.mode = MDP5_INTF_MODE_NONE,
	255	};
	256
00453981	257	/* Construct encoder for eDP: */
d145dd78	258	encoder = mdp5_encoder_init(dev, &intf);
00453981 HL	259	if (IS_ERR(encoder)) {
	260	dev_err(dev->dev, "failed to construct eDP encoder\n");
	261	ret = PTR_ERR(encoder);
	262	goto fail;
	263	}
	264
	265	encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
	266	priv->encoders[priv->num_encoders++] = encoder;
	267
	268	/* Construct bridge/connector for eDP: */
	269	ret = msm_edp_modeset_init(priv->edp, dev, encoder);
	270	if (ret) {
	271	dev_err(dev->dev, "failed to initialize eDP: %d\n",
	272	ret);
	273	goto fail;
	274	}
	275	}
	276
06c0dd96 RC	277	return 0;
	278
	279	fail:
	280	return ret;
	281	}
	282
2e362e17 SV	283	static void read_hw_revision(struct mdp5_kms *mdp5_kms,
	284	uint32_t major, uint32_t minor)
	285	{
	286	uint32_t version;
	287
	288	mdp5_enable(mdp5_kms);
	289	version = mdp5_read(mdp5_kms, REG_MDP5_MDP_VERSION);
	290	mdp5_disable(mdp5_kms);
	291
	292	*major = FIELD(version, MDP5_MDP_VERSION_MAJOR);
	293	*minor = FIELD(version, MDP5_MDP_VERSION_MINOR);
	294
	295	DBG("MDP5 version v%d.%d", major, minor);
	296	}
	297
06c0dd96 RC	298	static int get_clk(struct platform_device pdev, struct clk *clkp,
	299	const char *name)
	300	{
	301	struct device *dev = &pdev->dev;
	302	struct clk *clk = devm_clk_get(dev, name);
	303	if (IS_ERR(clk)) {
	304	dev_err(dev, "failed to get %s (%ld)\n", name, PTR_ERR(clk));
	305	return PTR_ERR(clk);
	306	}
	307	*clkp = clk;
	308	return 0;
	309	}
	310
	311	struct msm_kms mdp5_kms_init(struct drm_device dev)
	312	{
	313	struct platform_device *pdev = dev->platformdev;
2e362e17	314	struct mdp5_cfg *config;
06c0dd96 RC	315	struct mdp5_kms *mdp5_kms;
	316	struct msm_kms *kms = NULL;
	317	struct msm_mmu *mmu;
2e362e17	318	uint32_t major, minor;
3d47fd47	319	int i, ret;
06c0dd96 RC	320
	321	mdp5_kms = kzalloc(sizeof(*mdp5_kms), GFP_KERNEL);
	322	if (!mdp5_kms) {
	323	dev_err(dev->dev, "failed to allocate kms\n");
	324	ret = -ENOMEM;
	325	goto fail;
	326	}
	327
0deed25b SV	328	spin_lock_init(&mdp5_kms->resource_lock);
0deed25b SV	329
06c0dd96 RC	330	mdp_kms_init(&mdp5_kms->base, &kms_funcs);
	331
	332	kms = &mdp5_kms->base.base;
	333
	334	mdp5_kms->dev = dev;
06c0dd96 RC	335
	336	mdp5_kms->mmio = msm_ioremap(pdev, "mdp_phys", "MDP5");
	337	if (IS_ERR(mdp5_kms->mmio)) {
	338	ret = PTR_ERR(mdp5_kms->mmio);
	339	goto fail;
	340	}
	341
	342	mdp5_kms->vbif = msm_ioremap(pdev, "vbif_phys", "VBIF");
	343	if (IS_ERR(mdp5_kms->vbif)) {
	344	ret = PTR_ERR(mdp5_kms->vbif);
	345	goto fail;
	346	}
	347
	348	mdp5_kms->vdd = devm_regulator_get(&pdev->dev, "vdd");
	349	if (IS_ERR(mdp5_kms->vdd)) {
	350	ret = PTR_ERR(mdp5_kms->vdd);
	351	goto fail;
	352	}
	353
	354	ret = regulator_enable(mdp5_kms->vdd);
	355	if (ret) {
	356	dev_err(dev->dev, "failed to enable regulator vdd: %d\n", ret);
	357	goto fail;
	358	}
	359
a0906a02 RC	360	ret = get_clk(pdev, &mdp5_kms->axi_clk, "bus_clk");
	361	if (ret)
	362	goto fail;
	363	ret = get_clk(pdev, &mdp5_kms->ahb_clk, "iface_clk");
	364	if (ret)
	365	goto fail;
	366	ret = get_clk(pdev, &mdp5_kms->src_clk, "core_clk_src");
	367	if (ret)
	368	goto fail;
	369	ret = get_clk(pdev, &mdp5_kms->core_clk, "core_clk");
	370	if (ret)
	371	goto fail;
	372	ret = get_clk(pdev, &mdp5_kms->lut_clk, "lut_clk");
	373	if (ret)
	374	goto fail;
	375	ret = get_clk(pdev, &mdp5_kms->vsync_clk, "vsync_clk");
06c0dd96 RC	376	if (ret)
	377	goto fail;
	378
ac7a5704 RC	379	/* we need to set a default rate before enabling. Set a safe
	380	* rate first, then figure out hw revision, and then set a
	381	* more optimal rate:
	382	*/
	383	clk_set_rate(mdp5_kms->src_clk, 200000000);
	384
2e362e17	385	read_hw_revision(mdp5_kms, &major, &minor);
42238da8 RC	386
	387	mdp5_kms->cfg = mdp5_cfg_init(mdp5_kms, major, minor);
	388	if (IS_ERR(mdp5_kms->cfg)) {
	389	ret = PTR_ERR(mdp5_kms->cfg);
	390	mdp5_kms->cfg = NULL;
3d47fd47	391	goto fail;
2e362e17	392	}
42238da8 RC	393
42238da8 RC	394	config = mdp5_cfg_get_config(mdp5_kms->cfg);
3d47fd47	395
3f307963	396	/* TODO: compute core clock rate at runtime */
2e362e17	397	clk_set_rate(mdp5_kms->src_clk, config->hw->max_clk);
3f307963	398
42238da8 RC	399	mdp5_kms->smp = mdp5_smp_init(mdp5_kms->dev, &config->hw->smp);
	400	if (IS_ERR(mdp5_kms->smp)) {
	401	ret = PTR_ERR(mdp5_kms->smp);
	402	mdp5_kms->smp = NULL;
bfcdfb0e SV	403	goto fail;
bfcdfb0e SV	404	}
bfcdfb0e	405
42238da8 RC	406	mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, config->hw);
	407	if (IS_ERR(mdp5_kms->ctlm)) {
	408	ret = PTR_ERR(mdp5_kms->ctlm);
	409	mdp5_kms->ctlm = NULL;
0deed25b SV	410	goto fail;
0deed25b SV	411	}
0deed25b	412
06c0dd96 RC	413	/* make sure things are off before attaching iommu (bootloader could
	414	* have left things on, in which case we'll start getting faults if
	415	* we don't disable):
	416	*/
	417	mdp5_enable(mdp5_kms);
2e362e17	418	for (i = 0; i < config->hw->intf.count; i++)
3d47fd47	419	mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(i), 0);
06c0dd96 RC	420	mdp5_disable(mdp5_kms);
	421	mdelay(16);
	422
2e362e17 SV	423	if (config->platform.iommu) {
2e362e17 SV	424	mmu = msm_iommu_new(&pdev->dev, config->platform.iommu);
06c0dd96 RC	425	if (IS_ERR(mmu)) {
06c0dd96 RC	426	ret = PTR_ERR(mmu);
87e956e9	427	dev_err(dev->dev, "failed to init iommu: %d\n", ret);
06c0dd96 RC	428	goto fail;
06c0dd96 RC	429	}
87e956e9	430
06c0dd96 RC	431	ret = mmu->funcs->attach(mmu, iommu_ports,
06c0dd96 RC	432	ARRAY_SIZE(iommu_ports));
87e956e9 SV	433	if (ret) {
	434	dev_err(dev->dev, "failed to attach iommu: %d\n", ret);
	435	mmu->funcs->destroy(mmu);
06c0dd96	436	goto fail;
87e956e9	437	}
06c0dd96 RC	438	} else {
	439	dev_info(dev->dev, "no iommu, fallback to phys "
	440	"contig buffers for scanout\n");
	441	mmu = NULL;
	442	}
87e956e9	443	mdp5_kms->mmu = mmu;
06c0dd96 RC	444
	445	mdp5_kms->id = msm_register_mmu(dev, mmu);
	446	if (mdp5_kms->id < 0) {
	447	ret = mdp5_kms->id;
	448	dev_err(dev->dev, "failed to register mdp5 iommu: %d\n", ret);
	449	goto fail;
	450	}
	451
	452	ret = modeset_init(mdp5_kms);
	453	if (ret) {
	454	dev_err(dev->dev, "modeset_init failed: %d\n", ret);
	455	goto fail;
	456	}
	457
	458	return kms;
	459
	460	fail:
	461	if (kms)
	462	mdp5_destroy(kms);
	463	return ERR_PTR(ret);
	464	}